1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu-common.h" 24 #include "target/arm/idau.h" 25 #include "qemu/module.h" 26 #include "qapi/error.h" 27 #include "qapi/visitor.h" 28 #include "cpu.h" 29 #ifdef CONFIG_TCG 30 #include "hw/core/tcg-cpu-ops.h" 31 #endif /* CONFIG_TCG */ 32 #include "internals.h" 33 #include "exec/exec-all.h" 34 #include "hw/qdev-properties.h" 35 #if !defined(CONFIG_USER_ONLY) 36 #include "hw/loader.h" 37 #include "hw/boards.h" 38 #endif 39 #include "sysemu/sysemu.h" 40 #include "sysemu/tcg.h" 41 #include "sysemu/hw_accel.h" 42 #include "kvm_arm.h" 43 #include "disas/capstone.h" 44 #include "fpu/softfloat.h" 45 46 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 47 { 48 ARMCPU *cpu = ARM_CPU(cs); 49 CPUARMState *env = &cpu->env; 50 51 if (is_a64(env)) { 52 env->pc = value; 53 env->thumb = 0; 54 } else { 55 env->regs[15] = value & ~1; 56 env->thumb = value & 1; 57 } 58 } 59 60 #ifdef CONFIG_TCG 61 void arm_cpu_synchronize_from_tb(CPUState *cs, 62 const TranslationBlock *tb) 63 { 64 ARMCPU *cpu = ARM_CPU(cs); 65 CPUARMState *env = &cpu->env; 66 67 /* 68 * It's OK to look at env for the current mode here, because it's 69 * never possible for an AArch64 TB to chain to an AArch32 TB. 70 */ 71 if (is_a64(env)) { 72 env->pc = tb->pc; 73 } else { 74 env->regs[15] = tb->pc; 75 } 76 } 77 #endif /* CONFIG_TCG */ 78 79 static bool arm_cpu_has_work(CPUState *cs) 80 { 81 ARMCPU *cpu = ARM_CPU(cs); 82 83 return (cpu->power_state != PSCI_OFF) 84 && cs->interrupt_request & 85 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 86 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 87 | CPU_INTERRUPT_EXITTB); 88 } 89 90 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 91 void *opaque) 92 { 93 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 94 95 entry->hook = hook; 96 entry->opaque = opaque; 97 98 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 99 } 100 101 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 102 void *opaque) 103 { 104 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 105 106 entry->hook = hook; 107 entry->opaque = opaque; 108 109 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 110 } 111 112 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 113 { 114 /* Reset a single ARMCPRegInfo register */ 115 ARMCPRegInfo *ri = value; 116 ARMCPU *cpu = opaque; 117 118 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 119 return; 120 } 121 122 if (ri->resetfn) { 123 ri->resetfn(&cpu->env, ri); 124 return; 125 } 126 127 /* A zero offset is never possible as it would be regs[0] 128 * so we use it to indicate that reset is being handled elsewhere. 129 * This is basically only used for fields in non-core coprocessors 130 * (like the pxa2xx ones). 131 */ 132 if (!ri->fieldoffset) { 133 return; 134 } 135 136 if (cpreg_field_is_64bit(ri)) { 137 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 138 } else { 139 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 140 } 141 } 142 143 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 144 { 145 /* Purely an assertion check: we've already done reset once, 146 * so now check that running the reset for the cpreg doesn't 147 * change its value. This traps bugs where two different cpregs 148 * both try to reset the same state field but to different values. 149 */ 150 ARMCPRegInfo *ri = value; 151 ARMCPU *cpu = opaque; 152 uint64_t oldvalue, newvalue; 153 154 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 155 return; 156 } 157 158 oldvalue = read_raw_cp_reg(&cpu->env, ri); 159 cp_reg_reset(key, value, opaque); 160 newvalue = read_raw_cp_reg(&cpu->env, ri); 161 assert(oldvalue == newvalue); 162 } 163 164 static void arm_cpu_reset(DeviceState *dev) 165 { 166 CPUState *s = CPU(dev); 167 ARMCPU *cpu = ARM_CPU(s); 168 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 169 CPUARMState *env = &cpu->env; 170 171 acc->parent_reset(dev); 172 173 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 174 175 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 176 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 177 178 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 179 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 180 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 181 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 182 183 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; 184 185 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 186 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 187 } 188 189 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 190 /* 64 bit CPUs always start in 64 bit mode */ 191 env->aarch64 = 1; 192 #if defined(CONFIG_USER_ONLY) 193 env->pstate = PSTATE_MODE_EL0t; 194 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 195 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 196 /* Enable all PAC keys. */ 197 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 198 SCTLR_EnDA | SCTLR_EnDB); 199 /* and to the FP/Neon instructions */ 200 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 201 /* and to the SVE instructions */ 202 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 203 /* with reasonable vector length */ 204 if (cpu_isar_feature(aa64_sve, cpu)) { 205 env->vfp.zcr_el[1] = MIN(cpu->sve_max_vq - 1, 3); 206 } 207 /* 208 * Enable TBI0 and TBI1. While the real kernel only enables TBI0, 209 * turning on both here will produce smaller code and otherwise 210 * make no difference to the user-level emulation. 211 * 212 * In sve_probe_page, we assume that this is set. 213 * Do not modify this without other changes. 214 */ 215 env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); 216 #else 217 /* Reset into the highest available EL */ 218 if (arm_feature(env, ARM_FEATURE_EL3)) { 219 env->pstate = PSTATE_MODE_EL3h; 220 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 221 env->pstate = PSTATE_MODE_EL2h; 222 } else { 223 env->pstate = PSTATE_MODE_EL1h; 224 } 225 env->pc = cpu->rvbar; 226 #endif 227 } else { 228 #if defined(CONFIG_USER_ONLY) 229 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 230 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 231 #endif 232 } 233 234 #if defined(CONFIG_USER_ONLY) 235 env->uncached_cpsr = ARM_CPU_MODE_USR; 236 /* For user mode we must enable access to coprocessors */ 237 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 238 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 239 env->cp15.c15_cpar = 3; 240 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 241 env->cp15.c15_cpar = 1; 242 } 243 #else 244 245 /* 246 * If the highest available EL is EL2, AArch32 will start in Hyp 247 * mode; otherwise it starts in SVC. Note that if we start in 248 * AArch64 then these values in the uncached_cpsr will be ignored. 249 */ 250 if (arm_feature(env, ARM_FEATURE_EL2) && 251 !arm_feature(env, ARM_FEATURE_EL3)) { 252 env->uncached_cpsr = ARM_CPU_MODE_HYP; 253 } else { 254 env->uncached_cpsr = ARM_CPU_MODE_SVC; 255 } 256 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 257 258 if (arm_feature(env, ARM_FEATURE_M)) { 259 uint32_t initial_msp; /* Loaded from 0x0 */ 260 uint32_t initial_pc; /* Loaded from 0x4 */ 261 uint8_t *rom; 262 uint32_t vecbase; 263 264 if (cpu_isar_feature(aa32_lob, cpu)) { 265 /* 266 * LTPSIZE is constant 4 if MVE not implemented, and resets 267 * to an UNKNOWN value if MVE is implemented. We choose to 268 * always reset to 4. 269 */ 270 env->v7m.ltpsize = 4; 271 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 272 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 273 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 274 } 275 276 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 277 env->v7m.secure = true; 278 } else { 279 /* This bit resets to 0 if security is supported, but 1 if 280 * it is not. The bit is not present in v7M, but we set it 281 * here so we can avoid having to make checks on it conditional 282 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 283 */ 284 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 285 /* 286 * Set NSACR to indicate "NS access permitted to everything"; 287 * this avoids having to have all the tests of it being 288 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 289 * v8.1M the guest-visible value of NSACR in a CPU without the 290 * Security Extension is 0xcff. 291 */ 292 env->v7m.nsacr = 0xcff; 293 } 294 295 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 296 * that it resets to 1, so QEMU always does that rather than making 297 * it dependent on CPU model. In v8M it is RES1. 298 */ 299 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 300 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 301 if (arm_feature(env, ARM_FEATURE_V8)) { 302 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 303 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 304 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 305 } 306 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 307 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 308 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 309 } 310 311 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 312 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 313 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 314 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 315 } 316 /* Unlike A/R profile, M profile defines the reset LR value */ 317 env->regs[14] = 0xffffffff; 318 319 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 320 321 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 322 vecbase = env->v7m.vecbase[env->v7m.secure]; 323 rom = rom_ptr(vecbase, 8); 324 if (rom) { 325 /* Address zero is covered by ROM which hasn't yet been 326 * copied into physical memory. 327 */ 328 initial_msp = ldl_p(rom); 329 initial_pc = ldl_p(rom + 4); 330 } else { 331 /* Address zero not covered by a ROM blob, or the ROM blob 332 * is in non-modifiable memory and this is a second reset after 333 * it got copied into memory. In the latter case, rom_ptr 334 * will return a NULL pointer and we should use ldl_phys instead. 335 */ 336 initial_msp = ldl_phys(s->as, vecbase); 337 initial_pc = ldl_phys(s->as, vecbase + 4); 338 } 339 340 env->regs[13] = initial_msp & 0xFFFFFFFC; 341 env->regs[15] = initial_pc & ~1; 342 env->thumb = initial_pc & 1; 343 } 344 345 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 346 * executing as AArch32 then check if highvecs are enabled and 347 * adjust the PC accordingly. 348 */ 349 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 350 env->regs[15] = 0xFFFF0000; 351 } 352 353 /* M profile requires that reset clears the exclusive monitor; 354 * A profile does not, but clearing it makes more sense than having it 355 * set with an exclusive access on address zero. 356 */ 357 arm_clear_exclusive(env); 358 359 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 360 #endif 361 362 if (arm_feature(env, ARM_FEATURE_PMSA)) { 363 if (cpu->pmsav7_dregion > 0) { 364 if (arm_feature(env, ARM_FEATURE_V8)) { 365 memset(env->pmsav8.rbar[M_REG_NS], 0, 366 sizeof(*env->pmsav8.rbar[M_REG_NS]) 367 * cpu->pmsav7_dregion); 368 memset(env->pmsav8.rlar[M_REG_NS], 0, 369 sizeof(*env->pmsav8.rlar[M_REG_NS]) 370 * cpu->pmsav7_dregion); 371 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 372 memset(env->pmsav8.rbar[M_REG_S], 0, 373 sizeof(*env->pmsav8.rbar[M_REG_S]) 374 * cpu->pmsav7_dregion); 375 memset(env->pmsav8.rlar[M_REG_S], 0, 376 sizeof(*env->pmsav8.rlar[M_REG_S]) 377 * cpu->pmsav7_dregion); 378 } 379 } else if (arm_feature(env, ARM_FEATURE_V7)) { 380 memset(env->pmsav7.drbar, 0, 381 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 382 memset(env->pmsav7.drsr, 0, 383 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 384 memset(env->pmsav7.dracr, 0, 385 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 386 } 387 } 388 env->pmsav7.rnr[M_REG_NS] = 0; 389 env->pmsav7.rnr[M_REG_S] = 0; 390 env->pmsav8.mair0[M_REG_NS] = 0; 391 env->pmsav8.mair0[M_REG_S] = 0; 392 env->pmsav8.mair1[M_REG_NS] = 0; 393 env->pmsav8.mair1[M_REG_S] = 0; 394 } 395 396 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 397 if (cpu->sau_sregion > 0) { 398 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 399 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 400 } 401 env->sau.rnr = 0; 402 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 403 * the Cortex-M33 does. 404 */ 405 env->sau.ctrl = 0; 406 } 407 408 set_flush_to_zero(1, &env->vfp.standard_fp_status); 409 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 410 set_default_nan_mode(1, &env->vfp.standard_fp_status); 411 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); 412 set_float_detect_tininess(float_tininess_before_rounding, 413 &env->vfp.fp_status); 414 set_float_detect_tininess(float_tininess_before_rounding, 415 &env->vfp.standard_fp_status); 416 set_float_detect_tininess(float_tininess_before_rounding, 417 &env->vfp.fp_status_f16); 418 set_float_detect_tininess(float_tininess_before_rounding, 419 &env->vfp.standard_fp_status_f16); 420 #ifndef CONFIG_USER_ONLY 421 if (kvm_enabled()) { 422 kvm_arm_reset_vcpu(cpu); 423 } 424 #endif 425 426 hw_breakpoint_update_all(cpu); 427 hw_watchpoint_update_all(cpu); 428 arm_rebuild_hflags(env); 429 } 430 431 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 432 unsigned int target_el, 433 unsigned int cur_el, bool secure, 434 uint64_t hcr_el2) 435 { 436 CPUARMState *env = cs->env_ptr; 437 bool pstate_unmasked; 438 bool unmasked = false; 439 440 /* 441 * Don't take exceptions if they target a lower EL. 442 * This check should catch any exceptions that would not be taken 443 * but left pending. 444 */ 445 if (cur_el > target_el) { 446 return false; 447 } 448 449 switch (excp_idx) { 450 case EXCP_FIQ: 451 pstate_unmasked = !(env->daif & PSTATE_F); 452 break; 453 454 case EXCP_IRQ: 455 pstate_unmasked = !(env->daif & PSTATE_I); 456 break; 457 458 case EXCP_VFIQ: 459 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 460 /* VFIQs are only taken when hypervized. */ 461 return false; 462 } 463 return !(env->daif & PSTATE_F); 464 case EXCP_VIRQ: 465 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 466 /* VIRQs are only taken when hypervized. */ 467 return false; 468 } 469 return !(env->daif & PSTATE_I); 470 default: 471 g_assert_not_reached(); 472 } 473 474 /* 475 * Use the target EL, current execution state and SCR/HCR settings to 476 * determine whether the corresponding CPSR bit is used to mask the 477 * interrupt. 478 */ 479 if ((target_el > cur_el) && (target_el != 1)) { 480 /* Exceptions targeting a higher EL may not be maskable */ 481 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 482 /* 483 * 64-bit masking rules are simple: exceptions to EL3 484 * can't be masked, and exceptions to EL2 can only be 485 * masked from Secure state. The HCR and SCR settings 486 * don't affect the masking logic, only the interrupt routing. 487 */ 488 if (target_el == 3 || !secure || (env->cp15.scr_el3 & SCR_EEL2)) { 489 unmasked = true; 490 } 491 } else { 492 /* 493 * The old 32-bit-only environment has a more complicated 494 * masking setup. HCR and SCR bits not only affect interrupt 495 * routing but also change the behaviour of masking. 496 */ 497 bool hcr, scr; 498 499 switch (excp_idx) { 500 case EXCP_FIQ: 501 /* 502 * If FIQs are routed to EL3 or EL2 then there are cases where 503 * we override the CPSR.F in determining if the exception is 504 * masked or not. If neither of these are set then we fall back 505 * to the CPSR.F setting otherwise we further assess the state 506 * below. 507 */ 508 hcr = hcr_el2 & HCR_FMO; 509 scr = (env->cp15.scr_el3 & SCR_FIQ); 510 511 /* 512 * When EL3 is 32-bit, the SCR.FW bit controls whether the 513 * CPSR.F bit masks FIQ interrupts when taken in non-secure 514 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 515 * when non-secure but only when FIQs are only routed to EL3. 516 */ 517 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 518 break; 519 case EXCP_IRQ: 520 /* 521 * When EL3 execution state is 32-bit, if HCR.IMO is set then 522 * we may override the CPSR.I masking when in non-secure state. 523 * The SCR.IRQ setting has already been taken into consideration 524 * when setting the target EL, so it does not have a further 525 * affect here. 526 */ 527 hcr = hcr_el2 & HCR_IMO; 528 scr = false; 529 break; 530 default: 531 g_assert_not_reached(); 532 } 533 534 if ((scr || hcr) && !secure) { 535 unmasked = true; 536 } 537 } 538 } 539 540 /* 541 * The PSTATE bits only mask the interrupt if we have not overriden the 542 * ability above. 543 */ 544 return unmasked || pstate_unmasked; 545 } 546 547 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 548 { 549 CPUClass *cc = CPU_GET_CLASS(cs); 550 CPUARMState *env = cs->env_ptr; 551 uint32_t cur_el = arm_current_el(env); 552 bool secure = arm_is_secure(env); 553 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 554 uint32_t target_el; 555 uint32_t excp_idx; 556 557 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 558 559 if (interrupt_request & CPU_INTERRUPT_FIQ) { 560 excp_idx = EXCP_FIQ; 561 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 562 if (arm_excp_unmasked(cs, excp_idx, target_el, 563 cur_el, secure, hcr_el2)) { 564 goto found; 565 } 566 } 567 if (interrupt_request & CPU_INTERRUPT_HARD) { 568 excp_idx = EXCP_IRQ; 569 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 570 if (arm_excp_unmasked(cs, excp_idx, target_el, 571 cur_el, secure, hcr_el2)) { 572 goto found; 573 } 574 } 575 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 576 excp_idx = EXCP_VIRQ; 577 target_el = 1; 578 if (arm_excp_unmasked(cs, excp_idx, target_el, 579 cur_el, secure, hcr_el2)) { 580 goto found; 581 } 582 } 583 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 584 excp_idx = EXCP_VFIQ; 585 target_el = 1; 586 if (arm_excp_unmasked(cs, excp_idx, target_el, 587 cur_el, secure, hcr_el2)) { 588 goto found; 589 } 590 } 591 return false; 592 593 found: 594 cs->exception_index = excp_idx; 595 env->exception.target_el = target_el; 596 cc->tcg_ops->do_interrupt(cs); 597 return true; 598 } 599 600 void arm_cpu_update_virq(ARMCPU *cpu) 601 { 602 /* 603 * Update the interrupt level for VIRQ, which is the logical OR of 604 * the HCR_EL2.VI bit and the input line level from the GIC. 605 */ 606 CPUARMState *env = &cpu->env; 607 CPUState *cs = CPU(cpu); 608 609 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 610 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 611 612 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 613 if (new_state) { 614 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 615 } else { 616 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 617 } 618 } 619 } 620 621 void arm_cpu_update_vfiq(ARMCPU *cpu) 622 { 623 /* 624 * Update the interrupt level for VFIQ, which is the logical OR of 625 * the HCR_EL2.VF bit and the input line level from the GIC. 626 */ 627 CPUARMState *env = &cpu->env; 628 CPUState *cs = CPU(cpu); 629 630 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 631 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 632 633 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 634 if (new_state) { 635 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 636 } else { 637 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 638 } 639 } 640 } 641 642 #ifndef CONFIG_USER_ONLY 643 static void arm_cpu_set_irq(void *opaque, int irq, int level) 644 { 645 ARMCPU *cpu = opaque; 646 CPUARMState *env = &cpu->env; 647 CPUState *cs = CPU(cpu); 648 static const int mask[] = { 649 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 650 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 651 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 652 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 653 }; 654 655 if (level) { 656 env->irq_line_state |= mask[irq]; 657 } else { 658 env->irq_line_state &= ~mask[irq]; 659 } 660 661 switch (irq) { 662 case ARM_CPU_VIRQ: 663 assert(arm_feature(env, ARM_FEATURE_EL2)); 664 arm_cpu_update_virq(cpu); 665 break; 666 case ARM_CPU_VFIQ: 667 assert(arm_feature(env, ARM_FEATURE_EL2)); 668 arm_cpu_update_vfiq(cpu); 669 break; 670 case ARM_CPU_IRQ: 671 case ARM_CPU_FIQ: 672 if (level) { 673 cpu_interrupt(cs, mask[irq]); 674 } else { 675 cpu_reset_interrupt(cs, mask[irq]); 676 } 677 break; 678 default: 679 g_assert_not_reached(); 680 } 681 } 682 683 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 684 { 685 #ifdef CONFIG_KVM 686 ARMCPU *cpu = opaque; 687 CPUARMState *env = &cpu->env; 688 CPUState *cs = CPU(cpu); 689 uint32_t linestate_bit; 690 int irq_id; 691 692 switch (irq) { 693 case ARM_CPU_IRQ: 694 irq_id = KVM_ARM_IRQ_CPU_IRQ; 695 linestate_bit = CPU_INTERRUPT_HARD; 696 break; 697 case ARM_CPU_FIQ: 698 irq_id = KVM_ARM_IRQ_CPU_FIQ; 699 linestate_bit = CPU_INTERRUPT_FIQ; 700 break; 701 default: 702 g_assert_not_reached(); 703 } 704 705 if (level) { 706 env->irq_line_state |= linestate_bit; 707 } else { 708 env->irq_line_state &= ~linestate_bit; 709 } 710 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 711 #endif 712 } 713 714 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 715 { 716 ARMCPU *cpu = ARM_CPU(cs); 717 CPUARMState *env = &cpu->env; 718 719 cpu_synchronize_state(cs); 720 return arm_cpu_data_is_big_endian(env); 721 } 722 723 #endif 724 725 static int 726 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 727 { 728 return print_insn_arm(pc | 1, info); 729 } 730 731 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 732 { 733 ARMCPU *ac = ARM_CPU(cpu); 734 CPUARMState *env = &ac->env; 735 bool sctlr_b; 736 737 if (is_a64(env)) { 738 /* We might not be compiled with the A64 disassembler 739 * because it needs a C++ compiler. Leave print_insn 740 * unset in this case to use the caller default behaviour. 741 */ 742 #if defined(CONFIG_ARM_A64_DIS) 743 info->print_insn = print_insn_arm_a64; 744 #endif 745 info->cap_arch = CS_ARCH_ARM64; 746 info->cap_insn_unit = 4; 747 info->cap_insn_split = 4; 748 } else { 749 int cap_mode; 750 if (env->thumb) { 751 info->print_insn = print_insn_thumb1; 752 info->cap_insn_unit = 2; 753 info->cap_insn_split = 4; 754 cap_mode = CS_MODE_THUMB; 755 } else { 756 info->print_insn = print_insn_arm; 757 info->cap_insn_unit = 4; 758 info->cap_insn_split = 4; 759 cap_mode = CS_MODE_ARM; 760 } 761 if (arm_feature(env, ARM_FEATURE_V8)) { 762 cap_mode |= CS_MODE_V8; 763 } 764 if (arm_feature(env, ARM_FEATURE_M)) { 765 cap_mode |= CS_MODE_MCLASS; 766 } 767 info->cap_arch = CS_ARCH_ARM; 768 info->cap_mode = cap_mode; 769 } 770 771 sctlr_b = arm_sctlr_b(env); 772 if (bswap_code(sctlr_b)) { 773 #ifdef TARGET_WORDS_BIGENDIAN 774 info->endian = BFD_ENDIAN_LITTLE; 775 #else 776 info->endian = BFD_ENDIAN_BIG; 777 #endif 778 } 779 info->flags &= ~INSN_ARM_BE32; 780 #ifndef CONFIG_USER_ONLY 781 if (sctlr_b) { 782 info->flags |= INSN_ARM_BE32; 783 } 784 #endif 785 } 786 787 #ifdef TARGET_AARCH64 788 789 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 790 { 791 ARMCPU *cpu = ARM_CPU(cs); 792 CPUARMState *env = &cpu->env; 793 uint32_t psr = pstate_read(env); 794 int i; 795 int el = arm_current_el(env); 796 const char *ns_status; 797 798 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 799 for (i = 0; i < 32; i++) { 800 if (i == 31) { 801 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 802 } else { 803 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 804 (i + 2) % 3 ? " " : "\n"); 805 } 806 } 807 808 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 809 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 810 } else { 811 ns_status = ""; 812 } 813 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 814 psr, 815 psr & PSTATE_N ? 'N' : '-', 816 psr & PSTATE_Z ? 'Z' : '-', 817 psr & PSTATE_C ? 'C' : '-', 818 psr & PSTATE_V ? 'V' : '-', 819 ns_status, 820 el, 821 psr & PSTATE_SP ? 'h' : 't'); 822 823 if (cpu_isar_feature(aa64_bti, cpu)) { 824 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 825 } 826 if (!(flags & CPU_DUMP_FPU)) { 827 qemu_fprintf(f, "\n"); 828 return; 829 } 830 if (fp_exception_el(env, el) != 0) { 831 qemu_fprintf(f, " FPU disabled\n"); 832 return; 833 } 834 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 835 vfp_get_fpcr(env), vfp_get_fpsr(env)); 836 837 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { 838 int j, zcr_len = sve_zcr_len_for_el(env, el); 839 840 for (i = 0; i <= FFR_PRED_NUM; i++) { 841 bool eol; 842 if (i == FFR_PRED_NUM) { 843 qemu_fprintf(f, "FFR="); 844 /* It's last, so end the line. */ 845 eol = true; 846 } else { 847 qemu_fprintf(f, "P%02d=", i); 848 switch (zcr_len) { 849 case 0: 850 eol = i % 8 == 7; 851 break; 852 case 1: 853 eol = i % 6 == 5; 854 break; 855 case 2: 856 case 3: 857 eol = i % 3 == 2; 858 break; 859 default: 860 /* More than one quadword per predicate. */ 861 eol = true; 862 break; 863 } 864 } 865 for (j = zcr_len / 4; j >= 0; j--) { 866 int digits; 867 if (j * 4 + 4 <= zcr_len + 1) { 868 digits = 16; 869 } else { 870 digits = (zcr_len % 4 + 1) * 4; 871 } 872 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 873 env->vfp.pregs[i].p[j], 874 j ? ":" : eol ? "\n" : " "); 875 } 876 } 877 878 for (i = 0; i < 32; i++) { 879 if (zcr_len == 0) { 880 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 881 i, env->vfp.zregs[i].d[1], 882 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 883 } else if (zcr_len == 1) { 884 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 885 ":%016" PRIx64 ":%016" PRIx64 "\n", 886 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 887 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 888 } else { 889 for (j = zcr_len; j >= 0; j--) { 890 bool odd = (zcr_len - j) % 2 != 0; 891 if (j == zcr_len) { 892 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 893 } else if (!odd) { 894 if (j > 0) { 895 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 896 } else { 897 qemu_fprintf(f, " [%x]=", j); 898 } 899 } 900 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 901 env->vfp.zregs[i].d[j * 2 + 1], 902 env->vfp.zregs[i].d[j * 2], 903 odd || j == 0 ? "\n" : ":"); 904 } 905 } 906 } 907 } else { 908 for (i = 0; i < 32; i++) { 909 uint64_t *q = aa64_vfp_qreg(env, i); 910 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 911 i, q[1], q[0], (i & 1 ? "\n" : " ")); 912 } 913 } 914 } 915 916 #else 917 918 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 919 { 920 g_assert_not_reached(); 921 } 922 923 #endif 924 925 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 926 { 927 ARMCPU *cpu = ARM_CPU(cs); 928 CPUARMState *env = &cpu->env; 929 int i; 930 931 if (is_a64(env)) { 932 aarch64_cpu_dump_state(cs, f, flags); 933 return; 934 } 935 936 for (i = 0; i < 16; i++) { 937 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 938 if ((i % 4) == 3) { 939 qemu_fprintf(f, "\n"); 940 } else { 941 qemu_fprintf(f, " "); 942 } 943 } 944 945 if (arm_feature(env, ARM_FEATURE_M)) { 946 uint32_t xpsr = xpsr_read(env); 947 const char *mode; 948 const char *ns_status = ""; 949 950 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 951 ns_status = env->v7m.secure ? "S " : "NS "; 952 } 953 954 if (xpsr & XPSR_EXCP) { 955 mode = "handler"; 956 } else { 957 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 958 mode = "unpriv-thread"; 959 } else { 960 mode = "priv-thread"; 961 } 962 } 963 964 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 965 xpsr, 966 xpsr & XPSR_N ? 'N' : '-', 967 xpsr & XPSR_Z ? 'Z' : '-', 968 xpsr & XPSR_C ? 'C' : '-', 969 xpsr & XPSR_V ? 'V' : '-', 970 xpsr & XPSR_T ? 'T' : 'A', 971 ns_status, 972 mode); 973 } else { 974 uint32_t psr = cpsr_read(env); 975 const char *ns_status = ""; 976 977 if (arm_feature(env, ARM_FEATURE_EL3) && 978 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 979 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 980 } 981 982 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 983 psr, 984 psr & CPSR_N ? 'N' : '-', 985 psr & CPSR_Z ? 'Z' : '-', 986 psr & CPSR_C ? 'C' : '-', 987 psr & CPSR_V ? 'V' : '-', 988 psr & CPSR_T ? 'T' : 'A', 989 ns_status, 990 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 991 } 992 993 if (flags & CPU_DUMP_FPU) { 994 int numvfpregs = 0; 995 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 996 numvfpregs = 32; 997 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 998 numvfpregs = 16; 999 } 1000 for (i = 0; i < numvfpregs; i++) { 1001 uint64_t v = *aa32_vfp_dreg(env, i); 1002 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1003 i * 2, (uint32_t)v, 1004 i * 2 + 1, (uint32_t)(v >> 32), 1005 i, v); 1006 } 1007 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1008 } 1009 } 1010 1011 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 1012 { 1013 uint32_t Aff1 = idx / clustersz; 1014 uint32_t Aff0 = idx % clustersz; 1015 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1016 } 1017 1018 static void cpreg_hashtable_data_destroy(gpointer data) 1019 { 1020 /* 1021 * Destroy function for cpu->cp_regs hashtable data entries. 1022 * We must free the name string because it was g_strdup()ed in 1023 * add_cpreg_to_hashtable(). It's OK to cast away the 'const' 1024 * from r->name because we know we definitely allocated it. 1025 */ 1026 ARMCPRegInfo *r = data; 1027 1028 g_free((void *)r->name); 1029 g_free(r); 1030 } 1031 1032 static void arm_cpu_initfn(Object *obj) 1033 { 1034 ARMCPU *cpu = ARM_CPU(obj); 1035 1036 cpu_set_cpustate_pointers(cpu); 1037 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 1038 g_free, cpreg_hashtable_data_destroy); 1039 1040 QLIST_INIT(&cpu->pre_el_change_hooks); 1041 QLIST_INIT(&cpu->el_change_hooks); 1042 1043 #ifndef CONFIG_USER_ONLY 1044 /* Our inbound IRQ and FIQ lines */ 1045 if (kvm_enabled()) { 1046 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1047 * the same interface as non-KVM CPUs. 1048 */ 1049 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1050 } else { 1051 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1052 } 1053 1054 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1055 ARRAY_SIZE(cpu->gt_timer_outputs)); 1056 1057 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1058 "gicv3-maintenance-interrupt", 1); 1059 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1060 "pmu-interrupt", 1); 1061 #endif 1062 1063 /* DTB consumers generally don't in fact care what the 'compatible' 1064 * string is, so always provide some string and trust that a hypothetical 1065 * picky DTB consumer will also provide a helpful error message. 1066 */ 1067 cpu->dtb_compatible = "qemu,unknown"; 1068 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 1069 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1070 1071 if (tcg_enabled()) { 1072 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 1073 } 1074 } 1075 1076 static Property arm_cpu_gt_cntfrq_property = 1077 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1078 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1079 1080 static Property arm_cpu_reset_cbar_property = 1081 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1082 1083 static Property arm_cpu_reset_hivecs_property = 1084 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1085 1086 static Property arm_cpu_rvbar_property = 1087 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 1088 1089 #ifndef CONFIG_USER_ONLY 1090 static Property arm_cpu_has_el2_property = 1091 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1092 1093 static Property arm_cpu_has_el3_property = 1094 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1095 #endif 1096 1097 static Property arm_cpu_cfgend_property = 1098 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1099 1100 static Property arm_cpu_has_vfp_property = 1101 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1102 1103 static Property arm_cpu_has_neon_property = 1104 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1105 1106 static Property arm_cpu_has_dsp_property = 1107 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1108 1109 static Property arm_cpu_has_mpu_property = 1110 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1111 1112 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1113 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1114 * the right value for that particular CPU type, and we don't want 1115 * to override that with an incorrect constant value. 1116 */ 1117 static Property arm_cpu_pmsav7_dregion_property = 1118 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1119 pmsav7_dregion, 1120 qdev_prop_uint32, uint32_t); 1121 1122 static bool arm_get_pmu(Object *obj, Error **errp) 1123 { 1124 ARMCPU *cpu = ARM_CPU(obj); 1125 1126 return cpu->has_pmu; 1127 } 1128 1129 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1130 { 1131 ARMCPU *cpu = ARM_CPU(obj); 1132 1133 if (value) { 1134 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1135 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1136 return; 1137 } 1138 set_feature(&cpu->env, ARM_FEATURE_PMU); 1139 } else { 1140 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1141 } 1142 cpu->has_pmu = value; 1143 } 1144 1145 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1146 { 1147 /* 1148 * The exact approach to calculating guest ticks is: 1149 * 1150 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1151 * NANOSECONDS_PER_SECOND); 1152 * 1153 * We don't do that. Rather we intentionally use integer division 1154 * truncation below and in the caller for the conversion of host monotonic 1155 * time to guest ticks to provide the exact inverse for the semantics of 1156 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1157 * it loses precision when representing frequencies where 1158 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1159 * provide an exact inverse leads to scheduling timers with negative 1160 * periods, which in turn leads to sticky behaviour in the guest. 1161 * 1162 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1163 * cannot become zero. 1164 */ 1165 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1166 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1167 } 1168 1169 void arm_cpu_post_init(Object *obj) 1170 { 1171 ARMCPU *cpu = ARM_CPU(obj); 1172 1173 /* M profile implies PMSA. We have to do this here rather than 1174 * in realize with the other feature-implication checks because 1175 * we look at the PMSA bit to see if we should add some properties. 1176 */ 1177 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1178 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1179 } 1180 1181 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1182 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1183 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1184 } 1185 1186 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1187 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1188 } 1189 1190 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1191 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property); 1192 } 1193 1194 #ifndef CONFIG_USER_ONLY 1195 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1196 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1197 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1198 */ 1199 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1200 1201 object_property_add_link(obj, "secure-memory", 1202 TYPE_MEMORY_REGION, 1203 (Object **)&cpu->secure_memory, 1204 qdev_prop_allow_set_link_before_realize, 1205 OBJ_PROP_LINK_STRONG); 1206 } 1207 1208 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1209 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1210 } 1211 #endif 1212 1213 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1214 cpu->has_pmu = true; 1215 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1216 } 1217 1218 /* 1219 * Allow user to turn off VFP and Neon support, but only for TCG -- 1220 * KVM does not currently allow us to lie to the guest about its 1221 * ID/feature registers, so the guest always sees what the host has. 1222 */ 1223 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 1224 ? cpu_isar_feature(aa64_fp_simd, cpu) 1225 : cpu_isar_feature(aa32_vfp, cpu)) { 1226 cpu->has_vfp = true; 1227 if (!kvm_enabled()) { 1228 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1229 } 1230 } 1231 1232 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1233 cpu->has_neon = true; 1234 if (!kvm_enabled()) { 1235 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1236 } 1237 } 1238 1239 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1240 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1241 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1242 } 1243 1244 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1245 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1246 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1247 qdev_property_add_static(DEVICE(obj), 1248 &arm_cpu_pmsav7_dregion_property); 1249 } 1250 } 1251 1252 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1253 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1254 qdev_prop_allow_set_link_before_realize, 1255 OBJ_PROP_LINK_STRONG); 1256 /* 1257 * M profile: initial value of the Secure VTOR. We can't just use 1258 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1259 * the property to be set after realize. 1260 */ 1261 object_property_add_uint32_ptr(obj, "init-svtor", 1262 &cpu->init_svtor, 1263 OBJ_PROP_FLAG_READWRITE); 1264 } 1265 1266 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1267 1268 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1269 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1270 } 1271 1272 if (kvm_enabled()) { 1273 kvm_arm_add_vcpu_properties(obj); 1274 } 1275 1276 #ifndef CONFIG_USER_ONLY 1277 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1278 cpu_isar_feature(aa64_mte, cpu)) { 1279 object_property_add_link(obj, "tag-memory", 1280 TYPE_MEMORY_REGION, 1281 (Object **)&cpu->tag_memory, 1282 qdev_prop_allow_set_link_before_realize, 1283 OBJ_PROP_LINK_STRONG); 1284 1285 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1286 object_property_add_link(obj, "secure-tag-memory", 1287 TYPE_MEMORY_REGION, 1288 (Object **)&cpu->secure_tag_memory, 1289 qdev_prop_allow_set_link_before_realize, 1290 OBJ_PROP_LINK_STRONG); 1291 } 1292 } 1293 #endif 1294 } 1295 1296 static void arm_cpu_finalizefn(Object *obj) 1297 { 1298 ARMCPU *cpu = ARM_CPU(obj); 1299 ARMELChangeHook *hook, *next; 1300 1301 g_hash_table_destroy(cpu->cp_regs); 1302 1303 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1304 QLIST_REMOVE(hook, node); 1305 g_free(hook); 1306 } 1307 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1308 QLIST_REMOVE(hook, node); 1309 g_free(hook); 1310 } 1311 #ifndef CONFIG_USER_ONLY 1312 if (cpu->pmu_timer) { 1313 timer_free(cpu->pmu_timer); 1314 } 1315 #endif 1316 } 1317 1318 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1319 { 1320 Error *local_err = NULL; 1321 1322 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1323 arm_cpu_sve_finalize(cpu, &local_err); 1324 if (local_err != NULL) { 1325 error_propagate(errp, local_err); 1326 return; 1327 } 1328 1329 /* 1330 * KVM does not support modifications to this feature. 1331 * We have not registered the cpu properties when KVM 1332 * is in use, so the user will not be able to set them. 1333 */ 1334 if (!kvm_enabled()) { 1335 arm_cpu_pauth_finalize(cpu, &local_err); 1336 if (local_err != NULL) { 1337 error_propagate(errp, local_err); 1338 return; 1339 } 1340 } 1341 } 1342 1343 if (kvm_enabled()) { 1344 kvm_arm_steal_time_finalize(cpu, &local_err); 1345 if (local_err != NULL) { 1346 error_propagate(errp, local_err); 1347 return; 1348 } 1349 } 1350 } 1351 1352 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1353 { 1354 CPUState *cs = CPU(dev); 1355 ARMCPU *cpu = ARM_CPU(dev); 1356 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1357 CPUARMState *env = &cpu->env; 1358 int pagebits; 1359 Error *local_err = NULL; 1360 bool no_aa32 = false; 1361 1362 /* If we needed to query the host kernel for the CPU features 1363 * then it's possible that might have failed in the initfn, but 1364 * this is the first point where we can report it. 1365 */ 1366 if (cpu->host_cpu_probe_failed) { 1367 if (!kvm_enabled()) { 1368 error_setg(errp, "The 'host' CPU type can only be used with KVM"); 1369 } else { 1370 error_setg(errp, "Failed to retrieve host CPU features"); 1371 } 1372 return; 1373 } 1374 1375 #ifndef CONFIG_USER_ONLY 1376 /* The NVIC and M-profile CPU are two halves of a single piece of 1377 * hardware; trying to use one without the other is a command line 1378 * error and will result in segfaults if not caught here. 1379 */ 1380 if (arm_feature(env, ARM_FEATURE_M)) { 1381 if (!env->nvic) { 1382 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1383 return; 1384 } 1385 } else { 1386 if (env->nvic) { 1387 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1388 return; 1389 } 1390 } 1391 1392 { 1393 uint64_t scale; 1394 1395 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1396 if (!cpu->gt_cntfrq_hz) { 1397 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1398 cpu->gt_cntfrq_hz); 1399 return; 1400 } 1401 scale = gt_cntfrq_period_ns(cpu); 1402 } else { 1403 scale = GTIMER_SCALE; 1404 } 1405 1406 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1407 arm_gt_ptimer_cb, cpu); 1408 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1409 arm_gt_vtimer_cb, cpu); 1410 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1411 arm_gt_htimer_cb, cpu); 1412 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1413 arm_gt_stimer_cb, cpu); 1414 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1415 arm_gt_hvtimer_cb, cpu); 1416 } 1417 #endif 1418 1419 cpu_exec_realizefn(cs, &local_err); 1420 if (local_err != NULL) { 1421 error_propagate(errp, local_err); 1422 return; 1423 } 1424 1425 arm_cpu_finalize_features(cpu, &local_err); 1426 if (local_err != NULL) { 1427 error_propagate(errp, local_err); 1428 return; 1429 } 1430 1431 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1432 cpu->has_vfp != cpu->has_neon) { 1433 /* 1434 * This is an architectural requirement for AArch64; AArch32 is 1435 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1436 */ 1437 error_setg(errp, 1438 "AArch64 CPUs must have both VFP and Neon or neither"); 1439 return; 1440 } 1441 1442 if (!cpu->has_vfp) { 1443 uint64_t t; 1444 uint32_t u; 1445 1446 t = cpu->isar.id_aa64isar1; 1447 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1448 cpu->isar.id_aa64isar1 = t; 1449 1450 t = cpu->isar.id_aa64pfr0; 1451 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1452 cpu->isar.id_aa64pfr0 = t; 1453 1454 u = cpu->isar.id_isar6; 1455 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1456 cpu->isar.id_isar6 = u; 1457 1458 u = cpu->isar.mvfr0; 1459 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1460 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1461 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1462 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1463 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1464 if (!arm_feature(env, ARM_FEATURE_M)) { 1465 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1466 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1467 } 1468 cpu->isar.mvfr0 = u; 1469 1470 u = cpu->isar.mvfr1; 1471 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1472 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1473 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1474 if (arm_feature(env, ARM_FEATURE_M)) { 1475 u = FIELD_DP32(u, MVFR1, FP16, 0); 1476 } 1477 cpu->isar.mvfr1 = u; 1478 1479 u = cpu->isar.mvfr2; 1480 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1481 cpu->isar.mvfr2 = u; 1482 } 1483 1484 if (!cpu->has_neon) { 1485 uint64_t t; 1486 uint32_t u; 1487 1488 unset_feature(env, ARM_FEATURE_NEON); 1489 1490 t = cpu->isar.id_aa64isar0; 1491 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1492 cpu->isar.id_aa64isar0 = t; 1493 1494 t = cpu->isar.id_aa64isar1; 1495 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1496 cpu->isar.id_aa64isar1 = t; 1497 1498 t = cpu->isar.id_aa64pfr0; 1499 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1500 cpu->isar.id_aa64pfr0 = t; 1501 1502 u = cpu->isar.id_isar5; 1503 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1504 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1505 cpu->isar.id_isar5 = u; 1506 1507 u = cpu->isar.id_isar6; 1508 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1509 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1510 cpu->isar.id_isar6 = u; 1511 1512 if (!arm_feature(env, ARM_FEATURE_M)) { 1513 u = cpu->isar.mvfr1; 1514 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1515 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1516 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1517 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1518 cpu->isar.mvfr1 = u; 1519 1520 u = cpu->isar.mvfr2; 1521 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1522 cpu->isar.mvfr2 = u; 1523 } 1524 } 1525 1526 if (!cpu->has_neon && !cpu->has_vfp) { 1527 uint64_t t; 1528 uint32_t u; 1529 1530 t = cpu->isar.id_aa64isar0; 1531 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1532 cpu->isar.id_aa64isar0 = t; 1533 1534 t = cpu->isar.id_aa64isar1; 1535 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1536 cpu->isar.id_aa64isar1 = t; 1537 1538 u = cpu->isar.mvfr0; 1539 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1540 cpu->isar.mvfr0 = u; 1541 1542 /* Despite the name, this field covers both VFP and Neon */ 1543 u = cpu->isar.mvfr1; 1544 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1545 cpu->isar.mvfr1 = u; 1546 } 1547 1548 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1549 uint32_t u; 1550 1551 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1552 1553 u = cpu->isar.id_isar1; 1554 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1555 cpu->isar.id_isar1 = u; 1556 1557 u = cpu->isar.id_isar2; 1558 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1559 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1560 cpu->isar.id_isar2 = u; 1561 1562 u = cpu->isar.id_isar3; 1563 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1564 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1565 cpu->isar.id_isar3 = u; 1566 } 1567 1568 /* Some features automatically imply others: */ 1569 if (arm_feature(env, ARM_FEATURE_V8)) { 1570 if (arm_feature(env, ARM_FEATURE_M)) { 1571 set_feature(env, ARM_FEATURE_V7); 1572 } else { 1573 set_feature(env, ARM_FEATURE_V7VE); 1574 } 1575 } 1576 1577 /* 1578 * There exist AArch64 cpus without AArch32 support. When KVM 1579 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1580 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1581 * As a general principle, we also do not make ID register 1582 * consistency checks anywhere unless using TCG, because only 1583 * for TCG would a consistency-check failure be a QEMU bug. 1584 */ 1585 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1586 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1587 } 1588 1589 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1590 /* v7 Virtualization Extensions. In real hardware this implies 1591 * EL2 and also the presence of the Security Extensions. 1592 * For QEMU, for backwards-compatibility we implement some 1593 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1594 * include the various other features that V7VE implies. 1595 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1596 * Security Extensions is ARM_FEATURE_EL3. 1597 */ 1598 assert(!tcg_enabled() || no_aa32 || 1599 cpu_isar_feature(aa32_arm_div, cpu)); 1600 set_feature(env, ARM_FEATURE_LPAE); 1601 set_feature(env, ARM_FEATURE_V7); 1602 } 1603 if (arm_feature(env, ARM_FEATURE_V7)) { 1604 set_feature(env, ARM_FEATURE_VAPA); 1605 set_feature(env, ARM_FEATURE_THUMB2); 1606 set_feature(env, ARM_FEATURE_MPIDR); 1607 if (!arm_feature(env, ARM_FEATURE_M)) { 1608 set_feature(env, ARM_FEATURE_V6K); 1609 } else { 1610 set_feature(env, ARM_FEATURE_V6); 1611 } 1612 1613 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1614 * non-EL3 configs. This is needed by some legacy boards. 1615 */ 1616 set_feature(env, ARM_FEATURE_VBAR); 1617 } 1618 if (arm_feature(env, ARM_FEATURE_V6K)) { 1619 set_feature(env, ARM_FEATURE_V6); 1620 set_feature(env, ARM_FEATURE_MVFR); 1621 } 1622 if (arm_feature(env, ARM_FEATURE_V6)) { 1623 set_feature(env, ARM_FEATURE_V5); 1624 if (!arm_feature(env, ARM_FEATURE_M)) { 1625 assert(!tcg_enabled() || no_aa32 || 1626 cpu_isar_feature(aa32_jazelle, cpu)); 1627 set_feature(env, ARM_FEATURE_AUXCR); 1628 } 1629 } 1630 if (arm_feature(env, ARM_FEATURE_V5)) { 1631 set_feature(env, ARM_FEATURE_V4T); 1632 } 1633 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1634 set_feature(env, ARM_FEATURE_V7MP); 1635 } 1636 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1637 set_feature(env, ARM_FEATURE_CBAR); 1638 } 1639 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1640 !arm_feature(env, ARM_FEATURE_M)) { 1641 set_feature(env, ARM_FEATURE_THUMB_DSP); 1642 } 1643 1644 /* 1645 * We rely on no XScale CPU having VFP so we can use the same bits in the 1646 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1647 */ 1648 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1649 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1650 !arm_feature(env, ARM_FEATURE_XSCALE)); 1651 1652 if (arm_feature(env, ARM_FEATURE_V7) && 1653 !arm_feature(env, ARM_FEATURE_M) && 1654 !arm_feature(env, ARM_FEATURE_PMSA)) { 1655 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1656 * can use 4K pages. 1657 */ 1658 pagebits = 12; 1659 } else { 1660 /* For CPUs which might have tiny 1K pages, or which have an 1661 * MPU and might have small region sizes, stick with 1K pages. 1662 */ 1663 pagebits = 10; 1664 } 1665 if (!set_preferred_target_page_bits(pagebits)) { 1666 /* This can only ever happen for hotplugging a CPU, or if 1667 * the board code incorrectly creates a CPU which it has 1668 * promised via minimum_page_size that it will not. 1669 */ 1670 error_setg(errp, "This CPU requires a smaller page size than the " 1671 "system is using"); 1672 return; 1673 } 1674 1675 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1676 * We don't support setting cluster ID ([16..23]) (known as Aff2 1677 * in later ARM ARM versions), or any of the higher affinity level fields, 1678 * so these bits always RAZ. 1679 */ 1680 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1681 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1682 ARM_DEFAULT_CPUS_PER_CLUSTER); 1683 } 1684 1685 if (cpu->reset_hivecs) { 1686 cpu->reset_sctlr |= (1 << 13); 1687 } 1688 1689 if (cpu->cfgend) { 1690 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1691 cpu->reset_sctlr |= SCTLR_EE; 1692 } else { 1693 cpu->reset_sctlr |= SCTLR_B; 1694 } 1695 } 1696 1697 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 1698 /* If the has_el3 CPU property is disabled then we need to disable the 1699 * feature. 1700 */ 1701 unset_feature(env, ARM_FEATURE_EL3); 1702 1703 /* Disable the security extension feature bits in the processor feature 1704 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 1705 */ 1706 cpu->isar.id_pfr1 &= ~0xf0; 1707 cpu->isar.id_aa64pfr0 &= ~0xf000; 1708 } 1709 1710 if (!cpu->has_el2) { 1711 unset_feature(env, ARM_FEATURE_EL2); 1712 } 1713 1714 if (!cpu->has_pmu) { 1715 unset_feature(env, ARM_FEATURE_PMU); 1716 } 1717 if (arm_feature(env, ARM_FEATURE_PMU)) { 1718 pmu_init(cpu); 1719 1720 if (!kvm_enabled()) { 1721 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1722 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1723 } 1724 1725 #ifndef CONFIG_USER_ONLY 1726 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1727 cpu); 1728 #endif 1729 } else { 1730 cpu->isar.id_aa64dfr0 = 1731 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 1732 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 1733 cpu->pmceid0 = 0; 1734 cpu->pmceid1 = 0; 1735 } 1736 1737 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1738 /* Disable the hypervisor feature bits in the processor feature 1739 * registers if we don't have EL2. These are id_pfr1[15:12] and 1740 * id_aa64pfr0_el1[11:8]. 1741 */ 1742 cpu->isar.id_aa64pfr0 &= ~0xf00; 1743 cpu->isar.id_pfr1 &= ~0xf000; 1744 } 1745 1746 #ifndef CONFIG_USER_ONLY 1747 if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { 1748 /* 1749 * Disable the MTE feature bits if we do not have tag-memory 1750 * provided by the machine. 1751 */ 1752 cpu->isar.id_aa64pfr1 = 1753 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 1754 } 1755 #endif 1756 1757 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1758 * to false or by setting pmsav7-dregion to 0. 1759 */ 1760 if (!cpu->has_mpu) { 1761 cpu->pmsav7_dregion = 0; 1762 } 1763 if (cpu->pmsav7_dregion == 0) { 1764 cpu->has_mpu = false; 1765 } 1766 1767 if (arm_feature(env, ARM_FEATURE_PMSA) && 1768 arm_feature(env, ARM_FEATURE_V7)) { 1769 uint32_t nr = cpu->pmsav7_dregion; 1770 1771 if (nr > 0xff) { 1772 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1773 return; 1774 } 1775 1776 if (nr) { 1777 if (arm_feature(env, ARM_FEATURE_V8)) { 1778 /* PMSAv8 */ 1779 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1780 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1781 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1782 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1783 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1784 } 1785 } else { 1786 env->pmsav7.drbar = g_new0(uint32_t, nr); 1787 env->pmsav7.drsr = g_new0(uint32_t, nr); 1788 env->pmsav7.dracr = g_new0(uint32_t, nr); 1789 } 1790 } 1791 } 1792 1793 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1794 uint32_t nr = cpu->sau_sregion; 1795 1796 if (nr > 0xff) { 1797 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1798 return; 1799 } 1800 1801 if (nr) { 1802 env->sau.rbar = g_new0(uint32_t, nr); 1803 env->sau.rlar = g_new0(uint32_t, nr); 1804 } 1805 } 1806 1807 if (arm_feature(env, ARM_FEATURE_EL3)) { 1808 set_feature(env, ARM_FEATURE_VBAR); 1809 } 1810 1811 register_cp_regs_for_features(cpu); 1812 arm_cpu_register_gdb_regs_for_features(cpu); 1813 1814 init_cpreg_list(cpu); 1815 1816 #ifndef CONFIG_USER_ONLY 1817 MachineState *ms = MACHINE(qdev_get_machine()); 1818 unsigned int smp_cpus = ms->smp.cpus; 1819 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 1820 1821 /* 1822 * We must set cs->num_ases to the final value before 1823 * the first call to cpu_address_space_init. 1824 */ 1825 if (cpu->tag_memory != NULL) { 1826 cs->num_ases = 3 + has_secure; 1827 } else { 1828 cs->num_ases = 1 + has_secure; 1829 } 1830 1831 if (has_secure) { 1832 if (!cpu->secure_memory) { 1833 cpu->secure_memory = cs->memory; 1834 } 1835 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1836 cpu->secure_memory); 1837 } 1838 1839 if (cpu->tag_memory != NULL) { 1840 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 1841 cpu->tag_memory); 1842 if (has_secure) { 1843 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 1844 cpu->secure_tag_memory); 1845 } 1846 } 1847 1848 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1849 1850 /* No core_count specified, default to smp_cpus. */ 1851 if (cpu->core_count == -1) { 1852 cpu->core_count = smp_cpus; 1853 } 1854 #endif 1855 1856 if (tcg_enabled()) { 1857 int dcz_blocklen = 4 << cpu->dcz_blocksize; 1858 1859 /* 1860 * We only support DCZ blocklen that fits on one page. 1861 * 1862 * Architectually this is always true. However TARGET_PAGE_SIZE 1863 * is variable and, for compatibility with -machine virt-2.7, 1864 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 1865 * But even then, while the largest architectural DCZ blocklen 1866 * is 2KiB, no cpu actually uses such a large blocklen. 1867 */ 1868 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 1869 1870 /* 1871 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 1872 * both nibbles of each byte storing tag data may be written at once. 1873 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 1874 */ 1875 if (cpu_isar_feature(aa64_mte, cpu)) { 1876 assert(dcz_blocklen >= 2 * TAG_GRANULE); 1877 } 1878 } 1879 1880 qemu_init_vcpu(cs); 1881 cpu_reset(cs); 1882 1883 acc->parent_realize(dev, errp); 1884 } 1885 1886 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1887 { 1888 ObjectClass *oc; 1889 char *typename; 1890 char **cpuname; 1891 const char *cpunamestr; 1892 1893 cpuname = g_strsplit(cpu_model, ",", 1); 1894 cpunamestr = cpuname[0]; 1895 #ifdef CONFIG_USER_ONLY 1896 /* For backwards compatibility usermode emulation allows "-cpu any", 1897 * which has the same semantics as "-cpu max". 1898 */ 1899 if (!strcmp(cpunamestr, "any")) { 1900 cpunamestr = "max"; 1901 } 1902 #endif 1903 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 1904 oc = object_class_by_name(typename); 1905 g_strfreev(cpuname); 1906 g_free(typename); 1907 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 1908 object_class_is_abstract(oc)) { 1909 return NULL; 1910 } 1911 return oc; 1912 } 1913 1914 /* CPU models. These are not needed for the AArch64 linux-user build. */ 1915 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1916 1917 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1918 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1919 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1920 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1921 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1922 REGINFO_SENTINEL 1923 }; 1924 1925 static void cortex_a8_initfn(Object *obj) 1926 { 1927 ARMCPU *cpu = ARM_CPU(obj); 1928 1929 cpu->dtb_compatible = "arm,cortex-a8"; 1930 set_feature(&cpu->env, ARM_FEATURE_V7); 1931 set_feature(&cpu->env, ARM_FEATURE_NEON); 1932 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1933 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1934 set_feature(&cpu->env, ARM_FEATURE_EL3); 1935 cpu->midr = 0x410fc080; 1936 cpu->reset_fpsid = 0x410330c0; 1937 cpu->isar.mvfr0 = 0x11110222; 1938 cpu->isar.mvfr1 = 0x00011111; 1939 cpu->ctr = 0x82048004; 1940 cpu->reset_sctlr = 0x00c50078; 1941 cpu->isar.id_pfr0 = 0x1031; 1942 cpu->isar.id_pfr1 = 0x11; 1943 cpu->isar.id_dfr0 = 0x400; 1944 cpu->id_afr0 = 0; 1945 cpu->isar.id_mmfr0 = 0x31100003; 1946 cpu->isar.id_mmfr1 = 0x20000000; 1947 cpu->isar.id_mmfr2 = 0x01202000; 1948 cpu->isar.id_mmfr3 = 0x11; 1949 cpu->isar.id_isar0 = 0x00101111; 1950 cpu->isar.id_isar1 = 0x12112111; 1951 cpu->isar.id_isar2 = 0x21232031; 1952 cpu->isar.id_isar3 = 0x11112131; 1953 cpu->isar.id_isar4 = 0x00111142; 1954 cpu->isar.dbgdidr = 0x15141000; 1955 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1956 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1957 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1958 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1959 cpu->reset_auxcr = 2; 1960 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1961 } 1962 1963 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1964 /* power_control should be set to maximum latency. Again, 1965 * default to 0 and set by private hook 1966 */ 1967 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1968 .access = PL1_RW, .resetvalue = 0, 1969 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1970 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1971 .access = PL1_RW, .resetvalue = 0, 1972 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1973 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1974 .access = PL1_RW, .resetvalue = 0, 1975 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1976 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1977 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1978 /* TLB lockdown control */ 1979 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1980 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1981 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1982 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1983 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1984 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1985 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1986 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1987 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1988 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1989 REGINFO_SENTINEL 1990 }; 1991 1992 static void cortex_a9_initfn(Object *obj) 1993 { 1994 ARMCPU *cpu = ARM_CPU(obj); 1995 1996 cpu->dtb_compatible = "arm,cortex-a9"; 1997 set_feature(&cpu->env, ARM_FEATURE_V7); 1998 set_feature(&cpu->env, ARM_FEATURE_NEON); 1999 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2000 set_feature(&cpu->env, ARM_FEATURE_EL3); 2001 /* Note that A9 supports the MP extensions even for 2002 * A9UP and single-core A9MP (which are both different 2003 * and valid configurations; we don't model A9UP). 2004 */ 2005 set_feature(&cpu->env, ARM_FEATURE_V7MP); 2006 set_feature(&cpu->env, ARM_FEATURE_CBAR); 2007 cpu->midr = 0x410fc090; 2008 cpu->reset_fpsid = 0x41033090; 2009 cpu->isar.mvfr0 = 0x11110222; 2010 cpu->isar.mvfr1 = 0x01111111; 2011 cpu->ctr = 0x80038003; 2012 cpu->reset_sctlr = 0x00c50078; 2013 cpu->isar.id_pfr0 = 0x1031; 2014 cpu->isar.id_pfr1 = 0x11; 2015 cpu->isar.id_dfr0 = 0x000; 2016 cpu->id_afr0 = 0; 2017 cpu->isar.id_mmfr0 = 0x00100103; 2018 cpu->isar.id_mmfr1 = 0x20000000; 2019 cpu->isar.id_mmfr2 = 0x01230000; 2020 cpu->isar.id_mmfr3 = 0x00002111; 2021 cpu->isar.id_isar0 = 0x00101111; 2022 cpu->isar.id_isar1 = 0x13112111; 2023 cpu->isar.id_isar2 = 0x21232041; 2024 cpu->isar.id_isar3 = 0x11112131; 2025 cpu->isar.id_isar4 = 0x00111142; 2026 cpu->isar.dbgdidr = 0x35141000; 2027 cpu->clidr = (1 << 27) | (1 << 24) | 3; 2028 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 2029 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 2030 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 2031 } 2032 2033 #ifndef CONFIG_USER_ONLY 2034 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2035 { 2036 MachineState *ms = MACHINE(qdev_get_machine()); 2037 2038 /* Linux wants the number of processors from here. 2039 * Might as well set the interrupt-controller bit too. 2040 */ 2041 return ((ms->smp.cpus - 1) << 24) | (1 << 23); 2042 } 2043 #endif 2044 2045 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 2046 #ifndef CONFIG_USER_ONLY 2047 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 2048 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 2049 .writefn = arm_cp_write_ignore, }, 2050 #endif 2051 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 2052 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 2053 REGINFO_SENTINEL 2054 }; 2055 2056 static void cortex_a7_initfn(Object *obj) 2057 { 2058 ARMCPU *cpu = ARM_CPU(obj); 2059 2060 cpu->dtb_compatible = "arm,cortex-a7"; 2061 set_feature(&cpu->env, ARM_FEATURE_V7VE); 2062 set_feature(&cpu->env, ARM_FEATURE_NEON); 2063 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2064 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 2065 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2066 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 2067 set_feature(&cpu->env, ARM_FEATURE_EL2); 2068 set_feature(&cpu->env, ARM_FEATURE_EL3); 2069 set_feature(&cpu->env, ARM_FEATURE_PMU); 2070 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 2071 cpu->midr = 0x410fc075; 2072 cpu->reset_fpsid = 0x41023075; 2073 cpu->isar.mvfr0 = 0x10110222; 2074 cpu->isar.mvfr1 = 0x11111111; 2075 cpu->ctr = 0x84448003; 2076 cpu->reset_sctlr = 0x00c50078; 2077 cpu->isar.id_pfr0 = 0x00001131; 2078 cpu->isar.id_pfr1 = 0x00011011; 2079 cpu->isar.id_dfr0 = 0x02010555; 2080 cpu->id_afr0 = 0x00000000; 2081 cpu->isar.id_mmfr0 = 0x10101105; 2082 cpu->isar.id_mmfr1 = 0x40000000; 2083 cpu->isar.id_mmfr2 = 0x01240000; 2084 cpu->isar.id_mmfr3 = 0x02102211; 2085 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but 2086 * table 4-41 gives 0x02101110, which includes the arm div insns. 2087 */ 2088 cpu->isar.id_isar0 = 0x02101110; 2089 cpu->isar.id_isar1 = 0x13112111; 2090 cpu->isar.id_isar2 = 0x21232041; 2091 cpu->isar.id_isar3 = 0x11112131; 2092 cpu->isar.id_isar4 = 0x10011142; 2093 cpu->isar.dbgdidr = 0x3515f005; 2094 cpu->clidr = 0x0a200023; 2095 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 2096 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 2097 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 2098 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 2099 } 2100 2101 static void cortex_a15_initfn(Object *obj) 2102 { 2103 ARMCPU *cpu = ARM_CPU(obj); 2104 2105 cpu->dtb_compatible = "arm,cortex-a15"; 2106 set_feature(&cpu->env, ARM_FEATURE_V7VE); 2107 set_feature(&cpu->env, ARM_FEATURE_NEON); 2108 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2109 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 2110 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2111 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 2112 set_feature(&cpu->env, ARM_FEATURE_EL2); 2113 set_feature(&cpu->env, ARM_FEATURE_EL3); 2114 set_feature(&cpu->env, ARM_FEATURE_PMU); 2115 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 2116 cpu->midr = 0x412fc0f1; 2117 cpu->reset_fpsid = 0x410430f0; 2118 cpu->isar.mvfr0 = 0x10110222; 2119 cpu->isar.mvfr1 = 0x11111111; 2120 cpu->ctr = 0x8444c004; 2121 cpu->reset_sctlr = 0x00c50078; 2122 cpu->isar.id_pfr0 = 0x00001131; 2123 cpu->isar.id_pfr1 = 0x00011011; 2124 cpu->isar.id_dfr0 = 0x02010555; 2125 cpu->id_afr0 = 0x00000000; 2126 cpu->isar.id_mmfr0 = 0x10201105; 2127 cpu->isar.id_mmfr1 = 0x20000000; 2128 cpu->isar.id_mmfr2 = 0x01240000; 2129 cpu->isar.id_mmfr3 = 0x02102211; 2130 cpu->isar.id_isar0 = 0x02101110; 2131 cpu->isar.id_isar1 = 0x13112111; 2132 cpu->isar.id_isar2 = 0x21232041; 2133 cpu->isar.id_isar3 = 0x11112131; 2134 cpu->isar.id_isar4 = 0x10011142; 2135 cpu->isar.dbgdidr = 0x3515f021; 2136 cpu->clidr = 0x0a200023; 2137 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 2138 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 2139 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 2140 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 2141 } 2142 2143 #ifndef TARGET_AARCH64 2144 /* 2145 * -cpu max: a CPU with as many features enabled as our emulation supports. 2146 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; 2147 * this only needs to handle 32 bits, and need not care about KVM. 2148 */ 2149 static void arm_max_initfn(Object *obj) 2150 { 2151 ARMCPU *cpu = ARM_CPU(obj); 2152 2153 cortex_a15_initfn(obj); 2154 2155 /* old-style VFP short-vector support */ 2156 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 2157 2158 #ifdef CONFIG_USER_ONLY 2159 /* 2160 * We don't set these in system emulation mode for the moment, 2161 * since we don't correctly set (all of) the ID registers to 2162 * advertise them. 2163 */ 2164 set_feature(&cpu->env, ARM_FEATURE_V8); 2165 { 2166 uint32_t t; 2167 2168 t = cpu->isar.id_isar5; 2169 t = FIELD_DP32(t, ID_ISAR5, AES, 2); 2170 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); 2171 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); 2172 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); 2173 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); 2174 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); 2175 cpu->isar.id_isar5 = t; 2176 2177 t = cpu->isar.id_isar6; 2178 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); 2179 t = FIELD_DP32(t, ID_ISAR6, DP, 1); 2180 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); 2181 t = FIELD_DP32(t, ID_ISAR6, SB, 1); 2182 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); 2183 cpu->isar.id_isar6 = t; 2184 2185 t = cpu->isar.mvfr1; 2186 t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ 2187 t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ 2188 cpu->isar.mvfr1 = t; 2189 2190 t = cpu->isar.mvfr2; 2191 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ 2192 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ 2193 cpu->isar.mvfr2 = t; 2194 2195 t = cpu->isar.id_mmfr3; 2196 t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ 2197 cpu->isar.id_mmfr3 = t; 2198 2199 t = cpu->isar.id_mmfr4; 2200 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ 2201 t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ 2202 t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ 2203 t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ 2204 cpu->isar.id_mmfr4 = t; 2205 } 2206 #endif 2207 } 2208 #endif 2209 2210 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 2211 2212 static const ARMCPUInfo arm_cpus[] = { 2213 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 2214 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 2215 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 2216 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 2217 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 2218 #ifndef TARGET_AARCH64 2219 { .name = "max", .initfn = arm_max_initfn }, 2220 #endif 2221 #ifdef CONFIG_USER_ONLY 2222 { .name = "any", .initfn = arm_max_initfn }, 2223 #endif 2224 #endif 2225 }; 2226 2227 static Property arm_cpu_properties[] = { 2228 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 2229 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2230 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2231 mp_affinity, ARM64_AFFINITY_INVALID), 2232 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2233 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2234 DEFINE_PROP_END_OF_LIST() 2235 }; 2236 2237 static gchar *arm_gdb_arch_name(CPUState *cs) 2238 { 2239 ARMCPU *cpu = ARM_CPU(cs); 2240 CPUARMState *env = &cpu->env; 2241 2242 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2243 return g_strdup("iwmmxt"); 2244 } 2245 return g_strdup("arm"); 2246 } 2247 2248 #ifdef CONFIG_TCG 2249 static struct TCGCPUOps arm_tcg_ops = { 2250 .initialize = arm_translate_init, 2251 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2252 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2253 .tlb_fill = arm_cpu_tlb_fill, 2254 .debug_excp_handler = arm_debug_excp_handler, 2255 2256 #if !defined(CONFIG_USER_ONLY) 2257 .do_interrupt = arm_cpu_do_interrupt, 2258 .do_transaction_failed = arm_cpu_do_transaction_failed, 2259 .do_unaligned_access = arm_cpu_do_unaligned_access, 2260 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2261 .debug_check_watchpoint = arm_debug_check_watchpoint, 2262 #endif /* !CONFIG_USER_ONLY */ 2263 }; 2264 #endif /* CONFIG_TCG */ 2265 2266 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2267 { 2268 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2269 CPUClass *cc = CPU_CLASS(acc); 2270 DeviceClass *dc = DEVICE_CLASS(oc); 2271 2272 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2273 &acc->parent_realize); 2274 2275 device_class_set_props(dc, arm_cpu_properties); 2276 device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); 2277 2278 cc->class_by_name = arm_cpu_class_by_name; 2279 cc->has_work = arm_cpu_has_work; 2280 cc->dump_state = arm_cpu_dump_state; 2281 cc->set_pc = arm_cpu_set_pc; 2282 cc->gdb_read_register = arm_cpu_gdb_read_register; 2283 cc->gdb_write_register = arm_cpu_gdb_write_register; 2284 #ifndef CONFIG_USER_ONLY 2285 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 2286 cc->asidx_from_attrs = arm_asidx_from_attrs; 2287 cc->vmsd = &vmstate_arm_cpu; 2288 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 2289 cc->write_elf64_note = arm_cpu_write_elf64_note; 2290 cc->write_elf32_note = arm_cpu_write_elf32_note; 2291 #endif 2292 cc->gdb_num_core_regs = 26; 2293 cc->gdb_core_xml_file = "arm-core.xml"; 2294 cc->gdb_arch_name = arm_gdb_arch_name; 2295 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2296 cc->gdb_stop_before_watchpoint = true; 2297 cc->disas_set_info = arm_disas_set_info; 2298 2299 #ifdef CONFIG_TCG 2300 cc->tcg_ops = &arm_tcg_ops; 2301 #endif /* CONFIG_TCG */ 2302 } 2303 2304 #ifdef CONFIG_KVM 2305 static void arm_host_initfn(Object *obj) 2306 { 2307 ARMCPU *cpu = ARM_CPU(obj); 2308 2309 kvm_arm_set_cpu_features_from_host(cpu); 2310 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 2311 aarch64_add_sve_properties(obj); 2312 } 2313 arm_cpu_post_init(obj); 2314 } 2315 2316 static const TypeInfo host_arm_cpu_type_info = { 2317 .name = TYPE_ARM_HOST_CPU, 2318 .parent = TYPE_AARCH64_CPU, 2319 .instance_init = arm_host_initfn, 2320 }; 2321 2322 #endif 2323 2324 static void arm_cpu_instance_init(Object *obj) 2325 { 2326 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2327 2328 acc->info->initfn(obj); 2329 arm_cpu_post_init(obj); 2330 } 2331 2332 static void cpu_register_class_init(ObjectClass *oc, void *data) 2333 { 2334 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2335 2336 acc->info = data; 2337 } 2338 2339 void arm_cpu_register(const ARMCPUInfo *info) 2340 { 2341 TypeInfo type_info = { 2342 .parent = TYPE_ARM_CPU, 2343 .instance_size = sizeof(ARMCPU), 2344 .instance_align = __alignof__(ARMCPU), 2345 .instance_init = arm_cpu_instance_init, 2346 .class_size = sizeof(ARMCPUClass), 2347 .class_init = info->class_init ?: cpu_register_class_init, 2348 .class_data = (void *)info, 2349 }; 2350 2351 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2352 type_register(&type_info); 2353 g_free((void *)type_info.name); 2354 } 2355 2356 static const TypeInfo arm_cpu_type_info = { 2357 .name = TYPE_ARM_CPU, 2358 .parent = TYPE_CPU, 2359 .instance_size = sizeof(ARMCPU), 2360 .instance_align = __alignof__(ARMCPU), 2361 .instance_init = arm_cpu_initfn, 2362 .instance_finalize = arm_cpu_finalizefn, 2363 .abstract = true, 2364 .class_size = sizeof(ARMCPUClass), 2365 .class_init = arm_cpu_class_init, 2366 }; 2367 2368 static const TypeInfo idau_interface_type_info = { 2369 .name = TYPE_IDAU_INTERFACE, 2370 .parent = TYPE_INTERFACE, 2371 .class_size = sizeof(IDAUInterfaceClass), 2372 }; 2373 2374 static void arm_cpu_register_types(void) 2375 { 2376 const size_t cpu_count = ARRAY_SIZE(arm_cpus); 2377 2378 type_register_static(&arm_cpu_type_info); 2379 2380 #ifdef CONFIG_KVM 2381 type_register_static(&host_arm_cpu_type_info); 2382 #endif 2383 2384 if (cpu_count) { 2385 size_t i; 2386 2387 type_register_static(&idau_interface_type_info); 2388 for (i = 0; i < cpu_count; ++i) { 2389 arm_cpu_register(&arm_cpus[i]); 2390 } 2391 } 2392 } 2393 2394 type_init(arm_cpu_register_types) 2395