1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu-common.h" 24 #include "target/arm/idau.h" 25 #include "qemu/module.h" 26 #include "qapi/error.h" 27 #include "qapi/visitor.h" 28 #include "cpu.h" 29 #include "internals.h" 30 #include "exec/exec-all.h" 31 #include "hw/qdev-properties.h" 32 #if !defined(CONFIG_USER_ONLY) 33 #include "hw/loader.h" 34 #include "hw/boards.h" 35 #endif 36 #include "sysemu/sysemu.h" 37 #include "sysemu/tcg.h" 38 #include "sysemu/hw_accel.h" 39 #include "kvm_arm.h" 40 #include "disas/capstone.h" 41 #include "fpu/softfloat.h" 42 43 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 44 { 45 ARMCPU *cpu = ARM_CPU(cs); 46 CPUARMState *env = &cpu->env; 47 48 if (is_a64(env)) { 49 env->pc = value; 50 env->thumb = 0; 51 } else { 52 env->regs[15] = value & ~1; 53 env->thumb = value & 1; 54 } 55 } 56 57 static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 58 { 59 ARMCPU *cpu = ARM_CPU(cs); 60 CPUARMState *env = &cpu->env; 61 62 /* 63 * It's OK to look at env for the current mode here, because it's 64 * never possible for an AArch64 TB to chain to an AArch32 TB. 65 */ 66 if (is_a64(env)) { 67 env->pc = tb->pc; 68 } else { 69 env->regs[15] = tb->pc; 70 } 71 } 72 73 static bool arm_cpu_has_work(CPUState *cs) 74 { 75 ARMCPU *cpu = ARM_CPU(cs); 76 77 return (cpu->power_state != PSCI_OFF) 78 && cs->interrupt_request & 79 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 80 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 81 | CPU_INTERRUPT_EXITTB); 82 } 83 84 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 85 void *opaque) 86 { 87 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 88 89 entry->hook = hook; 90 entry->opaque = opaque; 91 92 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 93 } 94 95 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 96 void *opaque) 97 { 98 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 99 100 entry->hook = hook; 101 entry->opaque = opaque; 102 103 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 104 } 105 106 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 107 { 108 /* Reset a single ARMCPRegInfo register */ 109 ARMCPRegInfo *ri = value; 110 ARMCPU *cpu = opaque; 111 112 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 113 return; 114 } 115 116 if (ri->resetfn) { 117 ri->resetfn(&cpu->env, ri); 118 return; 119 } 120 121 /* A zero offset is never possible as it would be regs[0] 122 * so we use it to indicate that reset is being handled elsewhere. 123 * This is basically only used for fields in non-core coprocessors 124 * (like the pxa2xx ones). 125 */ 126 if (!ri->fieldoffset) { 127 return; 128 } 129 130 if (cpreg_field_is_64bit(ri)) { 131 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 132 } else { 133 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 134 } 135 } 136 137 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 138 { 139 /* Purely an assertion check: we've already done reset once, 140 * so now check that running the reset for the cpreg doesn't 141 * change its value. This traps bugs where two different cpregs 142 * both try to reset the same state field but to different values. 143 */ 144 ARMCPRegInfo *ri = value; 145 ARMCPU *cpu = opaque; 146 uint64_t oldvalue, newvalue; 147 148 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 149 return; 150 } 151 152 oldvalue = read_raw_cp_reg(&cpu->env, ri); 153 cp_reg_reset(key, value, opaque); 154 newvalue = read_raw_cp_reg(&cpu->env, ri); 155 assert(oldvalue == newvalue); 156 } 157 158 static void arm_cpu_reset(DeviceState *dev) 159 { 160 CPUState *s = CPU(dev); 161 ARMCPU *cpu = ARM_CPU(s); 162 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 163 CPUARMState *env = &cpu->env; 164 165 acc->parent_reset(dev); 166 167 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 168 169 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 170 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 171 172 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 173 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 174 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 175 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 176 177 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 178 s->halted = cpu->start_powered_off; 179 180 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 181 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 182 } 183 184 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 185 /* 64 bit CPUs always start in 64 bit mode */ 186 env->aarch64 = 1; 187 #if defined(CONFIG_USER_ONLY) 188 env->pstate = PSTATE_MODE_EL0t; 189 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 190 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 191 /* Enable all PAC keys. */ 192 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 193 SCTLR_EnDA | SCTLR_EnDB); 194 /* and to the FP/Neon instructions */ 195 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 196 /* and to the SVE instructions */ 197 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 198 /* with maximum vector length */ 199 env->vfp.zcr_el[1] = cpu_isar_feature(aa64_sve, cpu) ? 200 cpu->sve_max_vq - 1 : 0; 201 /* 202 * Enable TBI0 and TBI1. While the real kernel only enables TBI0, 203 * turning on both here will produce smaller code and otherwise 204 * make no difference to the user-level emulation. 205 */ 206 env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); 207 #else 208 /* Reset into the highest available EL */ 209 if (arm_feature(env, ARM_FEATURE_EL3)) { 210 env->pstate = PSTATE_MODE_EL3h; 211 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 212 env->pstate = PSTATE_MODE_EL2h; 213 } else { 214 env->pstate = PSTATE_MODE_EL1h; 215 } 216 env->pc = cpu->rvbar; 217 #endif 218 } else { 219 #if defined(CONFIG_USER_ONLY) 220 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 221 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 222 #endif 223 } 224 225 #if defined(CONFIG_USER_ONLY) 226 env->uncached_cpsr = ARM_CPU_MODE_USR; 227 /* For user mode we must enable access to coprocessors */ 228 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 229 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 230 env->cp15.c15_cpar = 3; 231 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 232 env->cp15.c15_cpar = 1; 233 } 234 #else 235 236 /* 237 * If the highest available EL is EL2, AArch32 will start in Hyp 238 * mode; otherwise it starts in SVC. Note that if we start in 239 * AArch64 then these values in the uncached_cpsr will be ignored. 240 */ 241 if (arm_feature(env, ARM_FEATURE_EL2) && 242 !arm_feature(env, ARM_FEATURE_EL3)) { 243 env->uncached_cpsr = ARM_CPU_MODE_HYP; 244 } else { 245 env->uncached_cpsr = ARM_CPU_MODE_SVC; 246 } 247 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 248 249 if (arm_feature(env, ARM_FEATURE_M)) { 250 uint32_t initial_msp; /* Loaded from 0x0 */ 251 uint32_t initial_pc; /* Loaded from 0x4 */ 252 uint8_t *rom; 253 uint32_t vecbase; 254 255 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 256 env->v7m.secure = true; 257 } else { 258 /* This bit resets to 0 if security is supported, but 1 if 259 * it is not. The bit is not present in v7M, but we set it 260 * here so we can avoid having to make checks on it conditional 261 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 262 */ 263 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 264 /* 265 * Set NSACR to indicate "NS access permitted to everything"; 266 * this avoids having to have all the tests of it being 267 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 268 * v8.1M the guest-visible value of NSACR in a CPU without the 269 * Security Extension is 0xcff. 270 */ 271 env->v7m.nsacr = 0xcff; 272 } 273 274 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 275 * that it resets to 1, so QEMU always does that rather than making 276 * it dependent on CPU model. In v8M it is RES1. 277 */ 278 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 279 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 280 if (arm_feature(env, ARM_FEATURE_V8)) { 281 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 282 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 283 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 284 } 285 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 286 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 287 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 288 } 289 290 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 291 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 292 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 293 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 294 } 295 /* Unlike A/R profile, M profile defines the reset LR value */ 296 env->regs[14] = 0xffffffff; 297 298 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 299 300 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 301 vecbase = env->v7m.vecbase[env->v7m.secure]; 302 rom = rom_ptr(vecbase, 8); 303 if (rom) { 304 /* Address zero is covered by ROM which hasn't yet been 305 * copied into physical memory. 306 */ 307 initial_msp = ldl_p(rom); 308 initial_pc = ldl_p(rom + 4); 309 } else { 310 /* Address zero not covered by a ROM blob, or the ROM blob 311 * is in non-modifiable memory and this is a second reset after 312 * it got copied into memory. In the latter case, rom_ptr 313 * will return a NULL pointer and we should use ldl_phys instead. 314 */ 315 initial_msp = ldl_phys(s->as, vecbase); 316 initial_pc = ldl_phys(s->as, vecbase + 4); 317 } 318 319 env->regs[13] = initial_msp & 0xFFFFFFFC; 320 env->regs[15] = initial_pc & ~1; 321 env->thumb = initial_pc & 1; 322 } 323 324 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 325 * executing as AArch32 then check if highvecs are enabled and 326 * adjust the PC accordingly. 327 */ 328 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 329 env->regs[15] = 0xFFFF0000; 330 } 331 332 /* M profile requires that reset clears the exclusive monitor; 333 * A profile does not, but clearing it makes more sense than having it 334 * set with an exclusive access on address zero. 335 */ 336 arm_clear_exclusive(env); 337 338 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 339 #endif 340 341 if (arm_feature(env, ARM_FEATURE_PMSA)) { 342 if (cpu->pmsav7_dregion > 0) { 343 if (arm_feature(env, ARM_FEATURE_V8)) { 344 memset(env->pmsav8.rbar[M_REG_NS], 0, 345 sizeof(*env->pmsav8.rbar[M_REG_NS]) 346 * cpu->pmsav7_dregion); 347 memset(env->pmsav8.rlar[M_REG_NS], 0, 348 sizeof(*env->pmsav8.rlar[M_REG_NS]) 349 * cpu->pmsav7_dregion); 350 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 351 memset(env->pmsav8.rbar[M_REG_S], 0, 352 sizeof(*env->pmsav8.rbar[M_REG_S]) 353 * cpu->pmsav7_dregion); 354 memset(env->pmsav8.rlar[M_REG_S], 0, 355 sizeof(*env->pmsav8.rlar[M_REG_S]) 356 * cpu->pmsav7_dregion); 357 } 358 } else if (arm_feature(env, ARM_FEATURE_V7)) { 359 memset(env->pmsav7.drbar, 0, 360 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 361 memset(env->pmsav7.drsr, 0, 362 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 363 memset(env->pmsav7.dracr, 0, 364 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 365 } 366 } 367 env->pmsav7.rnr[M_REG_NS] = 0; 368 env->pmsav7.rnr[M_REG_S] = 0; 369 env->pmsav8.mair0[M_REG_NS] = 0; 370 env->pmsav8.mair0[M_REG_S] = 0; 371 env->pmsav8.mair1[M_REG_NS] = 0; 372 env->pmsav8.mair1[M_REG_S] = 0; 373 } 374 375 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 376 if (cpu->sau_sregion > 0) { 377 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 378 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 379 } 380 env->sau.rnr = 0; 381 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 382 * the Cortex-M33 does. 383 */ 384 env->sau.ctrl = 0; 385 } 386 387 set_flush_to_zero(1, &env->vfp.standard_fp_status); 388 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 389 set_default_nan_mode(1, &env->vfp.standard_fp_status); 390 set_float_detect_tininess(float_tininess_before_rounding, 391 &env->vfp.fp_status); 392 set_float_detect_tininess(float_tininess_before_rounding, 393 &env->vfp.standard_fp_status); 394 set_float_detect_tininess(float_tininess_before_rounding, 395 &env->vfp.fp_status_f16); 396 #ifndef CONFIG_USER_ONLY 397 if (kvm_enabled()) { 398 kvm_arm_reset_vcpu(cpu); 399 } 400 #endif 401 402 hw_breakpoint_update_all(cpu); 403 hw_watchpoint_update_all(cpu); 404 arm_rebuild_hflags(env); 405 } 406 407 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 408 unsigned int target_el, 409 unsigned int cur_el, bool secure, 410 uint64_t hcr_el2) 411 { 412 CPUARMState *env = cs->env_ptr; 413 bool pstate_unmasked; 414 bool unmasked = false; 415 416 /* 417 * Don't take exceptions if they target a lower EL. 418 * This check should catch any exceptions that would not be taken 419 * but left pending. 420 */ 421 if (cur_el > target_el) { 422 return false; 423 } 424 425 switch (excp_idx) { 426 case EXCP_FIQ: 427 pstate_unmasked = !(env->daif & PSTATE_F); 428 break; 429 430 case EXCP_IRQ: 431 pstate_unmasked = !(env->daif & PSTATE_I); 432 break; 433 434 case EXCP_VFIQ: 435 if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 436 /* VFIQs are only taken when hypervized and non-secure. */ 437 return false; 438 } 439 return !(env->daif & PSTATE_F); 440 case EXCP_VIRQ: 441 if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 442 /* VIRQs are only taken when hypervized and non-secure. */ 443 return false; 444 } 445 return !(env->daif & PSTATE_I); 446 default: 447 g_assert_not_reached(); 448 } 449 450 /* 451 * Use the target EL, current execution state and SCR/HCR settings to 452 * determine whether the corresponding CPSR bit is used to mask the 453 * interrupt. 454 */ 455 if ((target_el > cur_el) && (target_el != 1)) { 456 /* Exceptions targeting a higher EL may not be maskable */ 457 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 458 /* 459 * 64-bit masking rules are simple: exceptions to EL3 460 * can't be masked, and exceptions to EL2 can only be 461 * masked from Secure state. The HCR and SCR settings 462 * don't affect the masking logic, only the interrupt routing. 463 */ 464 if (target_el == 3 || !secure) { 465 unmasked = true; 466 } 467 } else { 468 /* 469 * The old 32-bit-only environment has a more complicated 470 * masking setup. HCR and SCR bits not only affect interrupt 471 * routing but also change the behaviour of masking. 472 */ 473 bool hcr, scr; 474 475 switch (excp_idx) { 476 case EXCP_FIQ: 477 /* 478 * If FIQs are routed to EL3 or EL2 then there are cases where 479 * we override the CPSR.F in determining if the exception is 480 * masked or not. If neither of these are set then we fall back 481 * to the CPSR.F setting otherwise we further assess the state 482 * below. 483 */ 484 hcr = hcr_el2 & HCR_FMO; 485 scr = (env->cp15.scr_el3 & SCR_FIQ); 486 487 /* 488 * When EL3 is 32-bit, the SCR.FW bit controls whether the 489 * CPSR.F bit masks FIQ interrupts when taken in non-secure 490 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 491 * when non-secure but only when FIQs are only routed to EL3. 492 */ 493 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 494 break; 495 case EXCP_IRQ: 496 /* 497 * When EL3 execution state is 32-bit, if HCR.IMO is set then 498 * we may override the CPSR.I masking when in non-secure state. 499 * The SCR.IRQ setting has already been taken into consideration 500 * when setting the target EL, so it does not have a further 501 * affect here. 502 */ 503 hcr = hcr_el2 & HCR_IMO; 504 scr = false; 505 break; 506 default: 507 g_assert_not_reached(); 508 } 509 510 if ((scr || hcr) && !secure) { 511 unmasked = true; 512 } 513 } 514 } 515 516 /* 517 * The PSTATE bits only mask the interrupt if we have not overriden the 518 * ability above. 519 */ 520 return unmasked || pstate_unmasked; 521 } 522 523 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 524 { 525 CPUClass *cc = CPU_GET_CLASS(cs); 526 CPUARMState *env = cs->env_ptr; 527 uint32_t cur_el = arm_current_el(env); 528 bool secure = arm_is_secure(env); 529 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 530 uint32_t target_el; 531 uint32_t excp_idx; 532 533 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 534 535 if (interrupt_request & CPU_INTERRUPT_FIQ) { 536 excp_idx = EXCP_FIQ; 537 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 538 if (arm_excp_unmasked(cs, excp_idx, target_el, 539 cur_el, secure, hcr_el2)) { 540 goto found; 541 } 542 } 543 if (interrupt_request & CPU_INTERRUPT_HARD) { 544 excp_idx = EXCP_IRQ; 545 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 546 if (arm_excp_unmasked(cs, excp_idx, target_el, 547 cur_el, secure, hcr_el2)) { 548 goto found; 549 } 550 } 551 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 552 excp_idx = EXCP_VIRQ; 553 target_el = 1; 554 if (arm_excp_unmasked(cs, excp_idx, target_el, 555 cur_el, secure, hcr_el2)) { 556 goto found; 557 } 558 } 559 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 560 excp_idx = EXCP_VFIQ; 561 target_el = 1; 562 if (arm_excp_unmasked(cs, excp_idx, target_el, 563 cur_el, secure, hcr_el2)) { 564 goto found; 565 } 566 } 567 return false; 568 569 found: 570 cs->exception_index = excp_idx; 571 env->exception.target_el = target_el; 572 cc->do_interrupt(cs); 573 return true; 574 } 575 576 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 577 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 578 { 579 CPUClass *cc = CPU_GET_CLASS(cs); 580 ARMCPU *cpu = ARM_CPU(cs); 581 CPUARMState *env = &cpu->env; 582 bool ret = false; 583 584 /* ARMv7-M interrupt masking works differently than -A or -R. 585 * There is no FIQ/IRQ distinction. Instead of I and F bits 586 * masking FIQ and IRQ interrupts, an exception is taken only 587 * if it is higher priority than the current execution priority 588 * (which depends on state like BASEPRI, FAULTMASK and the 589 * currently active exception). 590 */ 591 if (interrupt_request & CPU_INTERRUPT_HARD 592 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 593 cs->exception_index = EXCP_IRQ; 594 cc->do_interrupt(cs); 595 ret = true; 596 } 597 return ret; 598 } 599 #endif 600 601 void arm_cpu_update_virq(ARMCPU *cpu) 602 { 603 /* 604 * Update the interrupt level for VIRQ, which is the logical OR of 605 * the HCR_EL2.VI bit and the input line level from the GIC. 606 */ 607 CPUARMState *env = &cpu->env; 608 CPUState *cs = CPU(cpu); 609 610 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 611 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 612 613 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 614 if (new_state) { 615 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 616 } else { 617 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 618 } 619 } 620 } 621 622 void arm_cpu_update_vfiq(ARMCPU *cpu) 623 { 624 /* 625 * Update the interrupt level for VFIQ, which is the logical OR of 626 * the HCR_EL2.VF bit and the input line level from the GIC. 627 */ 628 CPUARMState *env = &cpu->env; 629 CPUState *cs = CPU(cpu); 630 631 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 632 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 633 634 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 635 if (new_state) { 636 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 637 } else { 638 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 639 } 640 } 641 } 642 643 #ifndef CONFIG_USER_ONLY 644 static void arm_cpu_set_irq(void *opaque, int irq, int level) 645 { 646 ARMCPU *cpu = opaque; 647 CPUARMState *env = &cpu->env; 648 CPUState *cs = CPU(cpu); 649 static const int mask[] = { 650 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 651 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 652 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 653 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 654 }; 655 656 if (level) { 657 env->irq_line_state |= mask[irq]; 658 } else { 659 env->irq_line_state &= ~mask[irq]; 660 } 661 662 switch (irq) { 663 case ARM_CPU_VIRQ: 664 assert(arm_feature(env, ARM_FEATURE_EL2)); 665 arm_cpu_update_virq(cpu); 666 break; 667 case ARM_CPU_VFIQ: 668 assert(arm_feature(env, ARM_FEATURE_EL2)); 669 arm_cpu_update_vfiq(cpu); 670 break; 671 case ARM_CPU_IRQ: 672 case ARM_CPU_FIQ: 673 if (level) { 674 cpu_interrupt(cs, mask[irq]); 675 } else { 676 cpu_reset_interrupt(cs, mask[irq]); 677 } 678 break; 679 default: 680 g_assert_not_reached(); 681 } 682 } 683 684 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 685 { 686 #ifdef CONFIG_KVM 687 ARMCPU *cpu = opaque; 688 CPUARMState *env = &cpu->env; 689 CPUState *cs = CPU(cpu); 690 uint32_t linestate_bit; 691 int irq_id; 692 693 switch (irq) { 694 case ARM_CPU_IRQ: 695 irq_id = KVM_ARM_IRQ_CPU_IRQ; 696 linestate_bit = CPU_INTERRUPT_HARD; 697 break; 698 case ARM_CPU_FIQ: 699 irq_id = KVM_ARM_IRQ_CPU_FIQ; 700 linestate_bit = CPU_INTERRUPT_FIQ; 701 break; 702 default: 703 g_assert_not_reached(); 704 } 705 706 if (level) { 707 env->irq_line_state |= linestate_bit; 708 } else { 709 env->irq_line_state &= ~linestate_bit; 710 } 711 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 712 #endif 713 } 714 715 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 716 { 717 ARMCPU *cpu = ARM_CPU(cs); 718 CPUARMState *env = &cpu->env; 719 720 cpu_synchronize_state(cs); 721 return arm_cpu_data_is_big_endian(env); 722 } 723 724 #endif 725 726 static inline void set_feature(CPUARMState *env, int feature) 727 { 728 env->features |= 1ULL << feature; 729 } 730 731 static inline void unset_feature(CPUARMState *env, int feature) 732 { 733 env->features &= ~(1ULL << feature); 734 } 735 736 static int 737 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 738 { 739 return print_insn_arm(pc | 1, info); 740 } 741 742 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 743 { 744 ARMCPU *ac = ARM_CPU(cpu); 745 CPUARMState *env = &ac->env; 746 bool sctlr_b; 747 748 if (is_a64(env)) { 749 /* We might not be compiled with the A64 disassembler 750 * because it needs a C++ compiler. Leave print_insn 751 * unset in this case to use the caller default behaviour. 752 */ 753 #if defined(CONFIG_ARM_A64_DIS) 754 info->print_insn = print_insn_arm_a64; 755 #endif 756 info->cap_arch = CS_ARCH_ARM64; 757 info->cap_insn_unit = 4; 758 info->cap_insn_split = 4; 759 } else { 760 int cap_mode; 761 if (env->thumb) { 762 info->print_insn = print_insn_thumb1; 763 info->cap_insn_unit = 2; 764 info->cap_insn_split = 4; 765 cap_mode = CS_MODE_THUMB; 766 } else { 767 info->print_insn = print_insn_arm; 768 info->cap_insn_unit = 4; 769 info->cap_insn_split = 4; 770 cap_mode = CS_MODE_ARM; 771 } 772 if (arm_feature(env, ARM_FEATURE_V8)) { 773 cap_mode |= CS_MODE_V8; 774 } 775 if (arm_feature(env, ARM_FEATURE_M)) { 776 cap_mode |= CS_MODE_MCLASS; 777 } 778 info->cap_arch = CS_ARCH_ARM; 779 info->cap_mode = cap_mode; 780 } 781 782 sctlr_b = arm_sctlr_b(env); 783 if (bswap_code(sctlr_b)) { 784 #ifdef TARGET_WORDS_BIGENDIAN 785 info->endian = BFD_ENDIAN_LITTLE; 786 #else 787 info->endian = BFD_ENDIAN_BIG; 788 #endif 789 } 790 info->flags &= ~INSN_ARM_BE32; 791 #ifndef CONFIG_USER_ONLY 792 if (sctlr_b) { 793 info->flags |= INSN_ARM_BE32; 794 } 795 #endif 796 } 797 798 #ifdef TARGET_AARCH64 799 800 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 801 { 802 ARMCPU *cpu = ARM_CPU(cs); 803 CPUARMState *env = &cpu->env; 804 uint32_t psr = pstate_read(env); 805 int i; 806 int el = arm_current_el(env); 807 const char *ns_status; 808 809 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 810 for (i = 0; i < 32; i++) { 811 if (i == 31) { 812 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 813 } else { 814 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 815 (i + 2) % 3 ? " " : "\n"); 816 } 817 } 818 819 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 820 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 821 } else { 822 ns_status = ""; 823 } 824 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 825 psr, 826 psr & PSTATE_N ? 'N' : '-', 827 psr & PSTATE_Z ? 'Z' : '-', 828 psr & PSTATE_C ? 'C' : '-', 829 psr & PSTATE_V ? 'V' : '-', 830 ns_status, 831 el, 832 psr & PSTATE_SP ? 'h' : 't'); 833 834 if (cpu_isar_feature(aa64_bti, cpu)) { 835 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 836 } 837 if (!(flags & CPU_DUMP_FPU)) { 838 qemu_fprintf(f, "\n"); 839 return; 840 } 841 if (fp_exception_el(env, el) != 0) { 842 qemu_fprintf(f, " FPU disabled\n"); 843 return; 844 } 845 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 846 vfp_get_fpcr(env), vfp_get_fpsr(env)); 847 848 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { 849 int j, zcr_len = sve_zcr_len_for_el(env, el); 850 851 for (i = 0; i <= FFR_PRED_NUM; i++) { 852 bool eol; 853 if (i == FFR_PRED_NUM) { 854 qemu_fprintf(f, "FFR="); 855 /* It's last, so end the line. */ 856 eol = true; 857 } else { 858 qemu_fprintf(f, "P%02d=", i); 859 switch (zcr_len) { 860 case 0: 861 eol = i % 8 == 7; 862 break; 863 case 1: 864 eol = i % 6 == 5; 865 break; 866 case 2: 867 case 3: 868 eol = i % 3 == 2; 869 break; 870 default: 871 /* More than one quadword per predicate. */ 872 eol = true; 873 break; 874 } 875 } 876 for (j = zcr_len / 4; j >= 0; j--) { 877 int digits; 878 if (j * 4 + 4 <= zcr_len + 1) { 879 digits = 16; 880 } else { 881 digits = (zcr_len % 4 + 1) * 4; 882 } 883 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 884 env->vfp.pregs[i].p[j], 885 j ? ":" : eol ? "\n" : " "); 886 } 887 } 888 889 for (i = 0; i < 32; i++) { 890 if (zcr_len == 0) { 891 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 892 i, env->vfp.zregs[i].d[1], 893 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 894 } else if (zcr_len == 1) { 895 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 896 ":%016" PRIx64 ":%016" PRIx64 "\n", 897 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 898 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 899 } else { 900 for (j = zcr_len; j >= 0; j--) { 901 bool odd = (zcr_len - j) % 2 != 0; 902 if (j == zcr_len) { 903 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 904 } else if (!odd) { 905 if (j > 0) { 906 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 907 } else { 908 qemu_fprintf(f, " [%x]=", j); 909 } 910 } 911 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 912 env->vfp.zregs[i].d[j * 2 + 1], 913 env->vfp.zregs[i].d[j * 2], 914 odd || j == 0 ? "\n" : ":"); 915 } 916 } 917 } 918 } else { 919 for (i = 0; i < 32; i++) { 920 uint64_t *q = aa64_vfp_qreg(env, i); 921 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 922 i, q[1], q[0], (i & 1 ? "\n" : " ")); 923 } 924 } 925 } 926 927 #else 928 929 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 930 { 931 g_assert_not_reached(); 932 } 933 934 #endif 935 936 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 937 { 938 ARMCPU *cpu = ARM_CPU(cs); 939 CPUARMState *env = &cpu->env; 940 int i; 941 942 if (is_a64(env)) { 943 aarch64_cpu_dump_state(cs, f, flags); 944 return; 945 } 946 947 for (i = 0; i < 16; i++) { 948 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 949 if ((i % 4) == 3) { 950 qemu_fprintf(f, "\n"); 951 } else { 952 qemu_fprintf(f, " "); 953 } 954 } 955 956 if (arm_feature(env, ARM_FEATURE_M)) { 957 uint32_t xpsr = xpsr_read(env); 958 const char *mode; 959 const char *ns_status = ""; 960 961 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 962 ns_status = env->v7m.secure ? "S " : "NS "; 963 } 964 965 if (xpsr & XPSR_EXCP) { 966 mode = "handler"; 967 } else { 968 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 969 mode = "unpriv-thread"; 970 } else { 971 mode = "priv-thread"; 972 } 973 } 974 975 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 976 xpsr, 977 xpsr & XPSR_N ? 'N' : '-', 978 xpsr & XPSR_Z ? 'Z' : '-', 979 xpsr & XPSR_C ? 'C' : '-', 980 xpsr & XPSR_V ? 'V' : '-', 981 xpsr & XPSR_T ? 'T' : 'A', 982 ns_status, 983 mode); 984 } else { 985 uint32_t psr = cpsr_read(env); 986 const char *ns_status = ""; 987 988 if (arm_feature(env, ARM_FEATURE_EL3) && 989 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 990 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 991 } 992 993 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 994 psr, 995 psr & CPSR_N ? 'N' : '-', 996 psr & CPSR_Z ? 'Z' : '-', 997 psr & CPSR_C ? 'C' : '-', 998 psr & CPSR_V ? 'V' : '-', 999 psr & CPSR_T ? 'T' : 'A', 1000 ns_status, 1001 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1002 } 1003 1004 if (flags & CPU_DUMP_FPU) { 1005 int numvfpregs = 0; 1006 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1007 numvfpregs = 32; 1008 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1009 numvfpregs = 16; 1010 } 1011 for (i = 0; i < numvfpregs; i++) { 1012 uint64_t v = *aa32_vfp_dreg(env, i); 1013 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1014 i * 2, (uint32_t)v, 1015 i * 2 + 1, (uint32_t)(v >> 32), 1016 i, v); 1017 } 1018 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1019 } 1020 } 1021 1022 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 1023 { 1024 uint32_t Aff1 = idx / clustersz; 1025 uint32_t Aff0 = idx % clustersz; 1026 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1027 } 1028 1029 static void cpreg_hashtable_data_destroy(gpointer data) 1030 { 1031 /* 1032 * Destroy function for cpu->cp_regs hashtable data entries. 1033 * We must free the name string because it was g_strdup()ed in 1034 * add_cpreg_to_hashtable(). It's OK to cast away the 'const' 1035 * from r->name because we know we definitely allocated it. 1036 */ 1037 ARMCPRegInfo *r = data; 1038 1039 g_free((void *)r->name); 1040 g_free(r); 1041 } 1042 1043 static void arm_cpu_initfn(Object *obj) 1044 { 1045 ARMCPU *cpu = ARM_CPU(obj); 1046 1047 cpu_set_cpustate_pointers(cpu); 1048 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 1049 g_free, cpreg_hashtable_data_destroy); 1050 1051 QLIST_INIT(&cpu->pre_el_change_hooks); 1052 QLIST_INIT(&cpu->el_change_hooks); 1053 1054 #ifndef CONFIG_USER_ONLY 1055 /* Our inbound IRQ and FIQ lines */ 1056 if (kvm_enabled()) { 1057 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1058 * the same interface as non-KVM CPUs. 1059 */ 1060 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1061 } else { 1062 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1063 } 1064 1065 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1066 ARRAY_SIZE(cpu->gt_timer_outputs)); 1067 1068 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1069 "gicv3-maintenance-interrupt", 1); 1070 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1071 "pmu-interrupt", 1); 1072 #endif 1073 1074 /* DTB consumers generally don't in fact care what the 'compatible' 1075 * string is, so always provide some string and trust that a hypothetical 1076 * picky DTB consumer will also provide a helpful error message. 1077 */ 1078 cpu->dtb_compatible = "qemu,unknown"; 1079 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 1080 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1081 1082 if (tcg_enabled()) { 1083 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 1084 } 1085 } 1086 1087 static Property arm_cpu_gt_cntfrq_property = 1088 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1089 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1090 1091 static Property arm_cpu_reset_cbar_property = 1092 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1093 1094 static Property arm_cpu_reset_hivecs_property = 1095 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1096 1097 static Property arm_cpu_rvbar_property = 1098 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 1099 1100 #ifndef CONFIG_USER_ONLY 1101 static Property arm_cpu_has_el2_property = 1102 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1103 1104 static Property arm_cpu_has_el3_property = 1105 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1106 #endif 1107 1108 static Property arm_cpu_cfgend_property = 1109 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1110 1111 static Property arm_cpu_has_vfp_property = 1112 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1113 1114 static Property arm_cpu_has_neon_property = 1115 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1116 1117 static Property arm_cpu_has_dsp_property = 1118 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1119 1120 static Property arm_cpu_has_mpu_property = 1121 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1122 1123 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1124 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1125 * the right value for that particular CPU type, and we don't want 1126 * to override that with an incorrect constant value. 1127 */ 1128 static Property arm_cpu_pmsav7_dregion_property = 1129 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1130 pmsav7_dregion, 1131 qdev_prop_uint32, uint32_t); 1132 1133 static bool arm_get_pmu(Object *obj, Error **errp) 1134 { 1135 ARMCPU *cpu = ARM_CPU(obj); 1136 1137 return cpu->has_pmu; 1138 } 1139 1140 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1141 { 1142 ARMCPU *cpu = ARM_CPU(obj); 1143 1144 if (value) { 1145 if (kvm_enabled() && !kvm_arm_pmu_supported(CPU(cpu))) { 1146 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1147 return; 1148 } 1149 set_feature(&cpu->env, ARM_FEATURE_PMU); 1150 } else { 1151 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1152 } 1153 cpu->has_pmu = value; 1154 } 1155 1156 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1157 { 1158 /* 1159 * The exact approach to calculating guest ticks is: 1160 * 1161 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1162 * NANOSECONDS_PER_SECOND); 1163 * 1164 * We don't do that. Rather we intentionally use integer division 1165 * truncation below and in the caller for the conversion of host monotonic 1166 * time to guest ticks to provide the exact inverse for the semantics of 1167 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1168 * it loses precision when representing frequencies where 1169 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1170 * provide an exact inverse leads to scheduling timers with negative 1171 * periods, which in turn leads to sticky behaviour in the guest. 1172 * 1173 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1174 * cannot become zero. 1175 */ 1176 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1177 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1178 } 1179 1180 void arm_cpu_post_init(Object *obj) 1181 { 1182 ARMCPU *cpu = ARM_CPU(obj); 1183 1184 /* M profile implies PMSA. We have to do this here rather than 1185 * in realize with the other feature-implication checks because 1186 * we look at the PMSA bit to see if we should add some properties. 1187 */ 1188 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1189 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1190 } 1191 1192 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1193 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1194 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1195 } 1196 1197 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1198 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1199 } 1200 1201 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1202 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property); 1203 } 1204 1205 #ifndef CONFIG_USER_ONLY 1206 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1207 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1208 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1209 */ 1210 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1211 1212 object_property_add_link(obj, "secure-memory", 1213 TYPE_MEMORY_REGION, 1214 (Object **)&cpu->secure_memory, 1215 qdev_prop_allow_set_link_before_realize, 1216 OBJ_PROP_LINK_STRONG, 1217 &error_abort); 1218 } 1219 1220 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1221 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1222 } 1223 #endif 1224 1225 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1226 cpu->has_pmu = true; 1227 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu, 1228 &error_abort); 1229 } 1230 1231 /* 1232 * Allow user to turn off VFP and Neon support, but only for TCG -- 1233 * KVM does not currently allow us to lie to the guest about its 1234 * ID/feature registers, so the guest always sees what the host has. 1235 */ 1236 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 1237 ? cpu_isar_feature(aa64_fp_simd, cpu) 1238 : cpu_isar_feature(aa32_vfp, cpu)) { 1239 cpu->has_vfp = true; 1240 if (!kvm_enabled()) { 1241 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1242 } 1243 } 1244 1245 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1246 cpu->has_neon = true; 1247 if (!kvm_enabled()) { 1248 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1249 } 1250 } 1251 1252 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1253 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1254 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1255 } 1256 1257 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1258 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1259 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1260 qdev_property_add_static(DEVICE(obj), 1261 &arm_cpu_pmsav7_dregion_property); 1262 } 1263 } 1264 1265 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1266 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1267 qdev_prop_allow_set_link_before_realize, 1268 OBJ_PROP_LINK_STRONG, 1269 &error_abort); 1270 /* 1271 * M profile: initial value of the Secure VTOR. We can't just use 1272 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1273 * the property to be set after realize. 1274 */ 1275 object_property_add_uint32_ptr(obj, "init-svtor", 1276 &cpu->init_svtor, 1277 OBJ_PROP_FLAG_READWRITE, &error_abort); 1278 } 1279 1280 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1281 1282 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1283 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1284 } 1285 } 1286 1287 static void arm_cpu_finalizefn(Object *obj) 1288 { 1289 ARMCPU *cpu = ARM_CPU(obj); 1290 ARMELChangeHook *hook, *next; 1291 1292 g_hash_table_destroy(cpu->cp_regs); 1293 1294 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1295 QLIST_REMOVE(hook, node); 1296 g_free(hook); 1297 } 1298 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1299 QLIST_REMOVE(hook, node); 1300 g_free(hook); 1301 } 1302 #ifndef CONFIG_USER_ONLY 1303 if (cpu->pmu_timer) { 1304 timer_del(cpu->pmu_timer); 1305 timer_deinit(cpu->pmu_timer); 1306 timer_free(cpu->pmu_timer); 1307 } 1308 #endif 1309 } 1310 1311 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1312 { 1313 Error *local_err = NULL; 1314 1315 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1316 arm_cpu_sve_finalize(cpu, &local_err); 1317 if (local_err != NULL) { 1318 error_propagate(errp, local_err); 1319 return; 1320 } 1321 } 1322 } 1323 1324 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1325 { 1326 CPUState *cs = CPU(dev); 1327 ARMCPU *cpu = ARM_CPU(dev); 1328 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1329 CPUARMState *env = &cpu->env; 1330 int pagebits; 1331 Error *local_err = NULL; 1332 bool no_aa32 = false; 1333 1334 /* If we needed to query the host kernel for the CPU features 1335 * then it's possible that might have failed in the initfn, but 1336 * this is the first point where we can report it. 1337 */ 1338 if (cpu->host_cpu_probe_failed) { 1339 if (!kvm_enabled()) { 1340 error_setg(errp, "The 'host' CPU type can only be used with KVM"); 1341 } else { 1342 error_setg(errp, "Failed to retrieve host CPU features"); 1343 } 1344 return; 1345 } 1346 1347 #ifndef CONFIG_USER_ONLY 1348 /* The NVIC and M-profile CPU are two halves of a single piece of 1349 * hardware; trying to use one without the other is a command line 1350 * error and will result in segfaults if not caught here. 1351 */ 1352 if (arm_feature(env, ARM_FEATURE_M)) { 1353 if (!env->nvic) { 1354 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1355 return; 1356 } 1357 } else { 1358 if (env->nvic) { 1359 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1360 return; 1361 } 1362 } 1363 1364 { 1365 uint64_t scale; 1366 1367 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1368 if (!cpu->gt_cntfrq_hz) { 1369 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1370 cpu->gt_cntfrq_hz); 1371 return; 1372 } 1373 scale = gt_cntfrq_period_ns(cpu); 1374 } else { 1375 scale = GTIMER_SCALE; 1376 } 1377 1378 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1379 arm_gt_ptimer_cb, cpu); 1380 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1381 arm_gt_vtimer_cb, cpu); 1382 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1383 arm_gt_htimer_cb, cpu); 1384 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1385 arm_gt_stimer_cb, cpu); 1386 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1387 arm_gt_hvtimer_cb, cpu); 1388 } 1389 #endif 1390 1391 cpu_exec_realizefn(cs, &local_err); 1392 if (local_err != NULL) { 1393 error_propagate(errp, local_err); 1394 return; 1395 } 1396 1397 arm_cpu_finalize_features(cpu, &local_err); 1398 if (local_err != NULL) { 1399 error_propagate(errp, local_err); 1400 return; 1401 } 1402 1403 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1404 cpu->has_vfp != cpu->has_neon) { 1405 /* 1406 * This is an architectural requirement for AArch64; AArch32 is 1407 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1408 */ 1409 error_setg(errp, 1410 "AArch64 CPUs must have both VFP and Neon or neither"); 1411 return; 1412 } 1413 1414 if (!cpu->has_vfp) { 1415 uint64_t t; 1416 uint32_t u; 1417 1418 t = cpu->isar.id_aa64isar1; 1419 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1420 cpu->isar.id_aa64isar1 = t; 1421 1422 t = cpu->isar.id_aa64pfr0; 1423 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1424 cpu->isar.id_aa64pfr0 = t; 1425 1426 u = cpu->isar.id_isar6; 1427 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1428 cpu->isar.id_isar6 = u; 1429 1430 u = cpu->isar.mvfr0; 1431 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1432 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1433 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1434 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1435 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1436 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1437 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1438 cpu->isar.mvfr0 = u; 1439 1440 u = cpu->isar.mvfr1; 1441 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1442 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1443 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1444 cpu->isar.mvfr1 = u; 1445 1446 u = cpu->isar.mvfr2; 1447 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1448 cpu->isar.mvfr2 = u; 1449 } 1450 1451 if (!cpu->has_neon) { 1452 uint64_t t; 1453 uint32_t u; 1454 1455 unset_feature(env, ARM_FEATURE_NEON); 1456 1457 t = cpu->isar.id_aa64isar0; 1458 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1459 cpu->isar.id_aa64isar0 = t; 1460 1461 t = cpu->isar.id_aa64isar1; 1462 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1463 cpu->isar.id_aa64isar1 = t; 1464 1465 t = cpu->isar.id_aa64pfr0; 1466 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1467 cpu->isar.id_aa64pfr0 = t; 1468 1469 u = cpu->isar.id_isar5; 1470 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1471 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1472 cpu->isar.id_isar5 = u; 1473 1474 u = cpu->isar.id_isar6; 1475 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1476 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1477 cpu->isar.id_isar6 = u; 1478 1479 u = cpu->isar.mvfr1; 1480 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1481 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1482 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1483 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1484 cpu->isar.mvfr1 = u; 1485 1486 u = cpu->isar.mvfr2; 1487 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1488 cpu->isar.mvfr2 = u; 1489 } 1490 1491 if (!cpu->has_neon && !cpu->has_vfp) { 1492 uint64_t t; 1493 uint32_t u; 1494 1495 t = cpu->isar.id_aa64isar0; 1496 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1497 cpu->isar.id_aa64isar0 = t; 1498 1499 t = cpu->isar.id_aa64isar1; 1500 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1501 cpu->isar.id_aa64isar1 = t; 1502 1503 u = cpu->isar.mvfr0; 1504 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1505 cpu->isar.mvfr0 = u; 1506 1507 /* Despite the name, this field covers both VFP and Neon */ 1508 u = cpu->isar.mvfr1; 1509 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1510 cpu->isar.mvfr1 = u; 1511 } 1512 1513 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1514 uint32_t u; 1515 1516 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1517 1518 u = cpu->isar.id_isar1; 1519 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1520 cpu->isar.id_isar1 = u; 1521 1522 u = cpu->isar.id_isar2; 1523 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1524 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1525 cpu->isar.id_isar2 = u; 1526 1527 u = cpu->isar.id_isar3; 1528 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1529 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1530 cpu->isar.id_isar3 = u; 1531 } 1532 1533 /* Some features automatically imply others: */ 1534 if (arm_feature(env, ARM_FEATURE_V8)) { 1535 if (arm_feature(env, ARM_FEATURE_M)) { 1536 set_feature(env, ARM_FEATURE_V7); 1537 } else { 1538 set_feature(env, ARM_FEATURE_V7VE); 1539 } 1540 } 1541 1542 /* 1543 * There exist AArch64 cpus without AArch32 support. When KVM 1544 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1545 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1546 * As a general principle, we also do not make ID register 1547 * consistency checks anywhere unless using TCG, because only 1548 * for TCG would a consistency-check failure be a QEMU bug. 1549 */ 1550 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1551 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1552 } 1553 1554 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1555 /* v7 Virtualization Extensions. In real hardware this implies 1556 * EL2 and also the presence of the Security Extensions. 1557 * For QEMU, for backwards-compatibility we implement some 1558 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1559 * include the various other features that V7VE implies. 1560 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1561 * Security Extensions is ARM_FEATURE_EL3. 1562 */ 1563 assert(!tcg_enabled() || no_aa32 || 1564 cpu_isar_feature(aa32_arm_div, cpu)); 1565 set_feature(env, ARM_FEATURE_LPAE); 1566 set_feature(env, ARM_FEATURE_V7); 1567 } 1568 if (arm_feature(env, ARM_FEATURE_V7)) { 1569 set_feature(env, ARM_FEATURE_VAPA); 1570 set_feature(env, ARM_FEATURE_THUMB2); 1571 set_feature(env, ARM_FEATURE_MPIDR); 1572 if (!arm_feature(env, ARM_FEATURE_M)) { 1573 set_feature(env, ARM_FEATURE_V6K); 1574 } else { 1575 set_feature(env, ARM_FEATURE_V6); 1576 } 1577 1578 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1579 * non-EL3 configs. This is needed by some legacy boards. 1580 */ 1581 set_feature(env, ARM_FEATURE_VBAR); 1582 } 1583 if (arm_feature(env, ARM_FEATURE_V6K)) { 1584 set_feature(env, ARM_FEATURE_V6); 1585 set_feature(env, ARM_FEATURE_MVFR); 1586 } 1587 if (arm_feature(env, ARM_FEATURE_V6)) { 1588 set_feature(env, ARM_FEATURE_V5); 1589 if (!arm_feature(env, ARM_FEATURE_M)) { 1590 assert(!tcg_enabled() || no_aa32 || 1591 cpu_isar_feature(aa32_jazelle, cpu)); 1592 set_feature(env, ARM_FEATURE_AUXCR); 1593 } 1594 } 1595 if (arm_feature(env, ARM_FEATURE_V5)) { 1596 set_feature(env, ARM_FEATURE_V4T); 1597 } 1598 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1599 set_feature(env, ARM_FEATURE_V7MP); 1600 set_feature(env, ARM_FEATURE_PXN); 1601 } 1602 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1603 set_feature(env, ARM_FEATURE_CBAR); 1604 } 1605 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1606 !arm_feature(env, ARM_FEATURE_M)) { 1607 set_feature(env, ARM_FEATURE_THUMB_DSP); 1608 } 1609 1610 /* 1611 * We rely on no XScale CPU having VFP so we can use the same bits in the 1612 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1613 */ 1614 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1615 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1616 !arm_feature(env, ARM_FEATURE_XSCALE)); 1617 1618 if (arm_feature(env, ARM_FEATURE_V7) && 1619 !arm_feature(env, ARM_FEATURE_M) && 1620 !arm_feature(env, ARM_FEATURE_PMSA)) { 1621 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1622 * can use 4K pages. 1623 */ 1624 pagebits = 12; 1625 } else { 1626 /* For CPUs which might have tiny 1K pages, or which have an 1627 * MPU and might have small region sizes, stick with 1K pages. 1628 */ 1629 pagebits = 10; 1630 } 1631 if (!set_preferred_target_page_bits(pagebits)) { 1632 /* This can only ever happen for hotplugging a CPU, or if 1633 * the board code incorrectly creates a CPU which it has 1634 * promised via minimum_page_size that it will not. 1635 */ 1636 error_setg(errp, "This CPU requires a smaller page size than the " 1637 "system is using"); 1638 return; 1639 } 1640 1641 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1642 * We don't support setting cluster ID ([16..23]) (known as Aff2 1643 * in later ARM ARM versions), or any of the higher affinity level fields, 1644 * so these bits always RAZ. 1645 */ 1646 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1647 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1648 ARM_DEFAULT_CPUS_PER_CLUSTER); 1649 } 1650 1651 if (cpu->reset_hivecs) { 1652 cpu->reset_sctlr |= (1 << 13); 1653 } 1654 1655 if (cpu->cfgend) { 1656 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1657 cpu->reset_sctlr |= SCTLR_EE; 1658 } else { 1659 cpu->reset_sctlr |= SCTLR_B; 1660 } 1661 } 1662 1663 if (!cpu->has_el3) { 1664 /* If the has_el3 CPU property is disabled then we need to disable the 1665 * feature. 1666 */ 1667 unset_feature(env, ARM_FEATURE_EL3); 1668 1669 /* Disable the security extension feature bits in the processor feature 1670 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 1671 */ 1672 cpu->id_pfr1 &= ~0xf0; 1673 cpu->isar.id_aa64pfr0 &= ~0xf000; 1674 } 1675 1676 if (!cpu->has_el2) { 1677 unset_feature(env, ARM_FEATURE_EL2); 1678 } 1679 1680 if (!cpu->has_pmu) { 1681 unset_feature(env, ARM_FEATURE_PMU); 1682 } 1683 if (arm_feature(env, ARM_FEATURE_PMU)) { 1684 pmu_init(cpu); 1685 1686 if (!kvm_enabled()) { 1687 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1688 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1689 } 1690 1691 #ifndef CONFIG_USER_ONLY 1692 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1693 cpu); 1694 #endif 1695 } else { 1696 cpu->isar.id_aa64dfr0 = 1697 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 1698 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 1699 cpu->pmceid0 = 0; 1700 cpu->pmceid1 = 0; 1701 } 1702 1703 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1704 /* Disable the hypervisor feature bits in the processor feature 1705 * registers if we don't have EL2. These are id_pfr1[15:12] and 1706 * id_aa64pfr0_el1[11:8]. 1707 */ 1708 cpu->isar.id_aa64pfr0 &= ~0xf00; 1709 cpu->id_pfr1 &= ~0xf000; 1710 } 1711 1712 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1713 * to false or by setting pmsav7-dregion to 0. 1714 */ 1715 if (!cpu->has_mpu) { 1716 cpu->pmsav7_dregion = 0; 1717 } 1718 if (cpu->pmsav7_dregion == 0) { 1719 cpu->has_mpu = false; 1720 } 1721 1722 if (arm_feature(env, ARM_FEATURE_PMSA) && 1723 arm_feature(env, ARM_FEATURE_V7)) { 1724 uint32_t nr = cpu->pmsav7_dregion; 1725 1726 if (nr > 0xff) { 1727 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1728 return; 1729 } 1730 1731 if (nr) { 1732 if (arm_feature(env, ARM_FEATURE_V8)) { 1733 /* PMSAv8 */ 1734 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1735 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1736 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1737 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1738 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1739 } 1740 } else { 1741 env->pmsav7.drbar = g_new0(uint32_t, nr); 1742 env->pmsav7.drsr = g_new0(uint32_t, nr); 1743 env->pmsav7.dracr = g_new0(uint32_t, nr); 1744 } 1745 } 1746 } 1747 1748 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1749 uint32_t nr = cpu->sau_sregion; 1750 1751 if (nr > 0xff) { 1752 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1753 return; 1754 } 1755 1756 if (nr) { 1757 env->sau.rbar = g_new0(uint32_t, nr); 1758 env->sau.rlar = g_new0(uint32_t, nr); 1759 } 1760 } 1761 1762 if (arm_feature(env, ARM_FEATURE_EL3)) { 1763 set_feature(env, ARM_FEATURE_VBAR); 1764 } 1765 1766 register_cp_regs_for_features(cpu); 1767 arm_cpu_register_gdb_regs_for_features(cpu); 1768 1769 init_cpreg_list(cpu); 1770 1771 #ifndef CONFIG_USER_ONLY 1772 MachineState *ms = MACHINE(qdev_get_machine()); 1773 unsigned int smp_cpus = ms->smp.cpus; 1774 1775 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1776 cs->num_ases = 2; 1777 1778 if (!cpu->secure_memory) { 1779 cpu->secure_memory = cs->memory; 1780 } 1781 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1782 cpu->secure_memory); 1783 } else { 1784 cs->num_ases = 1; 1785 } 1786 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1787 1788 /* No core_count specified, default to smp_cpus. */ 1789 if (cpu->core_count == -1) { 1790 cpu->core_count = smp_cpus; 1791 } 1792 #endif 1793 1794 qemu_init_vcpu(cs); 1795 cpu_reset(cs); 1796 1797 acc->parent_realize(dev, errp); 1798 } 1799 1800 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1801 { 1802 ObjectClass *oc; 1803 char *typename; 1804 char **cpuname; 1805 const char *cpunamestr; 1806 1807 cpuname = g_strsplit(cpu_model, ",", 1); 1808 cpunamestr = cpuname[0]; 1809 #ifdef CONFIG_USER_ONLY 1810 /* For backwards compatibility usermode emulation allows "-cpu any", 1811 * which has the same semantics as "-cpu max". 1812 */ 1813 if (!strcmp(cpunamestr, "any")) { 1814 cpunamestr = "max"; 1815 } 1816 #endif 1817 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 1818 oc = object_class_by_name(typename); 1819 g_strfreev(cpuname); 1820 g_free(typename); 1821 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 1822 object_class_is_abstract(oc)) { 1823 return NULL; 1824 } 1825 return oc; 1826 } 1827 1828 /* CPU models. These are not needed for the AArch64 linux-user build. */ 1829 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1830 1831 static void arm926_initfn(Object *obj) 1832 { 1833 ARMCPU *cpu = ARM_CPU(obj); 1834 1835 cpu->dtb_compatible = "arm,arm926"; 1836 set_feature(&cpu->env, ARM_FEATURE_V5); 1837 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1838 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1839 cpu->midr = 0x41069265; 1840 cpu->reset_fpsid = 0x41011090; 1841 cpu->ctr = 0x1dd20d2; 1842 cpu->reset_sctlr = 0x00090078; 1843 1844 /* 1845 * ARMv5 does not have the ID_ISAR registers, but we can still 1846 * set the field to indicate Jazelle support within QEMU. 1847 */ 1848 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 1849 /* 1850 * Similarly, we need to set MVFR0 fields to enable vfp and short vector 1851 * support even though ARMv5 doesn't have this register. 1852 */ 1853 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 1854 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); 1855 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); 1856 } 1857 1858 static void arm946_initfn(Object *obj) 1859 { 1860 ARMCPU *cpu = ARM_CPU(obj); 1861 1862 cpu->dtb_compatible = "arm,arm946"; 1863 set_feature(&cpu->env, ARM_FEATURE_V5); 1864 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1865 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1866 cpu->midr = 0x41059461; 1867 cpu->ctr = 0x0f004006; 1868 cpu->reset_sctlr = 0x00000078; 1869 } 1870 1871 static void arm1026_initfn(Object *obj) 1872 { 1873 ARMCPU *cpu = ARM_CPU(obj); 1874 1875 cpu->dtb_compatible = "arm,arm1026"; 1876 set_feature(&cpu->env, ARM_FEATURE_V5); 1877 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 1878 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1879 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1880 cpu->midr = 0x4106a262; 1881 cpu->reset_fpsid = 0x410110a0; 1882 cpu->ctr = 0x1dd20d2; 1883 cpu->reset_sctlr = 0x00090078; 1884 cpu->reset_auxcr = 1; 1885 1886 /* 1887 * ARMv5 does not have the ID_ISAR registers, but we can still 1888 * set the field to indicate Jazelle support within QEMU. 1889 */ 1890 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 1891 /* 1892 * Similarly, we need to set MVFR0 fields to enable vfp and short vector 1893 * support even though ARMv5 doesn't have this register. 1894 */ 1895 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 1896 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); 1897 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); 1898 1899 { 1900 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 1901 ARMCPRegInfo ifar = { 1902 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 1903 .access = PL1_RW, 1904 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 1905 .resetvalue = 0 1906 }; 1907 define_one_arm_cp_reg(cpu, &ifar); 1908 } 1909 } 1910 1911 static void arm1136_r2_initfn(Object *obj) 1912 { 1913 ARMCPU *cpu = ARM_CPU(obj); 1914 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 1915 * older core than plain "arm1136". In particular this does not 1916 * have the v6K features. 1917 * These ID register values are correct for 1136 but may be wrong 1918 * for 1136_r2 (in particular r0p2 does not actually implement most 1919 * of the ID registers). 1920 */ 1921 1922 cpu->dtb_compatible = "arm,arm1136"; 1923 set_feature(&cpu->env, ARM_FEATURE_V6); 1924 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1925 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1926 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1927 cpu->midr = 0x4107b362; 1928 cpu->reset_fpsid = 0x410120b4; 1929 cpu->isar.mvfr0 = 0x11111111; 1930 cpu->isar.mvfr1 = 0x00000000; 1931 cpu->ctr = 0x1dd20d2; 1932 cpu->reset_sctlr = 0x00050078; 1933 cpu->id_pfr0 = 0x111; 1934 cpu->id_pfr1 = 0x1; 1935 cpu->isar.id_dfr0 = 0x2; 1936 cpu->id_afr0 = 0x3; 1937 cpu->isar.id_mmfr0 = 0x01130003; 1938 cpu->isar.id_mmfr1 = 0x10030302; 1939 cpu->isar.id_mmfr2 = 0x01222110; 1940 cpu->isar.id_isar0 = 0x00140011; 1941 cpu->isar.id_isar1 = 0x12002111; 1942 cpu->isar.id_isar2 = 0x11231111; 1943 cpu->isar.id_isar3 = 0x01102131; 1944 cpu->isar.id_isar4 = 0x141; 1945 cpu->reset_auxcr = 7; 1946 } 1947 1948 static void arm1136_initfn(Object *obj) 1949 { 1950 ARMCPU *cpu = ARM_CPU(obj); 1951 1952 cpu->dtb_compatible = "arm,arm1136"; 1953 set_feature(&cpu->env, ARM_FEATURE_V6K); 1954 set_feature(&cpu->env, ARM_FEATURE_V6); 1955 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1956 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1957 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1958 cpu->midr = 0x4117b363; 1959 cpu->reset_fpsid = 0x410120b4; 1960 cpu->isar.mvfr0 = 0x11111111; 1961 cpu->isar.mvfr1 = 0x00000000; 1962 cpu->ctr = 0x1dd20d2; 1963 cpu->reset_sctlr = 0x00050078; 1964 cpu->id_pfr0 = 0x111; 1965 cpu->id_pfr1 = 0x1; 1966 cpu->isar.id_dfr0 = 0x2; 1967 cpu->id_afr0 = 0x3; 1968 cpu->isar.id_mmfr0 = 0x01130003; 1969 cpu->isar.id_mmfr1 = 0x10030302; 1970 cpu->isar.id_mmfr2 = 0x01222110; 1971 cpu->isar.id_isar0 = 0x00140011; 1972 cpu->isar.id_isar1 = 0x12002111; 1973 cpu->isar.id_isar2 = 0x11231111; 1974 cpu->isar.id_isar3 = 0x01102131; 1975 cpu->isar.id_isar4 = 0x141; 1976 cpu->reset_auxcr = 7; 1977 } 1978 1979 static void arm1176_initfn(Object *obj) 1980 { 1981 ARMCPU *cpu = ARM_CPU(obj); 1982 1983 cpu->dtb_compatible = "arm,arm1176"; 1984 set_feature(&cpu->env, ARM_FEATURE_V6K); 1985 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1986 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1987 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1988 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1989 set_feature(&cpu->env, ARM_FEATURE_EL3); 1990 cpu->midr = 0x410fb767; 1991 cpu->reset_fpsid = 0x410120b5; 1992 cpu->isar.mvfr0 = 0x11111111; 1993 cpu->isar.mvfr1 = 0x00000000; 1994 cpu->ctr = 0x1dd20d2; 1995 cpu->reset_sctlr = 0x00050078; 1996 cpu->id_pfr0 = 0x111; 1997 cpu->id_pfr1 = 0x11; 1998 cpu->isar.id_dfr0 = 0x33; 1999 cpu->id_afr0 = 0; 2000 cpu->isar.id_mmfr0 = 0x01130003; 2001 cpu->isar.id_mmfr1 = 0x10030302; 2002 cpu->isar.id_mmfr2 = 0x01222100; 2003 cpu->isar.id_isar0 = 0x0140011; 2004 cpu->isar.id_isar1 = 0x12002111; 2005 cpu->isar.id_isar2 = 0x11231121; 2006 cpu->isar.id_isar3 = 0x01102131; 2007 cpu->isar.id_isar4 = 0x01141; 2008 cpu->reset_auxcr = 7; 2009 } 2010 2011 static void arm11mpcore_initfn(Object *obj) 2012 { 2013 ARMCPU *cpu = ARM_CPU(obj); 2014 2015 cpu->dtb_compatible = "arm,arm11mpcore"; 2016 set_feature(&cpu->env, ARM_FEATURE_V6K); 2017 set_feature(&cpu->env, ARM_FEATURE_VAPA); 2018 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 2019 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2020 cpu->midr = 0x410fb022; 2021 cpu->reset_fpsid = 0x410120b4; 2022 cpu->isar.mvfr0 = 0x11111111; 2023 cpu->isar.mvfr1 = 0x00000000; 2024 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 2025 cpu->id_pfr0 = 0x111; 2026 cpu->id_pfr1 = 0x1; 2027 cpu->isar.id_dfr0 = 0; 2028 cpu->id_afr0 = 0x2; 2029 cpu->isar.id_mmfr0 = 0x01100103; 2030 cpu->isar.id_mmfr1 = 0x10020302; 2031 cpu->isar.id_mmfr2 = 0x01222000; 2032 cpu->isar.id_isar0 = 0x00100011; 2033 cpu->isar.id_isar1 = 0x12002111; 2034 cpu->isar.id_isar2 = 0x11221011; 2035 cpu->isar.id_isar3 = 0x01102131; 2036 cpu->isar.id_isar4 = 0x141; 2037 cpu->reset_auxcr = 1; 2038 } 2039 2040 static void cortex_m0_initfn(Object *obj) 2041 { 2042 ARMCPU *cpu = ARM_CPU(obj); 2043 set_feature(&cpu->env, ARM_FEATURE_V6); 2044 set_feature(&cpu->env, ARM_FEATURE_M); 2045 2046 cpu->midr = 0x410cc200; 2047 } 2048 2049 static void cortex_m3_initfn(Object *obj) 2050 { 2051 ARMCPU *cpu = ARM_CPU(obj); 2052 set_feature(&cpu->env, ARM_FEATURE_V7); 2053 set_feature(&cpu->env, ARM_FEATURE_M); 2054 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 2055 cpu->midr = 0x410fc231; 2056 cpu->pmsav7_dregion = 8; 2057 cpu->id_pfr0 = 0x00000030; 2058 cpu->id_pfr1 = 0x00000200; 2059 cpu->isar.id_dfr0 = 0x00100000; 2060 cpu->id_afr0 = 0x00000000; 2061 cpu->isar.id_mmfr0 = 0x00000030; 2062 cpu->isar.id_mmfr1 = 0x00000000; 2063 cpu->isar.id_mmfr2 = 0x00000000; 2064 cpu->isar.id_mmfr3 = 0x00000000; 2065 cpu->isar.id_isar0 = 0x01141110; 2066 cpu->isar.id_isar1 = 0x02111000; 2067 cpu->isar.id_isar2 = 0x21112231; 2068 cpu->isar.id_isar3 = 0x01111110; 2069 cpu->isar.id_isar4 = 0x01310102; 2070 cpu->isar.id_isar5 = 0x00000000; 2071 cpu->isar.id_isar6 = 0x00000000; 2072 } 2073 2074 static void cortex_m4_initfn(Object *obj) 2075 { 2076 ARMCPU *cpu = ARM_CPU(obj); 2077 2078 set_feature(&cpu->env, ARM_FEATURE_V7); 2079 set_feature(&cpu->env, ARM_FEATURE_M); 2080 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 2081 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 2082 cpu->midr = 0x410fc240; /* r0p0 */ 2083 cpu->pmsav7_dregion = 8; 2084 cpu->isar.mvfr0 = 0x10110021; 2085 cpu->isar.mvfr1 = 0x11000011; 2086 cpu->isar.mvfr2 = 0x00000000; 2087 cpu->id_pfr0 = 0x00000030; 2088 cpu->id_pfr1 = 0x00000200; 2089 cpu->isar.id_dfr0 = 0x00100000; 2090 cpu->id_afr0 = 0x00000000; 2091 cpu->isar.id_mmfr0 = 0x00000030; 2092 cpu->isar.id_mmfr1 = 0x00000000; 2093 cpu->isar.id_mmfr2 = 0x00000000; 2094 cpu->isar.id_mmfr3 = 0x00000000; 2095 cpu->isar.id_isar0 = 0x01141110; 2096 cpu->isar.id_isar1 = 0x02111000; 2097 cpu->isar.id_isar2 = 0x21112231; 2098 cpu->isar.id_isar3 = 0x01111110; 2099 cpu->isar.id_isar4 = 0x01310102; 2100 cpu->isar.id_isar5 = 0x00000000; 2101 cpu->isar.id_isar6 = 0x00000000; 2102 } 2103 2104 static void cortex_m7_initfn(Object *obj) 2105 { 2106 ARMCPU *cpu = ARM_CPU(obj); 2107 2108 set_feature(&cpu->env, ARM_FEATURE_V7); 2109 set_feature(&cpu->env, ARM_FEATURE_M); 2110 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 2111 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 2112 cpu->midr = 0x411fc272; /* r1p2 */ 2113 cpu->pmsav7_dregion = 8; 2114 cpu->isar.mvfr0 = 0x10110221; 2115 cpu->isar.mvfr1 = 0x12000011; 2116 cpu->isar.mvfr2 = 0x00000040; 2117 cpu->id_pfr0 = 0x00000030; 2118 cpu->id_pfr1 = 0x00000200; 2119 cpu->isar.id_dfr0 = 0x00100000; 2120 cpu->id_afr0 = 0x00000000; 2121 cpu->isar.id_mmfr0 = 0x00100030; 2122 cpu->isar.id_mmfr1 = 0x00000000; 2123 cpu->isar.id_mmfr2 = 0x01000000; 2124 cpu->isar.id_mmfr3 = 0x00000000; 2125 cpu->isar.id_isar0 = 0x01101110; 2126 cpu->isar.id_isar1 = 0x02112000; 2127 cpu->isar.id_isar2 = 0x20232231; 2128 cpu->isar.id_isar3 = 0x01111131; 2129 cpu->isar.id_isar4 = 0x01310132; 2130 cpu->isar.id_isar5 = 0x00000000; 2131 cpu->isar.id_isar6 = 0x00000000; 2132 } 2133 2134 static void cortex_m33_initfn(Object *obj) 2135 { 2136 ARMCPU *cpu = ARM_CPU(obj); 2137 2138 set_feature(&cpu->env, ARM_FEATURE_V8); 2139 set_feature(&cpu->env, ARM_FEATURE_M); 2140 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 2141 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); 2142 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 2143 cpu->midr = 0x410fd213; /* r0p3 */ 2144 cpu->pmsav7_dregion = 16; 2145 cpu->sau_sregion = 8; 2146 cpu->isar.mvfr0 = 0x10110021; 2147 cpu->isar.mvfr1 = 0x11000011; 2148 cpu->isar.mvfr2 = 0x00000040; 2149 cpu->id_pfr0 = 0x00000030; 2150 cpu->id_pfr1 = 0x00000210; 2151 cpu->isar.id_dfr0 = 0x00200000; 2152 cpu->id_afr0 = 0x00000000; 2153 cpu->isar.id_mmfr0 = 0x00101F40; 2154 cpu->isar.id_mmfr1 = 0x00000000; 2155 cpu->isar.id_mmfr2 = 0x01000000; 2156 cpu->isar.id_mmfr3 = 0x00000000; 2157 cpu->isar.id_isar0 = 0x01101110; 2158 cpu->isar.id_isar1 = 0x02212000; 2159 cpu->isar.id_isar2 = 0x20232232; 2160 cpu->isar.id_isar3 = 0x01111131; 2161 cpu->isar.id_isar4 = 0x01310132; 2162 cpu->isar.id_isar5 = 0x00000000; 2163 cpu->isar.id_isar6 = 0x00000000; 2164 cpu->clidr = 0x00000000; 2165 cpu->ctr = 0x8000c000; 2166 } 2167 2168 static void arm_v7m_class_init(ObjectClass *oc, void *data) 2169 { 2170 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2171 CPUClass *cc = CPU_CLASS(oc); 2172 2173 acc->info = data; 2174 #ifndef CONFIG_USER_ONLY 2175 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 2176 #endif 2177 2178 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 2179 } 2180 2181 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 2182 /* Dummy the TCM region regs for the moment */ 2183 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 2184 .access = PL1_RW, .type = ARM_CP_CONST }, 2185 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 2186 .access = PL1_RW, .type = ARM_CP_CONST }, 2187 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 2188 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 2189 REGINFO_SENTINEL 2190 }; 2191 2192 static void cortex_r5_initfn(Object *obj) 2193 { 2194 ARMCPU *cpu = ARM_CPU(obj); 2195 2196 set_feature(&cpu->env, ARM_FEATURE_V7); 2197 set_feature(&cpu->env, ARM_FEATURE_V7MP); 2198 set_feature(&cpu->env, ARM_FEATURE_PMSA); 2199 set_feature(&cpu->env, ARM_FEATURE_PMU); 2200 cpu->midr = 0x411fc153; /* r1p3 */ 2201 cpu->id_pfr0 = 0x0131; 2202 cpu->id_pfr1 = 0x001; 2203 cpu->isar.id_dfr0 = 0x010400; 2204 cpu->id_afr0 = 0x0; 2205 cpu->isar.id_mmfr0 = 0x0210030; 2206 cpu->isar.id_mmfr1 = 0x00000000; 2207 cpu->isar.id_mmfr2 = 0x01200000; 2208 cpu->isar.id_mmfr3 = 0x0211; 2209 cpu->isar.id_isar0 = 0x02101111; 2210 cpu->isar.id_isar1 = 0x13112111; 2211 cpu->isar.id_isar2 = 0x21232141; 2212 cpu->isar.id_isar3 = 0x01112131; 2213 cpu->isar.id_isar4 = 0x0010142; 2214 cpu->isar.id_isar5 = 0x0; 2215 cpu->isar.id_isar6 = 0x0; 2216 cpu->mp_is_up = true; 2217 cpu->pmsav7_dregion = 16; 2218 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 2219 } 2220 2221 static void cortex_r5f_initfn(Object *obj) 2222 { 2223 ARMCPU *cpu = ARM_CPU(obj); 2224 2225 cortex_r5_initfn(obj); 2226 cpu->isar.mvfr0 = 0x10110221; 2227 cpu->isar.mvfr1 = 0x00000011; 2228 } 2229 2230 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 2231 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 2232 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 2233 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 2234 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 2235 REGINFO_SENTINEL 2236 }; 2237 2238 static void cortex_a8_initfn(Object *obj) 2239 { 2240 ARMCPU *cpu = ARM_CPU(obj); 2241 2242 cpu->dtb_compatible = "arm,cortex-a8"; 2243 set_feature(&cpu->env, ARM_FEATURE_V7); 2244 set_feature(&cpu->env, ARM_FEATURE_NEON); 2245 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2246 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2247 set_feature(&cpu->env, ARM_FEATURE_EL3); 2248 cpu->midr = 0x410fc080; 2249 cpu->reset_fpsid = 0x410330c0; 2250 cpu->isar.mvfr0 = 0x11110222; 2251 cpu->isar.mvfr1 = 0x00011111; 2252 cpu->ctr = 0x82048004; 2253 cpu->reset_sctlr = 0x00c50078; 2254 cpu->id_pfr0 = 0x1031; 2255 cpu->id_pfr1 = 0x11; 2256 cpu->isar.id_dfr0 = 0x400; 2257 cpu->id_afr0 = 0; 2258 cpu->isar.id_mmfr0 = 0x31100003; 2259 cpu->isar.id_mmfr1 = 0x20000000; 2260 cpu->isar.id_mmfr2 = 0x01202000; 2261 cpu->isar.id_mmfr3 = 0x11; 2262 cpu->isar.id_isar0 = 0x00101111; 2263 cpu->isar.id_isar1 = 0x12112111; 2264 cpu->isar.id_isar2 = 0x21232031; 2265 cpu->isar.id_isar3 = 0x11112131; 2266 cpu->isar.id_isar4 = 0x00111142; 2267 cpu->isar.dbgdidr = 0x15141000; 2268 cpu->clidr = (1 << 27) | (2 << 24) | 3; 2269 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 2270 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 2271 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 2272 cpu->reset_auxcr = 2; 2273 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 2274 } 2275 2276 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 2277 /* power_control should be set to maximum latency. Again, 2278 * default to 0 and set by private hook 2279 */ 2280 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 2281 .access = PL1_RW, .resetvalue = 0, 2282 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 2283 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 2284 .access = PL1_RW, .resetvalue = 0, 2285 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 2286 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 2287 .access = PL1_RW, .resetvalue = 0, 2288 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 2289 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 2290 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 2291 /* TLB lockdown control */ 2292 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 2293 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 2294 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 2295 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 2296 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 2297 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 2298 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 2299 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 2300 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 2301 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 2302 REGINFO_SENTINEL 2303 }; 2304 2305 static void cortex_a9_initfn(Object *obj) 2306 { 2307 ARMCPU *cpu = ARM_CPU(obj); 2308 2309 cpu->dtb_compatible = "arm,cortex-a9"; 2310 set_feature(&cpu->env, ARM_FEATURE_V7); 2311 set_feature(&cpu->env, ARM_FEATURE_NEON); 2312 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2313 set_feature(&cpu->env, ARM_FEATURE_EL3); 2314 /* Note that A9 supports the MP extensions even for 2315 * A9UP and single-core A9MP (which are both different 2316 * and valid configurations; we don't model A9UP). 2317 */ 2318 set_feature(&cpu->env, ARM_FEATURE_V7MP); 2319 set_feature(&cpu->env, ARM_FEATURE_CBAR); 2320 cpu->midr = 0x410fc090; 2321 cpu->reset_fpsid = 0x41033090; 2322 cpu->isar.mvfr0 = 0x11110222; 2323 cpu->isar.mvfr1 = 0x01111111; 2324 cpu->ctr = 0x80038003; 2325 cpu->reset_sctlr = 0x00c50078; 2326 cpu->id_pfr0 = 0x1031; 2327 cpu->id_pfr1 = 0x11; 2328 cpu->isar.id_dfr0 = 0x000; 2329 cpu->id_afr0 = 0; 2330 cpu->isar.id_mmfr0 = 0x00100103; 2331 cpu->isar.id_mmfr1 = 0x20000000; 2332 cpu->isar.id_mmfr2 = 0x01230000; 2333 cpu->isar.id_mmfr3 = 0x00002111; 2334 cpu->isar.id_isar0 = 0x00101111; 2335 cpu->isar.id_isar1 = 0x13112111; 2336 cpu->isar.id_isar2 = 0x21232041; 2337 cpu->isar.id_isar3 = 0x11112131; 2338 cpu->isar.id_isar4 = 0x00111142; 2339 cpu->isar.dbgdidr = 0x35141000; 2340 cpu->clidr = (1 << 27) | (1 << 24) | 3; 2341 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 2342 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 2343 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 2344 } 2345 2346 #ifndef CONFIG_USER_ONLY 2347 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2348 { 2349 MachineState *ms = MACHINE(qdev_get_machine()); 2350 2351 /* Linux wants the number of processors from here. 2352 * Might as well set the interrupt-controller bit too. 2353 */ 2354 return ((ms->smp.cpus - 1) << 24) | (1 << 23); 2355 } 2356 #endif 2357 2358 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 2359 #ifndef CONFIG_USER_ONLY 2360 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 2361 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 2362 .writefn = arm_cp_write_ignore, }, 2363 #endif 2364 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 2365 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 2366 REGINFO_SENTINEL 2367 }; 2368 2369 static void cortex_a7_initfn(Object *obj) 2370 { 2371 ARMCPU *cpu = ARM_CPU(obj); 2372 2373 cpu->dtb_compatible = "arm,cortex-a7"; 2374 set_feature(&cpu->env, ARM_FEATURE_V7VE); 2375 set_feature(&cpu->env, ARM_FEATURE_NEON); 2376 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2377 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 2378 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2379 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 2380 set_feature(&cpu->env, ARM_FEATURE_EL2); 2381 set_feature(&cpu->env, ARM_FEATURE_EL3); 2382 set_feature(&cpu->env, ARM_FEATURE_PMU); 2383 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 2384 cpu->midr = 0x410fc075; 2385 cpu->reset_fpsid = 0x41023075; 2386 cpu->isar.mvfr0 = 0x10110222; 2387 cpu->isar.mvfr1 = 0x11111111; 2388 cpu->ctr = 0x84448003; 2389 cpu->reset_sctlr = 0x00c50078; 2390 cpu->id_pfr0 = 0x00001131; 2391 cpu->id_pfr1 = 0x00011011; 2392 cpu->isar.id_dfr0 = 0x02010555; 2393 cpu->id_afr0 = 0x00000000; 2394 cpu->isar.id_mmfr0 = 0x10101105; 2395 cpu->isar.id_mmfr1 = 0x40000000; 2396 cpu->isar.id_mmfr2 = 0x01240000; 2397 cpu->isar.id_mmfr3 = 0x02102211; 2398 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but 2399 * table 4-41 gives 0x02101110, which includes the arm div insns. 2400 */ 2401 cpu->isar.id_isar0 = 0x02101110; 2402 cpu->isar.id_isar1 = 0x13112111; 2403 cpu->isar.id_isar2 = 0x21232041; 2404 cpu->isar.id_isar3 = 0x11112131; 2405 cpu->isar.id_isar4 = 0x10011142; 2406 cpu->isar.dbgdidr = 0x3515f005; 2407 cpu->clidr = 0x0a200023; 2408 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 2409 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 2410 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 2411 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 2412 } 2413 2414 static void cortex_a15_initfn(Object *obj) 2415 { 2416 ARMCPU *cpu = ARM_CPU(obj); 2417 2418 cpu->dtb_compatible = "arm,cortex-a15"; 2419 set_feature(&cpu->env, ARM_FEATURE_V7VE); 2420 set_feature(&cpu->env, ARM_FEATURE_NEON); 2421 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2422 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 2423 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2424 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 2425 set_feature(&cpu->env, ARM_FEATURE_EL2); 2426 set_feature(&cpu->env, ARM_FEATURE_EL3); 2427 set_feature(&cpu->env, ARM_FEATURE_PMU); 2428 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 2429 cpu->midr = 0x412fc0f1; 2430 cpu->reset_fpsid = 0x410430f0; 2431 cpu->isar.mvfr0 = 0x10110222; 2432 cpu->isar.mvfr1 = 0x11111111; 2433 cpu->ctr = 0x8444c004; 2434 cpu->reset_sctlr = 0x00c50078; 2435 cpu->id_pfr0 = 0x00001131; 2436 cpu->id_pfr1 = 0x00011011; 2437 cpu->isar.id_dfr0 = 0x02010555; 2438 cpu->id_afr0 = 0x00000000; 2439 cpu->isar.id_mmfr0 = 0x10201105; 2440 cpu->isar.id_mmfr1 = 0x20000000; 2441 cpu->isar.id_mmfr2 = 0x01240000; 2442 cpu->isar.id_mmfr3 = 0x02102211; 2443 cpu->isar.id_isar0 = 0x02101110; 2444 cpu->isar.id_isar1 = 0x13112111; 2445 cpu->isar.id_isar2 = 0x21232041; 2446 cpu->isar.id_isar3 = 0x11112131; 2447 cpu->isar.id_isar4 = 0x10011142; 2448 cpu->isar.dbgdidr = 0x3515f021; 2449 cpu->clidr = 0x0a200023; 2450 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 2451 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 2452 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 2453 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 2454 } 2455 2456 static void ti925t_initfn(Object *obj) 2457 { 2458 ARMCPU *cpu = ARM_CPU(obj); 2459 set_feature(&cpu->env, ARM_FEATURE_V4T); 2460 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 2461 cpu->midr = ARM_CPUID_TI925T; 2462 cpu->ctr = 0x5109149; 2463 cpu->reset_sctlr = 0x00000070; 2464 } 2465 2466 static void sa1100_initfn(Object *obj) 2467 { 2468 ARMCPU *cpu = ARM_CPU(obj); 2469 2470 cpu->dtb_compatible = "intel,sa1100"; 2471 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 2472 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2473 cpu->midr = 0x4401A11B; 2474 cpu->reset_sctlr = 0x00000070; 2475 } 2476 2477 static void sa1110_initfn(Object *obj) 2478 { 2479 ARMCPU *cpu = ARM_CPU(obj); 2480 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 2481 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2482 cpu->midr = 0x6901B119; 2483 cpu->reset_sctlr = 0x00000070; 2484 } 2485 2486 static void pxa250_initfn(Object *obj) 2487 { 2488 ARMCPU *cpu = ARM_CPU(obj); 2489 2490 cpu->dtb_compatible = "marvell,xscale"; 2491 set_feature(&cpu->env, ARM_FEATURE_V5); 2492 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2493 cpu->midr = 0x69052100; 2494 cpu->ctr = 0xd172172; 2495 cpu->reset_sctlr = 0x00000078; 2496 } 2497 2498 static void pxa255_initfn(Object *obj) 2499 { 2500 ARMCPU *cpu = ARM_CPU(obj); 2501 2502 cpu->dtb_compatible = "marvell,xscale"; 2503 set_feature(&cpu->env, ARM_FEATURE_V5); 2504 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2505 cpu->midr = 0x69052d00; 2506 cpu->ctr = 0xd172172; 2507 cpu->reset_sctlr = 0x00000078; 2508 } 2509 2510 static void pxa260_initfn(Object *obj) 2511 { 2512 ARMCPU *cpu = ARM_CPU(obj); 2513 2514 cpu->dtb_compatible = "marvell,xscale"; 2515 set_feature(&cpu->env, ARM_FEATURE_V5); 2516 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2517 cpu->midr = 0x69052903; 2518 cpu->ctr = 0xd172172; 2519 cpu->reset_sctlr = 0x00000078; 2520 } 2521 2522 static void pxa261_initfn(Object *obj) 2523 { 2524 ARMCPU *cpu = ARM_CPU(obj); 2525 2526 cpu->dtb_compatible = "marvell,xscale"; 2527 set_feature(&cpu->env, ARM_FEATURE_V5); 2528 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2529 cpu->midr = 0x69052d05; 2530 cpu->ctr = 0xd172172; 2531 cpu->reset_sctlr = 0x00000078; 2532 } 2533 2534 static void pxa262_initfn(Object *obj) 2535 { 2536 ARMCPU *cpu = ARM_CPU(obj); 2537 2538 cpu->dtb_compatible = "marvell,xscale"; 2539 set_feature(&cpu->env, ARM_FEATURE_V5); 2540 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2541 cpu->midr = 0x69052d06; 2542 cpu->ctr = 0xd172172; 2543 cpu->reset_sctlr = 0x00000078; 2544 } 2545 2546 static void pxa270a0_initfn(Object *obj) 2547 { 2548 ARMCPU *cpu = ARM_CPU(obj); 2549 2550 cpu->dtb_compatible = "marvell,xscale"; 2551 set_feature(&cpu->env, ARM_FEATURE_V5); 2552 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2553 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2554 cpu->midr = 0x69054110; 2555 cpu->ctr = 0xd172172; 2556 cpu->reset_sctlr = 0x00000078; 2557 } 2558 2559 static void pxa270a1_initfn(Object *obj) 2560 { 2561 ARMCPU *cpu = ARM_CPU(obj); 2562 2563 cpu->dtb_compatible = "marvell,xscale"; 2564 set_feature(&cpu->env, ARM_FEATURE_V5); 2565 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2566 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2567 cpu->midr = 0x69054111; 2568 cpu->ctr = 0xd172172; 2569 cpu->reset_sctlr = 0x00000078; 2570 } 2571 2572 static void pxa270b0_initfn(Object *obj) 2573 { 2574 ARMCPU *cpu = ARM_CPU(obj); 2575 2576 cpu->dtb_compatible = "marvell,xscale"; 2577 set_feature(&cpu->env, ARM_FEATURE_V5); 2578 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2579 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2580 cpu->midr = 0x69054112; 2581 cpu->ctr = 0xd172172; 2582 cpu->reset_sctlr = 0x00000078; 2583 } 2584 2585 static void pxa270b1_initfn(Object *obj) 2586 { 2587 ARMCPU *cpu = ARM_CPU(obj); 2588 2589 cpu->dtb_compatible = "marvell,xscale"; 2590 set_feature(&cpu->env, ARM_FEATURE_V5); 2591 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2592 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2593 cpu->midr = 0x69054113; 2594 cpu->ctr = 0xd172172; 2595 cpu->reset_sctlr = 0x00000078; 2596 } 2597 2598 static void pxa270c0_initfn(Object *obj) 2599 { 2600 ARMCPU *cpu = ARM_CPU(obj); 2601 2602 cpu->dtb_compatible = "marvell,xscale"; 2603 set_feature(&cpu->env, ARM_FEATURE_V5); 2604 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2605 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2606 cpu->midr = 0x69054114; 2607 cpu->ctr = 0xd172172; 2608 cpu->reset_sctlr = 0x00000078; 2609 } 2610 2611 static void pxa270c5_initfn(Object *obj) 2612 { 2613 ARMCPU *cpu = ARM_CPU(obj); 2614 2615 cpu->dtb_compatible = "marvell,xscale"; 2616 set_feature(&cpu->env, ARM_FEATURE_V5); 2617 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2618 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2619 cpu->midr = 0x69054117; 2620 cpu->ctr = 0xd172172; 2621 cpu->reset_sctlr = 0x00000078; 2622 } 2623 2624 #ifndef TARGET_AARCH64 2625 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 2626 * otherwise, a CPU with as many features enabled as our emulation supports. 2627 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; 2628 * this only needs to handle 32 bits. 2629 */ 2630 static void arm_max_initfn(Object *obj) 2631 { 2632 ARMCPU *cpu = ARM_CPU(obj); 2633 2634 if (kvm_enabled()) { 2635 kvm_arm_set_cpu_features_from_host(cpu); 2636 kvm_arm_add_vcpu_properties(obj); 2637 } else { 2638 cortex_a15_initfn(obj); 2639 2640 /* old-style VFP short-vector support */ 2641 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 2642 2643 #ifdef CONFIG_USER_ONLY 2644 /* We don't set these in system emulation mode for the moment, 2645 * since we don't correctly set (all of) the ID registers to 2646 * advertise them. 2647 */ 2648 set_feature(&cpu->env, ARM_FEATURE_V8); 2649 { 2650 uint32_t t; 2651 2652 t = cpu->isar.id_isar5; 2653 t = FIELD_DP32(t, ID_ISAR5, AES, 2); 2654 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); 2655 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); 2656 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); 2657 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); 2658 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); 2659 cpu->isar.id_isar5 = t; 2660 2661 t = cpu->isar.id_isar6; 2662 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); 2663 t = FIELD_DP32(t, ID_ISAR6, DP, 1); 2664 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); 2665 t = FIELD_DP32(t, ID_ISAR6, SB, 1); 2666 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); 2667 cpu->isar.id_isar6 = t; 2668 2669 t = cpu->isar.mvfr1; 2670 t = FIELD_DP32(t, MVFR1, FPHP, 2); /* v8.0 FP support */ 2671 cpu->isar.mvfr1 = t; 2672 2673 t = cpu->isar.mvfr2; 2674 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ 2675 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ 2676 cpu->isar.mvfr2 = t; 2677 2678 t = cpu->isar.id_mmfr3; 2679 t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ 2680 cpu->isar.id_mmfr3 = t; 2681 2682 t = cpu->isar.id_mmfr4; 2683 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ 2684 t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ 2685 t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ 2686 cpu->isar.id_mmfr4 = t; 2687 } 2688 #endif 2689 } 2690 } 2691 #endif 2692 2693 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 2694 2695 struct ARMCPUInfo { 2696 const char *name; 2697 void (*initfn)(Object *obj); 2698 void (*class_init)(ObjectClass *oc, void *data); 2699 }; 2700 2701 static const ARMCPUInfo arm_cpus[] = { 2702 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 2703 { .name = "arm926", .initfn = arm926_initfn }, 2704 { .name = "arm946", .initfn = arm946_initfn }, 2705 { .name = "arm1026", .initfn = arm1026_initfn }, 2706 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 2707 * older core than plain "arm1136". In particular this does not 2708 * have the v6K features. 2709 */ 2710 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 2711 { .name = "arm1136", .initfn = arm1136_initfn }, 2712 { .name = "arm1176", .initfn = arm1176_initfn }, 2713 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 2714 { .name = "cortex-m0", .initfn = cortex_m0_initfn, 2715 .class_init = arm_v7m_class_init }, 2716 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 2717 .class_init = arm_v7m_class_init }, 2718 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 2719 .class_init = arm_v7m_class_init }, 2720 { .name = "cortex-m7", .initfn = cortex_m7_initfn, 2721 .class_init = arm_v7m_class_init }, 2722 { .name = "cortex-m33", .initfn = cortex_m33_initfn, 2723 .class_init = arm_v7m_class_init }, 2724 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 2725 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, 2726 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 2727 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 2728 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 2729 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 2730 { .name = "ti925t", .initfn = ti925t_initfn }, 2731 { .name = "sa1100", .initfn = sa1100_initfn }, 2732 { .name = "sa1110", .initfn = sa1110_initfn }, 2733 { .name = "pxa250", .initfn = pxa250_initfn }, 2734 { .name = "pxa255", .initfn = pxa255_initfn }, 2735 { .name = "pxa260", .initfn = pxa260_initfn }, 2736 { .name = "pxa261", .initfn = pxa261_initfn }, 2737 { .name = "pxa262", .initfn = pxa262_initfn }, 2738 /* "pxa270" is an alias for "pxa270-a0" */ 2739 { .name = "pxa270", .initfn = pxa270a0_initfn }, 2740 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 2741 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 2742 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 2743 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 2744 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 2745 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 2746 #ifndef TARGET_AARCH64 2747 { .name = "max", .initfn = arm_max_initfn }, 2748 #endif 2749 #ifdef CONFIG_USER_ONLY 2750 { .name = "any", .initfn = arm_max_initfn }, 2751 #endif 2752 #endif 2753 { .name = NULL } 2754 }; 2755 2756 static Property arm_cpu_properties[] = { 2757 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 2758 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 2759 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 2760 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2761 mp_affinity, ARM64_AFFINITY_INVALID), 2762 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2763 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2764 DEFINE_PROP_END_OF_LIST() 2765 }; 2766 2767 static gchar *arm_gdb_arch_name(CPUState *cs) 2768 { 2769 ARMCPU *cpu = ARM_CPU(cs); 2770 CPUARMState *env = &cpu->env; 2771 2772 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2773 return g_strdup("iwmmxt"); 2774 } 2775 return g_strdup("arm"); 2776 } 2777 2778 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2779 { 2780 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2781 CPUClass *cc = CPU_CLASS(acc); 2782 DeviceClass *dc = DEVICE_CLASS(oc); 2783 2784 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2785 &acc->parent_realize); 2786 2787 device_class_set_props(dc, arm_cpu_properties); 2788 device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); 2789 2790 cc->class_by_name = arm_cpu_class_by_name; 2791 cc->has_work = arm_cpu_has_work; 2792 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 2793 cc->dump_state = arm_cpu_dump_state; 2794 cc->set_pc = arm_cpu_set_pc; 2795 cc->synchronize_from_tb = arm_cpu_synchronize_from_tb; 2796 cc->gdb_read_register = arm_cpu_gdb_read_register; 2797 cc->gdb_write_register = arm_cpu_gdb_write_register; 2798 #ifndef CONFIG_USER_ONLY 2799 cc->do_interrupt = arm_cpu_do_interrupt; 2800 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 2801 cc->asidx_from_attrs = arm_asidx_from_attrs; 2802 cc->vmsd = &vmstate_arm_cpu; 2803 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 2804 cc->write_elf64_note = arm_cpu_write_elf64_note; 2805 cc->write_elf32_note = arm_cpu_write_elf32_note; 2806 #endif 2807 cc->gdb_num_core_regs = 26; 2808 cc->gdb_core_xml_file = "arm-core.xml"; 2809 cc->gdb_arch_name = arm_gdb_arch_name; 2810 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2811 cc->gdb_stop_before_watchpoint = true; 2812 cc->disas_set_info = arm_disas_set_info; 2813 #ifdef CONFIG_TCG 2814 cc->tcg_initialize = arm_translate_init; 2815 cc->tlb_fill = arm_cpu_tlb_fill; 2816 cc->debug_excp_handler = arm_debug_excp_handler; 2817 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 2818 #if !defined(CONFIG_USER_ONLY) 2819 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 2820 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 2821 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 2822 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 2823 #endif 2824 } 2825 2826 #ifdef CONFIG_KVM 2827 static void arm_host_initfn(Object *obj) 2828 { 2829 ARMCPU *cpu = ARM_CPU(obj); 2830 2831 kvm_arm_set_cpu_features_from_host(cpu); 2832 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 2833 aarch64_add_sve_properties(obj); 2834 } 2835 kvm_arm_add_vcpu_properties(obj); 2836 arm_cpu_post_init(obj); 2837 } 2838 2839 static const TypeInfo host_arm_cpu_type_info = { 2840 .name = TYPE_ARM_HOST_CPU, 2841 #ifdef TARGET_AARCH64 2842 .parent = TYPE_AARCH64_CPU, 2843 #else 2844 .parent = TYPE_ARM_CPU, 2845 #endif 2846 .instance_init = arm_host_initfn, 2847 }; 2848 2849 #endif 2850 2851 static void arm_cpu_instance_init(Object *obj) 2852 { 2853 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2854 2855 acc->info->initfn(obj); 2856 arm_cpu_post_init(obj); 2857 } 2858 2859 static void cpu_register_class_init(ObjectClass *oc, void *data) 2860 { 2861 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2862 2863 acc->info = data; 2864 } 2865 2866 static void cpu_register(const ARMCPUInfo *info) 2867 { 2868 TypeInfo type_info = { 2869 .parent = TYPE_ARM_CPU, 2870 .instance_size = sizeof(ARMCPU), 2871 .instance_init = arm_cpu_instance_init, 2872 .class_size = sizeof(ARMCPUClass), 2873 .class_init = info->class_init ?: cpu_register_class_init, 2874 .class_data = (void *)info, 2875 }; 2876 2877 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2878 type_register(&type_info); 2879 g_free((void *)type_info.name); 2880 } 2881 2882 static const TypeInfo arm_cpu_type_info = { 2883 .name = TYPE_ARM_CPU, 2884 .parent = TYPE_CPU, 2885 .instance_size = sizeof(ARMCPU), 2886 .instance_init = arm_cpu_initfn, 2887 .instance_finalize = arm_cpu_finalizefn, 2888 .abstract = true, 2889 .class_size = sizeof(ARMCPUClass), 2890 .class_init = arm_cpu_class_init, 2891 }; 2892 2893 static const TypeInfo idau_interface_type_info = { 2894 .name = TYPE_IDAU_INTERFACE, 2895 .parent = TYPE_INTERFACE, 2896 .class_size = sizeof(IDAUInterfaceClass), 2897 }; 2898 2899 static void arm_cpu_register_types(void) 2900 { 2901 const ARMCPUInfo *info = arm_cpus; 2902 2903 type_register_static(&arm_cpu_type_info); 2904 type_register_static(&idau_interface_type_info); 2905 2906 while (info->name) { 2907 cpu_register(info); 2908 info++; 2909 } 2910 2911 #ifdef CONFIG_KVM 2912 type_register_static(&host_arm_cpu_type_info); 2913 #endif 2914 } 2915 2916 type_init(arm_cpu_register_types) 2917