1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu-common.h" 24 #include "target/arm/idau.h" 25 #include "qemu/module.h" 26 #include "qapi/error.h" 27 #include "qapi/visitor.h" 28 #include "cpu.h" 29 #ifdef CONFIG_TCG 30 #include "hw/core/tcg-cpu-ops.h" 31 #endif /* CONFIG_TCG */ 32 #include "internals.h" 33 #include "exec/exec-all.h" 34 #include "hw/qdev-properties.h" 35 #if !defined(CONFIG_USER_ONLY) 36 #include "hw/loader.h" 37 #include "hw/boards.h" 38 #endif 39 #include "sysemu/tcg.h" 40 #include "sysemu/hw_accel.h" 41 #include "kvm_arm.h" 42 #include "disas/capstone.h" 43 #include "fpu/softfloat.h" 44 45 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 46 { 47 ARMCPU *cpu = ARM_CPU(cs); 48 CPUARMState *env = &cpu->env; 49 50 if (is_a64(env)) { 51 env->pc = value; 52 env->thumb = 0; 53 } else { 54 env->regs[15] = value & ~1; 55 env->thumb = value & 1; 56 } 57 } 58 59 #ifdef CONFIG_TCG 60 void arm_cpu_synchronize_from_tb(CPUState *cs, 61 const TranslationBlock *tb) 62 { 63 ARMCPU *cpu = ARM_CPU(cs); 64 CPUARMState *env = &cpu->env; 65 66 /* 67 * It's OK to look at env for the current mode here, because it's 68 * never possible for an AArch64 TB to chain to an AArch32 TB. 69 */ 70 if (is_a64(env)) { 71 env->pc = tb->pc; 72 } else { 73 env->regs[15] = tb->pc; 74 } 75 } 76 #endif /* CONFIG_TCG */ 77 78 static bool arm_cpu_has_work(CPUState *cs) 79 { 80 ARMCPU *cpu = ARM_CPU(cs); 81 82 return (cpu->power_state != PSCI_OFF) 83 && cs->interrupt_request & 84 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 85 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 86 | CPU_INTERRUPT_EXITTB); 87 } 88 89 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 90 void *opaque) 91 { 92 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 93 94 entry->hook = hook; 95 entry->opaque = opaque; 96 97 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 98 } 99 100 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 101 void *opaque) 102 { 103 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 104 105 entry->hook = hook; 106 entry->opaque = opaque; 107 108 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 109 } 110 111 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 112 { 113 /* Reset a single ARMCPRegInfo register */ 114 ARMCPRegInfo *ri = value; 115 ARMCPU *cpu = opaque; 116 117 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 118 return; 119 } 120 121 if (ri->resetfn) { 122 ri->resetfn(&cpu->env, ri); 123 return; 124 } 125 126 /* A zero offset is never possible as it would be regs[0] 127 * so we use it to indicate that reset is being handled elsewhere. 128 * This is basically only used for fields in non-core coprocessors 129 * (like the pxa2xx ones). 130 */ 131 if (!ri->fieldoffset) { 132 return; 133 } 134 135 if (cpreg_field_is_64bit(ri)) { 136 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 137 } else { 138 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 139 } 140 } 141 142 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 143 { 144 /* Purely an assertion check: we've already done reset once, 145 * so now check that running the reset for the cpreg doesn't 146 * change its value. This traps bugs where two different cpregs 147 * both try to reset the same state field but to different values. 148 */ 149 ARMCPRegInfo *ri = value; 150 ARMCPU *cpu = opaque; 151 uint64_t oldvalue, newvalue; 152 153 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 154 return; 155 } 156 157 oldvalue = read_raw_cp_reg(&cpu->env, ri); 158 cp_reg_reset(key, value, opaque); 159 newvalue = read_raw_cp_reg(&cpu->env, ri); 160 assert(oldvalue == newvalue); 161 } 162 163 static void arm_cpu_reset(DeviceState *dev) 164 { 165 CPUState *s = CPU(dev); 166 ARMCPU *cpu = ARM_CPU(s); 167 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 168 CPUARMState *env = &cpu->env; 169 170 acc->parent_reset(dev); 171 172 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 173 174 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 175 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 176 177 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 178 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 179 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 180 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 181 182 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; 183 184 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 185 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 186 } 187 188 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 189 /* 64 bit CPUs always start in 64 bit mode */ 190 env->aarch64 = 1; 191 #if defined(CONFIG_USER_ONLY) 192 env->pstate = PSTATE_MODE_EL0t; 193 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 194 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 195 /* Enable all PAC keys. */ 196 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 197 SCTLR_EnDA | SCTLR_EnDB); 198 /* and to the FP/Neon instructions */ 199 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 200 /* and to the SVE instructions */ 201 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 202 /* with reasonable vector length */ 203 if (cpu_isar_feature(aa64_sve, cpu)) { 204 env->vfp.zcr_el[1] = MIN(cpu->sve_max_vq - 1, 3); 205 } 206 /* 207 * Enable TBI0 but not TBI1. 208 * Note that this must match useronly_clean_ptr. 209 */ 210 env->cp15.tcr_el[1].raw_tcr = (1ULL << 37); 211 212 /* Enable MTE */ 213 if (cpu_isar_feature(aa64_mte, cpu)) { 214 /* Enable tag access, but leave TCF0 as No Effect (0). */ 215 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 216 /* 217 * Exclude all tags, so that tag 0 is always used. 218 * This corresponds to Linux current->thread.gcr_incl = 0. 219 * 220 * Set RRND, so that helper_irg() will generate a seed later. 221 * Here in cpu_reset(), the crypto subsystem has not yet been 222 * initialized. 223 */ 224 env->cp15.gcr_el1 = 0x1ffff; 225 } 226 #else 227 /* Reset into the highest available EL */ 228 if (arm_feature(env, ARM_FEATURE_EL3)) { 229 env->pstate = PSTATE_MODE_EL3h; 230 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 231 env->pstate = PSTATE_MODE_EL2h; 232 } else { 233 env->pstate = PSTATE_MODE_EL1h; 234 } 235 env->pc = cpu->rvbar; 236 #endif 237 } else { 238 #if defined(CONFIG_USER_ONLY) 239 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 240 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 241 #endif 242 } 243 244 #if defined(CONFIG_USER_ONLY) 245 env->uncached_cpsr = ARM_CPU_MODE_USR; 246 /* For user mode we must enable access to coprocessors */ 247 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 248 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 249 env->cp15.c15_cpar = 3; 250 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 251 env->cp15.c15_cpar = 1; 252 } 253 #else 254 255 /* 256 * If the highest available EL is EL2, AArch32 will start in Hyp 257 * mode; otherwise it starts in SVC. Note that if we start in 258 * AArch64 then these values in the uncached_cpsr will be ignored. 259 */ 260 if (arm_feature(env, ARM_FEATURE_EL2) && 261 !arm_feature(env, ARM_FEATURE_EL3)) { 262 env->uncached_cpsr = ARM_CPU_MODE_HYP; 263 } else { 264 env->uncached_cpsr = ARM_CPU_MODE_SVC; 265 } 266 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 267 268 if (arm_feature(env, ARM_FEATURE_M)) { 269 uint32_t initial_msp; /* Loaded from 0x0 */ 270 uint32_t initial_pc; /* Loaded from 0x4 */ 271 uint8_t *rom; 272 uint32_t vecbase; 273 274 if (cpu_isar_feature(aa32_lob, cpu)) { 275 /* 276 * LTPSIZE is constant 4 if MVE not implemented, and resets 277 * to an UNKNOWN value if MVE is implemented. We choose to 278 * always reset to 4. 279 */ 280 env->v7m.ltpsize = 4; 281 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 282 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 283 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 284 } 285 286 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 287 env->v7m.secure = true; 288 } else { 289 /* This bit resets to 0 if security is supported, but 1 if 290 * it is not. The bit is not present in v7M, but we set it 291 * here so we can avoid having to make checks on it conditional 292 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 293 */ 294 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 295 /* 296 * Set NSACR to indicate "NS access permitted to everything"; 297 * this avoids having to have all the tests of it being 298 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 299 * v8.1M the guest-visible value of NSACR in a CPU without the 300 * Security Extension is 0xcff. 301 */ 302 env->v7m.nsacr = 0xcff; 303 } 304 305 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 306 * that it resets to 1, so QEMU always does that rather than making 307 * it dependent on CPU model. In v8M it is RES1. 308 */ 309 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 310 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 311 if (arm_feature(env, ARM_FEATURE_V8)) { 312 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 313 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 314 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 315 } 316 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 317 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 318 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 319 } 320 321 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 322 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 323 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 324 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 325 } 326 /* Unlike A/R profile, M profile defines the reset LR value */ 327 env->regs[14] = 0xffffffff; 328 329 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 330 331 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 332 vecbase = env->v7m.vecbase[env->v7m.secure]; 333 rom = rom_ptr_for_as(s->as, vecbase, 8); 334 if (rom) { 335 /* Address zero is covered by ROM which hasn't yet been 336 * copied into physical memory. 337 */ 338 initial_msp = ldl_p(rom); 339 initial_pc = ldl_p(rom + 4); 340 } else { 341 /* Address zero not covered by a ROM blob, or the ROM blob 342 * is in non-modifiable memory and this is a second reset after 343 * it got copied into memory. In the latter case, rom_ptr 344 * will return a NULL pointer and we should use ldl_phys instead. 345 */ 346 initial_msp = ldl_phys(s->as, vecbase); 347 initial_pc = ldl_phys(s->as, vecbase + 4); 348 } 349 350 env->regs[13] = initial_msp & 0xFFFFFFFC; 351 env->regs[15] = initial_pc & ~1; 352 env->thumb = initial_pc & 1; 353 } 354 355 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 356 * executing as AArch32 then check if highvecs are enabled and 357 * adjust the PC accordingly. 358 */ 359 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 360 env->regs[15] = 0xFFFF0000; 361 } 362 363 /* M profile requires that reset clears the exclusive monitor; 364 * A profile does not, but clearing it makes more sense than having it 365 * set with an exclusive access on address zero. 366 */ 367 arm_clear_exclusive(env); 368 369 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 370 #endif 371 372 if (arm_feature(env, ARM_FEATURE_PMSA)) { 373 if (cpu->pmsav7_dregion > 0) { 374 if (arm_feature(env, ARM_FEATURE_V8)) { 375 memset(env->pmsav8.rbar[M_REG_NS], 0, 376 sizeof(*env->pmsav8.rbar[M_REG_NS]) 377 * cpu->pmsav7_dregion); 378 memset(env->pmsav8.rlar[M_REG_NS], 0, 379 sizeof(*env->pmsav8.rlar[M_REG_NS]) 380 * cpu->pmsav7_dregion); 381 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 382 memset(env->pmsav8.rbar[M_REG_S], 0, 383 sizeof(*env->pmsav8.rbar[M_REG_S]) 384 * cpu->pmsav7_dregion); 385 memset(env->pmsav8.rlar[M_REG_S], 0, 386 sizeof(*env->pmsav8.rlar[M_REG_S]) 387 * cpu->pmsav7_dregion); 388 } 389 } else if (arm_feature(env, ARM_FEATURE_V7)) { 390 memset(env->pmsav7.drbar, 0, 391 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 392 memset(env->pmsav7.drsr, 0, 393 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 394 memset(env->pmsav7.dracr, 0, 395 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 396 } 397 } 398 env->pmsav7.rnr[M_REG_NS] = 0; 399 env->pmsav7.rnr[M_REG_S] = 0; 400 env->pmsav8.mair0[M_REG_NS] = 0; 401 env->pmsav8.mair0[M_REG_S] = 0; 402 env->pmsav8.mair1[M_REG_NS] = 0; 403 env->pmsav8.mair1[M_REG_S] = 0; 404 } 405 406 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 407 if (cpu->sau_sregion > 0) { 408 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 409 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 410 } 411 env->sau.rnr = 0; 412 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 413 * the Cortex-M33 does. 414 */ 415 env->sau.ctrl = 0; 416 } 417 418 set_flush_to_zero(1, &env->vfp.standard_fp_status); 419 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 420 set_default_nan_mode(1, &env->vfp.standard_fp_status); 421 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); 422 set_float_detect_tininess(float_tininess_before_rounding, 423 &env->vfp.fp_status); 424 set_float_detect_tininess(float_tininess_before_rounding, 425 &env->vfp.standard_fp_status); 426 set_float_detect_tininess(float_tininess_before_rounding, 427 &env->vfp.fp_status_f16); 428 set_float_detect_tininess(float_tininess_before_rounding, 429 &env->vfp.standard_fp_status_f16); 430 #ifndef CONFIG_USER_ONLY 431 if (kvm_enabled()) { 432 kvm_arm_reset_vcpu(cpu); 433 } 434 #endif 435 436 hw_breakpoint_update_all(cpu); 437 hw_watchpoint_update_all(cpu); 438 arm_rebuild_hflags(env); 439 } 440 441 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 442 unsigned int target_el, 443 unsigned int cur_el, bool secure, 444 uint64_t hcr_el2) 445 { 446 CPUARMState *env = cs->env_ptr; 447 bool pstate_unmasked; 448 bool unmasked = false; 449 450 /* 451 * Don't take exceptions if they target a lower EL. 452 * This check should catch any exceptions that would not be taken 453 * but left pending. 454 */ 455 if (cur_el > target_el) { 456 return false; 457 } 458 459 switch (excp_idx) { 460 case EXCP_FIQ: 461 pstate_unmasked = !(env->daif & PSTATE_F); 462 break; 463 464 case EXCP_IRQ: 465 pstate_unmasked = !(env->daif & PSTATE_I); 466 break; 467 468 case EXCP_VFIQ: 469 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 470 /* VFIQs are only taken when hypervized. */ 471 return false; 472 } 473 return !(env->daif & PSTATE_F); 474 case EXCP_VIRQ: 475 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 476 /* VIRQs are only taken when hypervized. */ 477 return false; 478 } 479 return !(env->daif & PSTATE_I); 480 default: 481 g_assert_not_reached(); 482 } 483 484 /* 485 * Use the target EL, current execution state and SCR/HCR settings to 486 * determine whether the corresponding CPSR bit is used to mask the 487 * interrupt. 488 */ 489 if ((target_el > cur_el) && (target_el != 1)) { 490 /* Exceptions targeting a higher EL may not be maskable */ 491 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 492 /* 493 * 64-bit masking rules are simple: exceptions to EL3 494 * can't be masked, and exceptions to EL2 can only be 495 * masked from Secure state. The HCR and SCR settings 496 * don't affect the masking logic, only the interrupt routing. 497 */ 498 if (target_el == 3 || !secure || (env->cp15.scr_el3 & SCR_EEL2)) { 499 unmasked = true; 500 } 501 } else { 502 /* 503 * The old 32-bit-only environment has a more complicated 504 * masking setup. HCR and SCR bits not only affect interrupt 505 * routing but also change the behaviour of masking. 506 */ 507 bool hcr, scr; 508 509 switch (excp_idx) { 510 case EXCP_FIQ: 511 /* 512 * If FIQs are routed to EL3 or EL2 then there are cases where 513 * we override the CPSR.F in determining if the exception is 514 * masked or not. If neither of these are set then we fall back 515 * to the CPSR.F setting otherwise we further assess the state 516 * below. 517 */ 518 hcr = hcr_el2 & HCR_FMO; 519 scr = (env->cp15.scr_el3 & SCR_FIQ); 520 521 /* 522 * When EL3 is 32-bit, the SCR.FW bit controls whether the 523 * CPSR.F bit masks FIQ interrupts when taken in non-secure 524 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 525 * when non-secure but only when FIQs are only routed to EL3. 526 */ 527 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 528 break; 529 case EXCP_IRQ: 530 /* 531 * When EL3 execution state is 32-bit, if HCR.IMO is set then 532 * we may override the CPSR.I masking when in non-secure state. 533 * The SCR.IRQ setting has already been taken into consideration 534 * when setting the target EL, so it does not have a further 535 * affect here. 536 */ 537 hcr = hcr_el2 & HCR_IMO; 538 scr = false; 539 break; 540 default: 541 g_assert_not_reached(); 542 } 543 544 if ((scr || hcr) && !secure) { 545 unmasked = true; 546 } 547 } 548 } 549 550 /* 551 * The PSTATE bits only mask the interrupt if we have not overriden the 552 * ability above. 553 */ 554 return unmasked || pstate_unmasked; 555 } 556 557 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 558 { 559 CPUClass *cc = CPU_GET_CLASS(cs); 560 CPUARMState *env = cs->env_ptr; 561 uint32_t cur_el = arm_current_el(env); 562 bool secure = arm_is_secure(env); 563 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 564 uint32_t target_el; 565 uint32_t excp_idx; 566 567 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 568 569 if (interrupt_request & CPU_INTERRUPT_FIQ) { 570 excp_idx = EXCP_FIQ; 571 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 572 if (arm_excp_unmasked(cs, excp_idx, target_el, 573 cur_el, secure, hcr_el2)) { 574 goto found; 575 } 576 } 577 if (interrupt_request & CPU_INTERRUPT_HARD) { 578 excp_idx = EXCP_IRQ; 579 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 580 if (arm_excp_unmasked(cs, excp_idx, target_el, 581 cur_el, secure, hcr_el2)) { 582 goto found; 583 } 584 } 585 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 586 excp_idx = EXCP_VIRQ; 587 target_el = 1; 588 if (arm_excp_unmasked(cs, excp_idx, target_el, 589 cur_el, secure, hcr_el2)) { 590 goto found; 591 } 592 } 593 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 594 excp_idx = EXCP_VFIQ; 595 target_el = 1; 596 if (arm_excp_unmasked(cs, excp_idx, target_el, 597 cur_el, secure, hcr_el2)) { 598 goto found; 599 } 600 } 601 return false; 602 603 found: 604 cs->exception_index = excp_idx; 605 env->exception.target_el = target_el; 606 cc->tcg_ops->do_interrupt(cs); 607 return true; 608 } 609 610 void arm_cpu_update_virq(ARMCPU *cpu) 611 { 612 /* 613 * Update the interrupt level for VIRQ, which is the logical OR of 614 * the HCR_EL2.VI bit and the input line level from the GIC. 615 */ 616 CPUARMState *env = &cpu->env; 617 CPUState *cs = CPU(cpu); 618 619 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 620 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 621 622 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 623 if (new_state) { 624 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 625 } else { 626 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 627 } 628 } 629 } 630 631 void arm_cpu_update_vfiq(ARMCPU *cpu) 632 { 633 /* 634 * Update the interrupt level for VFIQ, which is the logical OR of 635 * the HCR_EL2.VF bit and the input line level from the GIC. 636 */ 637 CPUARMState *env = &cpu->env; 638 CPUState *cs = CPU(cpu); 639 640 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 641 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 642 643 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 644 if (new_state) { 645 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 646 } else { 647 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 648 } 649 } 650 } 651 652 #ifndef CONFIG_USER_ONLY 653 static void arm_cpu_set_irq(void *opaque, int irq, int level) 654 { 655 ARMCPU *cpu = opaque; 656 CPUARMState *env = &cpu->env; 657 CPUState *cs = CPU(cpu); 658 static const int mask[] = { 659 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 660 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 661 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 662 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 663 }; 664 665 if (level) { 666 env->irq_line_state |= mask[irq]; 667 } else { 668 env->irq_line_state &= ~mask[irq]; 669 } 670 671 switch (irq) { 672 case ARM_CPU_VIRQ: 673 assert(arm_feature(env, ARM_FEATURE_EL2)); 674 arm_cpu_update_virq(cpu); 675 break; 676 case ARM_CPU_VFIQ: 677 assert(arm_feature(env, ARM_FEATURE_EL2)); 678 arm_cpu_update_vfiq(cpu); 679 break; 680 case ARM_CPU_IRQ: 681 case ARM_CPU_FIQ: 682 if (level) { 683 cpu_interrupt(cs, mask[irq]); 684 } else { 685 cpu_reset_interrupt(cs, mask[irq]); 686 } 687 break; 688 default: 689 g_assert_not_reached(); 690 } 691 } 692 693 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 694 { 695 #ifdef CONFIG_KVM 696 ARMCPU *cpu = opaque; 697 CPUARMState *env = &cpu->env; 698 CPUState *cs = CPU(cpu); 699 uint32_t linestate_bit; 700 int irq_id; 701 702 switch (irq) { 703 case ARM_CPU_IRQ: 704 irq_id = KVM_ARM_IRQ_CPU_IRQ; 705 linestate_bit = CPU_INTERRUPT_HARD; 706 break; 707 case ARM_CPU_FIQ: 708 irq_id = KVM_ARM_IRQ_CPU_FIQ; 709 linestate_bit = CPU_INTERRUPT_FIQ; 710 break; 711 default: 712 g_assert_not_reached(); 713 } 714 715 if (level) { 716 env->irq_line_state |= linestate_bit; 717 } else { 718 env->irq_line_state &= ~linestate_bit; 719 } 720 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 721 #endif 722 } 723 724 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 725 { 726 ARMCPU *cpu = ARM_CPU(cs); 727 CPUARMState *env = &cpu->env; 728 729 cpu_synchronize_state(cs); 730 return arm_cpu_data_is_big_endian(env); 731 } 732 733 #endif 734 735 static int 736 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 737 { 738 return print_insn_arm(pc | 1, info); 739 } 740 741 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 742 { 743 ARMCPU *ac = ARM_CPU(cpu); 744 CPUARMState *env = &ac->env; 745 bool sctlr_b; 746 747 if (is_a64(env)) { 748 /* We might not be compiled with the A64 disassembler 749 * because it needs a C++ compiler. Leave print_insn 750 * unset in this case to use the caller default behaviour. 751 */ 752 #if defined(CONFIG_ARM_A64_DIS) 753 info->print_insn = print_insn_arm_a64; 754 #endif 755 info->cap_arch = CS_ARCH_ARM64; 756 info->cap_insn_unit = 4; 757 info->cap_insn_split = 4; 758 } else { 759 int cap_mode; 760 if (env->thumb) { 761 info->print_insn = print_insn_thumb1; 762 info->cap_insn_unit = 2; 763 info->cap_insn_split = 4; 764 cap_mode = CS_MODE_THUMB; 765 } else { 766 info->print_insn = print_insn_arm; 767 info->cap_insn_unit = 4; 768 info->cap_insn_split = 4; 769 cap_mode = CS_MODE_ARM; 770 } 771 if (arm_feature(env, ARM_FEATURE_V8)) { 772 cap_mode |= CS_MODE_V8; 773 } 774 if (arm_feature(env, ARM_FEATURE_M)) { 775 cap_mode |= CS_MODE_MCLASS; 776 } 777 info->cap_arch = CS_ARCH_ARM; 778 info->cap_mode = cap_mode; 779 } 780 781 sctlr_b = arm_sctlr_b(env); 782 if (bswap_code(sctlr_b)) { 783 #ifdef TARGET_WORDS_BIGENDIAN 784 info->endian = BFD_ENDIAN_LITTLE; 785 #else 786 info->endian = BFD_ENDIAN_BIG; 787 #endif 788 } 789 info->flags &= ~INSN_ARM_BE32; 790 #ifndef CONFIG_USER_ONLY 791 if (sctlr_b) { 792 info->flags |= INSN_ARM_BE32; 793 } 794 #endif 795 } 796 797 #ifdef TARGET_AARCH64 798 799 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 800 { 801 ARMCPU *cpu = ARM_CPU(cs); 802 CPUARMState *env = &cpu->env; 803 uint32_t psr = pstate_read(env); 804 int i; 805 int el = arm_current_el(env); 806 const char *ns_status; 807 808 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 809 for (i = 0; i < 32; i++) { 810 if (i == 31) { 811 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 812 } else { 813 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 814 (i + 2) % 3 ? " " : "\n"); 815 } 816 } 817 818 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 819 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 820 } else { 821 ns_status = ""; 822 } 823 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 824 psr, 825 psr & PSTATE_N ? 'N' : '-', 826 psr & PSTATE_Z ? 'Z' : '-', 827 psr & PSTATE_C ? 'C' : '-', 828 psr & PSTATE_V ? 'V' : '-', 829 ns_status, 830 el, 831 psr & PSTATE_SP ? 'h' : 't'); 832 833 if (cpu_isar_feature(aa64_bti, cpu)) { 834 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 835 } 836 if (!(flags & CPU_DUMP_FPU)) { 837 qemu_fprintf(f, "\n"); 838 return; 839 } 840 if (fp_exception_el(env, el) != 0) { 841 qemu_fprintf(f, " FPU disabled\n"); 842 return; 843 } 844 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 845 vfp_get_fpcr(env), vfp_get_fpsr(env)); 846 847 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { 848 int j, zcr_len = sve_zcr_len_for_el(env, el); 849 850 for (i = 0; i <= FFR_PRED_NUM; i++) { 851 bool eol; 852 if (i == FFR_PRED_NUM) { 853 qemu_fprintf(f, "FFR="); 854 /* It's last, so end the line. */ 855 eol = true; 856 } else { 857 qemu_fprintf(f, "P%02d=", i); 858 switch (zcr_len) { 859 case 0: 860 eol = i % 8 == 7; 861 break; 862 case 1: 863 eol = i % 6 == 5; 864 break; 865 case 2: 866 case 3: 867 eol = i % 3 == 2; 868 break; 869 default: 870 /* More than one quadword per predicate. */ 871 eol = true; 872 break; 873 } 874 } 875 for (j = zcr_len / 4; j >= 0; j--) { 876 int digits; 877 if (j * 4 + 4 <= zcr_len + 1) { 878 digits = 16; 879 } else { 880 digits = (zcr_len % 4 + 1) * 4; 881 } 882 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 883 env->vfp.pregs[i].p[j], 884 j ? ":" : eol ? "\n" : " "); 885 } 886 } 887 888 for (i = 0; i < 32; i++) { 889 if (zcr_len == 0) { 890 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 891 i, env->vfp.zregs[i].d[1], 892 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 893 } else if (zcr_len == 1) { 894 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 895 ":%016" PRIx64 ":%016" PRIx64 "\n", 896 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 897 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 898 } else { 899 for (j = zcr_len; j >= 0; j--) { 900 bool odd = (zcr_len - j) % 2 != 0; 901 if (j == zcr_len) { 902 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 903 } else if (!odd) { 904 if (j > 0) { 905 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 906 } else { 907 qemu_fprintf(f, " [%x]=", j); 908 } 909 } 910 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 911 env->vfp.zregs[i].d[j * 2 + 1], 912 env->vfp.zregs[i].d[j * 2], 913 odd || j == 0 ? "\n" : ":"); 914 } 915 } 916 } 917 } else { 918 for (i = 0; i < 32; i++) { 919 uint64_t *q = aa64_vfp_qreg(env, i); 920 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 921 i, q[1], q[0], (i & 1 ? "\n" : " ")); 922 } 923 } 924 } 925 926 #else 927 928 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 929 { 930 g_assert_not_reached(); 931 } 932 933 #endif 934 935 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 936 { 937 ARMCPU *cpu = ARM_CPU(cs); 938 CPUARMState *env = &cpu->env; 939 int i; 940 941 if (is_a64(env)) { 942 aarch64_cpu_dump_state(cs, f, flags); 943 return; 944 } 945 946 for (i = 0; i < 16; i++) { 947 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 948 if ((i % 4) == 3) { 949 qemu_fprintf(f, "\n"); 950 } else { 951 qemu_fprintf(f, " "); 952 } 953 } 954 955 if (arm_feature(env, ARM_FEATURE_M)) { 956 uint32_t xpsr = xpsr_read(env); 957 const char *mode; 958 const char *ns_status = ""; 959 960 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 961 ns_status = env->v7m.secure ? "S " : "NS "; 962 } 963 964 if (xpsr & XPSR_EXCP) { 965 mode = "handler"; 966 } else { 967 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 968 mode = "unpriv-thread"; 969 } else { 970 mode = "priv-thread"; 971 } 972 } 973 974 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 975 xpsr, 976 xpsr & XPSR_N ? 'N' : '-', 977 xpsr & XPSR_Z ? 'Z' : '-', 978 xpsr & XPSR_C ? 'C' : '-', 979 xpsr & XPSR_V ? 'V' : '-', 980 xpsr & XPSR_T ? 'T' : 'A', 981 ns_status, 982 mode); 983 } else { 984 uint32_t psr = cpsr_read(env); 985 const char *ns_status = ""; 986 987 if (arm_feature(env, ARM_FEATURE_EL3) && 988 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 989 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 990 } 991 992 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 993 psr, 994 psr & CPSR_N ? 'N' : '-', 995 psr & CPSR_Z ? 'Z' : '-', 996 psr & CPSR_C ? 'C' : '-', 997 psr & CPSR_V ? 'V' : '-', 998 psr & CPSR_T ? 'T' : 'A', 999 ns_status, 1000 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1001 } 1002 1003 if (flags & CPU_DUMP_FPU) { 1004 int numvfpregs = 0; 1005 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1006 numvfpregs = 32; 1007 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1008 numvfpregs = 16; 1009 } 1010 for (i = 0; i < numvfpregs; i++) { 1011 uint64_t v = *aa32_vfp_dreg(env, i); 1012 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1013 i * 2, (uint32_t)v, 1014 i * 2 + 1, (uint32_t)(v >> 32), 1015 i, v); 1016 } 1017 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1018 } 1019 } 1020 1021 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 1022 { 1023 uint32_t Aff1 = idx / clustersz; 1024 uint32_t Aff0 = idx % clustersz; 1025 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1026 } 1027 1028 static void cpreg_hashtable_data_destroy(gpointer data) 1029 { 1030 /* 1031 * Destroy function for cpu->cp_regs hashtable data entries. 1032 * We must free the name string because it was g_strdup()ed in 1033 * add_cpreg_to_hashtable(). It's OK to cast away the 'const' 1034 * from r->name because we know we definitely allocated it. 1035 */ 1036 ARMCPRegInfo *r = data; 1037 1038 g_free((void *)r->name); 1039 g_free(r); 1040 } 1041 1042 static void arm_cpu_initfn(Object *obj) 1043 { 1044 ARMCPU *cpu = ARM_CPU(obj); 1045 1046 cpu_set_cpustate_pointers(cpu); 1047 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 1048 g_free, cpreg_hashtable_data_destroy); 1049 1050 QLIST_INIT(&cpu->pre_el_change_hooks); 1051 QLIST_INIT(&cpu->el_change_hooks); 1052 1053 #ifndef CONFIG_USER_ONLY 1054 /* Our inbound IRQ and FIQ lines */ 1055 if (kvm_enabled()) { 1056 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1057 * the same interface as non-KVM CPUs. 1058 */ 1059 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1060 } else { 1061 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1062 } 1063 1064 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1065 ARRAY_SIZE(cpu->gt_timer_outputs)); 1066 1067 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1068 "gicv3-maintenance-interrupt", 1); 1069 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1070 "pmu-interrupt", 1); 1071 #endif 1072 1073 /* DTB consumers generally don't in fact care what the 'compatible' 1074 * string is, so always provide some string and trust that a hypothetical 1075 * picky DTB consumer will also provide a helpful error message. 1076 */ 1077 cpu->dtb_compatible = "qemu,unknown"; 1078 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 1079 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1080 1081 if (tcg_enabled()) { 1082 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 1083 } 1084 } 1085 1086 static Property arm_cpu_gt_cntfrq_property = 1087 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1088 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1089 1090 static Property arm_cpu_reset_cbar_property = 1091 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1092 1093 static Property arm_cpu_reset_hivecs_property = 1094 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1095 1096 static Property arm_cpu_rvbar_property = 1097 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 1098 1099 #ifndef CONFIG_USER_ONLY 1100 static Property arm_cpu_has_el2_property = 1101 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1102 1103 static Property arm_cpu_has_el3_property = 1104 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1105 #endif 1106 1107 static Property arm_cpu_cfgend_property = 1108 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1109 1110 static Property arm_cpu_has_vfp_property = 1111 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1112 1113 static Property arm_cpu_has_neon_property = 1114 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1115 1116 static Property arm_cpu_has_dsp_property = 1117 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1118 1119 static Property arm_cpu_has_mpu_property = 1120 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1121 1122 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1123 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1124 * the right value for that particular CPU type, and we don't want 1125 * to override that with an incorrect constant value. 1126 */ 1127 static Property arm_cpu_pmsav7_dregion_property = 1128 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1129 pmsav7_dregion, 1130 qdev_prop_uint32, uint32_t); 1131 1132 static bool arm_get_pmu(Object *obj, Error **errp) 1133 { 1134 ARMCPU *cpu = ARM_CPU(obj); 1135 1136 return cpu->has_pmu; 1137 } 1138 1139 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1140 { 1141 ARMCPU *cpu = ARM_CPU(obj); 1142 1143 if (value) { 1144 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1145 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1146 return; 1147 } 1148 set_feature(&cpu->env, ARM_FEATURE_PMU); 1149 } else { 1150 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1151 } 1152 cpu->has_pmu = value; 1153 } 1154 1155 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1156 { 1157 /* 1158 * The exact approach to calculating guest ticks is: 1159 * 1160 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1161 * NANOSECONDS_PER_SECOND); 1162 * 1163 * We don't do that. Rather we intentionally use integer division 1164 * truncation below and in the caller for the conversion of host monotonic 1165 * time to guest ticks to provide the exact inverse for the semantics of 1166 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1167 * it loses precision when representing frequencies where 1168 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1169 * provide an exact inverse leads to scheduling timers with negative 1170 * periods, which in turn leads to sticky behaviour in the guest. 1171 * 1172 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1173 * cannot become zero. 1174 */ 1175 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1176 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1177 } 1178 1179 void arm_cpu_post_init(Object *obj) 1180 { 1181 ARMCPU *cpu = ARM_CPU(obj); 1182 1183 /* M profile implies PMSA. We have to do this here rather than 1184 * in realize with the other feature-implication checks because 1185 * we look at the PMSA bit to see if we should add some properties. 1186 */ 1187 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1188 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1189 } 1190 1191 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1192 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1193 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1194 } 1195 1196 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1197 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1198 } 1199 1200 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1201 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property); 1202 } 1203 1204 #ifndef CONFIG_USER_ONLY 1205 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1206 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1207 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1208 */ 1209 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1210 1211 object_property_add_link(obj, "secure-memory", 1212 TYPE_MEMORY_REGION, 1213 (Object **)&cpu->secure_memory, 1214 qdev_prop_allow_set_link_before_realize, 1215 OBJ_PROP_LINK_STRONG); 1216 } 1217 1218 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1219 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1220 } 1221 #endif 1222 1223 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1224 cpu->has_pmu = true; 1225 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1226 } 1227 1228 /* 1229 * Allow user to turn off VFP and Neon support, but only for TCG -- 1230 * KVM does not currently allow us to lie to the guest about its 1231 * ID/feature registers, so the guest always sees what the host has. 1232 */ 1233 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 1234 ? cpu_isar_feature(aa64_fp_simd, cpu) 1235 : cpu_isar_feature(aa32_vfp, cpu)) { 1236 cpu->has_vfp = true; 1237 if (!kvm_enabled()) { 1238 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1239 } 1240 } 1241 1242 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1243 cpu->has_neon = true; 1244 if (!kvm_enabled()) { 1245 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1246 } 1247 } 1248 1249 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1250 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1251 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1252 } 1253 1254 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1255 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1256 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1257 qdev_property_add_static(DEVICE(obj), 1258 &arm_cpu_pmsav7_dregion_property); 1259 } 1260 } 1261 1262 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1263 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1264 qdev_prop_allow_set_link_before_realize, 1265 OBJ_PROP_LINK_STRONG); 1266 /* 1267 * M profile: initial value of the Secure VTOR. We can't just use 1268 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1269 * the property to be set after realize. 1270 */ 1271 object_property_add_uint32_ptr(obj, "init-svtor", 1272 &cpu->init_svtor, 1273 OBJ_PROP_FLAG_READWRITE); 1274 } 1275 1276 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1277 1278 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1279 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1280 } 1281 1282 if (kvm_enabled()) { 1283 kvm_arm_add_vcpu_properties(obj); 1284 } 1285 1286 #ifndef CONFIG_USER_ONLY 1287 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1288 cpu_isar_feature(aa64_mte, cpu)) { 1289 object_property_add_link(obj, "tag-memory", 1290 TYPE_MEMORY_REGION, 1291 (Object **)&cpu->tag_memory, 1292 qdev_prop_allow_set_link_before_realize, 1293 OBJ_PROP_LINK_STRONG); 1294 1295 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1296 object_property_add_link(obj, "secure-tag-memory", 1297 TYPE_MEMORY_REGION, 1298 (Object **)&cpu->secure_tag_memory, 1299 qdev_prop_allow_set_link_before_realize, 1300 OBJ_PROP_LINK_STRONG); 1301 } 1302 } 1303 #endif 1304 } 1305 1306 static void arm_cpu_finalizefn(Object *obj) 1307 { 1308 ARMCPU *cpu = ARM_CPU(obj); 1309 ARMELChangeHook *hook, *next; 1310 1311 g_hash_table_destroy(cpu->cp_regs); 1312 1313 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1314 QLIST_REMOVE(hook, node); 1315 g_free(hook); 1316 } 1317 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1318 QLIST_REMOVE(hook, node); 1319 g_free(hook); 1320 } 1321 #ifndef CONFIG_USER_ONLY 1322 if (cpu->pmu_timer) { 1323 timer_free(cpu->pmu_timer); 1324 } 1325 #endif 1326 } 1327 1328 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1329 { 1330 Error *local_err = NULL; 1331 1332 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1333 arm_cpu_sve_finalize(cpu, &local_err); 1334 if (local_err != NULL) { 1335 error_propagate(errp, local_err); 1336 return; 1337 } 1338 1339 /* 1340 * KVM does not support modifications to this feature. 1341 * We have not registered the cpu properties when KVM 1342 * is in use, so the user will not be able to set them. 1343 */ 1344 if (!kvm_enabled()) { 1345 arm_cpu_pauth_finalize(cpu, &local_err); 1346 if (local_err != NULL) { 1347 error_propagate(errp, local_err); 1348 return; 1349 } 1350 } 1351 } 1352 1353 if (kvm_enabled()) { 1354 kvm_arm_steal_time_finalize(cpu, &local_err); 1355 if (local_err != NULL) { 1356 error_propagate(errp, local_err); 1357 return; 1358 } 1359 } 1360 } 1361 1362 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1363 { 1364 CPUState *cs = CPU(dev); 1365 ARMCPU *cpu = ARM_CPU(dev); 1366 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1367 CPUARMState *env = &cpu->env; 1368 int pagebits; 1369 Error *local_err = NULL; 1370 bool no_aa32 = false; 1371 1372 /* If we needed to query the host kernel for the CPU features 1373 * then it's possible that might have failed in the initfn, but 1374 * this is the first point where we can report it. 1375 */ 1376 if (cpu->host_cpu_probe_failed) { 1377 if (!kvm_enabled()) { 1378 error_setg(errp, "The 'host' CPU type can only be used with KVM"); 1379 } else { 1380 error_setg(errp, "Failed to retrieve host CPU features"); 1381 } 1382 return; 1383 } 1384 1385 #ifndef CONFIG_USER_ONLY 1386 /* The NVIC and M-profile CPU are two halves of a single piece of 1387 * hardware; trying to use one without the other is a command line 1388 * error and will result in segfaults if not caught here. 1389 */ 1390 if (arm_feature(env, ARM_FEATURE_M)) { 1391 if (!env->nvic) { 1392 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1393 return; 1394 } 1395 } else { 1396 if (env->nvic) { 1397 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1398 return; 1399 } 1400 } 1401 1402 { 1403 uint64_t scale; 1404 1405 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1406 if (!cpu->gt_cntfrq_hz) { 1407 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1408 cpu->gt_cntfrq_hz); 1409 return; 1410 } 1411 scale = gt_cntfrq_period_ns(cpu); 1412 } else { 1413 scale = GTIMER_SCALE; 1414 } 1415 1416 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1417 arm_gt_ptimer_cb, cpu); 1418 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1419 arm_gt_vtimer_cb, cpu); 1420 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1421 arm_gt_htimer_cb, cpu); 1422 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1423 arm_gt_stimer_cb, cpu); 1424 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1425 arm_gt_hvtimer_cb, cpu); 1426 } 1427 #endif 1428 1429 cpu_exec_realizefn(cs, &local_err); 1430 if (local_err != NULL) { 1431 error_propagate(errp, local_err); 1432 return; 1433 } 1434 1435 arm_cpu_finalize_features(cpu, &local_err); 1436 if (local_err != NULL) { 1437 error_propagate(errp, local_err); 1438 return; 1439 } 1440 1441 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1442 cpu->has_vfp != cpu->has_neon) { 1443 /* 1444 * This is an architectural requirement for AArch64; AArch32 is 1445 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1446 */ 1447 error_setg(errp, 1448 "AArch64 CPUs must have both VFP and Neon or neither"); 1449 return; 1450 } 1451 1452 if (!cpu->has_vfp) { 1453 uint64_t t; 1454 uint32_t u; 1455 1456 t = cpu->isar.id_aa64isar1; 1457 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1458 cpu->isar.id_aa64isar1 = t; 1459 1460 t = cpu->isar.id_aa64pfr0; 1461 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1462 cpu->isar.id_aa64pfr0 = t; 1463 1464 u = cpu->isar.id_isar6; 1465 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1466 cpu->isar.id_isar6 = u; 1467 1468 u = cpu->isar.mvfr0; 1469 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1470 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1471 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1472 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1473 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1474 if (!arm_feature(env, ARM_FEATURE_M)) { 1475 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1476 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1477 } 1478 cpu->isar.mvfr0 = u; 1479 1480 u = cpu->isar.mvfr1; 1481 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1482 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1483 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1484 if (arm_feature(env, ARM_FEATURE_M)) { 1485 u = FIELD_DP32(u, MVFR1, FP16, 0); 1486 } 1487 cpu->isar.mvfr1 = u; 1488 1489 u = cpu->isar.mvfr2; 1490 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1491 cpu->isar.mvfr2 = u; 1492 } 1493 1494 if (!cpu->has_neon) { 1495 uint64_t t; 1496 uint32_t u; 1497 1498 unset_feature(env, ARM_FEATURE_NEON); 1499 1500 t = cpu->isar.id_aa64isar0; 1501 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1502 cpu->isar.id_aa64isar0 = t; 1503 1504 t = cpu->isar.id_aa64isar1; 1505 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1506 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 1507 cpu->isar.id_aa64isar1 = t; 1508 1509 t = cpu->isar.id_aa64pfr0; 1510 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1511 cpu->isar.id_aa64pfr0 = t; 1512 1513 u = cpu->isar.id_isar5; 1514 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1515 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1516 cpu->isar.id_isar5 = u; 1517 1518 u = cpu->isar.id_isar6; 1519 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1520 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1521 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 1522 cpu->isar.id_isar6 = u; 1523 1524 if (!arm_feature(env, ARM_FEATURE_M)) { 1525 u = cpu->isar.mvfr1; 1526 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1527 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1528 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1529 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1530 cpu->isar.mvfr1 = u; 1531 1532 u = cpu->isar.mvfr2; 1533 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1534 cpu->isar.mvfr2 = u; 1535 } 1536 } 1537 1538 if (!cpu->has_neon && !cpu->has_vfp) { 1539 uint64_t t; 1540 uint32_t u; 1541 1542 t = cpu->isar.id_aa64isar0; 1543 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1544 cpu->isar.id_aa64isar0 = t; 1545 1546 t = cpu->isar.id_aa64isar1; 1547 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1548 cpu->isar.id_aa64isar1 = t; 1549 1550 u = cpu->isar.mvfr0; 1551 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1552 cpu->isar.mvfr0 = u; 1553 1554 /* Despite the name, this field covers both VFP and Neon */ 1555 u = cpu->isar.mvfr1; 1556 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1557 cpu->isar.mvfr1 = u; 1558 } 1559 1560 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1561 uint32_t u; 1562 1563 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1564 1565 u = cpu->isar.id_isar1; 1566 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1567 cpu->isar.id_isar1 = u; 1568 1569 u = cpu->isar.id_isar2; 1570 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1571 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1572 cpu->isar.id_isar2 = u; 1573 1574 u = cpu->isar.id_isar3; 1575 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1576 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1577 cpu->isar.id_isar3 = u; 1578 } 1579 1580 /* Some features automatically imply others: */ 1581 if (arm_feature(env, ARM_FEATURE_V8)) { 1582 if (arm_feature(env, ARM_FEATURE_M)) { 1583 set_feature(env, ARM_FEATURE_V7); 1584 } else { 1585 set_feature(env, ARM_FEATURE_V7VE); 1586 } 1587 } 1588 1589 /* 1590 * There exist AArch64 cpus without AArch32 support. When KVM 1591 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1592 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1593 * As a general principle, we also do not make ID register 1594 * consistency checks anywhere unless using TCG, because only 1595 * for TCG would a consistency-check failure be a QEMU bug. 1596 */ 1597 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1598 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1599 } 1600 1601 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1602 /* v7 Virtualization Extensions. In real hardware this implies 1603 * EL2 and also the presence of the Security Extensions. 1604 * For QEMU, for backwards-compatibility we implement some 1605 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1606 * include the various other features that V7VE implies. 1607 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1608 * Security Extensions is ARM_FEATURE_EL3. 1609 */ 1610 assert(!tcg_enabled() || no_aa32 || 1611 cpu_isar_feature(aa32_arm_div, cpu)); 1612 set_feature(env, ARM_FEATURE_LPAE); 1613 set_feature(env, ARM_FEATURE_V7); 1614 } 1615 if (arm_feature(env, ARM_FEATURE_V7)) { 1616 set_feature(env, ARM_FEATURE_VAPA); 1617 set_feature(env, ARM_FEATURE_THUMB2); 1618 set_feature(env, ARM_FEATURE_MPIDR); 1619 if (!arm_feature(env, ARM_FEATURE_M)) { 1620 set_feature(env, ARM_FEATURE_V6K); 1621 } else { 1622 set_feature(env, ARM_FEATURE_V6); 1623 } 1624 1625 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1626 * non-EL3 configs. This is needed by some legacy boards. 1627 */ 1628 set_feature(env, ARM_FEATURE_VBAR); 1629 } 1630 if (arm_feature(env, ARM_FEATURE_V6K)) { 1631 set_feature(env, ARM_FEATURE_V6); 1632 set_feature(env, ARM_FEATURE_MVFR); 1633 } 1634 if (arm_feature(env, ARM_FEATURE_V6)) { 1635 set_feature(env, ARM_FEATURE_V5); 1636 if (!arm_feature(env, ARM_FEATURE_M)) { 1637 assert(!tcg_enabled() || no_aa32 || 1638 cpu_isar_feature(aa32_jazelle, cpu)); 1639 set_feature(env, ARM_FEATURE_AUXCR); 1640 } 1641 } 1642 if (arm_feature(env, ARM_FEATURE_V5)) { 1643 set_feature(env, ARM_FEATURE_V4T); 1644 } 1645 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1646 set_feature(env, ARM_FEATURE_V7MP); 1647 } 1648 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1649 set_feature(env, ARM_FEATURE_CBAR); 1650 } 1651 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1652 !arm_feature(env, ARM_FEATURE_M)) { 1653 set_feature(env, ARM_FEATURE_THUMB_DSP); 1654 } 1655 1656 /* 1657 * We rely on no XScale CPU having VFP so we can use the same bits in the 1658 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1659 */ 1660 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1661 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1662 !arm_feature(env, ARM_FEATURE_XSCALE)); 1663 1664 if (arm_feature(env, ARM_FEATURE_V7) && 1665 !arm_feature(env, ARM_FEATURE_M) && 1666 !arm_feature(env, ARM_FEATURE_PMSA)) { 1667 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1668 * can use 4K pages. 1669 */ 1670 pagebits = 12; 1671 } else { 1672 /* For CPUs which might have tiny 1K pages, or which have an 1673 * MPU and might have small region sizes, stick with 1K pages. 1674 */ 1675 pagebits = 10; 1676 } 1677 if (!set_preferred_target_page_bits(pagebits)) { 1678 /* This can only ever happen for hotplugging a CPU, or if 1679 * the board code incorrectly creates a CPU which it has 1680 * promised via minimum_page_size that it will not. 1681 */ 1682 error_setg(errp, "This CPU requires a smaller page size than the " 1683 "system is using"); 1684 return; 1685 } 1686 1687 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1688 * We don't support setting cluster ID ([16..23]) (known as Aff2 1689 * in later ARM ARM versions), or any of the higher affinity level fields, 1690 * so these bits always RAZ. 1691 */ 1692 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1693 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1694 ARM_DEFAULT_CPUS_PER_CLUSTER); 1695 } 1696 1697 if (cpu->reset_hivecs) { 1698 cpu->reset_sctlr |= (1 << 13); 1699 } 1700 1701 if (cpu->cfgend) { 1702 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1703 cpu->reset_sctlr |= SCTLR_EE; 1704 } else { 1705 cpu->reset_sctlr |= SCTLR_B; 1706 } 1707 } 1708 1709 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 1710 /* If the has_el3 CPU property is disabled then we need to disable the 1711 * feature. 1712 */ 1713 unset_feature(env, ARM_FEATURE_EL3); 1714 1715 /* Disable the security extension feature bits in the processor feature 1716 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 1717 */ 1718 cpu->isar.id_pfr1 &= ~0xf0; 1719 cpu->isar.id_aa64pfr0 &= ~0xf000; 1720 } 1721 1722 if (!cpu->has_el2) { 1723 unset_feature(env, ARM_FEATURE_EL2); 1724 } 1725 1726 if (!cpu->has_pmu) { 1727 unset_feature(env, ARM_FEATURE_PMU); 1728 } 1729 if (arm_feature(env, ARM_FEATURE_PMU)) { 1730 pmu_init(cpu); 1731 1732 if (!kvm_enabled()) { 1733 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1734 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1735 } 1736 1737 #ifndef CONFIG_USER_ONLY 1738 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1739 cpu); 1740 #endif 1741 } else { 1742 cpu->isar.id_aa64dfr0 = 1743 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 1744 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 1745 cpu->pmceid0 = 0; 1746 cpu->pmceid1 = 0; 1747 } 1748 1749 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1750 /* Disable the hypervisor feature bits in the processor feature 1751 * registers if we don't have EL2. These are id_pfr1[15:12] and 1752 * id_aa64pfr0_el1[11:8]. 1753 */ 1754 cpu->isar.id_aa64pfr0 &= ~0xf00; 1755 cpu->isar.id_pfr1 &= ~0xf000; 1756 } 1757 1758 #ifndef CONFIG_USER_ONLY 1759 if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { 1760 /* 1761 * Disable the MTE feature bits if we do not have tag-memory 1762 * provided by the machine. 1763 */ 1764 cpu->isar.id_aa64pfr1 = 1765 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 1766 } 1767 #endif 1768 1769 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1770 * to false or by setting pmsav7-dregion to 0. 1771 */ 1772 if (!cpu->has_mpu) { 1773 cpu->pmsav7_dregion = 0; 1774 } 1775 if (cpu->pmsav7_dregion == 0) { 1776 cpu->has_mpu = false; 1777 } 1778 1779 if (arm_feature(env, ARM_FEATURE_PMSA) && 1780 arm_feature(env, ARM_FEATURE_V7)) { 1781 uint32_t nr = cpu->pmsav7_dregion; 1782 1783 if (nr > 0xff) { 1784 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1785 return; 1786 } 1787 1788 if (nr) { 1789 if (arm_feature(env, ARM_FEATURE_V8)) { 1790 /* PMSAv8 */ 1791 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1792 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1793 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1794 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1795 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1796 } 1797 } else { 1798 env->pmsav7.drbar = g_new0(uint32_t, nr); 1799 env->pmsav7.drsr = g_new0(uint32_t, nr); 1800 env->pmsav7.dracr = g_new0(uint32_t, nr); 1801 } 1802 } 1803 } 1804 1805 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1806 uint32_t nr = cpu->sau_sregion; 1807 1808 if (nr > 0xff) { 1809 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1810 return; 1811 } 1812 1813 if (nr) { 1814 env->sau.rbar = g_new0(uint32_t, nr); 1815 env->sau.rlar = g_new0(uint32_t, nr); 1816 } 1817 } 1818 1819 if (arm_feature(env, ARM_FEATURE_EL3)) { 1820 set_feature(env, ARM_FEATURE_VBAR); 1821 } 1822 1823 register_cp_regs_for_features(cpu); 1824 arm_cpu_register_gdb_regs_for_features(cpu); 1825 1826 init_cpreg_list(cpu); 1827 1828 #ifndef CONFIG_USER_ONLY 1829 MachineState *ms = MACHINE(qdev_get_machine()); 1830 unsigned int smp_cpus = ms->smp.cpus; 1831 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 1832 1833 /* 1834 * We must set cs->num_ases to the final value before 1835 * the first call to cpu_address_space_init. 1836 */ 1837 if (cpu->tag_memory != NULL) { 1838 cs->num_ases = 3 + has_secure; 1839 } else { 1840 cs->num_ases = 1 + has_secure; 1841 } 1842 1843 if (has_secure) { 1844 if (!cpu->secure_memory) { 1845 cpu->secure_memory = cs->memory; 1846 } 1847 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1848 cpu->secure_memory); 1849 } 1850 1851 if (cpu->tag_memory != NULL) { 1852 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 1853 cpu->tag_memory); 1854 if (has_secure) { 1855 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 1856 cpu->secure_tag_memory); 1857 } 1858 } 1859 1860 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1861 1862 /* No core_count specified, default to smp_cpus. */ 1863 if (cpu->core_count == -1) { 1864 cpu->core_count = smp_cpus; 1865 } 1866 #endif 1867 1868 if (tcg_enabled()) { 1869 int dcz_blocklen = 4 << cpu->dcz_blocksize; 1870 1871 /* 1872 * We only support DCZ blocklen that fits on one page. 1873 * 1874 * Architectually this is always true. However TARGET_PAGE_SIZE 1875 * is variable and, for compatibility with -machine virt-2.7, 1876 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 1877 * But even then, while the largest architectural DCZ blocklen 1878 * is 2KiB, no cpu actually uses such a large blocklen. 1879 */ 1880 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 1881 1882 /* 1883 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 1884 * both nibbles of each byte storing tag data may be written at once. 1885 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 1886 */ 1887 if (cpu_isar_feature(aa64_mte, cpu)) { 1888 assert(dcz_blocklen >= 2 * TAG_GRANULE); 1889 } 1890 } 1891 1892 qemu_init_vcpu(cs); 1893 cpu_reset(cs); 1894 1895 acc->parent_realize(dev, errp); 1896 } 1897 1898 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1899 { 1900 ObjectClass *oc; 1901 char *typename; 1902 char **cpuname; 1903 const char *cpunamestr; 1904 1905 cpuname = g_strsplit(cpu_model, ",", 1); 1906 cpunamestr = cpuname[0]; 1907 #ifdef CONFIG_USER_ONLY 1908 /* For backwards compatibility usermode emulation allows "-cpu any", 1909 * which has the same semantics as "-cpu max". 1910 */ 1911 if (!strcmp(cpunamestr, "any")) { 1912 cpunamestr = "max"; 1913 } 1914 #endif 1915 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 1916 oc = object_class_by_name(typename); 1917 g_strfreev(cpuname); 1918 g_free(typename); 1919 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 1920 object_class_is_abstract(oc)) { 1921 return NULL; 1922 } 1923 return oc; 1924 } 1925 1926 static Property arm_cpu_properties[] = { 1927 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 1928 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 1929 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 1930 mp_affinity, ARM64_AFFINITY_INVALID), 1931 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 1932 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 1933 DEFINE_PROP_END_OF_LIST() 1934 }; 1935 1936 static gchar *arm_gdb_arch_name(CPUState *cs) 1937 { 1938 ARMCPU *cpu = ARM_CPU(cs); 1939 CPUARMState *env = &cpu->env; 1940 1941 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 1942 return g_strdup("iwmmxt"); 1943 } 1944 return g_strdup("arm"); 1945 } 1946 1947 #ifndef CONFIG_USER_ONLY 1948 #include "hw/core/sysemu-cpu-ops.h" 1949 1950 static const struct SysemuCPUOps arm_sysemu_ops = { 1951 .write_elf32_note = arm_cpu_write_elf32_note, 1952 .write_elf64_note = arm_cpu_write_elf64_note, 1953 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 1954 .legacy_vmsd = &vmstate_arm_cpu, 1955 }; 1956 #endif 1957 1958 #ifdef CONFIG_TCG 1959 static struct TCGCPUOps arm_tcg_ops = { 1960 .initialize = arm_translate_init, 1961 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 1962 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 1963 .tlb_fill = arm_cpu_tlb_fill, 1964 .debug_excp_handler = arm_debug_excp_handler, 1965 1966 #if !defined(CONFIG_USER_ONLY) 1967 .do_interrupt = arm_cpu_do_interrupt, 1968 .do_transaction_failed = arm_cpu_do_transaction_failed, 1969 .do_unaligned_access = arm_cpu_do_unaligned_access, 1970 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 1971 .debug_check_watchpoint = arm_debug_check_watchpoint, 1972 #endif /* !CONFIG_USER_ONLY */ 1973 }; 1974 #endif /* CONFIG_TCG */ 1975 1976 static void arm_cpu_class_init(ObjectClass *oc, void *data) 1977 { 1978 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1979 CPUClass *cc = CPU_CLASS(acc); 1980 DeviceClass *dc = DEVICE_CLASS(oc); 1981 1982 device_class_set_parent_realize(dc, arm_cpu_realizefn, 1983 &acc->parent_realize); 1984 1985 device_class_set_props(dc, arm_cpu_properties); 1986 device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); 1987 1988 cc->class_by_name = arm_cpu_class_by_name; 1989 cc->has_work = arm_cpu_has_work; 1990 cc->dump_state = arm_cpu_dump_state; 1991 cc->set_pc = arm_cpu_set_pc; 1992 cc->gdb_read_register = arm_cpu_gdb_read_register; 1993 cc->gdb_write_register = arm_cpu_gdb_write_register; 1994 #ifndef CONFIG_USER_ONLY 1995 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 1996 cc->asidx_from_attrs = arm_asidx_from_attrs; 1997 cc->sysemu_ops = &arm_sysemu_ops; 1998 #endif 1999 cc->gdb_num_core_regs = 26; 2000 cc->gdb_core_xml_file = "arm-core.xml"; 2001 cc->gdb_arch_name = arm_gdb_arch_name; 2002 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2003 cc->gdb_stop_before_watchpoint = true; 2004 cc->disas_set_info = arm_disas_set_info; 2005 2006 #ifdef CONFIG_TCG 2007 cc->tcg_ops = &arm_tcg_ops; 2008 #endif /* CONFIG_TCG */ 2009 } 2010 2011 #ifdef CONFIG_KVM 2012 static void arm_host_initfn(Object *obj) 2013 { 2014 ARMCPU *cpu = ARM_CPU(obj); 2015 2016 kvm_arm_set_cpu_features_from_host(cpu); 2017 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 2018 aarch64_add_sve_properties(obj); 2019 } 2020 arm_cpu_post_init(obj); 2021 } 2022 2023 static const TypeInfo host_arm_cpu_type_info = { 2024 .name = TYPE_ARM_HOST_CPU, 2025 .parent = TYPE_AARCH64_CPU, 2026 .instance_init = arm_host_initfn, 2027 }; 2028 2029 #endif 2030 2031 static void arm_cpu_instance_init(Object *obj) 2032 { 2033 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2034 2035 acc->info->initfn(obj); 2036 arm_cpu_post_init(obj); 2037 } 2038 2039 static void cpu_register_class_init(ObjectClass *oc, void *data) 2040 { 2041 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2042 2043 acc->info = data; 2044 } 2045 2046 void arm_cpu_register(const ARMCPUInfo *info) 2047 { 2048 TypeInfo type_info = { 2049 .parent = TYPE_ARM_CPU, 2050 .instance_size = sizeof(ARMCPU), 2051 .instance_align = __alignof__(ARMCPU), 2052 .instance_init = arm_cpu_instance_init, 2053 .class_size = sizeof(ARMCPUClass), 2054 .class_init = info->class_init ?: cpu_register_class_init, 2055 .class_data = (void *)info, 2056 }; 2057 2058 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2059 type_register(&type_info); 2060 g_free((void *)type_info.name); 2061 } 2062 2063 static const TypeInfo arm_cpu_type_info = { 2064 .name = TYPE_ARM_CPU, 2065 .parent = TYPE_CPU, 2066 .instance_size = sizeof(ARMCPU), 2067 .instance_align = __alignof__(ARMCPU), 2068 .instance_init = arm_cpu_initfn, 2069 .instance_finalize = arm_cpu_finalizefn, 2070 .abstract = true, 2071 .class_size = sizeof(ARMCPUClass), 2072 .class_init = arm_cpu_class_init, 2073 }; 2074 2075 static void arm_cpu_register_types(void) 2076 { 2077 type_register_static(&arm_cpu_type_info); 2078 2079 #ifdef CONFIG_KVM 2080 type_register_static(&host_arm_cpu_type_info); 2081 #endif 2082 } 2083 2084 type_init(arm_cpu_register_types) 2085