1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu/timer.h" 24 #include "qemu/log.h" 25 #include "exec/page-vary.h" 26 #include "target/arm/idau.h" 27 #include "qemu/module.h" 28 #include "qapi/error.h" 29 #include "cpu.h" 30 #ifdef CONFIG_TCG 31 #include "hw/core/tcg-cpu-ops.h" 32 #endif /* CONFIG_TCG */ 33 #include "internals.h" 34 #include "cpu-features.h" 35 #include "exec/exec-all.h" 36 #include "hw/qdev-properties.h" 37 #if !defined(CONFIG_USER_ONLY) 38 #include "hw/loader.h" 39 #include "hw/boards.h" 40 #ifdef CONFIG_TCG 41 #include "hw/intc/armv7m_nvic.h" 42 #endif /* CONFIG_TCG */ 43 #endif /* !CONFIG_USER_ONLY */ 44 #include "sysemu/tcg.h" 45 #include "sysemu/qtest.h" 46 #include "sysemu/hw_accel.h" 47 #include "kvm_arm.h" 48 #include "disas/capstone.h" 49 #include "fpu/softfloat.h" 50 #include "cpregs.h" 51 #include "target/arm/cpu-qom.h" 52 #include "target/arm/gtimer.h" 53 54 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 55 { 56 ARMCPU *cpu = ARM_CPU(cs); 57 CPUARMState *env = &cpu->env; 58 59 if (is_a64(env)) { 60 env->pc = value; 61 env->thumb = false; 62 } else { 63 env->regs[15] = value & ~1; 64 env->thumb = value & 1; 65 } 66 } 67 68 static vaddr arm_cpu_get_pc(CPUState *cs) 69 { 70 ARMCPU *cpu = ARM_CPU(cs); 71 CPUARMState *env = &cpu->env; 72 73 if (is_a64(env)) { 74 return env->pc; 75 } else { 76 return env->regs[15]; 77 } 78 } 79 80 #ifdef CONFIG_TCG 81 void arm_cpu_synchronize_from_tb(CPUState *cs, 82 const TranslationBlock *tb) 83 { 84 /* The program counter is always up to date with CF_PCREL. */ 85 if (!(tb_cflags(tb) & CF_PCREL)) { 86 CPUARMState *env = cpu_env(cs); 87 /* 88 * It's OK to look at env for the current mode here, because it's 89 * never possible for an AArch64 TB to chain to an AArch32 TB. 90 */ 91 if (is_a64(env)) { 92 env->pc = tb->pc; 93 } else { 94 env->regs[15] = tb->pc; 95 } 96 } 97 } 98 99 void arm_restore_state_to_opc(CPUState *cs, 100 const TranslationBlock *tb, 101 const uint64_t *data) 102 { 103 CPUARMState *env = cpu_env(cs); 104 105 if (is_a64(env)) { 106 if (tb_cflags(tb) & CF_PCREL) { 107 env->pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 108 } else { 109 env->pc = data[0]; 110 } 111 env->condexec_bits = 0; 112 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 113 } else { 114 if (tb_cflags(tb) & CF_PCREL) { 115 env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0]; 116 } else { 117 env->regs[15] = data[0]; 118 } 119 env->condexec_bits = data[1]; 120 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 121 } 122 } 123 #endif /* CONFIG_TCG */ 124 125 /* 126 * With SCTLR_ELx.NMI == 0, IRQ with Superpriority is masked identically with 127 * IRQ without Superpriority. Moreover, if the GIC is configured so that 128 * FEAT_GICv3_NMI is only set if FEAT_NMI is set, then we won't ever see 129 * CPU_INTERRUPT_*NMI anyway. So we might as well accept NMI here 130 * unconditionally. 131 */ 132 static bool arm_cpu_has_work(CPUState *cs) 133 { 134 ARMCPU *cpu = ARM_CPU(cs); 135 136 return (cpu->power_state != PSCI_OFF) 137 && cs->interrupt_request & 138 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 139 | CPU_INTERRUPT_NMI | CPU_INTERRUPT_VINMI | CPU_INTERRUPT_VFNMI 140 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR 141 | CPU_INTERRUPT_EXITTB); 142 } 143 144 static int arm_cpu_mmu_index(CPUState *cs, bool ifetch) 145 { 146 return arm_env_mmu_index(cpu_env(cs)); 147 } 148 149 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 150 void *opaque) 151 { 152 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 153 154 entry->hook = hook; 155 entry->opaque = opaque; 156 157 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 158 } 159 160 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 161 void *opaque) 162 { 163 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 164 165 entry->hook = hook; 166 entry->opaque = opaque; 167 168 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 169 } 170 171 /* 172 * Set the float_status behaviour to match the Arm defaults: 173 * * tininess-before-rounding 174 * * 2-input NaN propagation prefers SNaN over QNaN, and then 175 * operand A over operand B (see FPProcessNaNs() pseudocode) 176 */ 177 static void arm_set_default_fp_behaviours(float_status *s) 178 { 179 set_float_detect_tininess(float_tininess_before_rounding, s); 180 set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); 181 } 182 183 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 184 { 185 /* Reset a single ARMCPRegInfo register */ 186 ARMCPRegInfo *ri = value; 187 ARMCPU *cpu = opaque; 188 189 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { 190 return; 191 } 192 193 if (ri->resetfn) { 194 ri->resetfn(&cpu->env, ri); 195 return; 196 } 197 198 /* A zero offset is never possible as it would be regs[0] 199 * so we use it to indicate that reset is being handled elsewhere. 200 * This is basically only used for fields in non-core coprocessors 201 * (like the pxa2xx ones). 202 */ 203 if (!ri->fieldoffset) { 204 return; 205 } 206 207 if (cpreg_field_is_64bit(ri)) { 208 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 209 } else { 210 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 211 } 212 } 213 214 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 215 { 216 /* Purely an assertion check: we've already done reset once, 217 * so now check that running the reset for the cpreg doesn't 218 * change its value. This traps bugs where two different cpregs 219 * both try to reset the same state field but to different values. 220 */ 221 ARMCPRegInfo *ri = value; 222 ARMCPU *cpu = opaque; 223 uint64_t oldvalue, newvalue; 224 225 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 226 return; 227 } 228 229 oldvalue = read_raw_cp_reg(&cpu->env, ri); 230 cp_reg_reset(key, value, opaque); 231 newvalue = read_raw_cp_reg(&cpu->env, ri); 232 assert(oldvalue == newvalue); 233 } 234 235 static void arm_cpu_reset_hold(Object *obj, ResetType type) 236 { 237 CPUState *cs = CPU(obj); 238 ARMCPU *cpu = ARM_CPU(cs); 239 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 240 CPUARMState *env = &cpu->env; 241 242 if (acc->parent_phases.hold) { 243 acc->parent_phases.hold(obj, type); 244 } 245 246 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 247 248 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 249 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 250 251 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 252 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 253 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 254 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 255 256 cpu->power_state = cs->start_powered_off ? PSCI_OFF : PSCI_ON; 257 258 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 259 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 260 } 261 262 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 263 /* 64 bit CPUs always start in 64 bit mode */ 264 env->aarch64 = true; 265 #if defined(CONFIG_USER_ONLY) 266 env->pstate = PSTATE_MODE_EL0t; 267 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 268 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 269 /* Enable all PAC keys. */ 270 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 271 SCTLR_EnDA | SCTLR_EnDB); 272 /* Trap on btype=3 for PACIxSP. */ 273 env->cp15.sctlr_el[1] |= SCTLR_BT0; 274 /* Trap on implementation defined registers. */ 275 if (cpu_isar_feature(aa64_tidcp1, cpu)) { 276 env->cp15.sctlr_el[1] |= SCTLR_TIDCP; 277 } 278 /* and to the FP/Neon instructions */ 279 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 280 CPACR_EL1, FPEN, 3); 281 /* and to the SVE instructions, with default vector length */ 282 if (cpu_isar_feature(aa64_sve, cpu)) { 283 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 284 CPACR_EL1, ZEN, 3); 285 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; 286 } 287 /* and for SME instructions, with default vector length, and TPIDR2 */ 288 if (cpu_isar_feature(aa64_sme, cpu)) { 289 env->cp15.sctlr_el[1] |= SCTLR_EnTP2; 290 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 291 CPACR_EL1, SMEN, 3); 292 env->vfp.smcr_el[1] = cpu->sme_default_vq - 1; 293 if (cpu_isar_feature(aa64_sme_fa64, cpu)) { 294 env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1], 295 SMCR, FA64, 1); 296 } 297 } 298 /* 299 * Enable 48-bit address space (TODO: take reserved_va into account). 300 * Enable TBI0 but not TBI1. 301 * Note that this must match useronly_clean_ptr. 302 */ 303 env->cp15.tcr_el[1] = 5 | (1ULL << 37); 304 305 /* Enable MTE */ 306 if (cpu_isar_feature(aa64_mte, cpu)) { 307 /* Enable tag access, but leave TCF0 as No Effect (0). */ 308 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 309 /* 310 * Exclude all tags, so that tag 0 is always used. 311 * This corresponds to Linux current->thread.gcr_incl = 0. 312 * 313 * Set RRND, so that helper_irg() will generate a seed later. 314 * Here in cpu_reset(), the crypto subsystem has not yet been 315 * initialized. 316 */ 317 env->cp15.gcr_el1 = 0x1ffff; 318 } 319 /* 320 * Disable access to SCXTNUM_EL0 from CSV2_1p2. 321 * This is not yet exposed from the Linux kernel in any way. 322 */ 323 env->cp15.sctlr_el[1] |= SCTLR_TSCXT; 324 /* Disable access to Debug Communication Channel (DCC). */ 325 env->cp15.mdscr_el1 |= 1 << 12; 326 /* Enable FEAT_MOPS */ 327 env->cp15.sctlr_el[1] |= SCTLR_MSCEN; 328 #else 329 /* Reset into the highest available EL */ 330 if (arm_feature(env, ARM_FEATURE_EL3)) { 331 env->pstate = PSTATE_MODE_EL3h; 332 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 333 env->pstate = PSTATE_MODE_EL2h; 334 } else { 335 env->pstate = PSTATE_MODE_EL1h; 336 } 337 338 /* Sample rvbar at reset. */ 339 env->cp15.rvbar = cpu->rvbar_prop; 340 env->pc = env->cp15.rvbar; 341 #endif 342 } else { 343 #if defined(CONFIG_USER_ONLY) 344 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 345 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 346 CPACR, CP10, 3); 347 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 348 CPACR, CP11, 3); 349 #endif 350 if (arm_feature(env, ARM_FEATURE_V8)) { 351 env->cp15.rvbar = cpu->rvbar_prop; 352 env->regs[15] = cpu->rvbar_prop; 353 } 354 } 355 356 #if defined(CONFIG_USER_ONLY) 357 env->uncached_cpsr = ARM_CPU_MODE_USR; 358 /* For user mode we must enable access to coprocessors */ 359 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 360 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 361 env->cp15.c15_cpar = 3; 362 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 363 env->cp15.c15_cpar = 1; 364 } 365 #else 366 367 /* 368 * If the highest available EL is EL2, AArch32 will start in Hyp 369 * mode; otherwise it starts in SVC. Note that if we start in 370 * AArch64 then these values in the uncached_cpsr will be ignored. 371 */ 372 if (arm_feature(env, ARM_FEATURE_EL2) && 373 !arm_feature(env, ARM_FEATURE_EL3)) { 374 env->uncached_cpsr = ARM_CPU_MODE_HYP; 375 } else { 376 env->uncached_cpsr = ARM_CPU_MODE_SVC; 377 } 378 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 379 380 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 381 * executing as AArch32 then check if highvecs are enabled and 382 * adjust the PC accordingly. 383 */ 384 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 385 env->regs[15] = 0xFFFF0000; 386 } 387 388 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 389 #endif 390 391 if (arm_feature(env, ARM_FEATURE_M)) { 392 #ifndef CONFIG_USER_ONLY 393 uint32_t initial_msp; /* Loaded from 0x0 */ 394 uint32_t initial_pc; /* Loaded from 0x4 */ 395 uint8_t *rom; 396 uint32_t vecbase; 397 #endif 398 399 if (cpu_isar_feature(aa32_lob, cpu)) { 400 /* 401 * LTPSIZE is constant 4 if MVE not implemented, and resets 402 * to an UNKNOWN value if MVE is implemented. We choose to 403 * always reset to 4. 404 */ 405 env->v7m.ltpsize = 4; 406 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 407 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 408 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 409 } 410 411 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 412 env->v7m.secure = true; 413 } else { 414 /* This bit resets to 0 if security is supported, but 1 if 415 * it is not. The bit is not present in v7M, but we set it 416 * here so we can avoid having to make checks on it conditional 417 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 418 */ 419 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 420 /* 421 * Set NSACR to indicate "NS access permitted to everything"; 422 * this avoids having to have all the tests of it being 423 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 424 * v8.1M the guest-visible value of NSACR in a CPU without the 425 * Security Extension is 0xcff. 426 */ 427 env->v7m.nsacr = 0xcff; 428 } 429 430 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 431 * that it resets to 1, so QEMU always does that rather than making 432 * it dependent on CPU model. In v8M it is RES1. 433 */ 434 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 435 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 436 if (arm_feature(env, ARM_FEATURE_V8)) { 437 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 438 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 439 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 440 } 441 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 442 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 443 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 444 } 445 446 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 447 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 448 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 449 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 450 } 451 452 #ifndef CONFIG_USER_ONLY 453 /* Unlike A/R profile, M profile defines the reset LR value */ 454 env->regs[14] = 0xffffffff; 455 456 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 457 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 458 459 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 460 vecbase = env->v7m.vecbase[env->v7m.secure]; 461 rom = rom_ptr_for_as(cs->as, vecbase, 8); 462 if (rom) { 463 /* Address zero is covered by ROM which hasn't yet been 464 * copied into physical memory. 465 */ 466 initial_msp = ldl_p(rom); 467 initial_pc = ldl_p(rom + 4); 468 } else { 469 /* Address zero not covered by a ROM blob, or the ROM blob 470 * is in non-modifiable memory and this is a second reset after 471 * it got copied into memory. In the latter case, rom_ptr 472 * will return a NULL pointer and we should use ldl_phys instead. 473 */ 474 initial_msp = ldl_phys(cs->as, vecbase); 475 initial_pc = ldl_phys(cs->as, vecbase + 4); 476 } 477 478 qemu_log_mask(CPU_LOG_INT, 479 "Loaded reset SP 0x%x PC 0x%x from vector table\n", 480 initial_msp, initial_pc); 481 482 env->regs[13] = initial_msp & 0xFFFFFFFC; 483 env->regs[15] = initial_pc & ~1; 484 env->thumb = initial_pc & 1; 485 #else 486 /* 487 * For user mode we run non-secure and with access to the FPU. 488 * The FPU context is active (ie does not need further setup) 489 * and is owned by non-secure. 490 */ 491 env->v7m.secure = false; 492 env->v7m.nsacr = 0xcff; 493 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 494 env->v7m.fpccr[M_REG_S] &= 495 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 496 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 497 #endif 498 } 499 500 /* M profile requires that reset clears the exclusive monitor; 501 * A profile does not, but clearing it makes more sense than having it 502 * set with an exclusive access on address zero. 503 */ 504 arm_clear_exclusive(env); 505 506 if (arm_feature(env, ARM_FEATURE_PMSA)) { 507 if (cpu->pmsav7_dregion > 0) { 508 if (arm_feature(env, ARM_FEATURE_V8)) { 509 memset(env->pmsav8.rbar[M_REG_NS], 0, 510 sizeof(*env->pmsav8.rbar[M_REG_NS]) 511 * cpu->pmsav7_dregion); 512 memset(env->pmsav8.rlar[M_REG_NS], 0, 513 sizeof(*env->pmsav8.rlar[M_REG_NS]) 514 * cpu->pmsav7_dregion); 515 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 516 memset(env->pmsav8.rbar[M_REG_S], 0, 517 sizeof(*env->pmsav8.rbar[M_REG_S]) 518 * cpu->pmsav7_dregion); 519 memset(env->pmsav8.rlar[M_REG_S], 0, 520 sizeof(*env->pmsav8.rlar[M_REG_S]) 521 * cpu->pmsav7_dregion); 522 } 523 } else if (arm_feature(env, ARM_FEATURE_V7)) { 524 memset(env->pmsav7.drbar, 0, 525 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 526 memset(env->pmsav7.drsr, 0, 527 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 528 memset(env->pmsav7.dracr, 0, 529 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 530 } 531 } 532 533 if (cpu->pmsav8r_hdregion > 0) { 534 memset(env->pmsav8.hprbar, 0, 535 sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion); 536 memset(env->pmsav8.hprlar, 0, 537 sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion); 538 } 539 540 env->pmsav7.rnr[M_REG_NS] = 0; 541 env->pmsav7.rnr[M_REG_S] = 0; 542 env->pmsav8.mair0[M_REG_NS] = 0; 543 env->pmsav8.mair0[M_REG_S] = 0; 544 env->pmsav8.mair1[M_REG_NS] = 0; 545 env->pmsav8.mair1[M_REG_S] = 0; 546 } 547 548 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 549 if (cpu->sau_sregion > 0) { 550 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 551 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 552 } 553 env->sau.rnr = 0; 554 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 555 * the Cortex-M33 does. 556 */ 557 env->sau.ctrl = 0; 558 } 559 560 set_flush_to_zero(1, &env->vfp.standard_fp_status); 561 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 562 set_default_nan_mode(1, &env->vfp.standard_fp_status); 563 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); 564 arm_set_default_fp_behaviours(&env->vfp.fp_status); 565 arm_set_default_fp_behaviours(&env->vfp.standard_fp_status); 566 arm_set_default_fp_behaviours(&env->vfp.fp_status_f16); 567 arm_set_default_fp_behaviours(&env->vfp.standard_fp_status_f16); 568 569 #ifndef CONFIG_USER_ONLY 570 if (kvm_enabled()) { 571 kvm_arm_reset_vcpu(cpu); 572 } 573 #endif 574 575 if (tcg_enabled()) { 576 hw_breakpoint_update_all(cpu); 577 hw_watchpoint_update_all(cpu); 578 579 arm_rebuild_hflags(env); 580 } 581 } 582 583 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el) 584 { 585 ARMCPU *cpu = ARM_CPU(cpustate); 586 CPUARMState *env = &cpu->env; 587 bool have_el3 = arm_feature(env, ARM_FEATURE_EL3); 588 bool have_el2 = arm_feature(env, ARM_FEATURE_EL2); 589 590 /* 591 * Check we have the EL we're aiming for. If that is the 592 * highest implemented EL, then cpu_reset has already done 593 * all the work. 594 */ 595 switch (target_el) { 596 case 3: 597 assert(have_el3); 598 return; 599 case 2: 600 assert(have_el2); 601 if (!have_el3) { 602 return; 603 } 604 break; 605 case 1: 606 if (!have_el3 && !have_el2) { 607 return; 608 } 609 break; 610 default: 611 g_assert_not_reached(); 612 } 613 614 if (have_el3) { 615 /* 616 * Set the EL3 state so code can run at EL2. This should match 617 * the requirements set by Linux in its booting spec. 618 */ 619 if (env->aarch64) { 620 env->cp15.scr_el3 |= SCR_RW; 621 if (cpu_isar_feature(aa64_pauth, cpu)) { 622 env->cp15.scr_el3 |= SCR_API | SCR_APK; 623 } 624 if (cpu_isar_feature(aa64_mte, cpu)) { 625 env->cp15.scr_el3 |= SCR_ATA; 626 } 627 if (cpu_isar_feature(aa64_sve, cpu)) { 628 env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK; 629 env->vfp.zcr_el[3] = 0xf; 630 } 631 if (cpu_isar_feature(aa64_sme, cpu)) { 632 env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK; 633 env->cp15.scr_el3 |= SCR_ENTP2; 634 env->vfp.smcr_el[3] = 0xf; 635 } 636 if (cpu_isar_feature(aa64_hcx, cpu)) { 637 env->cp15.scr_el3 |= SCR_HXEN; 638 } 639 if (cpu_isar_feature(aa64_fgt, cpu)) { 640 env->cp15.scr_el3 |= SCR_FGTEN; 641 } 642 } 643 644 if (target_el == 2) { 645 /* If the guest is at EL2 then Linux expects the HVC insn to work */ 646 env->cp15.scr_el3 |= SCR_HCE; 647 } 648 649 /* Put CPU into non-secure state */ 650 env->cp15.scr_el3 |= SCR_NS; 651 /* Set NSACR.{CP11,CP10} so NS can access the FPU */ 652 env->cp15.nsacr |= 3 << 10; 653 } 654 655 if (have_el2 && target_el < 2) { 656 /* Set EL2 state so code can run at EL1. */ 657 if (env->aarch64) { 658 env->cp15.hcr_el2 |= HCR_RW; 659 } 660 } 661 662 /* Set the CPU to the desired state */ 663 if (env->aarch64) { 664 env->pstate = aarch64_pstate_mode(target_el, true); 665 } else { 666 static const uint32_t mode_for_el[] = { 667 0, 668 ARM_CPU_MODE_SVC, 669 ARM_CPU_MODE_HYP, 670 ARM_CPU_MODE_SVC, 671 }; 672 673 cpsr_write(env, mode_for_el[target_el], CPSR_M, CPSRWriteRaw); 674 } 675 } 676 677 678 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 679 680 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 681 unsigned int target_el, 682 unsigned int cur_el, bool secure, 683 uint64_t hcr_el2) 684 { 685 CPUARMState *env = cpu_env(cs); 686 bool pstate_unmasked; 687 bool unmasked = false; 688 bool allIntMask = false; 689 690 /* 691 * Don't take exceptions if they target a lower EL. 692 * This check should catch any exceptions that would not be taken 693 * but left pending. 694 */ 695 if (cur_el > target_el) { 696 return false; 697 } 698 699 if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) && 700 env->cp15.sctlr_el[target_el] & SCTLR_NMI && cur_el == target_el) { 701 allIntMask = env->pstate & PSTATE_ALLINT || 702 ((env->cp15.sctlr_el[target_el] & SCTLR_SPINTMASK) && 703 (env->pstate & PSTATE_SP)); 704 } 705 706 switch (excp_idx) { 707 case EXCP_NMI: 708 pstate_unmasked = !allIntMask; 709 break; 710 711 case EXCP_VINMI: 712 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 713 /* VINMIs are only taken when hypervized. */ 714 return false; 715 } 716 return !allIntMask; 717 case EXCP_VFNMI: 718 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 719 /* VFNMIs are only taken when hypervized. */ 720 return false; 721 } 722 return !allIntMask; 723 case EXCP_FIQ: 724 pstate_unmasked = (!(env->daif & PSTATE_F)) && (!allIntMask); 725 break; 726 727 case EXCP_IRQ: 728 pstate_unmasked = (!(env->daif & PSTATE_I)) && (!allIntMask); 729 break; 730 731 case EXCP_VFIQ: 732 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 733 /* VFIQs are only taken when hypervized. */ 734 return false; 735 } 736 return !(env->daif & PSTATE_F) && (!allIntMask); 737 case EXCP_VIRQ: 738 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 739 /* VIRQs are only taken when hypervized. */ 740 return false; 741 } 742 return !(env->daif & PSTATE_I) && (!allIntMask); 743 case EXCP_VSERR: 744 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { 745 /* VIRQs are only taken when hypervized. */ 746 return false; 747 } 748 return !(env->daif & PSTATE_A); 749 default: 750 g_assert_not_reached(); 751 } 752 753 /* 754 * Use the target EL, current execution state and SCR/HCR settings to 755 * determine whether the corresponding CPSR bit is used to mask the 756 * interrupt. 757 */ 758 if ((target_el > cur_el) && (target_el != 1)) { 759 /* Exceptions targeting a higher EL may not be maskable */ 760 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 761 switch (target_el) { 762 case 2: 763 /* 764 * According to ARM DDI 0487H.a, an interrupt can be masked 765 * when HCR_E2H and HCR_TGE are both set regardless of the 766 * current Security state. Note that we need to revisit this 767 * part again once we need to support NMI. 768 */ 769 if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { 770 unmasked = true; 771 } 772 break; 773 case 3: 774 /* Interrupt cannot be masked when the target EL is 3 */ 775 unmasked = true; 776 break; 777 default: 778 g_assert_not_reached(); 779 } 780 } else { 781 /* 782 * The old 32-bit-only environment has a more complicated 783 * masking setup. HCR and SCR bits not only affect interrupt 784 * routing but also change the behaviour of masking. 785 */ 786 bool hcr, scr; 787 788 switch (excp_idx) { 789 case EXCP_FIQ: 790 /* 791 * If FIQs are routed to EL3 or EL2 then there are cases where 792 * we override the CPSR.F in determining if the exception is 793 * masked or not. If neither of these are set then we fall back 794 * to the CPSR.F setting otherwise we further assess the state 795 * below. 796 */ 797 hcr = hcr_el2 & HCR_FMO; 798 scr = (env->cp15.scr_el3 & SCR_FIQ); 799 800 /* 801 * When EL3 is 32-bit, the SCR.FW bit controls whether the 802 * CPSR.F bit masks FIQ interrupts when taken in non-secure 803 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 804 * when non-secure but only when FIQs are only routed to EL3. 805 */ 806 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 807 break; 808 case EXCP_IRQ: 809 /* 810 * When EL3 execution state is 32-bit, if HCR.IMO is set then 811 * we may override the CPSR.I masking when in non-secure state. 812 * The SCR.IRQ setting has already been taken into consideration 813 * when setting the target EL, so it does not have a further 814 * affect here. 815 */ 816 hcr = hcr_el2 & HCR_IMO; 817 scr = false; 818 break; 819 default: 820 g_assert_not_reached(); 821 } 822 823 if ((scr || hcr) && !secure) { 824 unmasked = true; 825 } 826 } 827 } 828 829 /* 830 * The PSTATE bits only mask the interrupt if we have not overridden the 831 * ability above. 832 */ 833 return unmasked || pstate_unmasked; 834 } 835 836 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 837 { 838 CPUClass *cc = CPU_GET_CLASS(cs); 839 CPUARMState *env = cpu_env(cs); 840 uint32_t cur_el = arm_current_el(env); 841 bool secure = arm_is_secure(env); 842 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 843 uint32_t target_el; 844 uint32_t excp_idx; 845 846 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 847 848 if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) && 849 (arm_sctlr(env, cur_el) & SCTLR_NMI)) { 850 if (interrupt_request & CPU_INTERRUPT_NMI) { 851 excp_idx = EXCP_NMI; 852 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 853 if (arm_excp_unmasked(cs, excp_idx, target_el, 854 cur_el, secure, hcr_el2)) { 855 goto found; 856 } 857 } 858 if (interrupt_request & CPU_INTERRUPT_VINMI) { 859 excp_idx = EXCP_VINMI; 860 target_el = 1; 861 if (arm_excp_unmasked(cs, excp_idx, target_el, 862 cur_el, secure, hcr_el2)) { 863 goto found; 864 } 865 } 866 if (interrupt_request & CPU_INTERRUPT_VFNMI) { 867 excp_idx = EXCP_VFNMI; 868 target_el = 1; 869 if (arm_excp_unmasked(cs, excp_idx, target_el, 870 cur_el, secure, hcr_el2)) { 871 goto found; 872 } 873 } 874 } else { 875 /* 876 * NMI disabled: interrupts with superpriority are handled 877 * as if they didn't have it 878 */ 879 if (interrupt_request & CPU_INTERRUPT_NMI) { 880 interrupt_request |= CPU_INTERRUPT_HARD; 881 } 882 if (interrupt_request & CPU_INTERRUPT_VINMI) { 883 interrupt_request |= CPU_INTERRUPT_VIRQ; 884 } 885 if (interrupt_request & CPU_INTERRUPT_VFNMI) { 886 interrupt_request |= CPU_INTERRUPT_VFIQ; 887 } 888 } 889 890 if (interrupt_request & CPU_INTERRUPT_FIQ) { 891 excp_idx = EXCP_FIQ; 892 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 893 if (arm_excp_unmasked(cs, excp_idx, target_el, 894 cur_el, secure, hcr_el2)) { 895 goto found; 896 } 897 } 898 if (interrupt_request & CPU_INTERRUPT_HARD) { 899 excp_idx = EXCP_IRQ; 900 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 901 if (arm_excp_unmasked(cs, excp_idx, target_el, 902 cur_el, secure, hcr_el2)) { 903 goto found; 904 } 905 } 906 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 907 excp_idx = EXCP_VIRQ; 908 target_el = 1; 909 if (arm_excp_unmasked(cs, excp_idx, target_el, 910 cur_el, secure, hcr_el2)) { 911 goto found; 912 } 913 } 914 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 915 excp_idx = EXCP_VFIQ; 916 target_el = 1; 917 if (arm_excp_unmasked(cs, excp_idx, target_el, 918 cur_el, secure, hcr_el2)) { 919 goto found; 920 } 921 } 922 if (interrupt_request & CPU_INTERRUPT_VSERR) { 923 excp_idx = EXCP_VSERR; 924 target_el = 1; 925 if (arm_excp_unmasked(cs, excp_idx, target_el, 926 cur_el, secure, hcr_el2)) { 927 /* Taking a virtual abort clears HCR_EL2.VSE */ 928 env->cp15.hcr_el2 &= ~HCR_VSE; 929 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 930 goto found; 931 } 932 } 933 return false; 934 935 found: 936 cs->exception_index = excp_idx; 937 env->exception.target_el = target_el; 938 cc->tcg_ops->do_interrupt(cs); 939 return true; 940 } 941 942 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 943 944 void arm_cpu_update_virq(ARMCPU *cpu) 945 { 946 /* 947 * Update the interrupt level for VIRQ, which is the logical OR of 948 * the HCR_EL2.VI bit and the input line level from the GIC. 949 */ 950 CPUARMState *env = &cpu->env; 951 CPUState *cs = CPU(cpu); 952 953 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VI) && 954 !(arm_hcrx_el2_eff(env) & HCRX_VINMI)) || 955 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 956 957 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 958 if (new_state) { 959 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 960 } else { 961 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 962 } 963 } 964 } 965 966 void arm_cpu_update_vfiq(ARMCPU *cpu) 967 { 968 /* 969 * Update the interrupt level for VFIQ, which is the logical OR of 970 * the HCR_EL2.VF bit and the input line level from the GIC. 971 */ 972 CPUARMState *env = &cpu->env; 973 CPUState *cs = CPU(cpu); 974 975 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VF) && 976 !(arm_hcrx_el2_eff(env) & HCRX_VFNMI)) || 977 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 978 979 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 980 if (new_state) { 981 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 982 } else { 983 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 984 } 985 } 986 } 987 988 void arm_cpu_update_vinmi(ARMCPU *cpu) 989 { 990 /* 991 * Update the interrupt level for VINMI, which is the logical OR of 992 * the HCRX_EL2.VINMI bit and the input line level from the GIC. 993 */ 994 CPUARMState *env = &cpu->env; 995 CPUState *cs = CPU(cpu); 996 997 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VI) && 998 (arm_hcrx_el2_eff(env) & HCRX_VINMI)) || 999 (env->irq_line_state & CPU_INTERRUPT_VINMI); 1000 1001 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VINMI) != 0)) { 1002 if (new_state) { 1003 cpu_interrupt(cs, CPU_INTERRUPT_VINMI); 1004 } else { 1005 cpu_reset_interrupt(cs, CPU_INTERRUPT_VINMI); 1006 } 1007 } 1008 } 1009 1010 void arm_cpu_update_vfnmi(ARMCPU *cpu) 1011 { 1012 /* 1013 * Update the interrupt level for VFNMI, which is the HCRX_EL2.VFNMI bit. 1014 */ 1015 CPUARMState *env = &cpu->env; 1016 CPUState *cs = CPU(cpu); 1017 1018 bool new_state = (arm_hcr_el2_eff(env) & HCR_VF) && 1019 (arm_hcrx_el2_eff(env) & HCRX_VFNMI); 1020 1021 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFNMI) != 0)) { 1022 if (new_state) { 1023 cpu_interrupt(cs, CPU_INTERRUPT_VFNMI); 1024 } else { 1025 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFNMI); 1026 } 1027 } 1028 } 1029 1030 void arm_cpu_update_vserr(ARMCPU *cpu) 1031 { 1032 /* 1033 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. 1034 */ 1035 CPUARMState *env = &cpu->env; 1036 CPUState *cs = CPU(cpu); 1037 1038 bool new_state = env->cp15.hcr_el2 & HCR_VSE; 1039 1040 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { 1041 if (new_state) { 1042 cpu_interrupt(cs, CPU_INTERRUPT_VSERR); 1043 } else { 1044 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 1045 } 1046 } 1047 } 1048 1049 #ifndef CONFIG_USER_ONLY 1050 static void arm_cpu_set_irq(void *opaque, int irq, int level) 1051 { 1052 ARMCPU *cpu = opaque; 1053 CPUARMState *env = &cpu->env; 1054 CPUState *cs = CPU(cpu); 1055 static const int mask[] = { 1056 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 1057 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 1058 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 1059 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ, 1060 [ARM_CPU_NMI] = CPU_INTERRUPT_NMI, 1061 [ARM_CPU_VINMI] = CPU_INTERRUPT_VINMI, 1062 }; 1063 1064 if (!arm_feature(env, ARM_FEATURE_EL2) && 1065 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { 1066 /* 1067 * The GIC might tell us about VIRQ and VFIQ state, but if we don't 1068 * have EL2 support we don't care. (Unless the guest is doing something 1069 * silly this will only be calls saying "level is still 0".) 1070 */ 1071 return; 1072 } 1073 1074 if (level) { 1075 env->irq_line_state |= mask[irq]; 1076 } else { 1077 env->irq_line_state &= ~mask[irq]; 1078 } 1079 1080 switch (irq) { 1081 case ARM_CPU_VIRQ: 1082 arm_cpu_update_virq(cpu); 1083 break; 1084 case ARM_CPU_VFIQ: 1085 arm_cpu_update_vfiq(cpu); 1086 break; 1087 case ARM_CPU_VINMI: 1088 arm_cpu_update_vinmi(cpu); 1089 break; 1090 case ARM_CPU_IRQ: 1091 case ARM_CPU_FIQ: 1092 case ARM_CPU_NMI: 1093 if (level) { 1094 cpu_interrupt(cs, mask[irq]); 1095 } else { 1096 cpu_reset_interrupt(cs, mask[irq]); 1097 } 1098 break; 1099 default: 1100 g_assert_not_reached(); 1101 } 1102 } 1103 1104 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 1105 { 1106 #ifdef CONFIG_KVM 1107 ARMCPU *cpu = opaque; 1108 CPUARMState *env = &cpu->env; 1109 CPUState *cs = CPU(cpu); 1110 uint32_t linestate_bit; 1111 int irq_id; 1112 1113 switch (irq) { 1114 case ARM_CPU_IRQ: 1115 irq_id = KVM_ARM_IRQ_CPU_IRQ; 1116 linestate_bit = CPU_INTERRUPT_HARD; 1117 break; 1118 case ARM_CPU_FIQ: 1119 irq_id = KVM_ARM_IRQ_CPU_FIQ; 1120 linestate_bit = CPU_INTERRUPT_FIQ; 1121 break; 1122 default: 1123 g_assert_not_reached(); 1124 } 1125 1126 if (level) { 1127 env->irq_line_state |= linestate_bit; 1128 } else { 1129 env->irq_line_state &= ~linestate_bit; 1130 } 1131 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 1132 #endif 1133 } 1134 1135 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 1136 { 1137 ARMCPU *cpu = ARM_CPU(cs); 1138 CPUARMState *env = &cpu->env; 1139 1140 cpu_synchronize_state(cs); 1141 return arm_cpu_data_is_big_endian(env); 1142 } 1143 1144 #ifdef CONFIG_TCG 1145 bool arm_cpu_exec_halt(CPUState *cs) 1146 { 1147 bool leave_halt = cpu_has_work(cs); 1148 1149 if (leave_halt) { 1150 /* We're about to come out of WFI/WFE: disable the WFxT timer */ 1151 ARMCPU *cpu = ARM_CPU(cs); 1152 if (cpu->wfxt_timer) { 1153 timer_del(cpu->wfxt_timer); 1154 } 1155 } 1156 return leave_halt; 1157 } 1158 #endif 1159 1160 static void arm_wfxt_timer_cb(void *opaque) 1161 { 1162 ARMCPU *cpu = opaque; 1163 CPUState *cs = CPU(cpu); 1164 1165 /* 1166 * We expect the CPU to be halted; this will cause arm_cpu_is_work() 1167 * to return true (so we will come out of halt even with no other 1168 * pending interrupt), and the TCG accelerator's cpu_exec_interrupt() 1169 * function auto-clears the CPU_INTERRUPT_EXITTB flag for us. 1170 */ 1171 cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); 1172 } 1173 #endif 1174 1175 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 1176 { 1177 ARMCPU *ac = ARM_CPU(cpu); 1178 CPUARMState *env = &ac->env; 1179 bool sctlr_b; 1180 1181 if (is_a64(env)) { 1182 info->cap_arch = CS_ARCH_ARM64; 1183 info->cap_insn_unit = 4; 1184 info->cap_insn_split = 4; 1185 } else { 1186 int cap_mode; 1187 if (env->thumb) { 1188 info->cap_insn_unit = 2; 1189 info->cap_insn_split = 4; 1190 cap_mode = CS_MODE_THUMB; 1191 } else { 1192 info->cap_insn_unit = 4; 1193 info->cap_insn_split = 4; 1194 cap_mode = CS_MODE_ARM; 1195 } 1196 if (arm_feature(env, ARM_FEATURE_V8)) { 1197 cap_mode |= CS_MODE_V8; 1198 } 1199 if (arm_feature(env, ARM_FEATURE_M)) { 1200 cap_mode |= CS_MODE_MCLASS; 1201 } 1202 info->cap_arch = CS_ARCH_ARM; 1203 info->cap_mode = cap_mode; 1204 } 1205 1206 sctlr_b = arm_sctlr_b(env); 1207 if (bswap_code(sctlr_b)) { 1208 #if TARGET_BIG_ENDIAN 1209 info->endian = BFD_ENDIAN_LITTLE; 1210 #else 1211 info->endian = BFD_ENDIAN_BIG; 1212 #endif 1213 } 1214 info->flags &= ~INSN_ARM_BE32; 1215 #ifndef CONFIG_USER_ONLY 1216 if (sctlr_b) { 1217 info->flags |= INSN_ARM_BE32; 1218 } 1219 #endif 1220 } 1221 1222 #ifdef TARGET_AARCH64 1223 1224 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1225 { 1226 ARMCPU *cpu = ARM_CPU(cs); 1227 CPUARMState *env = &cpu->env; 1228 uint32_t psr = pstate_read(env); 1229 int i, j; 1230 int el = arm_current_el(env); 1231 uint64_t hcr = arm_hcr_el2_eff(env); 1232 const char *ns_status; 1233 bool sve; 1234 1235 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 1236 for (i = 0; i < 32; i++) { 1237 if (i == 31) { 1238 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 1239 } else { 1240 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 1241 (i + 2) % 3 ? " " : "\n"); 1242 } 1243 } 1244 1245 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 1246 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1247 } else { 1248 ns_status = ""; 1249 } 1250 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 1251 psr, 1252 psr & PSTATE_N ? 'N' : '-', 1253 psr & PSTATE_Z ? 'Z' : '-', 1254 psr & PSTATE_C ? 'C' : '-', 1255 psr & PSTATE_V ? 'V' : '-', 1256 ns_status, 1257 el, 1258 psr & PSTATE_SP ? 'h' : 't'); 1259 1260 if (cpu_isar_feature(aa64_sme, cpu)) { 1261 qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c", 1262 env->svcr, 1263 (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), 1264 (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); 1265 } 1266 if (cpu_isar_feature(aa64_bti, cpu)) { 1267 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 1268 } 1269 qemu_fprintf(f, "%s%s%s", 1270 (hcr & HCR_NV) ? " NV" : "", 1271 (hcr & HCR_NV1) ? " NV1" : "", 1272 (hcr & HCR_NV2) ? " NV2" : ""); 1273 if (!(flags & CPU_DUMP_FPU)) { 1274 qemu_fprintf(f, "\n"); 1275 return; 1276 } 1277 if (fp_exception_el(env, el) != 0) { 1278 qemu_fprintf(f, " FPU disabled\n"); 1279 return; 1280 } 1281 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 1282 vfp_get_fpcr(env), vfp_get_fpsr(env)); 1283 1284 if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) { 1285 sve = sme_exception_el(env, el) == 0; 1286 } else if (cpu_isar_feature(aa64_sve, cpu)) { 1287 sve = sve_exception_el(env, el) == 0; 1288 } else { 1289 sve = false; 1290 } 1291 1292 if (sve) { 1293 int zcr_len = sve_vqm1_for_el(env, el); 1294 1295 for (i = 0; i <= FFR_PRED_NUM; i++) { 1296 bool eol; 1297 if (i == FFR_PRED_NUM) { 1298 qemu_fprintf(f, "FFR="); 1299 /* It's last, so end the line. */ 1300 eol = true; 1301 } else { 1302 qemu_fprintf(f, "P%02d=", i); 1303 switch (zcr_len) { 1304 case 0: 1305 eol = i % 8 == 7; 1306 break; 1307 case 1: 1308 eol = i % 6 == 5; 1309 break; 1310 case 2: 1311 case 3: 1312 eol = i % 3 == 2; 1313 break; 1314 default: 1315 /* More than one quadword per predicate. */ 1316 eol = true; 1317 break; 1318 } 1319 } 1320 for (j = zcr_len / 4; j >= 0; j--) { 1321 int digits; 1322 if (j * 4 + 4 <= zcr_len + 1) { 1323 digits = 16; 1324 } else { 1325 digits = (zcr_len % 4 + 1) * 4; 1326 } 1327 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 1328 env->vfp.pregs[i].p[j], 1329 j ? ":" : eol ? "\n" : " "); 1330 } 1331 } 1332 1333 if (zcr_len == 0) { 1334 /* 1335 * With vl=16, there are only 37 columns per register, 1336 * so output two registers per line. 1337 */ 1338 for (i = 0; i < 32; i++) { 1339 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1340 i, env->vfp.zregs[i].d[1], 1341 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 1342 } 1343 } else { 1344 for (i = 0; i < 32; i++) { 1345 qemu_fprintf(f, "Z%02d=", i); 1346 for (j = zcr_len; j >= 0; j--) { 1347 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 1348 env->vfp.zregs[i].d[j * 2 + 1], 1349 env->vfp.zregs[i].d[j * 2 + 0], 1350 j ? ":" : "\n"); 1351 } 1352 } 1353 } 1354 } else { 1355 for (i = 0; i < 32; i++) { 1356 uint64_t *q = aa64_vfp_qreg(env, i); 1357 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1358 i, q[1], q[0], (i & 1 ? "\n" : " ")); 1359 } 1360 } 1361 1362 if (cpu_isar_feature(aa64_sme, cpu) && 1363 FIELD_EX64(env->svcr, SVCR, ZA) && 1364 sme_exception_el(env, el) == 0) { 1365 int zcr_len = sve_vqm1_for_el_sm(env, el, true); 1366 int svl = (zcr_len + 1) * 16; 1367 int svl_lg10 = svl < 100 ? 2 : 3; 1368 1369 for (i = 0; i < svl; i++) { 1370 qemu_fprintf(f, "ZA[%0*d]=", svl_lg10, i); 1371 for (j = zcr_len; j >= 0; --j) { 1372 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%c", 1373 env->zarray[i].d[2 * j + 1], 1374 env->zarray[i].d[2 * j], 1375 j ? ':' : '\n'); 1376 } 1377 } 1378 } 1379 } 1380 1381 #else 1382 1383 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1384 { 1385 g_assert_not_reached(); 1386 } 1387 1388 #endif 1389 1390 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1391 { 1392 ARMCPU *cpu = ARM_CPU(cs); 1393 CPUARMState *env = &cpu->env; 1394 int i; 1395 1396 if (is_a64(env)) { 1397 aarch64_cpu_dump_state(cs, f, flags); 1398 return; 1399 } 1400 1401 for (i = 0; i < 16; i++) { 1402 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 1403 if ((i % 4) == 3) { 1404 qemu_fprintf(f, "\n"); 1405 } else { 1406 qemu_fprintf(f, " "); 1407 } 1408 } 1409 1410 if (arm_feature(env, ARM_FEATURE_M)) { 1411 uint32_t xpsr = xpsr_read(env); 1412 const char *mode; 1413 const char *ns_status = ""; 1414 1415 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1416 ns_status = env->v7m.secure ? "S " : "NS "; 1417 } 1418 1419 if (xpsr & XPSR_EXCP) { 1420 mode = "handler"; 1421 } else { 1422 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 1423 mode = "unpriv-thread"; 1424 } else { 1425 mode = "priv-thread"; 1426 } 1427 } 1428 1429 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 1430 xpsr, 1431 xpsr & XPSR_N ? 'N' : '-', 1432 xpsr & XPSR_Z ? 'Z' : '-', 1433 xpsr & XPSR_C ? 'C' : '-', 1434 xpsr & XPSR_V ? 'V' : '-', 1435 xpsr & XPSR_T ? 'T' : 'A', 1436 ns_status, 1437 mode); 1438 } else { 1439 uint32_t psr = cpsr_read(env); 1440 const char *ns_status = ""; 1441 1442 if (arm_feature(env, ARM_FEATURE_EL3) && 1443 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1444 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1445 } 1446 1447 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1448 psr, 1449 psr & CPSR_N ? 'N' : '-', 1450 psr & CPSR_Z ? 'Z' : '-', 1451 psr & CPSR_C ? 'C' : '-', 1452 psr & CPSR_V ? 'V' : '-', 1453 psr & CPSR_T ? 'T' : 'A', 1454 ns_status, 1455 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1456 } 1457 1458 if (flags & CPU_DUMP_FPU) { 1459 int numvfpregs = 0; 1460 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1461 numvfpregs = 32; 1462 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1463 numvfpregs = 16; 1464 } 1465 for (i = 0; i < numvfpregs; i++) { 1466 uint64_t v = *aa32_vfp_dreg(env, i); 1467 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1468 i * 2, (uint32_t)v, 1469 i * 2 + 1, (uint32_t)(v >> 32), 1470 i, v); 1471 } 1472 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1473 if (cpu_isar_feature(aa32_mve, cpu)) { 1474 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1475 } 1476 } 1477 } 1478 1479 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz) 1480 { 1481 uint32_t Aff1 = idx / clustersz; 1482 uint32_t Aff0 = idx % clustersz; 1483 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1484 } 1485 1486 uint64_t arm_cpu_mp_affinity(ARMCPU *cpu) 1487 { 1488 return cpu->mp_affinity; 1489 } 1490 1491 static void arm_cpu_initfn(Object *obj) 1492 { 1493 ARMCPU *cpu = ARM_CPU(obj); 1494 1495 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, 1496 NULL, g_free); 1497 1498 QLIST_INIT(&cpu->pre_el_change_hooks); 1499 QLIST_INIT(&cpu->el_change_hooks); 1500 1501 #ifdef CONFIG_USER_ONLY 1502 # ifdef TARGET_AARCH64 1503 /* 1504 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME. 1505 * These values were chosen to fit within the default signal frame. 1506 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length, 1507 * and our corresponding cpu property. 1508 */ 1509 cpu->sve_default_vq = 4; 1510 cpu->sme_default_vq = 2; 1511 # endif 1512 #else 1513 /* Our inbound IRQ and FIQ lines */ 1514 if (kvm_enabled()) { 1515 /* 1516 * VIRQ, VFIQ, NMI, VINMI are unused with KVM but we add 1517 * them to maintain the same interface as non-KVM CPUs. 1518 */ 1519 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 6); 1520 } else { 1521 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 6); 1522 } 1523 1524 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1525 ARRAY_SIZE(cpu->gt_timer_outputs)); 1526 1527 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1528 "gicv3-maintenance-interrupt", 1); 1529 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1530 "pmu-interrupt", 1); 1531 #endif 1532 1533 /* DTB consumers generally don't in fact care what the 'compatible' 1534 * string is, so always provide some string and trust that a hypothetical 1535 * picky DTB consumer will also provide a helpful error message. 1536 */ 1537 cpu->dtb_compatible = "qemu,unknown"; 1538 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ 1539 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1540 1541 if (tcg_enabled() || hvf_enabled()) { 1542 /* TCG and HVF implement PSCI 1.1 */ 1543 cpu->psci_version = QEMU_PSCI_VERSION_1_1; 1544 } 1545 } 1546 1547 /* 1548 * 0 means "unset, use the default value". That default might vary depending 1549 * on the CPU type, and is set in the realize fn. 1550 */ 1551 static Property arm_cpu_gt_cntfrq_property = 1552 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 0); 1553 1554 static Property arm_cpu_reset_cbar_property = 1555 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1556 1557 static Property arm_cpu_reset_hivecs_property = 1558 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1559 1560 #ifndef CONFIG_USER_ONLY 1561 static Property arm_cpu_has_el2_property = 1562 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1563 1564 static Property arm_cpu_has_el3_property = 1565 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1566 #endif 1567 1568 static Property arm_cpu_cfgend_property = 1569 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1570 1571 static Property arm_cpu_has_vfp_property = 1572 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1573 1574 static Property arm_cpu_has_vfp_d32_property = 1575 DEFINE_PROP_BOOL("vfp-d32", ARMCPU, has_vfp_d32, true); 1576 1577 static Property arm_cpu_has_neon_property = 1578 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1579 1580 static Property arm_cpu_has_dsp_property = 1581 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1582 1583 static Property arm_cpu_has_mpu_property = 1584 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1585 1586 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1587 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1588 * the right value for that particular CPU type, and we don't want 1589 * to override that with an incorrect constant value. 1590 */ 1591 static Property arm_cpu_pmsav7_dregion_property = 1592 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1593 pmsav7_dregion, 1594 qdev_prop_uint32, uint32_t); 1595 1596 static bool arm_get_pmu(Object *obj, Error **errp) 1597 { 1598 ARMCPU *cpu = ARM_CPU(obj); 1599 1600 return cpu->has_pmu; 1601 } 1602 1603 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1604 { 1605 ARMCPU *cpu = ARM_CPU(obj); 1606 1607 if (value) { 1608 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1609 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1610 return; 1611 } 1612 set_feature(&cpu->env, ARM_FEATURE_PMU); 1613 } else { 1614 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1615 } 1616 cpu->has_pmu = value; 1617 } 1618 1619 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1620 { 1621 /* 1622 * The exact approach to calculating guest ticks is: 1623 * 1624 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1625 * NANOSECONDS_PER_SECOND); 1626 * 1627 * We don't do that. Rather we intentionally use integer division 1628 * truncation below and in the caller for the conversion of host monotonic 1629 * time to guest ticks to provide the exact inverse for the semantics of 1630 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1631 * it loses precision when representing frequencies where 1632 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1633 * provide an exact inverse leads to scheduling timers with negative 1634 * periods, which in turn leads to sticky behaviour in the guest. 1635 * 1636 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1637 * cannot become zero. 1638 */ 1639 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1640 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1641 } 1642 1643 static void arm_cpu_propagate_feature_implications(ARMCPU *cpu) 1644 { 1645 CPUARMState *env = &cpu->env; 1646 bool no_aa32 = false; 1647 1648 /* 1649 * Some features automatically imply others: set the feature 1650 * bits explicitly for these cases. 1651 */ 1652 1653 if (arm_feature(env, ARM_FEATURE_M)) { 1654 set_feature(env, ARM_FEATURE_PMSA); 1655 } 1656 1657 if (arm_feature(env, ARM_FEATURE_V8)) { 1658 if (arm_feature(env, ARM_FEATURE_M)) { 1659 set_feature(env, ARM_FEATURE_V7); 1660 } else { 1661 set_feature(env, ARM_FEATURE_V7VE); 1662 } 1663 } 1664 1665 /* 1666 * There exist AArch64 cpus without AArch32 support. When KVM 1667 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1668 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1669 * As a general principle, we also do not make ID register 1670 * consistency checks anywhere unless using TCG, because only 1671 * for TCG would a consistency-check failure be a QEMU bug. 1672 */ 1673 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1674 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1675 } 1676 1677 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1678 /* 1679 * v7 Virtualization Extensions. In real hardware this implies 1680 * EL2 and also the presence of the Security Extensions. 1681 * For QEMU, for backwards-compatibility we implement some 1682 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1683 * include the various other features that V7VE implies. 1684 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1685 * Security Extensions is ARM_FEATURE_EL3. 1686 */ 1687 assert(!tcg_enabled() || no_aa32 || 1688 cpu_isar_feature(aa32_arm_div, cpu)); 1689 set_feature(env, ARM_FEATURE_LPAE); 1690 set_feature(env, ARM_FEATURE_V7); 1691 } 1692 if (arm_feature(env, ARM_FEATURE_V7)) { 1693 set_feature(env, ARM_FEATURE_VAPA); 1694 set_feature(env, ARM_FEATURE_THUMB2); 1695 set_feature(env, ARM_FEATURE_MPIDR); 1696 if (!arm_feature(env, ARM_FEATURE_M)) { 1697 set_feature(env, ARM_FEATURE_V6K); 1698 } else { 1699 set_feature(env, ARM_FEATURE_V6); 1700 } 1701 1702 /* 1703 * Always define VBAR for V7 CPUs even if it doesn't exist in 1704 * non-EL3 configs. This is needed by some legacy boards. 1705 */ 1706 set_feature(env, ARM_FEATURE_VBAR); 1707 } 1708 if (arm_feature(env, ARM_FEATURE_V6K)) { 1709 set_feature(env, ARM_FEATURE_V6); 1710 set_feature(env, ARM_FEATURE_MVFR); 1711 } 1712 if (arm_feature(env, ARM_FEATURE_V6)) { 1713 set_feature(env, ARM_FEATURE_V5); 1714 if (!arm_feature(env, ARM_FEATURE_M)) { 1715 assert(!tcg_enabled() || no_aa32 || 1716 cpu_isar_feature(aa32_jazelle, cpu)); 1717 set_feature(env, ARM_FEATURE_AUXCR); 1718 } 1719 } 1720 if (arm_feature(env, ARM_FEATURE_V5)) { 1721 set_feature(env, ARM_FEATURE_V4T); 1722 } 1723 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1724 set_feature(env, ARM_FEATURE_V7MP); 1725 } 1726 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1727 set_feature(env, ARM_FEATURE_CBAR); 1728 } 1729 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1730 !arm_feature(env, ARM_FEATURE_M)) { 1731 set_feature(env, ARM_FEATURE_THUMB_DSP); 1732 } 1733 } 1734 1735 void arm_cpu_post_init(Object *obj) 1736 { 1737 ARMCPU *cpu = ARM_CPU(obj); 1738 1739 /* 1740 * Some features imply others. Figure this out now, because we 1741 * are going to look at the feature bits in deciding which 1742 * properties to add. 1743 */ 1744 arm_cpu_propagate_feature_implications(cpu); 1745 1746 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1747 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1748 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1749 } 1750 1751 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1752 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1753 } 1754 1755 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1756 object_property_add_uint64_ptr(obj, "rvbar", 1757 &cpu->rvbar_prop, 1758 OBJ_PROP_FLAG_READWRITE); 1759 } 1760 1761 #ifndef CONFIG_USER_ONLY 1762 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1763 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1764 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1765 */ 1766 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1767 1768 object_property_add_link(obj, "secure-memory", 1769 TYPE_MEMORY_REGION, 1770 (Object **)&cpu->secure_memory, 1771 qdev_prop_allow_set_link_before_realize, 1772 OBJ_PROP_LINK_STRONG); 1773 } 1774 1775 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1776 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1777 } 1778 #endif 1779 1780 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1781 cpu->has_pmu = true; 1782 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1783 } 1784 1785 /* 1786 * Allow user to turn off VFP and Neon support, but only for TCG -- 1787 * KVM does not currently allow us to lie to the guest about its 1788 * ID/feature registers, so the guest always sees what the host has. 1789 */ 1790 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1791 if (cpu_isar_feature(aa64_fp_simd, cpu)) { 1792 cpu->has_vfp = true; 1793 cpu->has_vfp_d32 = true; 1794 if (tcg_enabled() || qtest_enabled()) { 1795 qdev_property_add_static(DEVICE(obj), 1796 &arm_cpu_has_vfp_property); 1797 } 1798 } 1799 } else if (cpu_isar_feature(aa32_vfp, cpu)) { 1800 cpu->has_vfp = true; 1801 if (tcg_enabled() || qtest_enabled()) { 1802 qdev_property_add_static(DEVICE(obj), 1803 &arm_cpu_has_vfp_property); 1804 } 1805 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1806 cpu->has_vfp_d32 = true; 1807 /* 1808 * The permitted values of the SIMDReg bits [3:0] on 1809 * Armv8-A are either 0b0000 and 0b0010. On such CPUs, 1810 * make sure that has_vfp_d32 can not be set to false. 1811 */ 1812 if ((tcg_enabled() || qtest_enabled()) 1813 && !(arm_feature(&cpu->env, ARM_FEATURE_V8) 1814 && !arm_feature(&cpu->env, ARM_FEATURE_M))) { 1815 qdev_property_add_static(DEVICE(obj), 1816 &arm_cpu_has_vfp_d32_property); 1817 } 1818 } 1819 } 1820 1821 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1822 cpu->has_neon = true; 1823 if (!kvm_enabled()) { 1824 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1825 } 1826 } 1827 1828 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1829 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1830 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1831 } 1832 1833 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1834 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1835 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1836 qdev_property_add_static(DEVICE(obj), 1837 &arm_cpu_pmsav7_dregion_property); 1838 } 1839 } 1840 1841 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1842 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1843 qdev_prop_allow_set_link_before_realize, 1844 OBJ_PROP_LINK_STRONG); 1845 /* 1846 * M profile: initial value of the Secure VTOR. We can't just use 1847 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1848 * the property to be set after realize. 1849 */ 1850 object_property_add_uint32_ptr(obj, "init-svtor", 1851 &cpu->init_svtor, 1852 OBJ_PROP_FLAG_READWRITE); 1853 } 1854 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1855 /* 1856 * Initial value of the NS VTOR (for cores without the Security 1857 * extension, this is the only VTOR) 1858 */ 1859 object_property_add_uint32_ptr(obj, "init-nsvtor", 1860 &cpu->init_nsvtor, 1861 OBJ_PROP_FLAG_READWRITE); 1862 } 1863 1864 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ 1865 object_property_add_uint32_ptr(obj, "psci-conduit", 1866 &cpu->psci_conduit, 1867 OBJ_PROP_FLAG_READWRITE); 1868 1869 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1870 1871 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1872 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1873 } 1874 1875 if (kvm_enabled()) { 1876 kvm_arm_add_vcpu_properties(cpu); 1877 } 1878 1879 #ifndef CONFIG_USER_ONLY 1880 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1881 cpu_isar_feature(aa64_mte, cpu)) { 1882 object_property_add_link(obj, "tag-memory", 1883 TYPE_MEMORY_REGION, 1884 (Object **)&cpu->tag_memory, 1885 qdev_prop_allow_set_link_before_realize, 1886 OBJ_PROP_LINK_STRONG); 1887 1888 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1889 object_property_add_link(obj, "secure-tag-memory", 1890 TYPE_MEMORY_REGION, 1891 (Object **)&cpu->secure_tag_memory, 1892 qdev_prop_allow_set_link_before_realize, 1893 OBJ_PROP_LINK_STRONG); 1894 } 1895 } 1896 #endif 1897 } 1898 1899 static void arm_cpu_finalizefn(Object *obj) 1900 { 1901 ARMCPU *cpu = ARM_CPU(obj); 1902 ARMELChangeHook *hook, *next; 1903 1904 g_hash_table_destroy(cpu->cp_regs); 1905 1906 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1907 QLIST_REMOVE(hook, node); 1908 g_free(hook); 1909 } 1910 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1911 QLIST_REMOVE(hook, node); 1912 g_free(hook); 1913 } 1914 #ifndef CONFIG_USER_ONLY 1915 if (cpu->pmu_timer) { 1916 timer_free(cpu->pmu_timer); 1917 } 1918 if (cpu->wfxt_timer) { 1919 timer_free(cpu->wfxt_timer); 1920 } 1921 #endif 1922 } 1923 1924 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1925 { 1926 Error *local_err = NULL; 1927 1928 #ifdef TARGET_AARCH64 1929 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1930 arm_cpu_sve_finalize(cpu, &local_err); 1931 if (local_err != NULL) { 1932 error_propagate(errp, local_err); 1933 return; 1934 } 1935 1936 /* 1937 * FEAT_SME is not architecturally dependent on FEAT_SVE (unless 1938 * FEAT_SME_FA64 is present). However our implementation currently 1939 * assumes it, so if the user asked for sve=off then turn off SME also. 1940 * (KVM doesn't currently support SME at all.) 1941 */ 1942 if (cpu_isar_feature(aa64_sme, cpu) && !cpu_isar_feature(aa64_sve, cpu)) { 1943 object_property_set_bool(OBJECT(cpu), "sme", false, &error_abort); 1944 } 1945 1946 arm_cpu_sme_finalize(cpu, &local_err); 1947 if (local_err != NULL) { 1948 error_propagate(errp, local_err); 1949 return; 1950 } 1951 1952 arm_cpu_pauth_finalize(cpu, &local_err); 1953 if (local_err != NULL) { 1954 error_propagate(errp, local_err); 1955 return; 1956 } 1957 1958 arm_cpu_lpa2_finalize(cpu, &local_err); 1959 if (local_err != NULL) { 1960 error_propagate(errp, local_err); 1961 return; 1962 } 1963 } 1964 #endif 1965 1966 if (kvm_enabled()) { 1967 kvm_arm_steal_time_finalize(cpu, &local_err); 1968 if (local_err != NULL) { 1969 error_propagate(errp, local_err); 1970 return; 1971 } 1972 } 1973 } 1974 1975 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1976 { 1977 CPUState *cs = CPU(dev); 1978 ARMCPU *cpu = ARM_CPU(dev); 1979 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1980 CPUARMState *env = &cpu->env; 1981 Error *local_err = NULL; 1982 1983 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 1984 /* Use pc-relative instructions in system-mode */ 1985 tcg_cflags_set(cs, CF_PCREL); 1986 #endif 1987 1988 /* If we needed to query the host kernel for the CPU features 1989 * then it's possible that might have failed in the initfn, but 1990 * this is the first point where we can report it. 1991 */ 1992 if (cpu->host_cpu_probe_failed) { 1993 if (!kvm_enabled() && !hvf_enabled()) { 1994 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1995 } else { 1996 error_setg(errp, "Failed to retrieve host CPU features"); 1997 } 1998 return; 1999 } 2000 2001 if (!cpu->gt_cntfrq_hz) { 2002 /* 2003 * 0 means "the board didn't set a value, use the default". (We also 2004 * get here for the CONFIG_USER_ONLY case.) 2005 * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before 2006 * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz, 2007 * which gives a 16ns tick period. 2008 * 2009 * We will use the back-compat value: 2010 * - for QEMU CPU types added before we standardized on 1GHz 2011 * - for versioned machine types with a version of 9.0 or earlier 2012 */ 2013 if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) || 2014 cpu->backcompat_cntfrq) { 2015 cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ; 2016 } else { 2017 cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ; 2018 } 2019 } 2020 2021 #ifndef CONFIG_USER_ONLY 2022 /* The NVIC and M-profile CPU are two halves of a single piece of 2023 * hardware; trying to use one without the other is a command line 2024 * error and will result in segfaults if not caught here. 2025 */ 2026 if (arm_feature(env, ARM_FEATURE_M)) { 2027 if (!env->nvic) { 2028 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 2029 return; 2030 } 2031 } else { 2032 if (env->nvic) { 2033 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 2034 return; 2035 } 2036 } 2037 2038 if (!tcg_enabled() && !qtest_enabled()) { 2039 /* 2040 * We assume that no accelerator except TCG (and the "not really an 2041 * accelerator" qtest) can handle these features, because Arm hardware 2042 * virtualization can't virtualize them. 2043 * 2044 * Catch all the cases which might cause us to create more than one 2045 * address space for the CPU (otherwise we will assert() later in 2046 * cpu_address_space_init()). 2047 */ 2048 if (arm_feature(env, ARM_FEATURE_M)) { 2049 error_setg(errp, 2050 "Cannot enable %s when using an M-profile guest CPU", 2051 current_accel_name()); 2052 return; 2053 } 2054 if (cpu->has_el3) { 2055 error_setg(errp, 2056 "Cannot enable %s when guest CPU has EL3 enabled", 2057 current_accel_name()); 2058 return; 2059 } 2060 if (cpu->tag_memory) { 2061 error_setg(errp, 2062 "Cannot enable %s when guest CPUs has MTE enabled", 2063 current_accel_name()); 2064 return; 2065 } 2066 } 2067 2068 { 2069 uint64_t scale = gt_cntfrq_period_ns(cpu); 2070 2071 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2072 arm_gt_ptimer_cb, cpu); 2073 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2074 arm_gt_vtimer_cb, cpu); 2075 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2076 arm_gt_htimer_cb, cpu); 2077 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2078 arm_gt_stimer_cb, cpu); 2079 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2080 arm_gt_hvtimer_cb, cpu); 2081 } 2082 #endif 2083 2084 cpu_exec_realizefn(cs, &local_err); 2085 if (local_err != NULL) { 2086 error_propagate(errp, local_err); 2087 return; 2088 } 2089 2090 arm_cpu_finalize_features(cpu, &local_err); 2091 if (local_err != NULL) { 2092 error_propagate(errp, local_err); 2093 return; 2094 } 2095 2096 #ifdef CONFIG_USER_ONLY 2097 /* 2098 * User mode relies on IC IVAU instructions to catch modification of 2099 * dual-mapped code. 2100 * 2101 * Clear CTR_EL0.DIC to ensure that software that honors these flags uses 2102 * IC IVAU even if the emulated processor does not normally require it. 2103 */ 2104 cpu->ctr = FIELD_DP64(cpu->ctr, CTR_EL0, DIC, 0); 2105 #endif 2106 2107 if (arm_feature(env, ARM_FEATURE_AARCH64) && 2108 cpu->has_vfp != cpu->has_neon) { 2109 /* 2110 * This is an architectural requirement for AArch64; AArch32 is 2111 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 2112 */ 2113 error_setg(errp, 2114 "AArch64 CPUs must have both VFP and Neon or neither"); 2115 return; 2116 } 2117 2118 if (cpu->has_vfp_d32 != cpu->has_neon) { 2119 error_setg(errp, "ARM CPUs must have both VFP-D32 and Neon or neither"); 2120 return; 2121 } 2122 2123 if (!cpu->has_vfp_d32) { 2124 uint32_t u; 2125 2126 u = cpu->isar.mvfr0; 2127 u = FIELD_DP32(u, MVFR0, SIMDREG, 1); /* 16 registers */ 2128 cpu->isar.mvfr0 = u; 2129 } 2130 2131 if (!cpu->has_vfp) { 2132 uint64_t t; 2133 uint32_t u; 2134 2135 t = cpu->isar.id_aa64isar1; 2136 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 2137 cpu->isar.id_aa64isar1 = t; 2138 2139 t = cpu->isar.id_aa64pfr0; 2140 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 2141 cpu->isar.id_aa64pfr0 = t; 2142 2143 u = cpu->isar.id_isar6; 2144 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 2145 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 2146 cpu->isar.id_isar6 = u; 2147 2148 u = cpu->isar.mvfr0; 2149 u = FIELD_DP32(u, MVFR0, FPSP, 0); 2150 u = FIELD_DP32(u, MVFR0, FPDP, 0); 2151 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 2152 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 2153 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 2154 if (!arm_feature(env, ARM_FEATURE_M)) { 2155 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 2156 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 2157 } 2158 cpu->isar.mvfr0 = u; 2159 2160 u = cpu->isar.mvfr1; 2161 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 2162 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 2163 u = FIELD_DP32(u, MVFR1, FPHP, 0); 2164 if (arm_feature(env, ARM_FEATURE_M)) { 2165 u = FIELD_DP32(u, MVFR1, FP16, 0); 2166 } 2167 cpu->isar.mvfr1 = u; 2168 2169 u = cpu->isar.mvfr2; 2170 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 2171 cpu->isar.mvfr2 = u; 2172 } 2173 2174 if (!cpu->has_neon) { 2175 uint64_t t; 2176 uint32_t u; 2177 2178 unset_feature(env, ARM_FEATURE_NEON); 2179 2180 t = cpu->isar.id_aa64isar0; 2181 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); 2182 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); 2183 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); 2184 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); 2185 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); 2186 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); 2187 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 2188 cpu->isar.id_aa64isar0 = t; 2189 2190 t = cpu->isar.id_aa64isar1; 2191 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 2192 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 2193 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 2194 cpu->isar.id_aa64isar1 = t; 2195 2196 t = cpu->isar.id_aa64pfr0; 2197 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 2198 cpu->isar.id_aa64pfr0 = t; 2199 2200 u = cpu->isar.id_isar5; 2201 u = FIELD_DP32(u, ID_ISAR5, AES, 0); 2202 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); 2203 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); 2204 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 2205 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 2206 cpu->isar.id_isar5 = u; 2207 2208 u = cpu->isar.id_isar6; 2209 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 2210 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 2211 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 2212 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 2213 cpu->isar.id_isar6 = u; 2214 2215 if (!arm_feature(env, ARM_FEATURE_M)) { 2216 u = cpu->isar.mvfr1; 2217 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 2218 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 2219 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 2220 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 2221 cpu->isar.mvfr1 = u; 2222 2223 u = cpu->isar.mvfr2; 2224 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 2225 cpu->isar.mvfr2 = u; 2226 } 2227 } 2228 2229 if (!cpu->has_neon && !cpu->has_vfp) { 2230 uint64_t t; 2231 uint32_t u; 2232 2233 t = cpu->isar.id_aa64isar0; 2234 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 2235 cpu->isar.id_aa64isar0 = t; 2236 2237 t = cpu->isar.id_aa64isar1; 2238 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 2239 cpu->isar.id_aa64isar1 = t; 2240 2241 u = cpu->isar.mvfr0; 2242 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 2243 cpu->isar.mvfr0 = u; 2244 2245 /* Despite the name, this field covers both VFP and Neon */ 2246 u = cpu->isar.mvfr1; 2247 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 2248 cpu->isar.mvfr1 = u; 2249 } 2250 2251 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 2252 uint32_t u; 2253 2254 unset_feature(env, ARM_FEATURE_THUMB_DSP); 2255 2256 u = cpu->isar.id_isar1; 2257 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 2258 cpu->isar.id_isar1 = u; 2259 2260 u = cpu->isar.id_isar2; 2261 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 2262 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 2263 cpu->isar.id_isar2 = u; 2264 2265 u = cpu->isar.id_isar3; 2266 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 2267 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 2268 cpu->isar.id_isar3 = u; 2269 } 2270 2271 2272 /* 2273 * We rely on no XScale CPU having VFP so we can use the same bits in the 2274 * TB flags field for VECSTRIDE and XSCALE_CPAR. 2275 */ 2276 assert(arm_feature(env, ARM_FEATURE_AARCH64) || 2277 !cpu_isar_feature(aa32_vfp_simd, cpu) || 2278 !arm_feature(env, ARM_FEATURE_XSCALE)); 2279 2280 #ifndef CONFIG_USER_ONLY 2281 { 2282 int pagebits; 2283 if (arm_feature(env, ARM_FEATURE_V7) && 2284 !arm_feature(env, ARM_FEATURE_M) && 2285 !arm_feature(env, ARM_FEATURE_PMSA)) { 2286 /* 2287 * v7VMSA drops support for the old ARMv5 tiny pages, 2288 * so we can use 4K pages. 2289 */ 2290 pagebits = 12; 2291 } else { 2292 /* 2293 * For CPUs which might have tiny 1K pages, or which have an 2294 * MPU and might have small region sizes, stick with 1K pages. 2295 */ 2296 pagebits = 10; 2297 } 2298 if (!set_preferred_target_page_bits(pagebits)) { 2299 /* 2300 * This can only ever happen for hotplugging a CPU, or if 2301 * the board code incorrectly creates a CPU which it has 2302 * promised via minimum_page_size that it will not. 2303 */ 2304 error_setg(errp, "This CPU requires a smaller page size " 2305 "than the system is using"); 2306 return; 2307 } 2308 } 2309 #endif 2310 2311 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 2312 * We don't support setting cluster ID ([16..23]) (known as Aff2 2313 * in later ARM ARM versions), or any of the higher affinity level fields, 2314 * so these bits always RAZ. 2315 */ 2316 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 2317 cpu->mp_affinity = arm_build_mp_affinity(cs->cpu_index, 2318 ARM_DEFAULT_CPUS_PER_CLUSTER); 2319 } 2320 2321 if (cpu->reset_hivecs) { 2322 cpu->reset_sctlr |= (1 << 13); 2323 } 2324 2325 if (cpu->cfgend) { 2326 if (arm_feature(env, ARM_FEATURE_V7)) { 2327 cpu->reset_sctlr |= SCTLR_EE; 2328 } else { 2329 cpu->reset_sctlr |= SCTLR_B; 2330 } 2331 } 2332 2333 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 2334 /* If the has_el3 CPU property is disabled then we need to disable the 2335 * feature. 2336 */ 2337 unset_feature(env, ARM_FEATURE_EL3); 2338 2339 /* 2340 * Disable the security extension feature bits in the processor 2341 * feature registers as well. 2342 */ 2343 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); 2344 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); 2345 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2346 ID_AA64PFR0, EL3, 0); 2347 2348 /* Disable the realm management extension, which requires EL3. */ 2349 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2350 ID_AA64PFR0, RME, 0); 2351 } 2352 2353 if (!cpu->has_el2) { 2354 unset_feature(env, ARM_FEATURE_EL2); 2355 } 2356 2357 if (!cpu->has_pmu) { 2358 unset_feature(env, ARM_FEATURE_PMU); 2359 } 2360 if (arm_feature(env, ARM_FEATURE_PMU)) { 2361 pmu_init(cpu); 2362 2363 if (!kvm_enabled()) { 2364 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 2365 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 2366 } 2367 2368 #ifndef CONFIG_USER_ONLY 2369 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 2370 cpu); 2371 #endif 2372 } else { 2373 cpu->isar.id_aa64dfr0 = 2374 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 2375 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 2376 cpu->pmceid0 = 0; 2377 cpu->pmceid1 = 0; 2378 } 2379 2380 if (!arm_feature(env, ARM_FEATURE_EL2)) { 2381 /* 2382 * Disable the hypervisor feature bits in the processor feature 2383 * registers if we don't have EL2. 2384 */ 2385 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2386 ID_AA64PFR0, EL2, 0); 2387 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, 2388 ID_PFR1, VIRTUALIZATION, 0); 2389 } 2390 2391 if (cpu_isar_feature(aa64_mte, cpu)) { 2392 /* 2393 * The architectural range of GM blocksize is 2-6, however qemu 2394 * doesn't support blocksize of 2 (see HELPER(ldgm)). 2395 */ 2396 if (tcg_enabled()) { 2397 assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6); 2398 } 2399 2400 #ifndef CONFIG_USER_ONLY 2401 /* 2402 * If we run with TCG and do not have tag-memory provided by 2403 * the machine, then reduce MTE support to instructions enabled at EL0. 2404 * This matches Cortex-A710 BROADCASTMTE input being LOW. 2405 */ 2406 if (tcg_enabled() && cpu->tag_memory == NULL) { 2407 cpu->isar.id_aa64pfr1 = 2408 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); 2409 } 2410 2411 /* 2412 * If MTE is supported by the host, however it should not be 2413 * enabled on the guest (i.e mte=off), clear guest's MTE bits." 2414 */ 2415 if (kvm_enabled() && !cpu->kvm_mte) { 2416 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 2417 } 2418 #endif 2419 } 2420 2421 #ifndef CONFIG_USER_ONLY 2422 if (tcg_enabled() && cpu_isar_feature(aa64_wfxt, cpu)) { 2423 cpu->wfxt_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 2424 arm_wfxt_timer_cb, cpu); 2425 } 2426 #endif 2427 2428 if (tcg_enabled()) { 2429 /* 2430 * Don't report some architectural features in the ID registers 2431 * where TCG does not yet implement it (not even a minimal 2432 * stub version). This avoids guests falling over when they 2433 * try to access the non-existent system registers for them. 2434 */ 2435 /* FEAT_SPE (Statistical Profiling Extension) */ 2436 cpu->isar.id_aa64dfr0 = 2437 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); 2438 /* FEAT_TRBE (Trace Buffer Extension) */ 2439 cpu->isar.id_aa64dfr0 = 2440 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0); 2441 /* FEAT_TRF (Self-hosted Trace Extension) */ 2442 cpu->isar.id_aa64dfr0 = 2443 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0); 2444 cpu->isar.id_dfr0 = 2445 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0); 2446 /* Trace Macrocell system register access */ 2447 cpu->isar.id_aa64dfr0 = 2448 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0); 2449 cpu->isar.id_dfr0 = 2450 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0); 2451 /* Memory mapped trace */ 2452 cpu->isar.id_dfr0 = 2453 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0); 2454 /* FEAT_AMU (Activity Monitors Extension) */ 2455 cpu->isar.id_aa64pfr0 = 2456 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, AMU, 0); 2457 cpu->isar.id_pfr0 = 2458 FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0); 2459 /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ 2460 cpu->isar.id_aa64pfr0 = 2461 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0); 2462 } 2463 2464 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 2465 * to false or by setting pmsav7-dregion to 0. 2466 */ 2467 if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) { 2468 cpu->has_mpu = false; 2469 cpu->pmsav7_dregion = 0; 2470 cpu->pmsav8r_hdregion = 0; 2471 } 2472 2473 if (arm_feature(env, ARM_FEATURE_PMSA) && 2474 arm_feature(env, ARM_FEATURE_V7)) { 2475 uint32_t nr = cpu->pmsav7_dregion; 2476 2477 if (nr > 0xff) { 2478 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 2479 return; 2480 } 2481 2482 if (nr) { 2483 if (arm_feature(env, ARM_FEATURE_V8)) { 2484 /* PMSAv8 */ 2485 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 2486 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 2487 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2488 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 2489 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 2490 } 2491 } else { 2492 env->pmsav7.drbar = g_new0(uint32_t, nr); 2493 env->pmsav7.drsr = g_new0(uint32_t, nr); 2494 env->pmsav7.dracr = g_new0(uint32_t, nr); 2495 } 2496 } 2497 2498 if (cpu->pmsav8r_hdregion > 0xff) { 2499 error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32, 2500 cpu->pmsav8r_hdregion); 2501 return; 2502 } 2503 2504 if (cpu->pmsav8r_hdregion) { 2505 env->pmsav8.hprbar = g_new0(uint32_t, 2506 cpu->pmsav8r_hdregion); 2507 env->pmsav8.hprlar = g_new0(uint32_t, 2508 cpu->pmsav8r_hdregion); 2509 } 2510 } 2511 2512 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2513 uint32_t nr = cpu->sau_sregion; 2514 2515 if (nr > 0xff) { 2516 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 2517 return; 2518 } 2519 2520 if (nr) { 2521 env->sau.rbar = g_new0(uint32_t, nr); 2522 env->sau.rlar = g_new0(uint32_t, nr); 2523 } 2524 } 2525 2526 if (arm_feature(env, ARM_FEATURE_EL3)) { 2527 set_feature(env, ARM_FEATURE_VBAR); 2528 } 2529 2530 #ifndef CONFIG_USER_ONLY 2531 if (tcg_enabled() && cpu_isar_feature(aa64_rme, cpu)) { 2532 arm_register_el_change_hook(cpu, >_rme_post_el_change, 0); 2533 } 2534 #endif 2535 2536 register_cp_regs_for_features(cpu); 2537 arm_cpu_register_gdb_regs_for_features(cpu); 2538 arm_cpu_register_gdb_commands(cpu); 2539 2540 init_cpreg_list(cpu); 2541 2542 #ifndef CONFIG_USER_ONLY 2543 MachineState *ms = MACHINE(qdev_get_machine()); 2544 unsigned int smp_cpus = ms->smp.cpus; 2545 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 2546 2547 /* 2548 * We must set cs->num_ases to the final value before 2549 * the first call to cpu_address_space_init. 2550 */ 2551 if (cpu->tag_memory != NULL) { 2552 cs->num_ases = 3 + has_secure; 2553 } else { 2554 cs->num_ases = 1 + has_secure; 2555 } 2556 2557 if (has_secure) { 2558 if (!cpu->secure_memory) { 2559 cpu->secure_memory = cs->memory; 2560 } 2561 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 2562 cpu->secure_memory); 2563 } 2564 2565 if (cpu->tag_memory != NULL) { 2566 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 2567 cpu->tag_memory); 2568 if (has_secure) { 2569 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 2570 cpu->secure_tag_memory); 2571 } 2572 } 2573 2574 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 2575 2576 /* No core_count specified, default to smp_cpus. */ 2577 if (cpu->core_count == -1) { 2578 cpu->core_count = smp_cpus; 2579 } 2580 #endif 2581 2582 if (tcg_enabled()) { 2583 int dcz_blocklen = 4 << cpu->dcz_blocksize; 2584 2585 /* 2586 * We only support DCZ blocklen that fits on one page. 2587 * 2588 * Architectually this is always true. However TARGET_PAGE_SIZE 2589 * is variable and, for compatibility with -machine virt-2.7, 2590 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 2591 * But even then, while the largest architectural DCZ blocklen 2592 * is 2KiB, no cpu actually uses such a large blocklen. 2593 */ 2594 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 2595 2596 /* 2597 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 2598 * both nibbles of each byte storing tag data may be written at once. 2599 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 2600 */ 2601 if (cpu_isar_feature(aa64_mte, cpu)) { 2602 assert(dcz_blocklen >= 2 * TAG_GRANULE); 2603 } 2604 } 2605 2606 qemu_init_vcpu(cs); 2607 cpu_reset(cs); 2608 2609 acc->parent_realize(dev, errp); 2610 } 2611 2612 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 2613 { 2614 ObjectClass *oc; 2615 char *typename; 2616 char **cpuname; 2617 const char *cpunamestr; 2618 2619 cpuname = g_strsplit(cpu_model, ",", 1); 2620 cpunamestr = cpuname[0]; 2621 #ifdef CONFIG_USER_ONLY 2622 /* For backwards compatibility usermode emulation allows "-cpu any", 2623 * which has the same semantics as "-cpu max". 2624 */ 2625 if (!strcmp(cpunamestr, "any")) { 2626 cpunamestr = "max"; 2627 } 2628 #endif 2629 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 2630 oc = object_class_by_name(typename); 2631 g_strfreev(cpuname); 2632 g_free(typename); 2633 2634 return oc; 2635 } 2636 2637 static Property arm_cpu_properties[] = { 2638 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2639 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2640 mp_affinity, ARM64_AFFINITY_INVALID), 2641 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2642 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2643 /* True to default to the backward-compat old CNTFRQ rather than 1Ghz */ 2644 DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false), 2645 DEFINE_PROP_END_OF_LIST() 2646 }; 2647 2648 static const gchar *arm_gdb_arch_name(CPUState *cs) 2649 { 2650 ARMCPU *cpu = ARM_CPU(cs); 2651 CPUARMState *env = &cpu->env; 2652 2653 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2654 return "iwmmxt"; 2655 } 2656 return "arm"; 2657 } 2658 2659 #ifndef CONFIG_USER_ONLY 2660 #include "hw/core/sysemu-cpu-ops.h" 2661 2662 static const struct SysemuCPUOps arm_sysemu_ops = { 2663 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2664 .asidx_from_attrs = arm_asidx_from_attrs, 2665 .write_elf32_note = arm_cpu_write_elf32_note, 2666 .write_elf64_note = arm_cpu_write_elf64_note, 2667 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2668 .legacy_vmsd = &vmstate_arm_cpu, 2669 }; 2670 #endif 2671 2672 #ifdef CONFIG_TCG 2673 static const TCGCPUOps arm_tcg_ops = { 2674 .initialize = arm_translate_init, 2675 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2676 .debug_excp_handler = arm_debug_excp_handler, 2677 .restore_state_to_opc = arm_restore_state_to_opc, 2678 2679 #ifdef CONFIG_USER_ONLY 2680 .record_sigsegv = arm_cpu_record_sigsegv, 2681 .record_sigbus = arm_cpu_record_sigbus, 2682 #else 2683 .tlb_fill_align = arm_cpu_tlb_fill_align, 2684 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2685 .cpu_exec_halt = arm_cpu_exec_halt, 2686 .do_interrupt = arm_cpu_do_interrupt, 2687 .do_transaction_failed = arm_cpu_do_transaction_failed, 2688 .do_unaligned_access = arm_cpu_do_unaligned_access, 2689 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2690 .debug_check_watchpoint = arm_debug_check_watchpoint, 2691 .debug_check_breakpoint = arm_debug_check_breakpoint, 2692 #endif /* !CONFIG_USER_ONLY */ 2693 }; 2694 #endif /* CONFIG_TCG */ 2695 2696 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2697 { 2698 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2699 CPUClass *cc = CPU_CLASS(acc); 2700 DeviceClass *dc = DEVICE_CLASS(oc); 2701 ResettableClass *rc = RESETTABLE_CLASS(oc); 2702 2703 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2704 &acc->parent_realize); 2705 2706 device_class_set_props(dc, arm_cpu_properties); 2707 2708 resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL, 2709 &acc->parent_phases); 2710 2711 cc->class_by_name = arm_cpu_class_by_name; 2712 cc->has_work = arm_cpu_has_work; 2713 cc->mmu_index = arm_cpu_mmu_index; 2714 cc->dump_state = arm_cpu_dump_state; 2715 cc->set_pc = arm_cpu_set_pc; 2716 cc->get_pc = arm_cpu_get_pc; 2717 cc->gdb_read_register = arm_cpu_gdb_read_register; 2718 cc->gdb_write_register = arm_cpu_gdb_write_register; 2719 #ifndef CONFIG_USER_ONLY 2720 cc->sysemu_ops = &arm_sysemu_ops; 2721 #endif 2722 cc->gdb_arch_name = arm_gdb_arch_name; 2723 cc->gdb_stop_before_watchpoint = true; 2724 cc->disas_set_info = arm_disas_set_info; 2725 2726 #ifdef CONFIG_TCG 2727 cc->tcg_ops = &arm_tcg_ops; 2728 #endif /* CONFIG_TCG */ 2729 } 2730 2731 static void arm_cpu_instance_init(Object *obj) 2732 { 2733 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2734 2735 acc->info->initfn(obj); 2736 arm_cpu_post_init(obj); 2737 } 2738 2739 static void cpu_register_class_init(ObjectClass *oc, void *data) 2740 { 2741 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2742 CPUClass *cc = CPU_CLASS(acc); 2743 2744 acc->info = data; 2745 cc->gdb_core_xml_file = "arm-core.xml"; 2746 } 2747 2748 void arm_cpu_register(const ARMCPUInfo *info) 2749 { 2750 TypeInfo type_info = { 2751 .parent = TYPE_ARM_CPU, 2752 .instance_init = arm_cpu_instance_init, 2753 .class_init = info->class_init ?: cpu_register_class_init, 2754 .class_data = (void *)info, 2755 }; 2756 2757 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2758 type_register(&type_info); 2759 g_free((void *)type_info.name); 2760 } 2761 2762 static const TypeInfo arm_cpu_type_info = { 2763 .name = TYPE_ARM_CPU, 2764 .parent = TYPE_CPU, 2765 .instance_size = sizeof(ARMCPU), 2766 .instance_align = __alignof__(ARMCPU), 2767 .instance_init = arm_cpu_initfn, 2768 .instance_finalize = arm_cpu_finalizefn, 2769 .abstract = true, 2770 .class_size = sizeof(ARMCPUClass), 2771 .class_init = arm_cpu_class_init, 2772 }; 2773 2774 static void arm_cpu_register_types(void) 2775 { 2776 type_register_static(&arm_cpu_type_info); 2777 } 2778 2779 type_init(arm_cpu_register_types) 2780