xref: /openbmc/qemu/target/arm/cpu.c (revision 6538692e)
1 /*
2  * QEMU ARM CPU
3  *
4  * Copyright (c) 2012 SUSE LINUX Products GmbH
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * as published by the Free Software Foundation; either version 2
9  * of the License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, see
18  * <http://www.gnu.org/licenses/gpl-2.0.html>
19  */
20 
21 #include "qemu/osdep.h"
22 #include "qemu/qemu-print.h"
23 #include "qemu/timer.h"
24 #include "qemu-common.h"
25 #include "target/arm/idau.h"
26 #include "qemu/module.h"
27 #include "qapi/error.h"
28 #include "qapi/visitor.h"
29 #include "cpu.h"
30 #ifdef CONFIG_TCG
31 #include "hw/core/tcg-cpu-ops.h"
32 #endif /* CONFIG_TCG */
33 #include "internals.h"
34 #include "exec/exec-all.h"
35 #include "hw/qdev-properties.h"
36 #if !defined(CONFIG_USER_ONLY)
37 #include "hw/loader.h"
38 #include "hw/boards.h"
39 #endif
40 #include "sysemu/tcg.h"
41 #include "sysemu/hw_accel.h"
42 #include "kvm_arm.h"
43 #include "disas/capstone.h"
44 #include "fpu/softfloat.h"
45 
46 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
47 {
48     ARMCPU *cpu = ARM_CPU(cs);
49     CPUARMState *env = &cpu->env;
50 
51     if (is_a64(env)) {
52         env->pc = value;
53         env->thumb = 0;
54     } else {
55         env->regs[15] = value & ~1;
56         env->thumb = value & 1;
57     }
58 }
59 
60 #ifdef CONFIG_TCG
61 void arm_cpu_synchronize_from_tb(CPUState *cs,
62                                  const TranslationBlock *tb)
63 {
64     ARMCPU *cpu = ARM_CPU(cs);
65     CPUARMState *env = &cpu->env;
66 
67     /*
68      * It's OK to look at env for the current mode here, because it's
69      * never possible for an AArch64 TB to chain to an AArch32 TB.
70      */
71     if (is_a64(env)) {
72         env->pc = tb->pc;
73     } else {
74         env->regs[15] = tb->pc;
75     }
76 }
77 #endif /* CONFIG_TCG */
78 
79 static bool arm_cpu_has_work(CPUState *cs)
80 {
81     ARMCPU *cpu = ARM_CPU(cs);
82 
83     return (cpu->power_state != PSCI_OFF)
84         && cs->interrupt_request &
85         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
86          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
87          | CPU_INTERRUPT_EXITTB);
88 }
89 
90 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
91                                  void *opaque)
92 {
93     ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
94 
95     entry->hook = hook;
96     entry->opaque = opaque;
97 
98     QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node);
99 }
100 
101 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
102                                  void *opaque)
103 {
104     ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
105 
106     entry->hook = hook;
107     entry->opaque = opaque;
108 
109     QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node);
110 }
111 
112 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
113 {
114     /* Reset a single ARMCPRegInfo register */
115     ARMCPRegInfo *ri = value;
116     ARMCPU *cpu = opaque;
117 
118     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
119         return;
120     }
121 
122     if (ri->resetfn) {
123         ri->resetfn(&cpu->env, ri);
124         return;
125     }
126 
127     /* A zero offset is never possible as it would be regs[0]
128      * so we use it to indicate that reset is being handled elsewhere.
129      * This is basically only used for fields in non-core coprocessors
130      * (like the pxa2xx ones).
131      */
132     if (!ri->fieldoffset) {
133         return;
134     }
135 
136     if (cpreg_field_is_64bit(ri)) {
137         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
138     } else {
139         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
140     }
141 }
142 
143 static void cp_reg_check_reset(gpointer key, gpointer value,  gpointer opaque)
144 {
145     /* Purely an assertion check: we've already done reset once,
146      * so now check that running the reset for the cpreg doesn't
147      * change its value. This traps bugs where two different cpregs
148      * both try to reset the same state field but to different values.
149      */
150     ARMCPRegInfo *ri = value;
151     ARMCPU *cpu = opaque;
152     uint64_t oldvalue, newvalue;
153 
154     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
155         return;
156     }
157 
158     oldvalue = read_raw_cp_reg(&cpu->env, ri);
159     cp_reg_reset(key, value, opaque);
160     newvalue = read_raw_cp_reg(&cpu->env, ri);
161     assert(oldvalue == newvalue);
162 }
163 
164 static void arm_cpu_reset(DeviceState *dev)
165 {
166     CPUState *s = CPU(dev);
167     ARMCPU *cpu = ARM_CPU(s);
168     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
169     CPUARMState *env = &cpu->env;
170 
171     acc->parent_reset(dev);
172 
173     memset(env, 0, offsetof(CPUARMState, end_reset_fields));
174 
175     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
176     g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
177 
178     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
179     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0;
180     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1;
181     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2;
182 
183     cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON;
184 
185     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
186         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
187     }
188 
189     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
190         /* 64 bit CPUs always start in 64 bit mode */
191         env->aarch64 = 1;
192 #if defined(CONFIG_USER_ONLY)
193         env->pstate = PSTATE_MODE_EL0t;
194         /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
195         env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
196         /* Enable all PAC keys.  */
197         env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
198                                   SCTLR_EnDA | SCTLR_EnDB);
199         /* and to the FP/Neon instructions */
200         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
201         /* and to the SVE instructions */
202         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
203         /* with reasonable vector length */
204         if (cpu_isar_feature(aa64_sve, cpu)) {
205             env->vfp.zcr_el[1] =
206                 aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1);
207         }
208         /*
209          * Enable 48-bit address space (TODO: take reserved_va into account).
210          * Enable TBI0 but not TBI1.
211          * Note that this must match useronly_clean_ptr.
212          */
213         env->cp15.tcr_el[1].raw_tcr = 5 | (1ULL << 37);
214 
215         /* Enable MTE */
216         if (cpu_isar_feature(aa64_mte, cpu)) {
217             /* Enable tag access, but leave TCF0 as No Effect (0). */
218             env->cp15.sctlr_el[1] |= SCTLR_ATA0;
219             /*
220              * Exclude all tags, so that tag 0 is always used.
221              * This corresponds to Linux current->thread.gcr_incl = 0.
222              *
223              * Set RRND, so that helper_irg() will generate a seed later.
224              * Here in cpu_reset(), the crypto subsystem has not yet been
225              * initialized.
226              */
227             env->cp15.gcr_el1 = 0x1ffff;
228         }
229 #else
230         /* Reset into the highest available EL */
231         if (arm_feature(env, ARM_FEATURE_EL3)) {
232             env->pstate = PSTATE_MODE_EL3h;
233         } else if (arm_feature(env, ARM_FEATURE_EL2)) {
234             env->pstate = PSTATE_MODE_EL2h;
235         } else {
236             env->pstate = PSTATE_MODE_EL1h;
237         }
238         env->pc = cpu->rvbar;
239 #endif
240     } else {
241 #if defined(CONFIG_USER_ONLY)
242         /* Userspace expects access to cp10 and cp11 for FP/Neon */
243         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
244 #endif
245     }
246 
247 #if defined(CONFIG_USER_ONLY)
248     env->uncached_cpsr = ARM_CPU_MODE_USR;
249     /* For user mode we must enable access to coprocessors */
250     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
251     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
252         env->cp15.c15_cpar = 3;
253     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
254         env->cp15.c15_cpar = 1;
255     }
256 #else
257 
258     /*
259      * If the highest available EL is EL2, AArch32 will start in Hyp
260      * mode; otherwise it starts in SVC. Note that if we start in
261      * AArch64 then these values in the uncached_cpsr will be ignored.
262      */
263     if (arm_feature(env, ARM_FEATURE_EL2) &&
264         !arm_feature(env, ARM_FEATURE_EL3)) {
265         env->uncached_cpsr = ARM_CPU_MODE_HYP;
266     } else {
267         env->uncached_cpsr = ARM_CPU_MODE_SVC;
268     }
269     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
270 
271     /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
272      * executing as AArch32 then check if highvecs are enabled and
273      * adjust the PC accordingly.
274      */
275     if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
276         env->regs[15] = 0xFFFF0000;
277     }
278 
279     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
280 #endif
281 
282     if (arm_feature(env, ARM_FEATURE_M)) {
283 #ifndef CONFIG_USER_ONLY
284         uint32_t initial_msp; /* Loaded from 0x0 */
285         uint32_t initial_pc; /* Loaded from 0x4 */
286         uint8_t *rom;
287         uint32_t vecbase;
288 #endif
289 
290         if (cpu_isar_feature(aa32_lob, cpu)) {
291             /*
292              * LTPSIZE is constant 4 if MVE not implemented, and resets
293              * to an UNKNOWN value if MVE is implemented. We choose to
294              * always reset to 4.
295              */
296             env->v7m.ltpsize = 4;
297             /* The LTPSIZE field in FPDSCR is constant and reads as 4. */
298             env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT;
299             env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT;
300         }
301 
302         if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
303             env->v7m.secure = true;
304         } else {
305             /* This bit resets to 0 if security is supported, but 1 if
306              * it is not. The bit is not present in v7M, but we set it
307              * here so we can avoid having to make checks on it conditional
308              * on ARM_FEATURE_V8 (we don't let the guest see the bit).
309              */
310             env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
311             /*
312              * Set NSACR to indicate "NS access permitted to everything";
313              * this avoids having to have all the tests of it being
314              * conditional on ARM_FEATURE_M_SECURITY. Note also that from
315              * v8.1M the guest-visible value of NSACR in a CPU without the
316              * Security Extension is 0xcff.
317              */
318             env->v7m.nsacr = 0xcff;
319         }
320 
321         /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
322          * that it resets to 1, so QEMU always does that rather than making
323          * it dependent on CPU model. In v8M it is RES1.
324          */
325         env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK;
326         env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK;
327         if (arm_feature(env, ARM_FEATURE_V8)) {
328             /* in v8M the NONBASETHRDENA bit [0] is RES1 */
329             env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK;
330             env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK;
331         }
332         if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
333             env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK;
334             env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
335         }
336 
337         if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
338             env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK;
339             env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK |
340                 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK;
341         }
342 
343 #ifndef CONFIG_USER_ONLY
344         /* Unlike A/R profile, M profile defines the reset LR value */
345         env->regs[14] = 0xffffffff;
346 
347         env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80;
348         env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80;
349 
350         /* Load the initial SP and PC from offset 0 and 4 in the vector table */
351         vecbase = env->v7m.vecbase[env->v7m.secure];
352         rom = rom_ptr_for_as(s->as, vecbase, 8);
353         if (rom) {
354             /* Address zero is covered by ROM which hasn't yet been
355              * copied into physical memory.
356              */
357             initial_msp = ldl_p(rom);
358             initial_pc = ldl_p(rom + 4);
359         } else {
360             /* Address zero not covered by a ROM blob, or the ROM blob
361              * is in non-modifiable memory and this is a second reset after
362              * it got copied into memory. In the latter case, rom_ptr
363              * will return a NULL pointer and we should use ldl_phys instead.
364              */
365             initial_msp = ldl_phys(s->as, vecbase);
366             initial_pc = ldl_phys(s->as, vecbase + 4);
367         }
368 
369         env->regs[13] = initial_msp & 0xFFFFFFFC;
370         env->regs[15] = initial_pc & ~1;
371         env->thumb = initial_pc & 1;
372 #else
373         /*
374          * For user mode we run non-secure and with access to the FPU.
375          * The FPU context is active (ie does not need further setup)
376          * and is owned by non-secure.
377          */
378         env->v7m.secure = false;
379         env->v7m.nsacr = 0xcff;
380         env->v7m.cpacr[M_REG_NS] = 0xf0ffff;
381         env->v7m.fpccr[M_REG_S] &=
382             ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK);
383         env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK;
384 #endif
385     }
386 
387     /* M profile requires that reset clears the exclusive monitor;
388      * A profile does not, but clearing it makes more sense than having it
389      * set with an exclusive access on address zero.
390      */
391     arm_clear_exclusive(env);
392 
393     if (arm_feature(env, ARM_FEATURE_PMSA)) {
394         if (cpu->pmsav7_dregion > 0) {
395             if (arm_feature(env, ARM_FEATURE_V8)) {
396                 memset(env->pmsav8.rbar[M_REG_NS], 0,
397                        sizeof(*env->pmsav8.rbar[M_REG_NS])
398                        * cpu->pmsav7_dregion);
399                 memset(env->pmsav8.rlar[M_REG_NS], 0,
400                        sizeof(*env->pmsav8.rlar[M_REG_NS])
401                        * cpu->pmsav7_dregion);
402                 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
403                     memset(env->pmsav8.rbar[M_REG_S], 0,
404                            sizeof(*env->pmsav8.rbar[M_REG_S])
405                            * cpu->pmsav7_dregion);
406                     memset(env->pmsav8.rlar[M_REG_S], 0,
407                            sizeof(*env->pmsav8.rlar[M_REG_S])
408                            * cpu->pmsav7_dregion);
409                 }
410             } else if (arm_feature(env, ARM_FEATURE_V7)) {
411                 memset(env->pmsav7.drbar, 0,
412                        sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
413                 memset(env->pmsav7.drsr, 0,
414                        sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
415                 memset(env->pmsav7.dracr, 0,
416                        sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
417             }
418         }
419         env->pmsav7.rnr[M_REG_NS] = 0;
420         env->pmsav7.rnr[M_REG_S] = 0;
421         env->pmsav8.mair0[M_REG_NS] = 0;
422         env->pmsav8.mair0[M_REG_S] = 0;
423         env->pmsav8.mair1[M_REG_NS] = 0;
424         env->pmsav8.mair1[M_REG_S] = 0;
425     }
426 
427     if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
428         if (cpu->sau_sregion > 0) {
429             memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion);
430             memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion);
431         }
432         env->sau.rnr = 0;
433         /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
434          * the Cortex-M33 does.
435          */
436         env->sau.ctrl = 0;
437     }
438 
439     set_flush_to_zero(1, &env->vfp.standard_fp_status);
440     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
441     set_default_nan_mode(1, &env->vfp.standard_fp_status);
442     set_default_nan_mode(1, &env->vfp.standard_fp_status_f16);
443     set_float_detect_tininess(float_tininess_before_rounding,
444                               &env->vfp.fp_status);
445     set_float_detect_tininess(float_tininess_before_rounding,
446                               &env->vfp.standard_fp_status);
447     set_float_detect_tininess(float_tininess_before_rounding,
448                               &env->vfp.fp_status_f16);
449     set_float_detect_tininess(float_tininess_before_rounding,
450                               &env->vfp.standard_fp_status_f16);
451 #ifndef CONFIG_USER_ONLY
452     if (kvm_enabled()) {
453         kvm_arm_reset_vcpu(cpu);
454     }
455 #endif
456 
457     hw_breakpoint_update_all(cpu);
458     hw_watchpoint_update_all(cpu);
459     arm_rebuild_hflags(env);
460 }
461 
462 #ifndef CONFIG_USER_ONLY
463 
464 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
465                                      unsigned int target_el,
466                                      unsigned int cur_el, bool secure,
467                                      uint64_t hcr_el2)
468 {
469     CPUARMState *env = cs->env_ptr;
470     bool pstate_unmasked;
471     bool unmasked = false;
472 
473     /*
474      * Don't take exceptions if they target a lower EL.
475      * This check should catch any exceptions that would not be taken
476      * but left pending.
477      */
478     if (cur_el > target_el) {
479         return false;
480     }
481 
482     switch (excp_idx) {
483     case EXCP_FIQ:
484         pstate_unmasked = !(env->daif & PSTATE_F);
485         break;
486 
487     case EXCP_IRQ:
488         pstate_unmasked = !(env->daif & PSTATE_I);
489         break;
490 
491     case EXCP_VFIQ:
492         if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
493             /* VFIQs are only taken when hypervized.  */
494             return false;
495         }
496         return !(env->daif & PSTATE_F);
497     case EXCP_VIRQ:
498         if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
499             /* VIRQs are only taken when hypervized.  */
500             return false;
501         }
502         return !(env->daif & PSTATE_I);
503     default:
504         g_assert_not_reached();
505     }
506 
507     /*
508      * Use the target EL, current execution state and SCR/HCR settings to
509      * determine whether the corresponding CPSR bit is used to mask the
510      * interrupt.
511      */
512     if ((target_el > cur_el) && (target_el != 1)) {
513         /* Exceptions targeting a higher EL may not be maskable */
514         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
515             /*
516              * 64-bit masking rules are simple: exceptions to EL3
517              * can't be masked, and exceptions to EL2 can only be
518              * masked from Secure state. The HCR and SCR settings
519              * don't affect the masking logic, only the interrupt routing.
520              */
521             if (target_el == 3 || !secure || (env->cp15.scr_el3 & SCR_EEL2)) {
522                 unmasked = true;
523             }
524         } else {
525             /*
526              * The old 32-bit-only environment has a more complicated
527              * masking setup. HCR and SCR bits not only affect interrupt
528              * routing but also change the behaviour of masking.
529              */
530             bool hcr, scr;
531 
532             switch (excp_idx) {
533             case EXCP_FIQ:
534                 /*
535                  * If FIQs are routed to EL3 or EL2 then there are cases where
536                  * we override the CPSR.F in determining if the exception is
537                  * masked or not. If neither of these are set then we fall back
538                  * to the CPSR.F setting otherwise we further assess the state
539                  * below.
540                  */
541                 hcr = hcr_el2 & HCR_FMO;
542                 scr = (env->cp15.scr_el3 & SCR_FIQ);
543 
544                 /*
545                  * When EL3 is 32-bit, the SCR.FW bit controls whether the
546                  * CPSR.F bit masks FIQ interrupts when taken in non-secure
547                  * state. If SCR.FW is set then FIQs can be masked by CPSR.F
548                  * when non-secure but only when FIQs are only routed to EL3.
549                  */
550                 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
551                 break;
552             case EXCP_IRQ:
553                 /*
554                  * When EL3 execution state is 32-bit, if HCR.IMO is set then
555                  * we may override the CPSR.I masking when in non-secure state.
556                  * The SCR.IRQ setting has already been taken into consideration
557                  * when setting the target EL, so it does not have a further
558                  * affect here.
559                  */
560                 hcr = hcr_el2 & HCR_IMO;
561                 scr = false;
562                 break;
563             default:
564                 g_assert_not_reached();
565             }
566 
567             if ((scr || hcr) && !secure) {
568                 unmasked = true;
569             }
570         }
571     }
572 
573     /*
574      * The PSTATE bits only mask the interrupt if we have not overriden the
575      * ability above.
576      */
577     return unmasked || pstate_unmasked;
578 }
579 
580 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
581 {
582     CPUClass *cc = CPU_GET_CLASS(cs);
583     CPUARMState *env = cs->env_ptr;
584     uint32_t cur_el = arm_current_el(env);
585     bool secure = arm_is_secure(env);
586     uint64_t hcr_el2 = arm_hcr_el2_eff(env);
587     uint32_t target_el;
588     uint32_t excp_idx;
589 
590     /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */
591 
592     if (interrupt_request & CPU_INTERRUPT_FIQ) {
593         excp_idx = EXCP_FIQ;
594         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
595         if (arm_excp_unmasked(cs, excp_idx, target_el,
596                               cur_el, secure, hcr_el2)) {
597             goto found;
598         }
599     }
600     if (interrupt_request & CPU_INTERRUPT_HARD) {
601         excp_idx = EXCP_IRQ;
602         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
603         if (arm_excp_unmasked(cs, excp_idx, target_el,
604                               cur_el, secure, hcr_el2)) {
605             goto found;
606         }
607     }
608     if (interrupt_request & CPU_INTERRUPT_VIRQ) {
609         excp_idx = EXCP_VIRQ;
610         target_el = 1;
611         if (arm_excp_unmasked(cs, excp_idx, target_el,
612                               cur_el, secure, hcr_el2)) {
613             goto found;
614         }
615     }
616     if (interrupt_request & CPU_INTERRUPT_VFIQ) {
617         excp_idx = EXCP_VFIQ;
618         target_el = 1;
619         if (arm_excp_unmasked(cs, excp_idx, target_el,
620                               cur_el, secure, hcr_el2)) {
621             goto found;
622         }
623     }
624     return false;
625 
626  found:
627     cs->exception_index = excp_idx;
628     env->exception.target_el = target_el;
629     cc->tcg_ops->do_interrupt(cs);
630     return true;
631 }
632 #endif /* !CONFIG_USER_ONLY */
633 
634 void arm_cpu_update_virq(ARMCPU *cpu)
635 {
636     /*
637      * Update the interrupt level for VIRQ, which is the logical OR of
638      * the HCR_EL2.VI bit and the input line level from the GIC.
639      */
640     CPUARMState *env = &cpu->env;
641     CPUState *cs = CPU(cpu);
642 
643     bool new_state = (env->cp15.hcr_el2 & HCR_VI) ||
644         (env->irq_line_state & CPU_INTERRUPT_VIRQ);
645 
646     if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) {
647         if (new_state) {
648             cpu_interrupt(cs, CPU_INTERRUPT_VIRQ);
649         } else {
650             cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ);
651         }
652     }
653 }
654 
655 void arm_cpu_update_vfiq(ARMCPU *cpu)
656 {
657     /*
658      * Update the interrupt level for VFIQ, which is the logical OR of
659      * the HCR_EL2.VF bit and the input line level from the GIC.
660      */
661     CPUARMState *env = &cpu->env;
662     CPUState *cs = CPU(cpu);
663 
664     bool new_state = (env->cp15.hcr_el2 & HCR_VF) ||
665         (env->irq_line_state & CPU_INTERRUPT_VFIQ);
666 
667     if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) {
668         if (new_state) {
669             cpu_interrupt(cs, CPU_INTERRUPT_VFIQ);
670         } else {
671             cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ);
672         }
673     }
674 }
675 
676 #ifndef CONFIG_USER_ONLY
677 static void arm_cpu_set_irq(void *opaque, int irq, int level)
678 {
679     ARMCPU *cpu = opaque;
680     CPUARMState *env = &cpu->env;
681     CPUState *cs = CPU(cpu);
682     static const int mask[] = {
683         [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
684         [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
685         [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
686         [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
687     };
688 
689     if (level) {
690         env->irq_line_state |= mask[irq];
691     } else {
692         env->irq_line_state &= ~mask[irq];
693     }
694 
695     switch (irq) {
696     case ARM_CPU_VIRQ:
697         assert(arm_feature(env, ARM_FEATURE_EL2));
698         arm_cpu_update_virq(cpu);
699         break;
700     case ARM_CPU_VFIQ:
701         assert(arm_feature(env, ARM_FEATURE_EL2));
702         arm_cpu_update_vfiq(cpu);
703         break;
704     case ARM_CPU_IRQ:
705     case ARM_CPU_FIQ:
706         if (level) {
707             cpu_interrupt(cs, mask[irq]);
708         } else {
709             cpu_reset_interrupt(cs, mask[irq]);
710         }
711         break;
712     default:
713         g_assert_not_reached();
714     }
715 }
716 
717 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
718 {
719 #ifdef CONFIG_KVM
720     ARMCPU *cpu = opaque;
721     CPUARMState *env = &cpu->env;
722     CPUState *cs = CPU(cpu);
723     uint32_t linestate_bit;
724     int irq_id;
725 
726     switch (irq) {
727     case ARM_CPU_IRQ:
728         irq_id = KVM_ARM_IRQ_CPU_IRQ;
729         linestate_bit = CPU_INTERRUPT_HARD;
730         break;
731     case ARM_CPU_FIQ:
732         irq_id = KVM_ARM_IRQ_CPU_FIQ;
733         linestate_bit = CPU_INTERRUPT_FIQ;
734         break;
735     default:
736         g_assert_not_reached();
737     }
738 
739     if (level) {
740         env->irq_line_state |= linestate_bit;
741     } else {
742         env->irq_line_state &= ~linestate_bit;
743     }
744     kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level);
745 #endif
746 }
747 
748 static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
749 {
750     ARMCPU *cpu = ARM_CPU(cs);
751     CPUARMState *env = &cpu->env;
752 
753     cpu_synchronize_state(cs);
754     return arm_cpu_data_is_big_endian(env);
755 }
756 
757 #endif
758 
759 static int
760 print_insn_thumb1(bfd_vma pc, disassemble_info *info)
761 {
762   return print_insn_arm(pc | 1, info);
763 }
764 
765 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
766 {
767     ARMCPU *ac = ARM_CPU(cpu);
768     CPUARMState *env = &ac->env;
769     bool sctlr_b;
770 
771     if (is_a64(env)) {
772         /* We might not be compiled with the A64 disassembler
773          * because it needs a C++ compiler. Leave print_insn
774          * unset in this case to use the caller default behaviour.
775          */
776 #if defined(CONFIG_ARM_A64_DIS)
777         info->print_insn = print_insn_arm_a64;
778 #endif
779         info->cap_arch = CS_ARCH_ARM64;
780         info->cap_insn_unit = 4;
781         info->cap_insn_split = 4;
782     } else {
783         int cap_mode;
784         if (env->thumb) {
785             info->print_insn = print_insn_thumb1;
786             info->cap_insn_unit = 2;
787             info->cap_insn_split = 4;
788             cap_mode = CS_MODE_THUMB;
789         } else {
790             info->print_insn = print_insn_arm;
791             info->cap_insn_unit = 4;
792             info->cap_insn_split = 4;
793             cap_mode = CS_MODE_ARM;
794         }
795         if (arm_feature(env, ARM_FEATURE_V8)) {
796             cap_mode |= CS_MODE_V8;
797         }
798         if (arm_feature(env, ARM_FEATURE_M)) {
799             cap_mode |= CS_MODE_MCLASS;
800         }
801         info->cap_arch = CS_ARCH_ARM;
802         info->cap_mode = cap_mode;
803     }
804 
805     sctlr_b = arm_sctlr_b(env);
806     if (bswap_code(sctlr_b)) {
807 #ifdef TARGET_WORDS_BIGENDIAN
808         info->endian = BFD_ENDIAN_LITTLE;
809 #else
810         info->endian = BFD_ENDIAN_BIG;
811 #endif
812     }
813     info->flags &= ~INSN_ARM_BE32;
814 #ifndef CONFIG_USER_ONLY
815     if (sctlr_b) {
816         info->flags |= INSN_ARM_BE32;
817     }
818 #endif
819 }
820 
821 #ifdef TARGET_AARCH64
822 
823 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
824 {
825     ARMCPU *cpu = ARM_CPU(cs);
826     CPUARMState *env = &cpu->env;
827     uint32_t psr = pstate_read(env);
828     int i;
829     int el = arm_current_el(env);
830     const char *ns_status;
831 
832     qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
833     for (i = 0; i < 32; i++) {
834         if (i == 31) {
835             qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
836         } else {
837             qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
838                          (i + 2) % 3 ? " " : "\n");
839         }
840     }
841 
842     if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
843         ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
844     } else {
845         ns_status = "";
846     }
847     qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c",
848                  psr,
849                  psr & PSTATE_N ? 'N' : '-',
850                  psr & PSTATE_Z ? 'Z' : '-',
851                  psr & PSTATE_C ? 'C' : '-',
852                  psr & PSTATE_V ? 'V' : '-',
853                  ns_status,
854                  el,
855                  psr & PSTATE_SP ? 'h' : 't');
856 
857     if (cpu_isar_feature(aa64_bti, cpu)) {
858         qemu_fprintf(f, "  BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
859     }
860     if (!(flags & CPU_DUMP_FPU)) {
861         qemu_fprintf(f, "\n");
862         return;
863     }
864     if (fp_exception_el(env, el) != 0) {
865         qemu_fprintf(f, "    FPU disabled\n");
866         return;
867     }
868     qemu_fprintf(f, "     FPCR=%08x FPSR=%08x\n",
869                  vfp_get_fpcr(env), vfp_get_fpsr(env));
870 
871     if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) {
872         int j, zcr_len = sve_zcr_len_for_el(env, el);
873 
874         for (i = 0; i <= FFR_PRED_NUM; i++) {
875             bool eol;
876             if (i == FFR_PRED_NUM) {
877                 qemu_fprintf(f, "FFR=");
878                 /* It's last, so end the line.  */
879                 eol = true;
880             } else {
881                 qemu_fprintf(f, "P%02d=", i);
882                 switch (zcr_len) {
883                 case 0:
884                     eol = i % 8 == 7;
885                     break;
886                 case 1:
887                     eol = i % 6 == 5;
888                     break;
889                 case 2:
890                 case 3:
891                     eol = i % 3 == 2;
892                     break;
893                 default:
894                     /* More than one quadword per predicate.  */
895                     eol = true;
896                     break;
897                 }
898             }
899             for (j = zcr_len / 4; j >= 0; j--) {
900                 int digits;
901                 if (j * 4 + 4 <= zcr_len + 1) {
902                     digits = 16;
903                 } else {
904                     digits = (zcr_len % 4 + 1) * 4;
905                 }
906                 qemu_fprintf(f, "%0*" PRIx64 "%s", digits,
907                              env->vfp.pregs[i].p[j],
908                              j ? ":" : eol ? "\n" : " ");
909             }
910         }
911 
912         for (i = 0; i < 32; i++) {
913             if (zcr_len == 0) {
914                 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
915                              i, env->vfp.zregs[i].d[1],
916                              env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
917             } else if (zcr_len == 1) {
918                 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64
919                              ":%016" PRIx64 ":%016" PRIx64 "\n",
920                              i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2],
921                              env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]);
922             } else {
923                 for (j = zcr_len; j >= 0; j--) {
924                     bool odd = (zcr_len - j) % 2 != 0;
925                     if (j == zcr_len) {
926                         qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1);
927                     } else if (!odd) {
928                         if (j > 0) {
929                             qemu_fprintf(f, "   [%x-%x]=", j, j - 1);
930                         } else {
931                             qemu_fprintf(f, "     [%x]=", j);
932                         }
933                     }
934                     qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
935                                  env->vfp.zregs[i].d[j * 2 + 1],
936                                  env->vfp.zregs[i].d[j * 2],
937                                  odd || j == 0 ? "\n" : ":");
938                 }
939             }
940         }
941     } else {
942         for (i = 0; i < 32; i++) {
943             uint64_t *q = aa64_vfp_qreg(env, i);
944             qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
945                          i, q[1], q[0], (i & 1 ? "\n" : " "));
946         }
947     }
948 }
949 
950 #else
951 
952 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
953 {
954     g_assert_not_reached();
955 }
956 
957 #endif
958 
959 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
960 {
961     ARMCPU *cpu = ARM_CPU(cs);
962     CPUARMState *env = &cpu->env;
963     int i;
964 
965     if (is_a64(env)) {
966         aarch64_cpu_dump_state(cs, f, flags);
967         return;
968     }
969 
970     for (i = 0; i < 16; i++) {
971         qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
972         if ((i % 4) == 3) {
973             qemu_fprintf(f, "\n");
974         } else {
975             qemu_fprintf(f, " ");
976         }
977     }
978 
979     if (arm_feature(env, ARM_FEATURE_M)) {
980         uint32_t xpsr = xpsr_read(env);
981         const char *mode;
982         const char *ns_status = "";
983 
984         if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
985             ns_status = env->v7m.secure ? "S " : "NS ";
986         }
987 
988         if (xpsr & XPSR_EXCP) {
989             mode = "handler";
990         } else {
991             if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) {
992                 mode = "unpriv-thread";
993             } else {
994                 mode = "priv-thread";
995             }
996         }
997 
998         qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
999                      xpsr,
1000                      xpsr & XPSR_N ? 'N' : '-',
1001                      xpsr & XPSR_Z ? 'Z' : '-',
1002                      xpsr & XPSR_C ? 'C' : '-',
1003                      xpsr & XPSR_V ? 'V' : '-',
1004                      xpsr & XPSR_T ? 'T' : 'A',
1005                      ns_status,
1006                      mode);
1007     } else {
1008         uint32_t psr = cpsr_read(env);
1009         const char *ns_status = "";
1010 
1011         if (arm_feature(env, ARM_FEATURE_EL3) &&
1012             (psr & CPSR_M) != ARM_CPU_MODE_MON) {
1013             ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
1014         }
1015 
1016         qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
1017                      psr,
1018                      psr & CPSR_N ? 'N' : '-',
1019                      psr & CPSR_Z ? 'Z' : '-',
1020                      psr & CPSR_C ? 'C' : '-',
1021                      psr & CPSR_V ? 'V' : '-',
1022                      psr & CPSR_T ? 'T' : 'A',
1023                      ns_status,
1024                      aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
1025     }
1026 
1027     if (flags & CPU_DUMP_FPU) {
1028         int numvfpregs = 0;
1029         if (cpu_isar_feature(aa32_simd_r32, cpu)) {
1030             numvfpregs = 32;
1031         } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
1032             numvfpregs = 16;
1033         }
1034         for (i = 0; i < numvfpregs; i++) {
1035             uint64_t v = *aa32_vfp_dreg(env, i);
1036             qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
1037                          i * 2, (uint32_t)v,
1038                          i * 2 + 1, (uint32_t)(v >> 32),
1039                          i, v);
1040         }
1041         qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env));
1042         if (cpu_isar_feature(aa32_mve, cpu)) {
1043             qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr);
1044         }
1045     }
1046 }
1047 
1048 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
1049 {
1050     uint32_t Aff1 = idx / clustersz;
1051     uint32_t Aff0 = idx % clustersz;
1052     return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
1053 }
1054 
1055 static void cpreg_hashtable_data_destroy(gpointer data)
1056 {
1057     /*
1058      * Destroy function for cpu->cp_regs hashtable data entries.
1059      * We must free the name string because it was g_strdup()ed in
1060      * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
1061      * from r->name because we know we definitely allocated it.
1062      */
1063     ARMCPRegInfo *r = data;
1064 
1065     g_free((void *)r->name);
1066     g_free(r);
1067 }
1068 
1069 static void arm_cpu_initfn(Object *obj)
1070 {
1071     ARMCPU *cpu = ARM_CPU(obj);
1072 
1073     cpu_set_cpustate_pointers(cpu);
1074     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
1075                                          g_free, cpreg_hashtable_data_destroy);
1076 
1077     QLIST_INIT(&cpu->pre_el_change_hooks);
1078     QLIST_INIT(&cpu->el_change_hooks);
1079 
1080 #ifdef CONFIG_USER_ONLY
1081 # ifdef TARGET_AARCH64
1082     /*
1083      * The linux kernel defaults to 512-bit vectors, when sve is supported.
1084      * See documentation for /proc/sys/abi/sve_default_vector_length, and
1085      * our corresponding sve-default-vector-length cpu property.
1086      */
1087     cpu->sve_default_vq = 4;
1088 # endif
1089 #else
1090     /* Our inbound IRQ and FIQ lines */
1091     if (kvm_enabled()) {
1092         /* VIRQ and VFIQ are unused with KVM but we add them to maintain
1093          * the same interface as non-KVM CPUs.
1094          */
1095         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
1096     } else {
1097         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
1098     }
1099 
1100     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
1101                        ARRAY_SIZE(cpu->gt_timer_outputs));
1102 
1103     qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
1104                              "gicv3-maintenance-interrupt", 1);
1105     qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt,
1106                              "pmu-interrupt", 1);
1107 #endif
1108 
1109     /* DTB consumers generally don't in fact care what the 'compatible'
1110      * string is, so always provide some string and trust that a hypothetical
1111      * picky DTB consumer will also provide a helpful error message.
1112      */
1113     cpu->dtb_compatible = "qemu,unknown";
1114     cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */
1115     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
1116 
1117     if (tcg_enabled() || hvf_enabled()) {
1118         /* TCG and HVF implement PSCI 1.1 */
1119         cpu->psci_version = QEMU_PSCI_VERSION_1_1;
1120     }
1121 }
1122 
1123 static Property arm_cpu_gt_cntfrq_property =
1124             DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz,
1125                                NANOSECONDS_PER_SECOND / GTIMER_SCALE);
1126 
1127 static Property arm_cpu_reset_cbar_property =
1128             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
1129 
1130 static Property arm_cpu_reset_hivecs_property =
1131             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
1132 
1133 static Property arm_cpu_rvbar_property =
1134             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
1135 
1136 #ifndef CONFIG_USER_ONLY
1137 static Property arm_cpu_has_el2_property =
1138             DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
1139 
1140 static Property arm_cpu_has_el3_property =
1141             DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
1142 #endif
1143 
1144 static Property arm_cpu_cfgend_property =
1145             DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
1146 
1147 static Property arm_cpu_has_vfp_property =
1148             DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true);
1149 
1150 static Property arm_cpu_has_neon_property =
1151             DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true);
1152 
1153 static Property arm_cpu_has_dsp_property =
1154             DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true);
1155 
1156 static Property arm_cpu_has_mpu_property =
1157             DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
1158 
1159 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1160  * because the CPU initfn will have already set cpu->pmsav7_dregion to
1161  * the right value for that particular CPU type, and we don't want
1162  * to override that with an incorrect constant value.
1163  */
1164 static Property arm_cpu_pmsav7_dregion_property =
1165             DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU,
1166                                            pmsav7_dregion,
1167                                            qdev_prop_uint32, uint32_t);
1168 
1169 static bool arm_get_pmu(Object *obj, Error **errp)
1170 {
1171     ARMCPU *cpu = ARM_CPU(obj);
1172 
1173     return cpu->has_pmu;
1174 }
1175 
1176 static void arm_set_pmu(Object *obj, bool value, Error **errp)
1177 {
1178     ARMCPU *cpu = ARM_CPU(obj);
1179 
1180     if (value) {
1181         if (kvm_enabled() && !kvm_arm_pmu_supported()) {
1182             error_setg(errp, "'pmu' feature not supported by KVM on this host");
1183             return;
1184         }
1185         set_feature(&cpu->env, ARM_FEATURE_PMU);
1186     } else {
1187         unset_feature(&cpu->env, ARM_FEATURE_PMU);
1188     }
1189     cpu->has_pmu = value;
1190 }
1191 
1192 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
1193 {
1194     /*
1195      * The exact approach to calculating guest ticks is:
1196      *
1197      *     muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz,
1198      *              NANOSECONDS_PER_SECOND);
1199      *
1200      * We don't do that. Rather we intentionally use integer division
1201      * truncation below and in the caller for the conversion of host monotonic
1202      * time to guest ticks to provide the exact inverse for the semantics of
1203      * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so
1204      * it loses precision when representing frequencies where
1205      * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to
1206      * provide an exact inverse leads to scheduling timers with negative
1207      * periods, which in turn leads to sticky behaviour in the guest.
1208      *
1209      * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor
1210      * cannot become zero.
1211      */
1212     return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ?
1213       NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1;
1214 }
1215 
1216 void arm_cpu_post_init(Object *obj)
1217 {
1218     ARMCPU *cpu = ARM_CPU(obj);
1219 
1220     /* M profile implies PMSA. We have to do this here rather than
1221      * in realize with the other feature-implication checks because
1222      * we look at the PMSA bit to see if we should add some properties.
1223      */
1224     if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
1225         set_feature(&cpu->env, ARM_FEATURE_PMSA);
1226     }
1227 
1228     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
1229         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
1230         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property);
1231     }
1232 
1233     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
1234         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property);
1235     }
1236 
1237     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1238         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property);
1239     }
1240 
1241 #ifndef CONFIG_USER_ONLY
1242     if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
1243         /* Add the has_el3 state CPU property only if EL3 is allowed.  This will
1244          * prevent "has_el3" from existing on CPUs which cannot support EL3.
1245          */
1246         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property);
1247 
1248         object_property_add_link(obj, "secure-memory",
1249                                  TYPE_MEMORY_REGION,
1250                                  (Object **)&cpu->secure_memory,
1251                                  qdev_prop_allow_set_link_before_realize,
1252                                  OBJ_PROP_LINK_STRONG);
1253     }
1254 
1255     if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
1256         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property);
1257     }
1258 #endif
1259 
1260     if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
1261         cpu->has_pmu = true;
1262         object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu);
1263     }
1264 
1265     /*
1266      * Allow user to turn off VFP and Neon support, but only for TCG --
1267      * KVM does not currently allow us to lie to the guest about its
1268      * ID/feature registers, so the guest always sees what the host has.
1269      */
1270     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)
1271         ? cpu_isar_feature(aa64_fp_simd, cpu)
1272         : cpu_isar_feature(aa32_vfp, cpu)) {
1273         cpu->has_vfp = true;
1274         if (!kvm_enabled()) {
1275             qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property);
1276         }
1277     }
1278 
1279     if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) {
1280         cpu->has_neon = true;
1281         if (!kvm_enabled()) {
1282             qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property);
1283         }
1284     }
1285 
1286     if (arm_feature(&cpu->env, ARM_FEATURE_M) &&
1287         arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) {
1288         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property);
1289     }
1290 
1291     if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
1292         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property);
1293         if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1294             qdev_property_add_static(DEVICE(obj),
1295                                      &arm_cpu_pmsav7_dregion_property);
1296         }
1297     }
1298 
1299     if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) {
1300         object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau,
1301                                  qdev_prop_allow_set_link_before_realize,
1302                                  OBJ_PROP_LINK_STRONG);
1303         /*
1304          * M profile: initial value of the Secure VTOR. We can't just use
1305          * a simple DEFINE_PROP_UINT32 for this because we want to permit
1306          * the property to be set after realize.
1307          */
1308         object_property_add_uint32_ptr(obj, "init-svtor",
1309                                        &cpu->init_svtor,
1310                                        OBJ_PROP_FLAG_READWRITE);
1311     }
1312     if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
1313         /*
1314          * Initial value of the NS VTOR (for cores without the Security
1315          * extension, this is the only VTOR)
1316          */
1317         object_property_add_uint32_ptr(obj, "init-nsvtor",
1318                                        &cpu->init_nsvtor,
1319                                        OBJ_PROP_FLAG_READWRITE);
1320     }
1321 
1322     /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */
1323     object_property_add_uint32_ptr(obj, "psci-conduit",
1324                                    &cpu->psci_conduit,
1325                                    OBJ_PROP_FLAG_READWRITE);
1326 
1327     qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property);
1328 
1329     if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) {
1330         qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property);
1331     }
1332 
1333     if (kvm_enabled()) {
1334         kvm_arm_add_vcpu_properties(obj);
1335     }
1336 
1337 #ifndef CONFIG_USER_ONLY
1338     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) &&
1339         cpu_isar_feature(aa64_mte, cpu)) {
1340         object_property_add_link(obj, "tag-memory",
1341                                  TYPE_MEMORY_REGION,
1342                                  (Object **)&cpu->tag_memory,
1343                                  qdev_prop_allow_set_link_before_realize,
1344                                  OBJ_PROP_LINK_STRONG);
1345 
1346         if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
1347             object_property_add_link(obj, "secure-tag-memory",
1348                                      TYPE_MEMORY_REGION,
1349                                      (Object **)&cpu->secure_tag_memory,
1350                                      qdev_prop_allow_set_link_before_realize,
1351                                      OBJ_PROP_LINK_STRONG);
1352         }
1353     }
1354 #endif
1355 }
1356 
1357 static void arm_cpu_finalizefn(Object *obj)
1358 {
1359     ARMCPU *cpu = ARM_CPU(obj);
1360     ARMELChangeHook *hook, *next;
1361 
1362     g_hash_table_destroy(cpu->cp_regs);
1363 
1364     QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
1365         QLIST_REMOVE(hook, node);
1366         g_free(hook);
1367     }
1368     QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
1369         QLIST_REMOVE(hook, node);
1370         g_free(hook);
1371     }
1372 #ifndef CONFIG_USER_ONLY
1373     if (cpu->pmu_timer) {
1374         timer_free(cpu->pmu_timer);
1375     }
1376 #endif
1377 }
1378 
1379 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
1380 {
1381     Error *local_err = NULL;
1382 
1383     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1384         arm_cpu_sve_finalize(cpu, &local_err);
1385         if (local_err != NULL) {
1386             error_propagate(errp, local_err);
1387             return;
1388         }
1389 
1390         arm_cpu_pauth_finalize(cpu, &local_err);
1391         if (local_err != NULL) {
1392             error_propagate(errp, local_err);
1393             return;
1394         }
1395     }
1396 
1397     if (kvm_enabled()) {
1398         kvm_arm_steal_time_finalize(cpu, &local_err);
1399         if (local_err != NULL) {
1400             error_propagate(errp, local_err);
1401             return;
1402         }
1403     }
1404 }
1405 
1406 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
1407 {
1408     CPUState *cs = CPU(dev);
1409     ARMCPU *cpu = ARM_CPU(dev);
1410     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
1411     CPUARMState *env = &cpu->env;
1412     int pagebits;
1413     Error *local_err = NULL;
1414     bool no_aa32 = false;
1415 
1416     /* If we needed to query the host kernel for the CPU features
1417      * then it's possible that might have failed in the initfn, but
1418      * this is the first point where we can report it.
1419      */
1420     if (cpu->host_cpu_probe_failed) {
1421         if (!kvm_enabled() && !hvf_enabled()) {
1422             error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF");
1423         } else {
1424             error_setg(errp, "Failed to retrieve host CPU features");
1425         }
1426         return;
1427     }
1428 
1429 #ifndef CONFIG_USER_ONLY
1430     /* The NVIC and M-profile CPU are two halves of a single piece of
1431      * hardware; trying to use one without the other is a command line
1432      * error and will result in segfaults if not caught here.
1433      */
1434     if (arm_feature(env, ARM_FEATURE_M)) {
1435         if (!env->nvic) {
1436             error_setg(errp, "This board cannot be used with Cortex-M CPUs");
1437             return;
1438         }
1439     } else {
1440         if (env->nvic) {
1441             error_setg(errp, "This board can only be used with Cortex-M CPUs");
1442             return;
1443         }
1444     }
1445 
1446     if (kvm_enabled()) {
1447         /*
1448          * Catch all the cases which might cause us to create more than one
1449          * address space for the CPU (otherwise we will assert() later in
1450          * cpu_address_space_init()).
1451          */
1452         if (arm_feature(env, ARM_FEATURE_M)) {
1453             error_setg(errp,
1454                        "Cannot enable KVM when using an M-profile guest CPU");
1455             return;
1456         }
1457         if (cpu->has_el3) {
1458             error_setg(errp,
1459                        "Cannot enable KVM when guest CPU has EL3 enabled");
1460             return;
1461         }
1462         if (cpu->tag_memory) {
1463             error_setg(errp,
1464                        "Cannot enable KVM when guest CPUs has MTE enabled");
1465             return;
1466         }
1467     }
1468 
1469     {
1470         uint64_t scale;
1471 
1472         if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
1473             if (!cpu->gt_cntfrq_hz) {
1474                 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz",
1475                            cpu->gt_cntfrq_hz);
1476                 return;
1477             }
1478             scale = gt_cntfrq_period_ns(cpu);
1479         } else {
1480             scale = GTIMER_SCALE;
1481         }
1482 
1483         cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1484                                                arm_gt_ptimer_cb, cpu);
1485         cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1486                                                arm_gt_vtimer_cb, cpu);
1487         cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1488                                               arm_gt_htimer_cb, cpu);
1489         cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1490                                               arm_gt_stimer_cb, cpu);
1491         cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1492                                                   arm_gt_hvtimer_cb, cpu);
1493     }
1494 #endif
1495 
1496     cpu_exec_realizefn(cs, &local_err);
1497     if (local_err != NULL) {
1498         error_propagate(errp, local_err);
1499         return;
1500     }
1501 
1502     arm_cpu_finalize_features(cpu, &local_err);
1503     if (local_err != NULL) {
1504         error_propagate(errp, local_err);
1505         return;
1506     }
1507 
1508     if (arm_feature(env, ARM_FEATURE_AARCH64) &&
1509         cpu->has_vfp != cpu->has_neon) {
1510         /*
1511          * This is an architectural requirement for AArch64; AArch32 is
1512          * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1513          */
1514         error_setg(errp,
1515                    "AArch64 CPUs must have both VFP and Neon or neither");
1516         return;
1517     }
1518 
1519     if (!cpu->has_vfp) {
1520         uint64_t t;
1521         uint32_t u;
1522 
1523         t = cpu->isar.id_aa64isar1;
1524         t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0);
1525         cpu->isar.id_aa64isar1 = t;
1526 
1527         t = cpu->isar.id_aa64pfr0;
1528         t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf);
1529         cpu->isar.id_aa64pfr0 = t;
1530 
1531         u = cpu->isar.id_isar6;
1532         u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0);
1533         u = FIELD_DP32(u, ID_ISAR6, BF16, 0);
1534         cpu->isar.id_isar6 = u;
1535 
1536         u = cpu->isar.mvfr0;
1537         u = FIELD_DP32(u, MVFR0, FPSP, 0);
1538         u = FIELD_DP32(u, MVFR0, FPDP, 0);
1539         u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0);
1540         u = FIELD_DP32(u, MVFR0, FPSQRT, 0);
1541         u = FIELD_DP32(u, MVFR0, FPROUND, 0);
1542         if (!arm_feature(env, ARM_FEATURE_M)) {
1543             u = FIELD_DP32(u, MVFR0, FPTRAP, 0);
1544             u = FIELD_DP32(u, MVFR0, FPSHVEC, 0);
1545         }
1546         cpu->isar.mvfr0 = u;
1547 
1548         u = cpu->isar.mvfr1;
1549         u = FIELD_DP32(u, MVFR1, FPFTZ, 0);
1550         u = FIELD_DP32(u, MVFR1, FPDNAN, 0);
1551         u = FIELD_DP32(u, MVFR1, FPHP, 0);
1552         if (arm_feature(env, ARM_FEATURE_M)) {
1553             u = FIELD_DP32(u, MVFR1, FP16, 0);
1554         }
1555         cpu->isar.mvfr1 = u;
1556 
1557         u = cpu->isar.mvfr2;
1558         u = FIELD_DP32(u, MVFR2, FPMISC, 0);
1559         cpu->isar.mvfr2 = u;
1560     }
1561 
1562     if (!cpu->has_neon) {
1563         uint64_t t;
1564         uint32_t u;
1565 
1566         unset_feature(env, ARM_FEATURE_NEON);
1567 
1568         t = cpu->isar.id_aa64isar0;
1569         t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0);
1570         cpu->isar.id_aa64isar0 = t;
1571 
1572         t = cpu->isar.id_aa64isar1;
1573         t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0);
1574         t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0);
1575         t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0);
1576         cpu->isar.id_aa64isar1 = t;
1577 
1578         t = cpu->isar.id_aa64pfr0;
1579         t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf);
1580         cpu->isar.id_aa64pfr0 = t;
1581 
1582         u = cpu->isar.id_isar5;
1583         u = FIELD_DP32(u, ID_ISAR5, RDM, 0);
1584         u = FIELD_DP32(u, ID_ISAR5, VCMA, 0);
1585         cpu->isar.id_isar5 = u;
1586 
1587         u = cpu->isar.id_isar6;
1588         u = FIELD_DP32(u, ID_ISAR6, DP, 0);
1589         u = FIELD_DP32(u, ID_ISAR6, FHM, 0);
1590         u = FIELD_DP32(u, ID_ISAR6, BF16, 0);
1591         u = FIELD_DP32(u, ID_ISAR6, I8MM, 0);
1592         cpu->isar.id_isar6 = u;
1593 
1594         if (!arm_feature(env, ARM_FEATURE_M)) {
1595             u = cpu->isar.mvfr1;
1596             u = FIELD_DP32(u, MVFR1, SIMDLS, 0);
1597             u = FIELD_DP32(u, MVFR1, SIMDINT, 0);
1598             u = FIELD_DP32(u, MVFR1, SIMDSP, 0);
1599             u = FIELD_DP32(u, MVFR1, SIMDHP, 0);
1600             cpu->isar.mvfr1 = u;
1601 
1602             u = cpu->isar.mvfr2;
1603             u = FIELD_DP32(u, MVFR2, SIMDMISC, 0);
1604             cpu->isar.mvfr2 = u;
1605         }
1606     }
1607 
1608     if (!cpu->has_neon && !cpu->has_vfp) {
1609         uint64_t t;
1610         uint32_t u;
1611 
1612         t = cpu->isar.id_aa64isar0;
1613         t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0);
1614         cpu->isar.id_aa64isar0 = t;
1615 
1616         t = cpu->isar.id_aa64isar1;
1617         t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0);
1618         cpu->isar.id_aa64isar1 = t;
1619 
1620         u = cpu->isar.mvfr0;
1621         u = FIELD_DP32(u, MVFR0, SIMDREG, 0);
1622         cpu->isar.mvfr0 = u;
1623 
1624         /* Despite the name, this field covers both VFP and Neon */
1625         u = cpu->isar.mvfr1;
1626         u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0);
1627         cpu->isar.mvfr1 = u;
1628     }
1629 
1630     if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) {
1631         uint32_t u;
1632 
1633         unset_feature(env, ARM_FEATURE_THUMB_DSP);
1634 
1635         u = cpu->isar.id_isar1;
1636         u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1);
1637         cpu->isar.id_isar1 = u;
1638 
1639         u = cpu->isar.id_isar2;
1640         u = FIELD_DP32(u, ID_ISAR2, MULTU, 1);
1641         u = FIELD_DP32(u, ID_ISAR2, MULTS, 1);
1642         cpu->isar.id_isar2 = u;
1643 
1644         u = cpu->isar.id_isar3;
1645         u = FIELD_DP32(u, ID_ISAR3, SIMD, 1);
1646         u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0);
1647         cpu->isar.id_isar3 = u;
1648     }
1649 
1650     /* Some features automatically imply others: */
1651     if (arm_feature(env, ARM_FEATURE_V8)) {
1652         if (arm_feature(env, ARM_FEATURE_M)) {
1653             set_feature(env, ARM_FEATURE_V7);
1654         } else {
1655             set_feature(env, ARM_FEATURE_V7VE);
1656         }
1657     }
1658 
1659     /*
1660      * There exist AArch64 cpus without AArch32 support.  When KVM
1661      * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1662      * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1663      * As a general principle, we also do not make ID register
1664      * consistency checks anywhere unless using TCG, because only
1665      * for TCG would a consistency-check failure be a QEMU bug.
1666      */
1667     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1668         no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
1669     }
1670 
1671     if (arm_feature(env, ARM_FEATURE_V7VE)) {
1672         /* v7 Virtualization Extensions. In real hardware this implies
1673          * EL2 and also the presence of the Security Extensions.
1674          * For QEMU, for backwards-compatibility we implement some
1675          * CPUs or CPU configs which have no actual EL2 or EL3 but do
1676          * include the various other features that V7VE implies.
1677          * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1678          * Security Extensions is ARM_FEATURE_EL3.
1679          */
1680         assert(!tcg_enabled() || no_aa32 ||
1681                cpu_isar_feature(aa32_arm_div, cpu));
1682         set_feature(env, ARM_FEATURE_LPAE);
1683         set_feature(env, ARM_FEATURE_V7);
1684     }
1685     if (arm_feature(env, ARM_FEATURE_V7)) {
1686         set_feature(env, ARM_FEATURE_VAPA);
1687         set_feature(env, ARM_FEATURE_THUMB2);
1688         set_feature(env, ARM_FEATURE_MPIDR);
1689         if (!arm_feature(env, ARM_FEATURE_M)) {
1690             set_feature(env, ARM_FEATURE_V6K);
1691         } else {
1692             set_feature(env, ARM_FEATURE_V6);
1693         }
1694 
1695         /* Always define VBAR for V7 CPUs even if it doesn't exist in
1696          * non-EL3 configs. This is needed by some legacy boards.
1697          */
1698         set_feature(env, ARM_FEATURE_VBAR);
1699     }
1700     if (arm_feature(env, ARM_FEATURE_V6K)) {
1701         set_feature(env, ARM_FEATURE_V6);
1702         set_feature(env, ARM_FEATURE_MVFR);
1703     }
1704     if (arm_feature(env, ARM_FEATURE_V6)) {
1705         set_feature(env, ARM_FEATURE_V5);
1706         if (!arm_feature(env, ARM_FEATURE_M)) {
1707             assert(!tcg_enabled() || no_aa32 ||
1708                    cpu_isar_feature(aa32_jazelle, cpu));
1709             set_feature(env, ARM_FEATURE_AUXCR);
1710         }
1711     }
1712     if (arm_feature(env, ARM_FEATURE_V5)) {
1713         set_feature(env, ARM_FEATURE_V4T);
1714     }
1715     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1716         set_feature(env, ARM_FEATURE_V7MP);
1717     }
1718     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
1719         set_feature(env, ARM_FEATURE_CBAR);
1720     }
1721     if (arm_feature(env, ARM_FEATURE_THUMB2) &&
1722         !arm_feature(env, ARM_FEATURE_M)) {
1723         set_feature(env, ARM_FEATURE_THUMB_DSP);
1724     }
1725 
1726     /*
1727      * We rely on no XScale CPU having VFP so we can use the same bits in the
1728      * TB flags field for VECSTRIDE and XSCALE_CPAR.
1729      */
1730     assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) ||
1731            !cpu_isar_feature(aa32_vfp_simd, cpu) ||
1732            !arm_feature(env, ARM_FEATURE_XSCALE));
1733 
1734     if (arm_feature(env, ARM_FEATURE_V7) &&
1735         !arm_feature(env, ARM_FEATURE_M) &&
1736         !arm_feature(env, ARM_FEATURE_PMSA)) {
1737         /* v7VMSA drops support for the old ARMv5 tiny pages, so we
1738          * can use 4K pages.
1739          */
1740         pagebits = 12;
1741     } else {
1742         /* For CPUs which might have tiny 1K pages, or which have an
1743          * MPU and might have small region sizes, stick with 1K pages.
1744          */
1745         pagebits = 10;
1746     }
1747     if (!set_preferred_target_page_bits(pagebits)) {
1748         /* This can only ever happen for hotplugging a CPU, or if
1749          * the board code incorrectly creates a CPU which it has
1750          * promised via minimum_page_size that it will not.
1751          */
1752         error_setg(errp, "This CPU requires a smaller page size than the "
1753                    "system is using");
1754         return;
1755     }
1756 
1757     /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
1758      * We don't support setting cluster ID ([16..23]) (known as Aff2
1759      * in later ARM ARM versions), or any of the higher affinity level fields,
1760      * so these bits always RAZ.
1761      */
1762     if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
1763         cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index,
1764                                                ARM_DEFAULT_CPUS_PER_CLUSTER);
1765     }
1766 
1767     if (cpu->reset_hivecs) {
1768             cpu->reset_sctlr |= (1 << 13);
1769     }
1770 
1771     if (cpu->cfgend) {
1772         if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1773             cpu->reset_sctlr |= SCTLR_EE;
1774         } else {
1775             cpu->reset_sctlr |= SCTLR_B;
1776         }
1777     }
1778 
1779     if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) {
1780         /* If the has_el3 CPU property is disabled then we need to disable the
1781          * feature.
1782          */
1783         unset_feature(env, ARM_FEATURE_EL3);
1784 
1785         /* Disable the security extension feature bits in the processor feature
1786          * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
1787          */
1788         cpu->isar.id_pfr1 &= ~0xf0;
1789         cpu->isar.id_aa64pfr0 &= ~0xf000;
1790     }
1791 
1792     if (!cpu->has_el2) {
1793         unset_feature(env, ARM_FEATURE_EL2);
1794     }
1795 
1796     if (!cpu->has_pmu) {
1797         unset_feature(env, ARM_FEATURE_PMU);
1798     }
1799     if (arm_feature(env, ARM_FEATURE_PMU)) {
1800         pmu_init(cpu);
1801 
1802         if (!kvm_enabled()) {
1803             arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
1804             arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
1805         }
1806 
1807 #ifndef CONFIG_USER_ONLY
1808         cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb,
1809                 cpu);
1810 #endif
1811     } else {
1812         cpu->isar.id_aa64dfr0 =
1813             FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
1814         cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0);
1815         cpu->pmceid0 = 0;
1816         cpu->pmceid1 = 0;
1817     }
1818 
1819     if (!arm_feature(env, ARM_FEATURE_EL2)) {
1820         /* Disable the hypervisor feature bits in the processor feature
1821          * registers if we don't have EL2. These are id_pfr1[15:12] and
1822          * id_aa64pfr0_el1[11:8].
1823          */
1824         cpu->isar.id_aa64pfr0 &= ~0xf00;
1825         cpu->isar.id_pfr1 &= ~0xf000;
1826     }
1827 
1828 #ifndef CONFIG_USER_ONLY
1829     if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) {
1830         /*
1831          * Disable the MTE feature bits if we do not have tag-memory
1832          * provided by the machine.
1833          */
1834         cpu->isar.id_aa64pfr1 =
1835             FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
1836     }
1837 #endif
1838 
1839     /* MPU can be configured out of a PMSA CPU either by setting has-mpu
1840      * to false or by setting pmsav7-dregion to 0.
1841      */
1842     if (!cpu->has_mpu) {
1843         cpu->pmsav7_dregion = 0;
1844     }
1845     if (cpu->pmsav7_dregion == 0) {
1846         cpu->has_mpu = false;
1847     }
1848 
1849     if (arm_feature(env, ARM_FEATURE_PMSA) &&
1850         arm_feature(env, ARM_FEATURE_V7)) {
1851         uint32_t nr = cpu->pmsav7_dregion;
1852 
1853         if (nr > 0xff) {
1854             error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
1855             return;
1856         }
1857 
1858         if (nr) {
1859             if (arm_feature(env, ARM_FEATURE_V8)) {
1860                 /* PMSAv8 */
1861                 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr);
1862                 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr);
1863                 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1864                     env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr);
1865                     env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr);
1866                 }
1867             } else {
1868                 env->pmsav7.drbar = g_new0(uint32_t, nr);
1869                 env->pmsav7.drsr = g_new0(uint32_t, nr);
1870                 env->pmsav7.dracr = g_new0(uint32_t, nr);
1871             }
1872         }
1873     }
1874 
1875     if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1876         uint32_t nr = cpu->sau_sregion;
1877 
1878         if (nr > 0xff) {
1879             error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr);
1880             return;
1881         }
1882 
1883         if (nr) {
1884             env->sau.rbar = g_new0(uint32_t, nr);
1885             env->sau.rlar = g_new0(uint32_t, nr);
1886         }
1887     }
1888 
1889     if (arm_feature(env, ARM_FEATURE_EL3)) {
1890         set_feature(env, ARM_FEATURE_VBAR);
1891     }
1892 
1893     register_cp_regs_for_features(cpu);
1894     arm_cpu_register_gdb_regs_for_features(cpu);
1895 
1896     init_cpreg_list(cpu);
1897 
1898 #ifndef CONFIG_USER_ONLY
1899     MachineState *ms = MACHINE(qdev_get_machine());
1900     unsigned int smp_cpus = ms->smp.cpus;
1901     bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY);
1902 
1903     /*
1904      * We must set cs->num_ases to the final value before
1905      * the first call to cpu_address_space_init.
1906      */
1907     if (cpu->tag_memory != NULL) {
1908         cs->num_ases = 3 + has_secure;
1909     } else {
1910         cs->num_ases = 1 + has_secure;
1911     }
1912 
1913     if (has_secure) {
1914         if (!cpu->secure_memory) {
1915             cpu->secure_memory = cs->memory;
1916         }
1917         cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory",
1918                                cpu->secure_memory);
1919     }
1920 
1921     if (cpu->tag_memory != NULL) {
1922         cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory",
1923                                cpu->tag_memory);
1924         if (has_secure) {
1925             cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory",
1926                                    cpu->secure_tag_memory);
1927         }
1928     }
1929 
1930     cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
1931 
1932     /* No core_count specified, default to smp_cpus. */
1933     if (cpu->core_count == -1) {
1934         cpu->core_count = smp_cpus;
1935     }
1936 #endif
1937 
1938     if (tcg_enabled()) {
1939         int dcz_blocklen = 4 << cpu->dcz_blocksize;
1940 
1941         /*
1942          * We only support DCZ blocklen that fits on one page.
1943          *
1944          * Architectually this is always true.  However TARGET_PAGE_SIZE
1945          * is variable and, for compatibility with -machine virt-2.7,
1946          * is only 1KiB, as an artifact of legacy ARMv5 subpage support.
1947          * But even then, while the largest architectural DCZ blocklen
1948          * is 2KiB, no cpu actually uses such a large blocklen.
1949          */
1950         assert(dcz_blocklen <= TARGET_PAGE_SIZE);
1951 
1952         /*
1953          * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say
1954          * both nibbles of each byte storing tag data may be written at once.
1955          * Since TAG_GRANULE is 16, this means that blocklen must be >= 32.
1956          */
1957         if (cpu_isar_feature(aa64_mte, cpu)) {
1958             assert(dcz_blocklen >= 2 * TAG_GRANULE);
1959         }
1960     }
1961 
1962     qemu_init_vcpu(cs);
1963     cpu_reset(cs);
1964 
1965     acc->parent_realize(dev, errp);
1966 }
1967 
1968 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
1969 {
1970     ObjectClass *oc;
1971     char *typename;
1972     char **cpuname;
1973     const char *cpunamestr;
1974 
1975     cpuname = g_strsplit(cpu_model, ",", 1);
1976     cpunamestr = cpuname[0];
1977 #ifdef CONFIG_USER_ONLY
1978     /* For backwards compatibility usermode emulation allows "-cpu any",
1979      * which has the same semantics as "-cpu max".
1980      */
1981     if (!strcmp(cpunamestr, "any")) {
1982         cpunamestr = "max";
1983     }
1984 #endif
1985     typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr);
1986     oc = object_class_by_name(typename);
1987     g_strfreev(cpuname);
1988     g_free(typename);
1989     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
1990         object_class_is_abstract(oc)) {
1991         return NULL;
1992     }
1993     return oc;
1994 }
1995 
1996 static Property arm_cpu_properties[] = {
1997     DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0),
1998     DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
1999                         mp_affinity, ARM64_AFFINITY_INVALID),
2000     DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
2001     DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
2002     DEFINE_PROP_END_OF_LIST()
2003 };
2004 
2005 static gchar *arm_gdb_arch_name(CPUState *cs)
2006 {
2007     ARMCPU *cpu = ARM_CPU(cs);
2008     CPUARMState *env = &cpu->env;
2009 
2010     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
2011         return g_strdup("iwmmxt");
2012     }
2013     return g_strdup("arm");
2014 }
2015 
2016 #ifndef CONFIG_USER_ONLY
2017 #include "hw/core/sysemu-cpu-ops.h"
2018 
2019 static const struct SysemuCPUOps arm_sysemu_ops = {
2020     .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug,
2021     .asidx_from_attrs = arm_asidx_from_attrs,
2022     .write_elf32_note = arm_cpu_write_elf32_note,
2023     .write_elf64_note = arm_cpu_write_elf64_note,
2024     .virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
2025     .legacy_vmsd = &vmstate_arm_cpu,
2026 };
2027 #endif
2028 
2029 #ifdef CONFIG_TCG
2030 static const struct TCGCPUOps arm_tcg_ops = {
2031     .initialize = arm_translate_init,
2032     .synchronize_from_tb = arm_cpu_synchronize_from_tb,
2033     .debug_excp_handler = arm_debug_excp_handler,
2034 
2035 #ifdef CONFIG_USER_ONLY
2036     .record_sigsegv = arm_cpu_record_sigsegv,
2037     .record_sigbus = arm_cpu_record_sigbus,
2038 #else
2039     .tlb_fill = arm_cpu_tlb_fill,
2040     .cpu_exec_interrupt = arm_cpu_exec_interrupt,
2041     .do_interrupt = arm_cpu_do_interrupt,
2042     .do_transaction_failed = arm_cpu_do_transaction_failed,
2043     .do_unaligned_access = arm_cpu_do_unaligned_access,
2044     .adjust_watchpoint_address = arm_adjust_watchpoint_address,
2045     .debug_check_watchpoint = arm_debug_check_watchpoint,
2046     .debug_check_breakpoint = arm_debug_check_breakpoint,
2047 #endif /* !CONFIG_USER_ONLY */
2048 };
2049 #endif /* CONFIG_TCG */
2050 
2051 static void arm_cpu_class_init(ObjectClass *oc, void *data)
2052 {
2053     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2054     CPUClass *cc = CPU_CLASS(acc);
2055     DeviceClass *dc = DEVICE_CLASS(oc);
2056 
2057     device_class_set_parent_realize(dc, arm_cpu_realizefn,
2058                                     &acc->parent_realize);
2059 
2060     device_class_set_props(dc, arm_cpu_properties);
2061     device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset);
2062 
2063     cc->class_by_name = arm_cpu_class_by_name;
2064     cc->has_work = arm_cpu_has_work;
2065     cc->dump_state = arm_cpu_dump_state;
2066     cc->set_pc = arm_cpu_set_pc;
2067     cc->gdb_read_register = arm_cpu_gdb_read_register;
2068     cc->gdb_write_register = arm_cpu_gdb_write_register;
2069 #ifndef CONFIG_USER_ONLY
2070     cc->sysemu_ops = &arm_sysemu_ops;
2071 #endif
2072     cc->gdb_num_core_regs = 26;
2073     cc->gdb_core_xml_file = "arm-core.xml";
2074     cc->gdb_arch_name = arm_gdb_arch_name;
2075     cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml;
2076     cc->gdb_stop_before_watchpoint = true;
2077     cc->disas_set_info = arm_disas_set_info;
2078 
2079 #ifdef CONFIG_TCG
2080     cc->tcg_ops = &arm_tcg_ops;
2081 #endif /* CONFIG_TCG */
2082 }
2083 
2084 static void arm_cpu_instance_init(Object *obj)
2085 {
2086     ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
2087 
2088     acc->info->initfn(obj);
2089     arm_cpu_post_init(obj);
2090 }
2091 
2092 static void cpu_register_class_init(ObjectClass *oc, void *data)
2093 {
2094     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2095 
2096     acc->info = data;
2097 }
2098 
2099 void arm_cpu_register(const ARMCPUInfo *info)
2100 {
2101     TypeInfo type_info = {
2102         .parent = TYPE_ARM_CPU,
2103         .instance_size = sizeof(ARMCPU),
2104         .instance_align = __alignof__(ARMCPU),
2105         .instance_init = arm_cpu_instance_init,
2106         .class_size = sizeof(ARMCPUClass),
2107         .class_init = info->class_init ?: cpu_register_class_init,
2108         .class_data = (void *)info,
2109     };
2110 
2111     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
2112     type_register(&type_info);
2113     g_free((void *)type_info.name);
2114 }
2115 
2116 static const TypeInfo arm_cpu_type_info = {
2117     .name = TYPE_ARM_CPU,
2118     .parent = TYPE_CPU,
2119     .instance_size = sizeof(ARMCPU),
2120     .instance_align = __alignof__(ARMCPU),
2121     .instance_init = arm_cpu_initfn,
2122     .instance_finalize = arm_cpu_finalizefn,
2123     .abstract = true,
2124     .class_size = sizeof(ARMCPUClass),
2125     .class_init = arm_cpu_class_init,
2126 };
2127 
2128 static void arm_cpu_register_types(void)
2129 {
2130     type_register_static(&arm_cpu_type_info);
2131 }
2132 
2133 type_init(arm_cpu_register_types)
2134