1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu-common.h" 24 #include "target/arm/idau.h" 25 #include "qemu/module.h" 26 #include "qapi/error.h" 27 #include "qapi/visitor.h" 28 #include "cpu.h" 29 #include "internals.h" 30 #include "exec/exec-all.h" 31 #include "hw/qdev-properties.h" 32 #if !defined(CONFIG_USER_ONLY) 33 #include "hw/loader.h" 34 #include "hw/boards.h" 35 #endif 36 #include "sysemu/sysemu.h" 37 #include "sysemu/tcg.h" 38 #include "sysemu/hw_accel.h" 39 #include "kvm_arm.h" 40 #include "disas/capstone.h" 41 #include "fpu/softfloat.h" 42 43 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 44 { 45 ARMCPU *cpu = ARM_CPU(cs); 46 CPUARMState *env = &cpu->env; 47 48 if (is_a64(env)) { 49 env->pc = value; 50 env->thumb = 0; 51 } else { 52 env->regs[15] = value & ~1; 53 env->thumb = value & 1; 54 } 55 } 56 57 static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 58 { 59 ARMCPU *cpu = ARM_CPU(cs); 60 CPUARMState *env = &cpu->env; 61 62 /* 63 * It's OK to look at env for the current mode here, because it's 64 * never possible for an AArch64 TB to chain to an AArch32 TB. 65 */ 66 if (is_a64(env)) { 67 env->pc = tb->pc; 68 } else { 69 env->regs[15] = tb->pc; 70 } 71 } 72 73 static bool arm_cpu_has_work(CPUState *cs) 74 { 75 ARMCPU *cpu = ARM_CPU(cs); 76 77 return (cpu->power_state != PSCI_OFF) 78 && cs->interrupt_request & 79 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 80 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 81 | CPU_INTERRUPT_EXITTB); 82 } 83 84 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 85 void *opaque) 86 { 87 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 88 89 entry->hook = hook; 90 entry->opaque = opaque; 91 92 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 93 } 94 95 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 96 void *opaque) 97 { 98 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 99 100 entry->hook = hook; 101 entry->opaque = opaque; 102 103 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 104 } 105 106 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 107 { 108 /* Reset a single ARMCPRegInfo register */ 109 ARMCPRegInfo *ri = value; 110 ARMCPU *cpu = opaque; 111 112 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 113 return; 114 } 115 116 if (ri->resetfn) { 117 ri->resetfn(&cpu->env, ri); 118 return; 119 } 120 121 /* A zero offset is never possible as it would be regs[0] 122 * so we use it to indicate that reset is being handled elsewhere. 123 * This is basically only used for fields in non-core coprocessors 124 * (like the pxa2xx ones). 125 */ 126 if (!ri->fieldoffset) { 127 return; 128 } 129 130 if (cpreg_field_is_64bit(ri)) { 131 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 132 } else { 133 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 134 } 135 } 136 137 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 138 { 139 /* Purely an assertion check: we've already done reset once, 140 * so now check that running the reset for the cpreg doesn't 141 * change its value. This traps bugs where two different cpregs 142 * both try to reset the same state field but to different values. 143 */ 144 ARMCPRegInfo *ri = value; 145 ARMCPU *cpu = opaque; 146 uint64_t oldvalue, newvalue; 147 148 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 149 return; 150 } 151 152 oldvalue = read_raw_cp_reg(&cpu->env, ri); 153 cp_reg_reset(key, value, opaque); 154 newvalue = read_raw_cp_reg(&cpu->env, ri); 155 assert(oldvalue == newvalue); 156 } 157 158 static void arm_cpu_reset(DeviceState *dev) 159 { 160 CPUState *s = CPU(dev); 161 ARMCPU *cpu = ARM_CPU(s); 162 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 163 CPUARMState *env = &cpu->env; 164 165 acc->parent_reset(dev); 166 167 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 168 169 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 170 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 171 172 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 173 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 174 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 175 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 176 177 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 178 s->halted = cpu->start_powered_off; 179 180 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 181 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 182 } 183 184 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 185 /* 64 bit CPUs always start in 64 bit mode */ 186 env->aarch64 = 1; 187 #if defined(CONFIG_USER_ONLY) 188 env->pstate = PSTATE_MODE_EL0t; 189 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 190 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 191 /* Enable all PAC keys. */ 192 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 193 SCTLR_EnDA | SCTLR_EnDB); 194 /* and to the FP/Neon instructions */ 195 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 196 /* and to the SVE instructions */ 197 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 198 /* with reasonable vector length */ 199 if (cpu_isar_feature(aa64_sve, cpu)) { 200 env->vfp.zcr_el[1] = MIN(cpu->sve_max_vq - 1, 3); 201 } 202 /* 203 * Enable TBI0 and TBI1. While the real kernel only enables TBI0, 204 * turning on both here will produce smaller code and otherwise 205 * make no difference to the user-level emulation. 206 * 207 * In sve_probe_page, we assume that this is set. 208 * Do not modify this without other changes. 209 */ 210 env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); 211 #else 212 /* Reset into the highest available EL */ 213 if (arm_feature(env, ARM_FEATURE_EL3)) { 214 env->pstate = PSTATE_MODE_EL3h; 215 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 216 env->pstate = PSTATE_MODE_EL2h; 217 } else { 218 env->pstate = PSTATE_MODE_EL1h; 219 } 220 env->pc = cpu->rvbar; 221 #endif 222 } else { 223 #if defined(CONFIG_USER_ONLY) 224 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 225 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 226 #endif 227 } 228 229 #if defined(CONFIG_USER_ONLY) 230 env->uncached_cpsr = ARM_CPU_MODE_USR; 231 /* For user mode we must enable access to coprocessors */ 232 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 233 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 234 env->cp15.c15_cpar = 3; 235 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 236 env->cp15.c15_cpar = 1; 237 } 238 #else 239 240 /* 241 * If the highest available EL is EL2, AArch32 will start in Hyp 242 * mode; otherwise it starts in SVC. Note that if we start in 243 * AArch64 then these values in the uncached_cpsr will be ignored. 244 */ 245 if (arm_feature(env, ARM_FEATURE_EL2) && 246 !arm_feature(env, ARM_FEATURE_EL3)) { 247 env->uncached_cpsr = ARM_CPU_MODE_HYP; 248 } else { 249 env->uncached_cpsr = ARM_CPU_MODE_SVC; 250 } 251 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 252 253 if (arm_feature(env, ARM_FEATURE_M)) { 254 uint32_t initial_msp; /* Loaded from 0x0 */ 255 uint32_t initial_pc; /* Loaded from 0x4 */ 256 uint8_t *rom; 257 uint32_t vecbase; 258 259 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 260 env->v7m.secure = true; 261 } else { 262 /* This bit resets to 0 if security is supported, but 1 if 263 * it is not. The bit is not present in v7M, but we set it 264 * here so we can avoid having to make checks on it conditional 265 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 266 */ 267 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 268 /* 269 * Set NSACR to indicate "NS access permitted to everything"; 270 * this avoids having to have all the tests of it being 271 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 272 * v8.1M the guest-visible value of NSACR in a CPU without the 273 * Security Extension is 0xcff. 274 */ 275 env->v7m.nsacr = 0xcff; 276 } 277 278 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 279 * that it resets to 1, so QEMU always does that rather than making 280 * it dependent on CPU model. In v8M it is RES1. 281 */ 282 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 283 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 284 if (arm_feature(env, ARM_FEATURE_V8)) { 285 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 286 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 287 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 288 } 289 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 290 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 291 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 292 } 293 294 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 295 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 296 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 297 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 298 } 299 /* Unlike A/R profile, M profile defines the reset LR value */ 300 env->regs[14] = 0xffffffff; 301 302 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 303 304 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 305 vecbase = env->v7m.vecbase[env->v7m.secure]; 306 rom = rom_ptr(vecbase, 8); 307 if (rom) { 308 /* Address zero is covered by ROM which hasn't yet been 309 * copied into physical memory. 310 */ 311 initial_msp = ldl_p(rom); 312 initial_pc = ldl_p(rom + 4); 313 } else { 314 /* Address zero not covered by a ROM blob, or the ROM blob 315 * is in non-modifiable memory and this is a second reset after 316 * it got copied into memory. In the latter case, rom_ptr 317 * will return a NULL pointer and we should use ldl_phys instead. 318 */ 319 initial_msp = ldl_phys(s->as, vecbase); 320 initial_pc = ldl_phys(s->as, vecbase + 4); 321 } 322 323 env->regs[13] = initial_msp & 0xFFFFFFFC; 324 env->regs[15] = initial_pc & ~1; 325 env->thumb = initial_pc & 1; 326 } 327 328 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 329 * executing as AArch32 then check if highvecs are enabled and 330 * adjust the PC accordingly. 331 */ 332 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 333 env->regs[15] = 0xFFFF0000; 334 } 335 336 /* M profile requires that reset clears the exclusive monitor; 337 * A profile does not, but clearing it makes more sense than having it 338 * set with an exclusive access on address zero. 339 */ 340 arm_clear_exclusive(env); 341 342 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 343 #endif 344 345 if (arm_feature(env, ARM_FEATURE_PMSA)) { 346 if (cpu->pmsav7_dregion > 0) { 347 if (arm_feature(env, ARM_FEATURE_V8)) { 348 memset(env->pmsav8.rbar[M_REG_NS], 0, 349 sizeof(*env->pmsav8.rbar[M_REG_NS]) 350 * cpu->pmsav7_dregion); 351 memset(env->pmsav8.rlar[M_REG_NS], 0, 352 sizeof(*env->pmsav8.rlar[M_REG_NS]) 353 * cpu->pmsav7_dregion); 354 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 355 memset(env->pmsav8.rbar[M_REG_S], 0, 356 sizeof(*env->pmsav8.rbar[M_REG_S]) 357 * cpu->pmsav7_dregion); 358 memset(env->pmsav8.rlar[M_REG_S], 0, 359 sizeof(*env->pmsav8.rlar[M_REG_S]) 360 * cpu->pmsav7_dregion); 361 } 362 } else if (arm_feature(env, ARM_FEATURE_V7)) { 363 memset(env->pmsav7.drbar, 0, 364 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 365 memset(env->pmsav7.drsr, 0, 366 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 367 memset(env->pmsav7.dracr, 0, 368 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 369 } 370 } 371 env->pmsav7.rnr[M_REG_NS] = 0; 372 env->pmsav7.rnr[M_REG_S] = 0; 373 env->pmsav8.mair0[M_REG_NS] = 0; 374 env->pmsav8.mair0[M_REG_S] = 0; 375 env->pmsav8.mair1[M_REG_NS] = 0; 376 env->pmsav8.mair1[M_REG_S] = 0; 377 } 378 379 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 380 if (cpu->sau_sregion > 0) { 381 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 382 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 383 } 384 env->sau.rnr = 0; 385 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 386 * the Cortex-M33 does. 387 */ 388 env->sau.ctrl = 0; 389 } 390 391 set_flush_to_zero(1, &env->vfp.standard_fp_status); 392 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 393 set_default_nan_mode(1, &env->vfp.standard_fp_status); 394 set_float_detect_tininess(float_tininess_before_rounding, 395 &env->vfp.fp_status); 396 set_float_detect_tininess(float_tininess_before_rounding, 397 &env->vfp.standard_fp_status); 398 set_float_detect_tininess(float_tininess_before_rounding, 399 &env->vfp.fp_status_f16); 400 #ifndef CONFIG_USER_ONLY 401 if (kvm_enabled()) { 402 kvm_arm_reset_vcpu(cpu); 403 } 404 #endif 405 406 hw_breakpoint_update_all(cpu); 407 hw_watchpoint_update_all(cpu); 408 arm_rebuild_hflags(env); 409 } 410 411 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 412 unsigned int target_el, 413 unsigned int cur_el, bool secure, 414 uint64_t hcr_el2) 415 { 416 CPUARMState *env = cs->env_ptr; 417 bool pstate_unmasked; 418 bool unmasked = false; 419 420 /* 421 * Don't take exceptions if they target a lower EL. 422 * This check should catch any exceptions that would not be taken 423 * but left pending. 424 */ 425 if (cur_el > target_el) { 426 return false; 427 } 428 429 switch (excp_idx) { 430 case EXCP_FIQ: 431 pstate_unmasked = !(env->daif & PSTATE_F); 432 break; 433 434 case EXCP_IRQ: 435 pstate_unmasked = !(env->daif & PSTATE_I); 436 break; 437 438 case EXCP_VFIQ: 439 if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 440 /* VFIQs are only taken when hypervized and non-secure. */ 441 return false; 442 } 443 return !(env->daif & PSTATE_F); 444 case EXCP_VIRQ: 445 if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 446 /* VIRQs are only taken when hypervized and non-secure. */ 447 return false; 448 } 449 return !(env->daif & PSTATE_I); 450 default: 451 g_assert_not_reached(); 452 } 453 454 /* 455 * Use the target EL, current execution state and SCR/HCR settings to 456 * determine whether the corresponding CPSR bit is used to mask the 457 * interrupt. 458 */ 459 if ((target_el > cur_el) && (target_el != 1)) { 460 /* Exceptions targeting a higher EL may not be maskable */ 461 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 462 /* 463 * 64-bit masking rules are simple: exceptions to EL3 464 * can't be masked, and exceptions to EL2 can only be 465 * masked from Secure state. The HCR and SCR settings 466 * don't affect the masking logic, only the interrupt routing. 467 */ 468 if (target_el == 3 || !secure) { 469 unmasked = true; 470 } 471 } else { 472 /* 473 * The old 32-bit-only environment has a more complicated 474 * masking setup. HCR and SCR bits not only affect interrupt 475 * routing but also change the behaviour of masking. 476 */ 477 bool hcr, scr; 478 479 switch (excp_idx) { 480 case EXCP_FIQ: 481 /* 482 * If FIQs are routed to EL3 or EL2 then there are cases where 483 * we override the CPSR.F in determining if the exception is 484 * masked or not. If neither of these are set then we fall back 485 * to the CPSR.F setting otherwise we further assess the state 486 * below. 487 */ 488 hcr = hcr_el2 & HCR_FMO; 489 scr = (env->cp15.scr_el3 & SCR_FIQ); 490 491 /* 492 * When EL3 is 32-bit, the SCR.FW bit controls whether the 493 * CPSR.F bit masks FIQ interrupts when taken in non-secure 494 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 495 * when non-secure but only when FIQs are only routed to EL3. 496 */ 497 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 498 break; 499 case EXCP_IRQ: 500 /* 501 * When EL3 execution state is 32-bit, if HCR.IMO is set then 502 * we may override the CPSR.I masking when in non-secure state. 503 * The SCR.IRQ setting has already been taken into consideration 504 * when setting the target EL, so it does not have a further 505 * affect here. 506 */ 507 hcr = hcr_el2 & HCR_IMO; 508 scr = false; 509 break; 510 default: 511 g_assert_not_reached(); 512 } 513 514 if ((scr || hcr) && !secure) { 515 unmasked = true; 516 } 517 } 518 } 519 520 /* 521 * The PSTATE bits only mask the interrupt if we have not overriden the 522 * ability above. 523 */ 524 return unmasked || pstate_unmasked; 525 } 526 527 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 528 { 529 CPUClass *cc = CPU_GET_CLASS(cs); 530 CPUARMState *env = cs->env_ptr; 531 uint32_t cur_el = arm_current_el(env); 532 bool secure = arm_is_secure(env); 533 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 534 uint32_t target_el; 535 uint32_t excp_idx; 536 537 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 538 539 if (interrupt_request & CPU_INTERRUPT_FIQ) { 540 excp_idx = EXCP_FIQ; 541 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 542 if (arm_excp_unmasked(cs, excp_idx, target_el, 543 cur_el, secure, hcr_el2)) { 544 goto found; 545 } 546 } 547 if (interrupt_request & CPU_INTERRUPT_HARD) { 548 excp_idx = EXCP_IRQ; 549 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 550 if (arm_excp_unmasked(cs, excp_idx, target_el, 551 cur_el, secure, hcr_el2)) { 552 goto found; 553 } 554 } 555 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 556 excp_idx = EXCP_VIRQ; 557 target_el = 1; 558 if (arm_excp_unmasked(cs, excp_idx, target_el, 559 cur_el, secure, hcr_el2)) { 560 goto found; 561 } 562 } 563 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 564 excp_idx = EXCP_VFIQ; 565 target_el = 1; 566 if (arm_excp_unmasked(cs, excp_idx, target_el, 567 cur_el, secure, hcr_el2)) { 568 goto found; 569 } 570 } 571 return false; 572 573 found: 574 cs->exception_index = excp_idx; 575 env->exception.target_el = target_el; 576 cc->do_interrupt(cs); 577 return true; 578 } 579 580 void arm_cpu_update_virq(ARMCPU *cpu) 581 { 582 /* 583 * Update the interrupt level for VIRQ, which is the logical OR of 584 * the HCR_EL2.VI bit and the input line level from the GIC. 585 */ 586 CPUARMState *env = &cpu->env; 587 CPUState *cs = CPU(cpu); 588 589 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 590 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 591 592 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 593 if (new_state) { 594 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 595 } else { 596 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 597 } 598 } 599 } 600 601 void arm_cpu_update_vfiq(ARMCPU *cpu) 602 { 603 /* 604 * Update the interrupt level for VFIQ, which is the logical OR of 605 * the HCR_EL2.VF bit and the input line level from the GIC. 606 */ 607 CPUARMState *env = &cpu->env; 608 CPUState *cs = CPU(cpu); 609 610 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 611 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 612 613 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 614 if (new_state) { 615 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 616 } else { 617 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 618 } 619 } 620 } 621 622 #ifndef CONFIG_USER_ONLY 623 static void arm_cpu_set_irq(void *opaque, int irq, int level) 624 { 625 ARMCPU *cpu = opaque; 626 CPUARMState *env = &cpu->env; 627 CPUState *cs = CPU(cpu); 628 static const int mask[] = { 629 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 630 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 631 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 632 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 633 }; 634 635 if (level) { 636 env->irq_line_state |= mask[irq]; 637 } else { 638 env->irq_line_state &= ~mask[irq]; 639 } 640 641 switch (irq) { 642 case ARM_CPU_VIRQ: 643 assert(arm_feature(env, ARM_FEATURE_EL2)); 644 arm_cpu_update_virq(cpu); 645 break; 646 case ARM_CPU_VFIQ: 647 assert(arm_feature(env, ARM_FEATURE_EL2)); 648 arm_cpu_update_vfiq(cpu); 649 break; 650 case ARM_CPU_IRQ: 651 case ARM_CPU_FIQ: 652 if (level) { 653 cpu_interrupt(cs, mask[irq]); 654 } else { 655 cpu_reset_interrupt(cs, mask[irq]); 656 } 657 break; 658 default: 659 g_assert_not_reached(); 660 } 661 } 662 663 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 664 { 665 #ifdef CONFIG_KVM 666 ARMCPU *cpu = opaque; 667 CPUARMState *env = &cpu->env; 668 CPUState *cs = CPU(cpu); 669 uint32_t linestate_bit; 670 int irq_id; 671 672 switch (irq) { 673 case ARM_CPU_IRQ: 674 irq_id = KVM_ARM_IRQ_CPU_IRQ; 675 linestate_bit = CPU_INTERRUPT_HARD; 676 break; 677 case ARM_CPU_FIQ: 678 irq_id = KVM_ARM_IRQ_CPU_FIQ; 679 linestate_bit = CPU_INTERRUPT_FIQ; 680 break; 681 default: 682 g_assert_not_reached(); 683 } 684 685 if (level) { 686 env->irq_line_state |= linestate_bit; 687 } else { 688 env->irq_line_state &= ~linestate_bit; 689 } 690 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 691 #endif 692 } 693 694 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 695 { 696 ARMCPU *cpu = ARM_CPU(cs); 697 CPUARMState *env = &cpu->env; 698 699 cpu_synchronize_state(cs); 700 return arm_cpu_data_is_big_endian(env); 701 } 702 703 #endif 704 705 static int 706 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 707 { 708 return print_insn_arm(pc | 1, info); 709 } 710 711 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 712 { 713 ARMCPU *ac = ARM_CPU(cpu); 714 CPUARMState *env = &ac->env; 715 bool sctlr_b; 716 717 if (is_a64(env)) { 718 /* We might not be compiled with the A64 disassembler 719 * because it needs a C++ compiler. Leave print_insn 720 * unset in this case to use the caller default behaviour. 721 */ 722 #if defined(CONFIG_ARM_A64_DIS) 723 info->print_insn = print_insn_arm_a64; 724 #endif 725 info->cap_arch = CS_ARCH_ARM64; 726 info->cap_insn_unit = 4; 727 info->cap_insn_split = 4; 728 } else { 729 int cap_mode; 730 if (env->thumb) { 731 info->print_insn = print_insn_thumb1; 732 info->cap_insn_unit = 2; 733 info->cap_insn_split = 4; 734 cap_mode = CS_MODE_THUMB; 735 } else { 736 info->print_insn = print_insn_arm; 737 info->cap_insn_unit = 4; 738 info->cap_insn_split = 4; 739 cap_mode = CS_MODE_ARM; 740 } 741 if (arm_feature(env, ARM_FEATURE_V8)) { 742 cap_mode |= CS_MODE_V8; 743 } 744 if (arm_feature(env, ARM_FEATURE_M)) { 745 cap_mode |= CS_MODE_MCLASS; 746 } 747 info->cap_arch = CS_ARCH_ARM; 748 info->cap_mode = cap_mode; 749 } 750 751 sctlr_b = arm_sctlr_b(env); 752 if (bswap_code(sctlr_b)) { 753 #ifdef TARGET_WORDS_BIGENDIAN 754 info->endian = BFD_ENDIAN_LITTLE; 755 #else 756 info->endian = BFD_ENDIAN_BIG; 757 #endif 758 } 759 info->flags &= ~INSN_ARM_BE32; 760 #ifndef CONFIG_USER_ONLY 761 if (sctlr_b) { 762 info->flags |= INSN_ARM_BE32; 763 } 764 #endif 765 } 766 767 #ifdef TARGET_AARCH64 768 769 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 770 { 771 ARMCPU *cpu = ARM_CPU(cs); 772 CPUARMState *env = &cpu->env; 773 uint32_t psr = pstate_read(env); 774 int i; 775 int el = arm_current_el(env); 776 const char *ns_status; 777 778 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 779 for (i = 0; i < 32; i++) { 780 if (i == 31) { 781 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 782 } else { 783 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 784 (i + 2) % 3 ? " " : "\n"); 785 } 786 } 787 788 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 789 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 790 } else { 791 ns_status = ""; 792 } 793 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 794 psr, 795 psr & PSTATE_N ? 'N' : '-', 796 psr & PSTATE_Z ? 'Z' : '-', 797 psr & PSTATE_C ? 'C' : '-', 798 psr & PSTATE_V ? 'V' : '-', 799 ns_status, 800 el, 801 psr & PSTATE_SP ? 'h' : 't'); 802 803 if (cpu_isar_feature(aa64_bti, cpu)) { 804 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 805 } 806 if (!(flags & CPU_DUMP_FPU)) { 807 qemu_fprintf(f, "\n"); 808 return; 809 } 810 if (fp_exception_el(env, el) != 0) { 811 qemu_fprintf(f, " FPU disabled\n"); 812 return; 813 } 814 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 815 vfp_get_fpcr(env), vfp_get_fpsr(env)); 816 817 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { 818 int j, zcr_len = sve_zcr_len_for_el(env, el); 819 820 for (i = 0; i <= FFR_PRED_NUM; i++) { 821 bool eol; 822 if (i == FFR_PRED_NUM) { 823 qemu_fprintf(f, "FFR="); 824 /* It's last, so end the line. */ 825 eol = true; 826 } else { 827 qemu_fprintf(f, "P%02d=", i); 828 switch (zcr_len) { 829 case 0: 830 eol = i % 8 == 7; 831 break; 832 case 1: 833 eol = i % 6 == 5; 834 break; 835 case 2: 836 case 3: 837 eol = i % 3 == 2; 838 break; 839 default: 840 /* More than one quadword per predicate. */ 841 eol = true; 842 break; 843 } 844 } 845 for (j = zcr_len / 4; j >= 0; j--) { 846 int digits; 847 if (j * 4 + 4 <= zcr_len + 1) { 848 digits = 16; 849 } else { 850 digits = (zcr_len % 4 + 1) * 4; 851 } 852 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 853 env->vfp.pregs[i].p[j], 854 j ? ":" : eol ? "\n" : " "); 855 } 856 } 857 858 for (i = 0; i < 32; i++) { 859 if (zcr_len == 0) { 860 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 861 i, env->vfp.zregs[i].d[1], 862 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 863 } else if (zcr_len == 1) { 864 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 865 ":%016" PRIx64 ":%016" PRIx64 "\n", 866 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 867 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 868 } else { 869 for (j = zcr_len; j >= 0; j--) { 870 bool odd = (zcr_len - j) % 2 != 0; 871 if (j == zcr_len) { 872 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 873 } else if (!odd) { 874 if (j > 0) { 875 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 876 } else { 877 qemu_fprintf(f, " [%x]=", j); 878 } 879 } 880 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 881 env->vfp.zregs[i].d[j * 2 + 1], 882 env->vfp.zregs[i].d[j * 2], 883 odd || j == 0 ? "\n" : ":"); 884 } 885 } 886 } 887 } else { 888 for (i = 0; i < 32; i++) { 889 uint64_t *q = aa64_vfp_qreg(env, i); 890 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 891 i, q[1], q[0], (i & 1 ? "\n" : " ")); 892 } 893 } 894 } 895 896 #else 897 898 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 899 { 900 g_assert_not_reached(); 901 } 902 903 #endif 904 905 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 906 { 907 ARMCPU *cpu = ARM_CPU(cs); 908 CPUARMState *env = &cpu->env; 909 int i; 910 911 if (is_a64(env)) { 912 aarch64_cpu_dump_state(cs, f, flags); 913 return; 914 } 915 916 for (i = 0; i < 16; i++) { 917 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 918 if ((i % 4) == 3) { 919 qemu_fprintf(f, "\n"); 920 } else { 921 qemu_fprintf(f, " "); 922 } 923 } 924 925 if (arm_feature(env, ARM_FEATURE_M)) { 926 uint32_t xpsr = xpsr_read(env); 927 const char *mode; 928 const char *ns_status = ""; 929 930 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 931 ns_status = env->v7m.secure ? "S " : "NS "; 932 } 933 934 if (xpsr & XPSR_EXCP) { 935 mode = "handler"; 936 } else { 937 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 938 mode = "unpriv-thread"; 939 } else { 940 mode = "priv-thread"; 941 } 942 } 943 944 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 945 xpsr, 946 xpsr & XPSR_N ? 'N' : '-', 947 xpsr & XPSR_Z ? 'Z' : '-', 948 xpsr & XPSR_C ? 'C' : '-', 949 xpsr & XPSR_V ? 'V' : '-', 950 xpsr & XPSR_T ? 'T' : 'A', 951 ns_status, 952 mode); 953 } else { 954 uint32_t psr = cpsr_read(env); 955 const char *ns_status = ""; 956 957 if (arm_feature(env, ARM_FEATURE_EL3) && 958 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 959 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 960 } 961 962 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 963 psr, 964 psr & CPSR_N ? 'N' : '-', 965 psr & CPSR_Z ? 'Z' : '-', 966 psr & CPSR_C ? 'C' : '-', 967 psr & CPSR_V ? 'V' : '-', 968 psr & CPSR_T ? 'T' : 'A', 969 ns_status, 970 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 971 } 972 973 if (flags & CPU_DUMP_FPU) { 974 int numvfpregs = 0; 975 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 976 numvfpregs = 32; 977 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 978 numvfpregs = 16; 979 } 980 for (i = 0; i < numvfpregs; i++) { 981 uint64_t v = *aa32_vfp_dreg(env, i); 982 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 983 i * 2, (uint32_t)v, 984 i * 2 + 1, (uint32_t)(v >> 32), 985 i, v); 986 } 987 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 988 } 989 } 990 991 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 992 { 993 uint32_t Aff1 = idx / clustersz; 994 uint32_t Aff0 = idx % clustersz; 995 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 996 } 997 998 static void cpreg_hashtable_data_destroy(gpointer data) 999 { 1000 /* 1001 * Destroy function for cpu->cp_regs hashtable data entries. 1002 * We must free the name string because it was g_strdup()ed in 1003 * add_cpreg_to_hashtable(). It's OK to cast away the 'const' 1004 * from r->name because we know we definitely allocated it. 1005 */ 1006 ARMCPRegInfo *r = data; 1007 1008 g_free((void *)r->name); 1009 g_free(r); 1010 } 1011 1012 static void arm_cpu_initfn(Object *obj) 1013 { 1014 ARMCPU *cpu = ARM_CPU(obj); 1015 1016 cpu_set_cpustate_pointers(cpu); 1017 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 1018 g_free, cpreg_hashtable_data_destroy); 1019 1020 QLIST_INIT(&cpu->pre_el_change_hooks); 1021 QLIST_INIT(&cpu->el_change_hooks); 1022 1023 #ifndef CONFIG_USER_ONLY 1024 /* Our inbound IRQ and FIQ lines */ 1025 if (kvm_enabled()) { 1026 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1027 * the same interface as non-KVM CPUs. 1028 */ 1029 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1030 } else { 1031 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1032 } 1033 1034 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1035 ARRAY_SIZE(cpu->gt_timer_outputs)); 1036 1037 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1038 "gicv3-maintenance-interrupt", 1); 1039 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1040 "pmu-interrupt", 1); 1041 #endif 1042 1043 /* DTB consumers generally don't in fact care what the 'compatible' 1044 * string is, so always provide some string and trust that a hypothetical 1045 * picky DTB consumer will also provide a helpful error message. 1046 */ 1047 cpu->dtb_compatible = "qemu,unknown"; 1048 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 1049 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1050 1051 if (tcg_enabled()) { 1052 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 1053 } 1054 } 1055 1056 static Property arm_cpu_gt_cntfrq_property = 1057 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1058 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1059 1060 static Property arm_cpu_reset_cbar_property = 1061 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1062 1063 static Property arm_cpu_reset_hivecs_property = 1064 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1065 1066 static Property arm_cpu_rvbar_property = 1067 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 1068 1069 #ifndef CONFIG_USER_ONLY 1070 static Property arm_cpu_has_el2_property = 1071 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1072 1073 static Property arm_cpu_has_el3_property = 1074 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1075 #endif 1076 1077 static Property arm_cpu_cfgend_property = 1078 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1079 1080 static Property arm_cpu_has_vfp_property = 1081 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1082 1083 static Property arm_cpu_has_neon_property = 1084 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1085 1086 static Property arm_cpu_has_dsp_property = 1087 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1088 1089 static Property arm_cpu_has_mpu_property = 1090 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1091 1092 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1093 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1094 * the right value for that particular CPU type, and we don't want 1095 * to override that with an incorrect constant value. 1096 */ 1097 static Property arm_cpu_pmsav7_dregion_property = 1098 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1099 pmsav7_dregion, 1100 qdev_prop_uint32, uint32_t); 1101 1102 static bool arm_get_pmu(Object *obj, Error **errp) 1103 { 1104 ARMCPU *cpu = ARM_CPU(obj); 1105 1106 return cpu->has_pmu; 1107 } 1108 1109 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1110 { 1111 ARMCPU *cpu = ARM_CPU(obj); 1112 1113 if (value) { 1114 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1115 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1116 return; 1117 } 1118 set_feature(&cpu->env, ARM_FEATURE_PMU); 1119 } else { 1120 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1121 } 1122 cpu->has_pmu = value; 1123 } 1124 1125 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1126 { 1127 /* 1128 * The exact approach to calculating guest ticks is: 1129 * 1130 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1131 * NANOSECONDS_PER_SECOND); 1132 * 1133 * We don't do that. Rather we intentionally use integer division 1134 * truncation below and in the caller for the conversion of host monotonic 1135 * time to guest ticks to provide the exact inverse for the semantics of 1136 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1137 * it loses precision when representing frequencies where 1138 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1139 * provide an exact inverse leads to scheduling timers with negative 1140 * periods, which in turn leads to sticky behaviour in the guest. 1141 * 1142 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1143 * cannot become zero. 1144 */ 1145 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1146 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1147 } 1148 1149 void arm_cpu_post_init(Object *obj) 1150 { 1151 ARMCPU *cpu = ARM_CPU(obj); 1152 1153 /* M profile implies PMSA. We have to do this here rather than 1154 * in realize with the other feature-implication checks because 1155 * we look at the PMSA bit to see if we should add some properties. 1156 */ 1157 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1158 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1159 } 1160 1161 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1162 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1163 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1164 } 1165 1166 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1167 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1168 } 1169 1170 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1171 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property); 1172 } 1173 1174 #ifndef CONFIG_USER_ONLY 1175 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1176 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1177 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1178 */ 1179 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1180 1181 object_property_add_link(obj, "secure-memory", 1182 TYPE_MEMORY_REGION, 1183 (Object **)&cpu->secure_memory, 1184 qdev_prop_allow_set_link_before_realize, 1185 OBJ_PROP_LINK_STRONG); 1186 } 1187 1188 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1189 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1190 } 1191 #endif 1192 1193 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1194 cpu->has_pmu = true; 1195 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1196 } 1197 1198 /* 1199 * Allow user to turn off VFP and Neon support, but only for TCG -- 1200 * KVM does not currently allow us to lie to the guest about its 1201 * ID/feature registers, so the guest always sees what the host has. 1202 */ 1203 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 1204 ? cpu_isar_feature(aa64_fp_simd, cpu) 1205 : cpu_isar_feature(aa32_vfp, cpu)) { 1206 cpu->has_vfp = true; 1207 if (!kvm_enabled()) { 1208 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1209 } 1210 } 1211 1212 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1213 cpu->has_neon = true; 1214 if (!kvm_enabled()) { 1215 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1216 } 1217 } 1218 1219 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1220 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1221 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1222 } 1223 1224 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1225 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1226 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1227 qdev_property_add_static(DEVICE(obj), 1228 &arm_cpu_pmsav7_dregion_property); 1229 } 1230 } 1231 1232 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1233 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1234 qdev_prop_allow_set_link_before_realize, 1235 OBJ_PROP_LINK_STRONG); 1236 /* 1237 * M profile: initial value of the Secure VTOR. We can't just use 1238 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1239 * the property to be set after realize. 1240 */ 1241 object_property_add_uint32_ptr(obj, "init-svtor", 1242 &cpu->init_svtor, 1243 OBJ_PROP_FLAG_READWRITE); 1244 } 1245 1246 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1247 1248 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1249 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1250 } 1251 1252 if (kvm_enabled()) { 1253 kvm_arm_add_vcpu_properties(obj); 1254 } 1255 1256 #ifndef CONFIG_USER_ONLY 1257 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1258 cpu_isar_feature(aa64_mte, cpu)) { 1259 object_property_add_link(obj, "tag-memory", 1260 TYPE_MEMORY_REGION, 1261 (Object **)&cpu->tag_memory, 1262 qdev_prop_allow_set_link_before_realize, 1263 OBJ_PROP_LINK_STRONG); 1264 1265 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1266 object_property_add_link(obj, "secure-tag-memory", 1267 TYPE_MEMORY_REGION, 1268 (Object **)&cpu->secure_tag_memory, 1269 qdev_prop_allow_set_link_before_realize, 1270 OBJ_PROP_LINK_STRONG); 1271 } 1272 } 1273 #endif 1274 } 1275 1276 static void arm_cpu_finalizefn(Object *obj) 1277 { 1278 ARMCPU *cpu = ARM_CPU(obj); 1279 ARMELChangeHook *hook, *next; 1280 1281 g_hash_table_destroy(cpu->cp_regs); 1282 1283 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1284 QLIST_REMOVE(hook, node); 1285 g_free(hook); 1286 } 1287 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1288 QLIST_REMOVE(hook, node); 1289 g_free(hook); 1290 } 1291 #ifndef CONFIG_USER_ONLY 1292 if (cpu->pmu_timer) { 1293 timer_del(cpu->pmu_timer); 1294 timer_deinit(cpu->pmu_timer); 1295 timer_free(cpu->pmu_timer); 1296 } 1297 #endif 1298 } 1299 1300 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1301 { 1302 Error *local_err = NULL; 1303 1304 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1305 arm_cpu_sve_finalize(cpu, &local_err); 1306 if (local_err != NULL) { 1307 error_propagate(errp, local_err); 1308 return; 1309 } 1310 } 1311 } 1312 1313 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1314 { 1315 CPUState *cs = CPU(dev); 1316 ARMCPU *cpu = ARM_CPU(dev); 1317 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1318 CPUARMState *env = &cpu->env; 1319 int pagebits; 1320 Error *local_err = NULL; 1321 bool no_aa32 = false; 1322 1323 /* If we needed to query the host kernel for the CPU features 1324 * then it's possible that might have failed in the initfn, but 1325 * this is the first point where we can report it. 1326 */ 1327 if (cpu->host_cpu_probe_failed) { 1328 if (!kvm_enabled()) { 1329 error_setg(errp, "The 'host' CPU type can only be used with KVM"); 1330 } else { 1331 error_setg(errp, "Failed to retrieve host CPU features"); 1332 } 1333 return; 1334 } 1335 1336 #ifndef CONFIG_USER_ONLY 1337 /* The NVIC and M-profile CPU are two halves of a single piece of 1338 * hardware; trying to use one without the other is a command line 1339 * error and will result in segfaults if not caught here. 1340 */ 1341 if (arm_feature(env, ARM_FEATURE_M)) { 1342 if (!env->nvic) { 1343 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1344 return; 1345 } 1346 } else { 1347 if (env->nvic) { 1348 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1349 return; 1350 } 1351 } 1352 1353 { 1354 uint64_t scale; 1355 1356 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1357 if (!cpu->gt_cntfrq_hz) { 1358 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1359 cpu->gt_cntfrq_hz); 1360 return; 1361 } 1362 scale = gt_cntfrq_period_ns(cpu); 1363 } else { 1364 scale = GTIMER_SCALE; 1365 } 1366 1367 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1368 arm_gt_ptimer_cb, cpu); 1369 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1370 arm_gt_vtimer_cb, cpu); 1371 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1372 arm_gt_htimer_cb, cpu); 1373 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1374 arm_gt_stimer_cb, cpu); 1375 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1376 arm_gt_hvtimer_cb, cpu); 1377 } 1378 #endif 1379 1380 cpu_exec_realizefn(cs, &local_err); 1381 if (local_err != NULL) { 1382 error_propagate(errp, local_err); 1383 return; 1384 } 1385 1386 arm_cpu_finalize_features(cpu, &local_err); 1387 if (local_err != NULL) { 1388 error_propagate(errp, local_err); 1389 return; 1390 } 1391 1392 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1393 cpu->has_vfp != cpu->has_neon) { 1394 /* 1395 * This is an architectural requirement for AArch64; AArch32 is 1396 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1397 */ 1398 error_setg(errp, 1399 "AArch64 CPUs must have both VFP and Neon or neither"); 1400 return; 1401 } 1402 1403 if (!cpu->has_vfp) { 1404 uint64_t t; 1405 uint32_t u; 1406 1407 t = cpu->isar.id_aa64isar1; 1408 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1409 cpu->isar.id_aa64isar1 = t; 1410 1411 t = cpu->isar.id_aa64pfr0; 1412 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1413 cpu->isar.id_aa64pfr0 = t; 1414 1415 u = cpu->isar.id_isar6; 1416 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1417 cpu->isar.id_isar6 = u; 1418 1419 u = cpu->isar.mvfr0; 1420 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1421 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1422 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1423 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1424 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1425 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1426 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1427 cpu->isar.mvfr0 = u; 1428 1429 u = cpu->isar.mvfr1; 1430 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1431 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1432 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1433 cpu->isar.mvfr1 = u; 1434 1435 u = cpu->isar.mvfr2; 1436 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1437 cpu->isar.mvfr2 = u; 1438 } 1439 1440 if (!cpu->has_neon) { 1441 uint64_t t; 1442 uint32_t u; 1443 1444 unset_feature(env, ARM_FEATURE_NEON); 1445 1446 t = cpu->isar.id_aa64isar0; 1447 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1448 cpu->isar.id_aa64isar0 = t; 1449 1450 t = cpu->isar.id_aa64isar1; 1451 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1452 cpu->isar.id_aa64isar1 = t; 1453 1454 t = cpu->isar.id_aa64pfr0; 1455 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1456 cpu->isar.id_aa64pfr0 = t; 1457 1458 u = cpu->isar.id_isar5; 1459 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1460 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1461 cpu->isar.id_isar5 = u; 1462 1463 u = cpu->isar.id_isar6; 1464 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1465 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1466 cpu->isar.id_isar6 = u; 1467 1468 u = cpu->isar.mvfr1; 1469 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1470 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1471 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1472 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1473 cpu->isar.mvfr1 = u; 1474 1475 u = cpu->isar.mvfr2; 1476 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1477 cpu->isar.mvfr2 = u; 1478 } 1479 1480 if (!cpu->has_neon && !cpu->has_vfp) { 1481 uint64_t t; 1482 uint32_t u; 1483 1484 t = cpu->isar.id_aa64isar0; 1485 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1486 cpu->isar.id_aa64isar0 = t; 1487 1488 t = cpu->isar.id_aa64isar1; 1489 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1490 cpu->isar.id_aa64isar1 = t; 1491 1492 u = cpu->isar.mvfr0; 1493 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1494 cpu->isar.mvfr0 = u; 1495 1496 /* Despite the name, this field covers both VFP and Neon */ 1497 u = cpu->isar.mvfr1; 1498 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1499 cpu->isar.mvfr1 = u; 1500 } 1501 1502 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1503 uint32_t u; 1504 1505 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1506 1507 u = cpu->isar.id_isar1; 1508 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1509 cpu->isar.id_isar1 = u; 1510 1511 u = cpu->isar.id_isar2; 1512 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1513 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1514 cpu->isar.id_isar2 = u; 1515 1516 u = cpu->isar.id_isar3; 1517 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1518 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1519 cpu->isar.id_isar3 = u; 1520 } 1521 1522 /* Some features automatically imply others: */ 1523 if (arm_feature(env, ARM_FEATURE_V8)) { 1524 if (arm_feature(env, ARM_FEATURE_M)) { 1525 set_feature(env, ARM_FEATURE_V7); 1526 } else { 1527 set_feature(env, ARM_FEATURE_V7VE); 1528 } 1529 } 1530 1531 /* 1532 * There exist AArch64 cpus without AArch32 support. When KVM 1533 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1534 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1535 * As a general principle, we also do not make ID register 1536 * consistency checks anywhere unless using TCG, because only 1537 * for TCG would a consistency-check failure be a QEMU bug. 1538 */ 1539 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1540 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1541 } 1542 1543 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1544 /* v7 Virtualization Extensions. In real hardware this implies 1545 * EL2 and also the presence of the Security Extensions. 1546 * For QEMU, for backwards-compatibility we implement some 1547 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1548 * include the various other features that V7VE implies. 1549 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1550 * Security Extensions is ARM_FEATURE_EL3. 1551 */ 1552 assert(!tcg_enabled() || no_aa32 || 1553 cpu_isar_feature(aa32_arm_div, cpu)); 1554 set_feature(env, ARM_FEATURE_LPAE); 1555 set_feature(env, ARM_FEATURE_V7); 1556 } 1557 if (arm_feature(env, ARM_FEATURE_V7)) { 1558 set_feature(env, ARM_FEATURE_VAPA); 1559 set_feature(env, ARM_FEATURE_THUMB2); 1560 set_feature(env, ARM_FEATURE_MPIDR); 1561 if (!arm_feature(env, ARM_FEATURE_M)) { 1562 set_feature(env, ARM_FEATURE_V6K); 1563 } else { 1564 set_feature(env, ARM_FEATURE_V6); 1565 } 1566 1567 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1568 * non-EL3 configs. This is needed by some legacy boards. 1569 */ 1570 set_feature(env, ARM_FEATURE_VBAR); 1571 } 1572 if (arm_feature(env, ARM_FEATURE_V6K)) { 1573 set_feature(env, ARM_FEATURE_V6); 1574 set_feature(env, ARM_FEATURE_MVFR); 1575 } 1576 if (arm_feature(env, ARM_FEATURE_V6)) { 1577 set_feature(env, ARM_FEATURE_V5); 1578 if (!arm_feature(env, ARM_FEATURE_M)) { 1579 assert(!tcg_enabled() || no_aa32 || 1580 cpu_isar_feature(aa32_jazelle, cpu)); 1581 set_feature(env, ARM_FEATURE_AUXCR); 1582 } 1583 } 1584 if (arm_feature(env, ARM_FEATURE_V5)) { 1585 set_feature(env, ARM_FEATURE_V4T); 1586 } 1587 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1588 set_feature(env, ARM_FEATURE_V7MP); 1589 set_feature(env, ARM_FEATURE_PXN); 1590 } 1591 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1592 set_feature(env, ARM_FEATURE_CBAR); 1593 } 1594 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1595 !arm_feature(env, ARM_FEATURE_M)) { 1596 set_feature(env, ARM_FEATURE_THUMB_DSP); 1597 } 1598 1599 /* 1600 * We rely on no XScale CPU having VFP so we can use the same bits in the 1601 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1602 */ 1603 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1604 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1605 !arm_feature(env, ARM_FEATURE_XSCALE)); 1606 1607 if (arm_feature(env, ARM_FEATURE_V7) && 1608 !arm_feature(env, ARM_FEATURE_M) && 1609 !arm_feature(env, ARM_FEATURE_PMSA)) { 1610 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1611 * can use 4K pages. 1612 */ 1613 pagebits = 12; 1614 } else { 1615 /* For CPUs which might have tiny 1K pages, or which have an 1616 * MPU and might have small region sizes, stick with 1K pages. 1617 */ 1618 pagebits = 10; 1619 } 1620 if (!set_preferred_target_page_bits(pagebits)) { 1621 /* This can only ever happen for hotplugging a CPU, or if 1622 * the board code incorrectly creates a CPU which it has 1623 * promised via minimum_page_size that it will not. 1624 */ 1625 error_setg(errp, "This CPU requires a smaller page size than the " 1626 "system is using"); 1627 return; 1628 } 1629 1630 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1631 * We don't support setting cluster ID ([16..23]) (known as Aff2 1632 * in later ARM ARM versions), or any of the higher affinity level fields, 1633 * so these bits always RAZ. 1634 */ 1635 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1636 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1637 ARM_DEFAULT_CPUS_PER_CLUSTER); 1638 } 1639 1640 if (cpu->reset_hivecs) { 1641 cpu->reset_sctlr |= (1 << 13); 1642 } 1643 1644 if (cpu->cfgend) { 1645 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1646 cpu->reset_sctlr |= SCTLR_EE; 1647 } else { 1648 cpu->reset_sctlr |= SCTLR_B; 1649 } 1650 } 1651 1652 if (!cpu->has_el3) { 1653 /* If the has_el3 CPU property is disabled then we need to disable the 1654 * feature. 1655 */ 1656 unset_feature(env, ARM_FEATURE_EL3); 1657 1658 /* Disable the security extension feature bits in the processor feature 1659 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 1660 */ 1661 cpu->id_pfr1 &= ~0xf0; 1662 cpu->isar.id_aa64pfr0 &= ~0xf000; 1663 } 1664 1665 if (!cpu->has_el2) { 1666 unset_feature(env, ARM_FEATURE_EL2); 1667 } 1668 1669 if (!cpu->has_pmu) { 1670 unset_feature(env, ARM_FEATURE_PMU); 1671 } 1672 if (arm_feature(env, ARM_FEATURE_PMU)) { 1673 pmu_init(cpu); 1674 1675 if (!kvm_enabled()) { 1676 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1677 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1678 } 1679 1680 #ifndef CONFIG_USER_ONLY 1681 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1682 cpu); 1683 #endif 1684 } else { 1685 cpu->isar.id_aa64dfr0 = 1686 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 1687 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 1688 cpu->pmceid0 = 0; 1689 cpu->pmceid1 = 0; 1690 } 1691 1692 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1693 /* Disable the hypervisor feature bits in the processor feature 1694 * registers if we don't have EL2. These are id_pfr1[15:12] and 1695 * id_aa64pfr0_el1[11:8]. 1696 */ 1697 cpu->isar.id_aa64pfr0 &= ~0xf00; 1698 cpu->id_pfr1 &= ~0xf000; 1699 } 1700 1701 #ifndef CONFIG_USER_ONLY 1702 if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { 1703 /* 1704 * Disable the MTE feature bits if we do not have tag-memory 1705 * provided by the machine. 1706 */ 1707 cpu->isar.id_aa64pfr1 = 1708 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 1709 } 1710 #endif 1711 1712 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1713 * to false or by setting pmsav7-dregion to 0. 1714 */ 1715 if (!cpu->has_mpu) { 1716 cpu->pmsav7_dregion = 0; 1717 } 1718 if (cpu->pmsav7_dregion == 0) { 1719 cpu->has_mpu = false; 1720 } 1721 1722 if (arm_feature(env, ARM_FEATURE_PMSA) && 1723 arm_feature(env, ARM_FEATURE_V7)) { 1724 uint32_t nr = cpu->pmsav7_dregion; 1725 1726 if (nr > 0xff) { 1727 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1728 return; 1729 } 1730 1731 if (nr) { 1732 if (arm_feature(env, ARM_FEATURE_V8)) { 1733 /* PMSAv8 */ 1734 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1735 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1736 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1737 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1738 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1739 } 1740 } else { 1741 env->pmsav7.drbar = g_new0(uint32_t, nr); 1742 env->pmsav7.drsr = g_new0(uint32_t, nr); 1743 env->pmsav7.dracr = g_new0(uint32_t, nr); 1744 } 1745 } 1746 } 1747 1748 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1749 uint32_t nr = cpu->sau_sregion; 1750 1751 if (nr > 0xff) { 1752 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1753 return; 1754 } 1755 1756 if (nr) { 1757 env->sau.rbar = g_new0(uint32_t, nr); 1758 env->sau.rlar = g_new0(uint32_t, nr); 1759 } 1760 } 1761 1762 if (arm_feature(env, ARM_FEATURE_EL3)) { 1763 set_feature(env, ARM_FEATURE_VBAR); 1764 } 1765 1766 register_cp_regs_for_features(cpu); 1767 arm_cpu_register_gdb_regs_for_features(cpu); 1768 1769 init_cpreg_list(cpu); 1770 1771 #ifndef CONFIG_USER_ONLY 1772 MachineState *ms = MACHINE(qdev_get_machine()); 1773 unsigned int smp_cpus = ms->smp.cpus; 1774 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 1775 1776 /* 1777 * We must set cs->num_ases to the final value before 1778 * the first call to cpu_address_space_init. 1779 */ 1780 if (cpu->tag_memory != NULL) { 1781 cs->num_ases = 3 + has_secure; 1782 } else { 1783 cs->num_ases = 1 + has_secure; 1784 } 1785 1786 if (has_secure) { 1787 if (!cpu->secure_memory) { 1788 cpu->secure_memory = cs->memory; 1789 } 1790 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1791 cpu->secure_memory); 1792 } 1793 1794 if (cpu->tag_memory != NULL) { 1795 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 1796 cpu->tag_memory); 1797 if (has_secure) { 1798 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 1799 cpu->secure_tag_memory); 1800 } 1801 } 1802 1803 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1804 1805 /* No core_count specified, default to smp_cpus. */ 1806 if (cpu->core_count == -1) { 1807 cpu->core_count = smp_cpus; 1808 } 1809 #endif 1810 1811 if (tcg_enabled()) { 1812 int dcz_blocklen = 4 << cpu->dcz_blocksize; 1813 1814 /* 1815 * We only support DCZ blocklen that fits on one page. 1816 * 1817 * Architectually this is always true. However TARGET_PAGE_SIZE 1818 * is variable and, for compatibility with -machine virt-2.7, 1819 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 1820 * But even then, while the largest architectural DCZ blocklen 1821 * is 2KiB, no cpu actually uses such a large blocklen. 1822 */ 1823 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 1824 1825 /* 1826 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 1827 * both nibbles of each byte storing tag data may be written at once. 1828 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 1829 */ 1830 if (cpu_isar_feature(aa64_mte, cpu)) { 1831 assert(dcz_blocklen >= 2 * TAG_GRANULE); 1832 } 1833 } 1834 1835 qemu_init_vcpu(cs); 1836 cpu_reset(cs); 1837 1838 acc->parent_realize(dev, errp); 1839 } 1840 1841 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1842 { 1843 ObjectClass *oc; 1844 char *typename; 1845 char **cpuname; 1846 const char *cpunamestr; 1847 1848 cpuname = g_strsplit(cpu_model, ",", 1); 1849 cpunamestr = cpuname[0]; 1850 #ifdef CONFIG_USER_ONLY 1851 /* For backwards compatibility usermode emulation allows "-cpu any", 1852 * which has the same semantics as "-cpu max". 1853 */ 1854 if (!strcmp(cpunamestr, "any")) { 1855 cpunamestr = "max"; 1856 } 1857 #endif 1858 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 1859 oc = object_class_by_name(typename); 1860 g_strfreev(cpuname); 1861 g_free(typename); 1862 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 1863 object_class_is_abstract(oc)) { 1864 return NULL; 1865 } 1866 return oc; 1867 } 1868 1869 /* CPU models. These are not needed for the AArch64 linux-user build. */ 1870 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1871 1872 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1873 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1874 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1875 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1876 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1877 REGINFO_SENTINEL 1878 }; 1879 1880 static void cortex_a8_initfn(Object *obj) 1881 { 1882 ARMCPU *cpu = ARM_CPU(obj); 1883 1884 cpu->dtb_compatible = "arm,cortex-a8"; 1885 set_feature(&cpu->env, ARM_FEATURE_V7); 1886 set_feature(&cpu->env, ARM_FEATURE_NEON); 1887 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1888 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1889 set_feature(&cpu->env, ARM_FEATURE_EL3); 1890 cpu->midr = 0x410fc080; 1891 cpu->reset_fpsid = 0x410330c0; 1892 cpu->isar.mvfr0 = 0x11110222; 1893 cpu->isar.mvfr1 = 0x00011111; 1894 cpu->ctr = 0x82048004; 1895 cpu->reset_sctlr = 0x00c50078; 1896 cpu->id_pfr0 = 0x1031; 1897 cpu->id_pfr1 = 0x11; 1898 cpu->isar.id_dfr0 = 0x400; 1899 cpu->id_afr0 = 0; 1900 cpu->isar.id_mmfr0 = 0x31100003; 1901 cpu->isar.id_mmfr1 = 0x20000000; 1902 cpu->isar.id_mmfr2 = 0x01202000; 1903 cpu->isar.id_mmfr3 = 0x11; 1904 cpu->isar.id_isar0 = 0x00101111; 1905 cpu->isar.id_isar1 = 0x12112111; 1906 cpu->isar.id_isar2 = 0x21232031; 1907 cpu->isar.id_isar3 = 0x11112131; 1908 cpu->isar.id_isar4 = 0x00111142; 1909 cpu->isar.dbgdidr = 0x15141000; 1910 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1911 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1912 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1913 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1914 cpu->reset_auxcr = 2; 1915 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1916 } 1917 1918 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1919 /* power_control should be set to maximum latency. Again, 1920 * default to 0 and set by private hook 1921 */ 1922 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1923 .access = PL1_RW, .resetvalue = 0, 1924 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1925 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1926 .access = PL1_RW, .resetvalue = 0, 1927 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1928 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1929 .access = PL1_RW, .resetvalue = 0, 1930 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1931 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1932 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1933 /* TLB lockdown control */ 1934 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1935 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1936 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1937 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1938 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1939 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1940 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1941 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1942 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1943 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1944 REGINFO_SENTINEL 1945 }; 1946 1947 static void cortex_a9_initfn(Object *obj) 1948 { 1949 ARMCPU *cpu = ARM_CPU(obj); 1950 1951 cpu->dtb_compatible = "arm,cortex-a9"; 1952 set_feature(&cpu->env, ARM_FEATURE_V7); 1953 set_feature(&cpu->env, ARM_FEATURE_NEON); 1954 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1955 set_feature(&cpu->env, ARM_FEATURE_EL3); 1956 /* Note that A9 supports the MP extensions even for 1957 * A9UP and single-core A9MP (which are both different 1958 * and valid configurations; we don't model A9UP). 1959 */ 1960 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1961 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1962 cpu->midr = 0x410fc090; 1963 cpu->reset_fpsid = 0x41033090; 1964 cpu->isar.mvfr0 = 0x11110222; 1965 cpu->isar.mvfr1 = 0x01111111; 1966 cpu->ctr = 0x80038003; 1967 cpu->reset_sctlr = 0x00c50078; 1968 cpu->id_pfr0 = 0x1031; 1969 cpu->id_pfr1 = 0x11; 1970 cpu->isar.id_dfr0 = 0x000; 1971 cpu->id_afr0 = 0; 1972 cpu->isar.id_mmfr0 = 0x00100103; 1973 cpu->isar.id_mmfr1 = 0x20000000; 1974 cpu->isar.id_mmfr2 = 0x01230000; 1975 cpu->isar.id_mmfr3 = 0x00002111; 1976 cpu->isar.id_isar0 = 0x00101111; 1977 cpu->isar.id_isar1 = 0x13112111; 1978 cpu->isar.id_isar2 = 0x21232041; 1979 cpu->isar.id_isar3 = 0x11112131; 1980 cpu->isar.id_isar4 = 0x00111142; 1981 cpu->isar.dbgdidr = 0x35141000; 1982 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1983 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1984 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1985 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1986 } 1987 1988 #ifndef CONFIG_USER_ONLY 1989 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1990 { 1991 MachineState *ms = MACHINE(qdev_get_machine()); 1992 1993 /* Linux wants the number of processors from here. 1994 * Might as well set the interrupt-controller bit too. 1995 */ 1996 return ((ms->smp.cpus - 1) << 24) | (1 << 23); 1997 } 1998 #endif 1999 2000 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 2001 #ifndef CONFIG_USER_ONLY 2002 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 2003 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 2004 .writefn = arm_cp_write_ignore, }, 2005 #endif 2006 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 2007 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 2008 REGINFO_SENTINEL 2009 }; 2010 2011 static void cortex_a7_initfn(Object *obj) 2012 { 2013 ARMCPU *cpu = ARM_CPU(obj); 2014 2015 cpu->dtb_compatible = "arm,cortex-a7"; 2016 set_feature(&cpu->env, ARM_FEATURE_V7VE); 2017 set_feature(&cpu->env, ARM_FEATURE_NEON); 2018 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2019 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 2020 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2021 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 2022 set_feature(&cpu->env, ARM_FEATURE_EL2); 2023 set_feature(&cpu->env, ARM_FEATURE_EL3); 2024 set_feature(&cpu->env, ARM_FEATURE_PMU); 2025 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 2026 cpu->midr = 0x410fc075; 2027 cpu->reset_fpsid = 0x41023075; 2028 cpu->isar.mvfr0 = 0x10110222; 2029 cpu->isar.mvfr1 = 0x11111111; 2030 cpu->ctr = 0x84448003; 2031 cpu->reset_sctlr = 0x00c50078; 2032 cpu->id_pfr0 = 0x00001131; 2033 cpu->id_pfr1 = 0x00011011; 2034 cpu->isar.id_dfr0 = 0x02010555; 2035 cpu->id_afr0 = 0x00000000; 2036 cpu->isar.id_mmfr0 = 0x10101105; 2037 cpu->isar.id_mmfr1 = 0x40000000; 2038 cpu->isar.id_mmfr2 = 0x01240000; 2039 cpu->isar.id_mmfr3 = 0x02102211; 2040 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but 2041 * table 4-41 gives 0x02101110, which includes the arm div insns. 2042 */ 2043 cpu->isar.id_isar0 = 0x02101110; 2044 cpu->isar.id_isar1 = 0x13112111; 2045 cpu->isar.id_isar2 = 0x21232041; 2046 cpu->isar.id_isar3 = 0x11112131; 2047 cpu->isar.id_isar4 = 0x10011142; 2048 cpu->isar.dbgdidr = 0x3515f005; 2049 cpu->clidr = 0x0a200023; 2050 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 2051 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 2052 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 2053 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 2054 } 2055 2056 static void cortex_a15_initfn(Object *obj) 2057 { 2058 ARMCPU *cpu = ARM_CPU(obj); 2059 2060 cpu->dtb_compatible = "arm,cortex-a15"; 2061 set_feature(&cpu->env, ARM_FEATURE_V7VE); 2062 set_feature(&cpu->env, ARM_FEATURE_NEON); 2063 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2064 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 2065 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2066 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 2067 set_feature(&cpu->env, ARM_FEATURE_EL2); 2068 set_feature(&cpu->env, ARM_FEATURE_EL3); 2069 set_feature(&cpu->env, ARM_FEATURE_PMU); 2070 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 2071 cpu->midr = 0x412fc0f1; 2072 cpu->reset_fpsid = 0x410430f0; 2073 cpu->isar.mvfr0 = 0x10110222; 2074 cpu->isar.mvfr1 = 0x11111111; 2075 cpu->ctr = 0x8444c004; 2076 cpu->reset_sctlr = 0x00c50078; 2077 cpu->id_pfr0 = 0x00001131; 2078 cpu->id_pfr1 = 0x00011011; 2079 cpu->isar.id_dfr0 = 0x02010555; 2080 cpu->id_afr0 = 0x00000000; 2081 cpu->isar.id_mmfr0 = 0x10201105; 2082 cpu->isar.id_mmfr1 = 0x20000000; 2083 cpu->isar.id_mmfr2 = 0x01240000; 2084 cpu->isar.id_mmfr3 = 0x02102211; 2085 cpu->isar.id_isar0 = 0x02101110; 2086 cpu->isar.id_isar1 = 0x13112111; 2087 cpu->isar.id_isar2 = 0x21232041; 2088 cpu->isar.id_isar3 = 0x11112131; 2089 cpu->isar.id_isar4 = 0x10011142; 2090 cpu->isar.dbgdidr = 0x3515f021; 2091 cpu->clidr = 0x0a200023; 2092 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 2093 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 2094 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 2095 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 2096 } 2097 2098 #ifndef TARGET_AARCH64 2099 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 2100 * otherwise, a CPU with as many features enabled as our emulation supports. 2101 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; 2102 * this only needs to handle 32 bits. 2103 */ 2104 static void arm_max_initfn(Object *obj) 2105 { 2106 ARMCPU *cpu = ARM_CPU(obj); 2107 2108 if (kvm_enabled()) { 2109 kvm_arm_set_cpu_features_from_host(cpu); 2110 } else { 2111 cortex_a15_initfn(obj); 2112 2113 /* old-style VFP short-vector support */ 2114 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 2115 2116 #ifdef CONFIG_USER_ONLY 2117 /* We don't set these in system emulation mode for the moment, 2118 * since we don't correctly set (all of) the ID registers to 2119 * advertise them. 2120 */ 2121 set_feature(&cpu->env, ARM_FEATURE_V8); 2122 { 2123 uint32_t t; 2124 2125 t = cpu->isar.id_isar5; 2126 t = FIELD_DP32(t, ID_ISAR5, AES, 2); 2127 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); 2128 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); 2129 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); 2130 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); 2131 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); 2132 cpu->isar.id_isar5 = t; 2133 2134 t = cpu->isar.id_isar6; 2135 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); 2136 t = FIELD_DP32(t, ID_ISAR6, DP, 1); 2137 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); 2138 t = FIELD_DP32(t, ID_ISAR6, SB, 1); 2139 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); 2140 cpu->isar.id_isar6 = t; 2141 2142 t = cpu->isar.mvfr1; 2143 t = FIELD_DP32(t, MVFR1, FPHP, 2); /* v8.0 FP support */ 2144 cpu->isar.mvfr1 = t; 2145 2146 t = cpu->isar.mvfr2; 2147 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ 2148 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ 2149 cpu->isar.mvfr2 = t; 2150 2151 t = cpu->isar.id_mmfr3; 2152 t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ 2153 cpu->isar.id_mmfr3 = t; 2154 2155 t = cpu->isar.id_mmfr4; 2156 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ 2157 t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ 2158 t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ 2159 t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ 2160 cpu->isar.id_mmfr4 = t; 2161 } 2162 #endif 2163 } 2164 } 2165 #endif 2166 2167 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 2168 2169 static const ARMCPUInfo arm_cpus[] = { 2170 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 2171 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 2172 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 2173 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 2174 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 2175 #ifndef TARGET_AARCH64 2176 { .name = "max", .initfn = arm_max_initfn }, 2177 #endif 2178 #ifdef CONFIG_USER_ONLY 2179 { .name = "any", .initfn = arm_max_initfn }, 2180 #endif 2181 #endif 2182 }; 2183 2184 static Property arm_cpu_properties[] = { 2185 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 2186 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 2187 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2188 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2189 mp_affinity, ARM64_AFFINITY_INVALID), 2190 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2191 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2192 DEFINE_PROP_END_OF_LIST() 2193 }; 2194 2195 static gchar *arm_gdb_arch_name(CPUState *cs) 2196 { 2197 ARMCPU *cpu = ARM_CPU(cs); 2198 CPUARMState *env = &cpu->env; 2199 2200 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2201 return g_strdup("iwmmxt"); 2202 } 2203 return g_strdup("arm"); 2204 } 2205 2206 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2207 { 2208 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2209 CPUClass *cc = CPU_CLASS(acc); 2210 DeviceClass *dc = DEVICE_CLASS(oc); 2211 2212 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2213 &acc->parent_realize); 2214 2215 device_class_set_props(dc, arm_cpu_properties); 2216 device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); 2217 2218 cc->class_by_name = arm_cpu_class_by_name; 2219 cc->has_work = arm_cpu_has_work; 2220 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 2221 cc->dump_state = arm_cpu_dump_state; 2222 cc->set_pc = arm_cpu_set_pc; 2223 cc->synchronize_from_tb = arm_cpu_synchronize_from_tb; 2224 cc->gdb_read_register = arm_cpu_gdb_read_register; 2225 cc->gdb_write_register = arm_cpu_gdb_write_register; 2226 #ifndef CONFIG_USER_ONLY 2227 cc->do_interrupt = arm_cpu_do_interrupt; 2228 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 2229 cc->asidx_from_attrs = arm_asidx_from_attrs; 2230 cc->vmsd = &vmstate_arm_cpu; 2231 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 2232 cc->write_elf64_note = arm_cpu_write_elf64_note; 2233 cc->write_elf32_note = arm_cpu_write_elf32_note; 2234 #endif 2235 cc->gdb_num_core_regs = 26; 2236 cc->gdb_core_xml_file = "arm-core.xml"; 2237 cc->gdb_arch_name = arm_gdb_arch_name; 2238 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2239 cc->gdb_stop_before_watchpoint = true; 2240 cc->disas_set_info = arm_disas_set_info; 2241 #ifdef CONFIG_TCG 2242 cc->tcg_initialize = arm_translate_init; 2243 cc->tlb_fill = arm_cpu_tlb_fill; 2244 cc->debug_excp_handler = arm_debug_excp_handler; 2245 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 2246 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 2247 #if !defined(CONFIG_USER_ONLY) 2248 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 2249 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 2250 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 2251 #endif 2252 } 2253 2254 #ifdef CONFIG_KVM 2255 static void arm_host_initfn(Object *obj) 2256 { 2257 ARMCPU *cpu = ARM_CPU(obj); 2258 2259 kvm_arm_set_cpu_features_from_host(cpu); 2260 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 2261 aarch64_add_sve_properties(obj); 2262 } 2263 arm_cpu_post_init(obj); 2264 } 2265 2266 static const TypeInfo host_arm_cpu_type_info = { 2267 .name = TYPE_ARM_HOST_CPU, 2268 #ifdef TARGET_AARCH64 2269 .parent = TYPE_AARCH64_CPU, 2270 #else 2271 .parent = TYPE_ARM_CPU, 2272 #endif 2273 .instance_init = arm_host_initfn, 2274 }; 2275 2276 #endif 2277 2278 static void arm_cpu_instance_init(Object *obj) 2279 { 2280 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2281 2282 acc->info->initfn(obj); 2283 arm_cpu_post_init(obj); 2284 } 2285 2286 static void cpu_register_class_init(ObjectClass *oc, void *data) 2287 { 2288 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2289 2290 acc->info = data; 2291 } 2292 2293 void arm_cpu_register(const ARMCPUInfo *info) 2294 { 2295 TypeInfo type_info = { 2296 .parent = TYPE_ARM_CPU, 2297 .instance_size = sizeof(ARMCPU), 2298 .instance_init = arm_cpu_instance_init, 2299 .class_size = sizeof(ARMCPUClass), 2300 .class_init = info->class_init ?: cpu_register_class_init, 2301 .class_data = (void *)info, 2302 }; 2303 2304 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2305 type_register(&type_info); 2306 g_free((void *)type_info.name); 2307 } 2308 2309 static const TypeInfo arm_cpu_type_info = { 2310 .name = TYPE_ARM_CPU, 2311 .parent = TYPE_CPU, 2312 .instance_size = sizeof(ARMCPU), 2313 .instance_init = arm_cpu_initfn, 2314 .instance_finalize = arm_cpu_finalizefn, 2315 .abstract = true, 2316 .class_size = sizeof(ARMCPUClass), 2317 .class_init = arm_cpu_class_init, 2318 }; 2319 2320 static const TypeInfo idau_interface_type_info = { 2321 .name = TYPE_IDAU_INTERFACE, 2322 .parent = TYPE_INTERFACE, 2323 .class_size = sizeof(IDAUInterfaceClass), 2324 }; 2325 2326 static void arm_cpu_register_types(void) 2327 { 2328 const size_t cpu_count = ARRAY_SIZE(arm_cpus); 2329 2330 type_register_static(&arm_cpu_type_info); 2331 2332 #ifdef CONFIG_KVM 2333 type_register_static(&host_arm_cpu_type_info); 2334 #endif 2335 2336 if (cpu_count) { 2337 size_t i; 2338 2339 type_register_static(&idau_interface_type_info); 2340 for (i = 0; i < cpu_count; ++i) { 2341 arm_cpu_register(&arm_cpus[i]); 2342 } 2343 } 2344 } 2345 2346 type_init(arm_cpu_register_types) 2347