1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu-common.h" 24 #include "target/arm/idau.h" 25 #include "qemu/module.h" 26 #include "qapi/error.h" 27 #include "qapi/visitor.h" 28 #include "cpu.h" 29 #include "internals.h" 30 #include "exec/exec-all.h" 31 #include "hw/qdev-properties.h" 32 #if !defined(CONFIG_USER_ONLY) 33 #include "hw/loader.h" 34 #include "hw/boards.h" 35 #endif 36 #include "sysemu/sysemu.h" 37 #include "sysemu/tcg.h" 38 #include "sysemu/hw_accel.h" 39 #include "kvm_arm.h" 40 #include "disas/capstone.h" 41 #include "fpu/softfloat.h" 42 43 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 44 { 45 ARMCPU *cpu = ARM_CPU(cs); 46 CPUARMState *env = &cpu->env; 47 48 if (is_a64(env)) { 49 env->pc = value; 50 env->thumb = 0; 51 } else { 52 env->regs[15] = value & ~1; 53 env->thumb = value & 1; 54 } 55 } 56 57 static void arm_cpu_synchronize_from_tb(CPUState *cs, 58 const TranslationBlock *tb) 59 { 60 ARMCPU *cpu = ARM_CPU(cs); 61 CPUARMState *env = &cpu->env; 62 63 /* 64 * It's OK to look at env for the current mode here, because it's 65 * never possible for an AArch64 TB to chain to an AArch32 TB. 66 */ 67 if (is_a64(env)) { 68 env->pc = tb->pc; 69 } else { 70 env->regs[15] = tb->pc; 71 } 72 } 73 74 static bool arm_cpu_has_work(CPUState *cs) 75 { 76 ARMCPU *cpu = ARM_CPU(cs); 77 78 return (cpu->power_state != PSCI_OFF) 79 && cs->interrupt_request & 80 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 81 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 82 | CPU_INTERRUPT_EXITTB); 83 } 84 85 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 86 void *opaque) 87 { 88 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 89 90 entry->hook = hook; 91 entry->opaque = opaque; 92 93 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 94 } 95 96 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 97 void *opaque) 98 { 99 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 100 101 entry->hook = hook; 102 entry->opaque = opaque; 103 104 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 105 } 106 107 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 108 { 109 /* Reset a single ARMCPRegInfo register */ 110 ARMCPRegInfo *ri = value; 111 ARMCPU *cpu = opaque; 112 113 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 114 return; 115 } 116 117 if (ri->resetfn) { 118 ri->resetfn(&cpu->env, ri); 119 return; 120 } 121 122 /* A zero offset is never possible as it would be regs[0] 123 * so we use it to indicate that reset is being handled elsewhere. 124 * This is basically only used for fields in non-core coprocessors 125 * (like the pxa2xx ones). 126 */ 127 if (!ri->fieldoffset) { 128 return; 129 } 130 131 if (cpreg_field_is_64bit(ri)) { 132 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 133 } else { 134 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 135 } 136 } 137 138 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 139 { 140 /* Purely an assertion check: we've already done reset once, 141 * so now check that running the reset for the cpreg doesn't 142 * change its value. This traps bugs where two different cpregs 143 * both try to reset the same state field but to different values. 144 */ 145 ARMCPRegInfo *ri = value; 146 ARMCPU *cpu = opaque; 147 uint64_t oldvalue, newvalue; 148 149 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 150 return; 151 } 152 153 oldvalue = read_raw_cp_reg(&cpu->env, ri); 154 cp_reg_reset(key, value, opaque); 155 newvalue = read_raw_cp_reg(&cpu->env, ri); 156 assert(oldvalue == newvalue); 157 } 158 159 static void arm_cpu_reset(DeviceState *dev) 160 { 161 CPUState *s = CPU(dev); 162 ARMCPU *cpu = ARM_CPU(s); 163 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 164 CPUARMState *env = &cpu->env; 165 166 acc->parent_reset(dev); 167 168 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 169 170 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 171 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 172 173 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 174 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 175 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 176 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 177 178 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; 179 180 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 181 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 182 } 183 184 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 185 /* 64 bit CPUs always start in 64 bit mode */ 186 env->aarch64 = 1; 187 #if defined(CONFIG_USER_ONLY) 188 env->pstate = PSTATE_MODE_EL0t; 189 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 190 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 191 /* Enable all PAC keys. */ 192 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 193 SCTLR_EnDA | SCTLR_EnDB); 194 /* and to the FP/Neon instructions */ 195 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 196 /* and to the SVE instructions */ 197 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 198 /* with reasonable vector length */ 199 if (cpu_isar_feature(aa64_sve, cpu)) { 200 env->vfp.zcr_el[1] = MIN(cpu->sve_max_vq - 1, 3); 201 } 202 /* 203 * Enable TBI0 and TBI1. While the real kernel only enables TBI0, 204 * turning on both here will produce smaller code and otherwise 205 * make no difference to the user-level emulation. 206 * 207 * In sve_probe_page, we assume that this is set. 208 * Do not modify this without other changes. 209 */ 210 env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); 211 #else 212 /* Reset into the highest available EL */ 213 if (arm_feature(env, ARM_FEATURE_EL3)) { 214 env->pstate = PSTATE_MODE_EL3h; 215 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 216 env->pstate = PSTATE_MODE_EL2h; 217 } else { 218 env->pstate = PSTATE_MODE_EL1h; 219 } 220 env->pc = cpu->rvbar; 221 #endif 222 } else { 223 #if defined(CONFIG_USER_ONLY) 224 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 225 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 226 #endif 227 } 228 229 #if defined(CONFIG_USER_ONLY) 230 env->uncached_cpsr = ARM_CPU_MODE_USR; 231 /* For user mode we must enable access to coprocessors */ 232 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 233 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 234 env->cp15.c15_cpar = 3; 235 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 236 env->cp15.c15_cpar = 1; 237 } 238 #else 239 240 /* 241 * If the highest available EL is EL2, AArch32 will start in Hyp 242 * mode; otherwise it starts in SVC. Note that if we start in 243 * AArch64 then these values in the uncached_cpsr will be ignored. 244 */ 245 if (arm_feature(env, ARM_FEATURE_EL2) && 246 !arm_feature(env, ARM_FEATURE_EL3)) { 247 env->uncached_cpsr = ARM_CPU_MODE_HYP; 248 } else { 249 env->uncached_cpsr = ARM_CPU_MODE_SVC; 250 } 251 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 252 253 if (arm_feature(env, ARM_FEATURE_M)) { 254 uint32_t initial_msp; /* Loaded from 0x0 */ 255 uint32_t initial_pc; /* Loaded from 0x4 */ 256 uint8_t *rom; 257 uint32_t vecbase; 258 259 if (cpu_isar_feature(aa32_lob, cpu)) { 260 /* 261 * LTPSIZE is constant 4 if MVE not implemented, and resets 262 * to an UNKNOWN value if MVE is implemented. We choose to 263 * always reset to 4. 264 */ 265 env->v7m.ltpsize = 4; 266 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 267 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 268 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 269 } 270 271 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 272 env->v7m.secure = true; 273 } else { 274 /* This bit resets to 0 if security is supported, but 1 if 275 * it is not. The bit is not present in v7M, but we set it 276 * here so we can avoid having to make checks on it conditional 277 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 278 */ 279 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 280 /* 281 * Set NSACR to indicate "NS access permitted to everything"; 282 * this avoids having to have all the tests of it being 283 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 284 * v8.1M the guest-visible value of NSACR in a CPU without the 285 * Security Extension is 0xcff. 286 */ 287 env->v7m.nsacr = 0xcff; 288 } 289 290 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 291 * that it resets to 1, so QEMU always does that rather than making 292 * it dependent on CPU model. In v8M it is RES1. 293 */ 294 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 295 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 296 if (arm_feature(env, ARM_FEATURE_V8)) { 297 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 298 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 299 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 300 } 301 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 302 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 303 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 304 } 305 306 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 307 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 308 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 309 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 310 } 311 /* Unlike A/R profile, M profile defines the reset LR value */ 312 env->regs[14] = 0xffffffff; 313 314 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 315 316 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 317 vecbase = env->v7m.vecbase[env->v7m.secure]; 318 rom = rom_ptr(vecbase, 8); 319 if (rom) { 320 /* Address zero is covered by ROM which hasn't yet been 321 * copied into physical memory. 322 */ 323 initial_msp = ldl_p(rom); 324 initial_pc = ldl_p(rom + 4); 325 } else { 326 /* Address zero not covered by a ROM blob, or the ROM blob 327 * is in non-modifiable memory and this is a second reset after 328 * it got copied into memory. In the latter case, rom_ptr 329 * will return a NULL pointer and we should use ldl_phys instead. 330 */ 331 initial_msp = ldl_phys(s->as, vecbase); 332 initial_pc = ldl_phys(s->as, vecbase + 4); 333 } 334 335 env->regs[13] = initial_msp & 0xFFFFFFFC; 336 env->regs[15] = initial_pc & ~1; 337 env->thumb = initial_pc & 1; 338 } 339 340 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 341 * executing as AArch32 then check if highvecs are enabled and 342 * adjust the PC accordingly. 343 */ 344 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 345 env->regs[15] = 0xFFFF0000; 346 } 347 348 /* M profile requires that reset clears the exclusive monitor; 349 * A profile does not, but clearing it makes more sense than having it 350 * set with an exclusive access on address zero. 351 */ 352 arm_clear_exclusive(env); 353 354 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 355 #endif 356 357 if (arm_feature(env, ARM_FEATURE_PMSA)) { 358 if (cpu->pmsav7_dregion > 0) { 359 if (arm_feature(env, ARM_FEATURE_V8)) { 360 memset(env->pmsav8.rbar[M_REG_NS], 0, 361 sizeof(*env->pmsav8.rbar[M_REG_NS]) 362 * cpu->pmsav7_dregion); 363 memset(env->pmsav8.rlar[M_REG_NS], 0, 364 sizeof(*env->pmsav8.rlar[M_REG_NS]) 365 * cpu->pmsav7_dregion); 366 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 367 memset(env->pmsav8.rbar[M_REG_S], 0, 368 sizeof(*env->pmsav8.rbar[M_REG_S]) 369 * cpu->pmsav7_dregion); 370 memset(env->pmsav8.rlar[M_REG_S], 0, 371 sizeof(*env->pmsav8.rlar[M_REG_S]) 372 * cpu->pmsav7_dregion); 373 } 374 } else if (arm_feature(env, ARM_FEATURE_V7)) { 375 memset(env->pmsav7.drbar, 0, 376 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 377 memset(env->pmsav7.drsr, 0, 378 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 379 memset(env->pmsav7.dracr, 0, 380 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 381 } 382 } 383 env->pmsav7.rnr[M_REG_NS] = 0; 384 env->pmsav7.rnr[M_REG_S] = 0; 385 env->pmsav8.mair0[M_REG_NS] = 0; 386 env->pmsav8.mair0[M_REG_S] = 0; 387 env->pmsav8.mair1[M_REG_NS] = 0; 388 env->pmsav8.mair1[M_REG_S] = 0; 389 } 390 391 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 392 if (cpu->sau_sregion > 0) { 393 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 394 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 395 } 396 env->sau.rnr = 0; 397 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 398 * the Cortex-M33 does. 399 */ 400 env->sau.ctrl = 0; 401 } 402 403 set_flush_to_zero(1, &env->vfp.standard_fp_status); 404 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 405 set_default_nan_mode(1, &env->vfp.standard_fp_status); 406 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); 407 set_float_detect_tininess(float_tininess_before_rounding, 408 &env->vfp.fp_status); 409 set_float_detect_tininess(float_tininess_before_rounding, 410 &env->vfp.standard_fp_status); 411 set_float_detect_tininess(float_tininess_before_rounding, 412 &env->vfp.fp_status_f16); 413 set_float_detect_tininess(float_tininess_before_rounding, 414 &env->vfp.standard_fp_status_f16); 415 #ifndef CONFIG_USER_ONLY 416 if (kvm_enabled()) { 417 kvm_arm_reset_vcpu(cpu); 418 } 419 #endif 420 421 hw_breakpoint_update_all(cpu); 422 hw_watchpoint_update_all(cpu); 423 arm_rebuild_hflags(env); 424 } 425 426 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 427 unsigned int target_el, 428 unsigned int cur_el, bool secure, 429 uint64_t hcr_el2) 430 { 431 CPUARMState *env = cs->env_ptr; 432 bool pstate_unmasked; 433 bool unmasked = false; 434 435 /* 436 * Don't take exceptions if they target a lower EL. 437 * This check should catch any exceptions that would not be taken 438 * but left pending. 439 */ 440 if (cur_el > target_el) { 441 return false; 442 } 443 444 switch (excp_idx) { 445 case EXCP_FIQ: 446 pstate_unmasked = !(env->daif & PSTATE_F); 447 break; 448 449 case EXCP_IRQ: 450 pstate_unmasked = !(env->daif & PSTATE_I); 451 break; 452 453 case EXCP_VFIQ: 454 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 455 /* VFIQs are only taken when hypervized. */ 456 return false; 457 } 458 return !(env->daif & PSTATE_F); 459 case EXCP_VIRQ: 460 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 461 /* VIRQs are only taken when hypervized. */ 462 return false; 463 } 464 return !(env->daif & PSTATE_I); 465 default: 466 g_assert_not_reached(); 467 } 468 469 /* 470 * Use the target EL, current execution state and SCR/HCR settings to 471 * determine whether the corresponding CPSR bit is used to mask the 472 * interrupt. 473 */ 474 if ((target_el > cur_el) && (target_el != 1)) { 475 /* Exceptions targeting a higher EL may not be maskable */ 476 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 477 /* 478 * 64-bit masking rules are simple: exceptions to EL3 479 * can't be masked, and exceptions to EL2 can only be 480 * masked from Secure state. The HCR and SCR settings 481 * don't affect the masking logic, only the interrupt routing. 482 */ 483 if (target_el == 3 || !secure || (env->cp15.scr_el3 & SCR_EEL2)) { 484 unmasked = true; 485 } 486 } else { 487 /* 488 * The old 32-bit-only environment has a more complicated 489 * masking setup. HCR and SCR bits not only affect interrupt 490 * routing but also change the behaviour of masking. 491 */ 492 bool hcr, scr; 493 494 switch (excp_idx) { 495 case EXCP_FIQ: 496 /* 497 * If FIQs are routed to EL3 or EL2 then there are cases where 498 * we override the CPSR.F in determining if the exception is 499 * masked or not. If neither of these are set then we fall back 500 * to the CPSR.F setting otherwise we further assess the state 501 * below. 502 */ 503 hcr = hcr_el2 & HCR_FMO; 504 scr = (env->cp15.scr_el3 & SCR_FIQ); 505 506 /* 507 * When EL3 is 32-bit, the SCR.FW bit controls whether the 508 * CPSR.F bit masks FIQ interrupts when taken in non-secure 509 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 510 * when non-secure but only when FIQs are only routed to EL3. 511 */ 512 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 513 break; 514 case EXCP_IRQ: 515 /* 516 * When EL3 execution state is 32-bit, if HCR.IMO is set then 517 * we may override the CPSR.I masking when in non-secure state. 518 * The SCR.IRQ setting has already been taken into consideration 519 * when setting the target EL, so it does not have a further 520 * affect here. 521 */ 522 hcr = hcr_el2 & HCR_IMO; 523 scr = false; 524 break; 525 default: 526 g_assert_not_reached(); 527 } 528 529 if ((scr || hcr) && !secure) { 530 unmasked = true; 531 } 532 } 533 } 534 535 /* 536 * The PSTATE bits only mask the interrupt if we have not overriden the 537 * ability above. 538 */ 539 return unmasked || pstate_unmasked; 540 } 541 542 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 543 { 544 CPUClass *cc = CPU_GET_CLASS(cs); 545 CPUARMState *env = cs->env_ptr; 546 uint32_t cur_el = arm_current_el(env); 547 bool secure = arm_is_secure(env); 548 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 549 uint32_t target_el; 550 uint32_t excp_idx; 551 552 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 553 554 if (interrupt_request & CPU_INTERRUPT_FIQ) { 555 excp_idx = EXCP_FIQ; 556 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 557 if (arm_excp_unmasked(cs, excp_idx, target_el, 558 cur_el, secure, hcr_el2)) { 559 goto found; 560 } 561 } 562 if (interrupt_request & CPU_INTERRUPT_HARD) { 563 excp_idx = EXCP_IRQ; 564 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 565 if (arm_excp_unmasked(cs, excp_idx, target_el, 566 cur_el, secure, hcr_el2)) { 567 goto found; 568 } 569 } 570 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 571 excp_idx = EXCP_VIRQ; 572 target_el = 1; 573 if (arm_excp_unmasked(cs, excp_idx, target_el, 574 cur_el, secure, hcr_el2)) { 575 goto found; 576 } 577 } 578 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 579 excp_idx = EXCP_VFIQ; 580 target_el = 1; 581 if (arm_excp_unmasked(cs, excp_idx, target_el, 582 cur_el, secure, hcr_el2)) { 583 goto found; 584 } 585 } 586 return false; 587 588 found: 589 cs->exception_index = excp_idx; 590 env->exception.target_el = target_el; 591 cc->do_interrupt(cs); 592 return true; 593 } 594 595 void arm_cpu_update_virq(ARMCPU *cpu) 596 { 597 /* 598 * Update the interrupt level for VIRQ, which is the logical OR of 599 * the HCR_EL2.VI bit and the input line level from the GIC. 600 */ 601 CPUARMState *env = &cpu->env; 602 CPUState *cs = CPU(cpu); 603 604 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 605 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 606 607 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 608 if (new_state) { 609 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 610 } else { 611 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 612 } 613 } 614 } 615 616 void arm_cpu_update_vfiq(ARMCPU *cpu) 617 { 618 /* 619 * Update the interrupt level for VFIQ, which is the logical OR of 620 * the HCR_EL2.VF bit and the input line level from the GIC. 621 */ 622 CPUARMState *env = &cpu->env; 623 CPUState *cs = CPU(cpu); 624 625 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 626 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 627 628 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 629 if (new_state) { 630 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 631 } else { 632 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 633 } 634 } 635 } 636 637 #ifndef CONFIG_USER_ONLY 638 static void arm_cpu_set_irq(void *opaque, int irq, int level) 639 { 640 ARMCPU *cpu = opaque; 641 CPUARMState *env = &cpu->env; 642 CPUState *cs = CPU(cpu); 643 static const int mask[] = { 644 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 645 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 646 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 647 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 648 }; 649 650 if (level) { 651 env->irq_line_state |= mask[irq]; 652 } else { 653 env->irq_line_state &= ~mask[irq]; 654 } 655 656 switch (irq) { 657 case ARM_CPU_VIRQ: 658 assert(arm_feature(env, ARM_FEATURE_EL2)); 659 arm_cpu_update_virq(cpu); 660 break; 661 case ARM_CPU_VFIQ: 662 assert(arm_feature(env, ARM_FEATURE_EL2)); 663 arm_cpu_update_vfiq(cpu); 664 break; 665 case ARM_CPU_IRQ: 666 case ARM_CPU_FIQ: 667 if (level) { 668 cpu_interrupt(cs, mask[irq]); 669 } else { 670 cpu_reset_interrupt(cs, mask[irq]); 671 } 672 break; 673 default: 674 g_assert_not_reached(); 675 } 676 } 677 678 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 679 { 680 #ifdef CONFIG_KVM 681 ARMCPU *cpu = opaque; 682 CPUARMState *env = &cpu->env; 683 CPUState *cs = CPU(cpu); 684 uint32_t linestate_bit; 685 int irq_id; 686 687 switch (irq) { 688 case ARM_CPU_IRQ: 689 irq_id = KVM_ARM_IRQ_CPU_IRQ; 690 linestate_bit = CPU_INTERRUPT_HARD; 691 break; 692 case ARM_CPU_FIQ: 693 irq_id = KVM_ARM_IRQ_CPU_FIQ; 694 linestate_bit = CPU_INTERRUPT_FIQ; 695 break; 696 default: 697 g_assert_not_reached(); 698 } 699 700 if (level) { 701 env->irq_line_state |= linestate_bit; 702 } else { 703 env->irq_line_state &= ~linestate_bit; 704 } 705 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 706 #endif 707 } 708 709 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 710 { 711 ARMCPU *cpu = ARM_CPU(cs); 712 CPUARMState *env = &cpu->env; 713 714 cpu_synchronize_state(cs); 715 return arm_cpu_data_is_big_endian(env); 716 } 717 718 #endif 719 720 static int 721 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 722 { 723 return print_insn_arm(pc | 1, info); 724 } 725 726 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 727 { 728 ARMCPU *ac = ARM_CPU(cpu); 729 CPUARMState *env = &ac->env; 730 bool sctlr_b; 731 732 if (is_a64(env)) { 733 /* We might not be compiled with the A64 disassembler 734 * because it needs a C++ compiler. Leave print_insn 735 * unset in this case to use the caller default behaviour. 736 */ 737 #if defined(CONFIG_ARM_A64_DIS) 738 info->print_insn = print_insn_arm_a64; 739 #endif 740 info->cap_arch = CS_ARCH_ARM64; 741 info->cap_insn_unit = 4; 742 info->cap_insn_split = 4; 743 } else { 744 int cap_mode; 745 if (env->thumb) { 746 info->print_insn = print_insn_thumb1; 747 info->cap_insn_unit = 2; 748 info->cap_insn_split = 4; 749 cap_mode = CS_MODE_THUMB; 750 } else { 751 info->print_insn = print_insn_arm; 752 info->cap_insn_unit = 4; 753 info->cap_insn_split = 4; 754 cap_mode = CS_MODE_ARM; 755 } 756 if (arm_feature(env, ARM_FEATURE_V8)) { 757 cap_mode |= CS_MODE_V8; 758 } 759 if (arm_feature(env, ARM_FEATURE_M)) { 760 cap_mode |= CS_MODE_MCLASS; 761 } 762 info->cap_arch = CS_ARCH_ARM; 763 info->cap_mode = cap_mode; 764 } 765 766 sctlr_b = arm_sctlr_b(env); 767 if (bswap_code(sctlr_b)) { 768 #ifdef TARGET_WORDS_BIGENDIAN 769 info->endian = BFD_ENDIAN_LITTLE; 770 #else 771 info->endian = BFD_ENDIAN_BIG; 772 #endif 773 } 774 info->flags &= ~INSN_ARM_BE32; 775 #ifndef CONFIG_USER_ONLY 776 if (sctlr_b) { 777 info->flags |= INSN_ARM_BE32; 778 } 779 #endif 780 } 781 782 #ifdef TARGET_AARCH64 783 784 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 785 { 786 ARMCPU *cpu = ARM_CPU(cs); 787 CPUARMState *env = &cpu->env; 788 uint32_t psr = pstate_read(env); 789 int i; 790 int el = arm_current_el(env); 791 const char *ns_status; 792 793 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 794 for (i = 0; i < 32; i++) { 795 if (i == 31) { 796 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 797 } else { 798 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 799 (i + 2) % 3 ? " " : "\n"); 800 } 801 } 802 803 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 804 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 805 } else { 806 ns_status = ""; 807 } 808 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 809 psr, 810 psr & PSTATE_N ? 'N' : '-', 811 psr & PSTATE_Z ? 'Z' : '-', 812 psr & PSTATE_C ? 'C' : '-', 813 psr & PSTATE_V ? 'V' : '-', 814 ns_status, 815 el, 816 psr & PSTATE_SP ? 'h' : 't'); 817 818 if (cpu_isar_feature(aa64_bti, cpu)) { 819 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 820 } 821 if (!(flags & CPU_DUMP_FPU)) { 822 qemu_fprintf(f, "\n"); 823 return; 824 } 825 if (fp_exception_el(env, el) != 0) { 826 qemu_fprintf(f, " FPU disabled\n"); 827 return; 828 } 829 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 830 vfp_get_fpcr(env), vfp_get_fpsr(env)); 831 832 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { 833 int j, zcr_len = sve_zcr_len_for_el(env, el); 834 835 for (i = 0; i <= FFR_PRED_NUM; i++) { 836 bool eol; 837 if (i == FFR_PRED_NUM) { 838 qemu_fprintf(f, "FFR="); 839 /* It's last, so end the line. */ 840 eol = true; 841 } else { 842 qemu_fprintf(f, "P%02d=", i); 843 switch (zcr_len) { 844 case 0: 845 eol = i % 8 == 7; 846 break; 847 case 1: 848 eol = i % 6 == 5; 849 break; 850 case 2: 851 case 3: 852 eol = i % 3 == 2; 853 break; 854 default: 855 /* More than one quadword per predicate. */ 856 eol = true; 857 break; 858 } 859 } 860 for (j = zcr_len / 4; j >= 0; j--) { 861 int digits; 862 if (j * 4 + 4 <= zcr_len + 1) { 863 digits = 16; 864 } else { 865 digits = (zcr_len % 4 + 1) * 4; 866 } 867 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 868 env->vfp.pregs[i].p[j], 869 j ? ":" : eol ? "\n" : " "); 870 } 871 } 872 873 for (i = 0; i < 32; i++) { 874 if (zcr_len == 0) { 875 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 876 i, env->vfp.zregs[i].d[1], 877 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 878 } else if (zcr_len == 1) { 879 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 880 ":%016" PRIx64 ":%016" PRIx64 "\n", 881 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 882 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 883 } else { 884 for (j = zcr_len; j >= 0; j--) { 885 bool odd = (zcr_len - j) % 2 != 0; 886 if (j == zcr_len) { 887 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 888 } else if (!odd) { 889 if (j > 0) { 890 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 891 } else { 892 qemu_fprintf(f, " [%x]=", j); 893 } 894 } 895 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 896 env->vfp.zregs[i].d[j * 2 + 1], 897 env->vfp.zregs[i].d[j * 2], 898 odd || j == 0 ? "\n" : ":"); 899 } 900 } 901 } 902 } else { 903 for (i = 0; i < 32; i++) { 904 uint64_t *q = aa64_vfp_qreg(env, i); 905 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 906 i, q[1], q[0], (i & 1 ? "\n" : " ")); 907 } 908 } 909 } 910 911 #else 912 913 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 914 { 915 g_assert_not_reached(); 916 } 917 918 #endif 919 920 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 921 { 922 ARMCPU *cpu = ARM_CPU(cs); 923 CPUARMState *env = &cpu->env; 924 int i; 925 926 if (is_a64(env)) { 927 aarch64_cpu_dump_state(cs, f, flags); 928 return; 929 } 930 931 for (i = 0; i < 16; i++) { 932 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 933 if ((i % 4) == 3) { 934 qemu_fprintf(f, "\n"); 935 } else { 936 qemu_fprintf(f, " "); 937 } 938 } 939 940 if (arm_feature(env, ARM_FEATURE_M)) { 941 uint32_t xpsr = xpsr_read(env); 942 const char *mode; 943 const char *ns_status = ""; 944 945 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 946 ns_status = env->v7m.secure ? "S " : "NS "; 947 } 948 949 if (xpsr & XPSR_EXCP) { 950 mode = "handler"; 951 } else { 952 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 953 mode = "unpriv-thread"; 954 } else { 955 mode = "priv-thread"; 956 } 957 } 958 959 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 960 xpsr, 961 xpsr & XPSR_N ? 'N' : '-', 962 xpsr & XPSR_Z ? 'Z' : '-', 963 xpsr & XPSR_C ? 'C' : '-', 964 xpsr & XPSR_V ? 'V' : '-', 965 xpsr & XPSR_T ? 'T' : 'A', 966 ns_status, 967 mode); 968 } else { 969 uint32_t psr = cpsr_read(env); 970 const char *ns_status = ""; 971 972 if (arm_feature(env, ARM_FEATURE_EL3) && 973 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 974 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 975 } 976 977 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 978 psr, 979 psr & CPSR_N ? 'N' : '-', 980 psr & CPSR_Z ? 'Z' : '-', 981 psr & CPSR_C ? 'C' : '-', 982 psr & CPSR_V ? 'V' : '-', 983 psr & CPSR_T ? 'T' : 'A', 984 ns_status, 985 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 986 } 987 988 if (flags & CPU_DUMP_FPU) { 989 int numvfpregs = 0; 990 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 991 numvfpregs = 32; 992 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 993 numvfpregs = 16; 994 } 995 for (i = 0; i < numvfpregs; i++) { 996 uint64_t v = *aa32_vfp_dreg(env, i); 997 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 998 i * 2, (uint32_t)v, 999 i * 2 + 1, (uint32_t)(v >> 32), 1000 i, v); 1001 } 1002 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1003 } 1004 } 1005 1006 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 1007 { 1008 uint32_t Aff1 = idx / clustersz; 1009 uint32_t Aff0 = idx % clustersz; 1010 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1011 } 1012 1013 static void cpreg_hashtable_data_destroy(gpointer data) 1014 { 1015 /* 1016 * Destroy function for cpu->cp_regs hashtable data entries. 1017 * We must free the name string because it was g_strdup()ed in 1018 * add_cpreg_to_hashtable(). It's OK to cast away the 'const' 1019 * from r->name because we know we definitely allocated it. 1020 */ 1021 ARMCPRegInfo *r = data; 1022 1023 g_free((void *)r->name); 1024 g_free(r); 1025 } 1026 1027 static void arm_cpu_initfn(Object *obj) 1028 { 1029 ARMCPU *cpu = ARM_CPU(obj); 1030 1031 cpu_set_cpustate_pointers(cpu); 1032 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 1033 g_free, cpreg_hashtable_data_destroy); 1034 1035 QLIST_INIT(&cpu->pre_el_change_hooks); 1036 QLIST_INIT(&cpu->el_change_hooks); 1037 1038 #ifndef CONFIG_USER_ONLY 1039 /* Our inbound IRQ and FIQ lines */ 1040 if (kvm_enabled()) { 1041 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1042 * the same interface as non-KVM CPUs. 1043 */ 1044 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1045 } else { 1046 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1047 } 1048 1049 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1050 ARRAY_SIZE(cpu->gt_timer_outputs)); 1051 1052 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1053 "gicv3-maintenance-interrupt", 1); 1054 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1055 "pmu-interrupt", 1); 1056 #endif 1057 1058 /* DTB consumers generally don't in fact care what the 'compatible' 1059 * string is, so always provide some string and trust that a hypothetical 1060 * picky DTB consumer will also provide a helpful error message. 1061 */ 1062 cpu->dtb_compatible = "qemu,unknown"; 1063 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 1064 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1065 1066 if (tcg_enabled()) { 1067 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 1068 } 1069 } 1070 1071 static Property arm_cpu_gt_cntfrq_property = 1072 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1073 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1074 1075 static Property arm_cpu_reset_cbar_property = 1076 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1077 1078 static Property arm_cpu_reset_hivecs_property = 1079 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1080 1081 static Property arm_cpu_rvbar_property = 1082 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 1083 1084 #ifndef CONFIG_USER_ONLY 1085 static Property arm_cpu_has_el2_property = 1086 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1087 1088 static Property arm_cpu_has_el3_property = 1089 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1090 #endif 1091 1092 static Property arm_cpu_cfgend_property = 1093 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1094 1095 static Property arm_cpu_has_vfp_property = 1096 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1097 1098 static Property arm_cpu_has_neon_property = 1099 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1100 1101 static Property arm_cpu_has_dsp_property = 1102 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1103 1104 static Property arm_cpu_has_mpu_property = 1105 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1106 1107 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1108 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1109 * the right value for that particular CPU type, and we don't want 1110 * to override that with an incorrect constant value. 1111 */ 1112 static Property arm_cpu_pmsav7_dregion_property = 1113 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1114 pmsav7_dregion, 1115 qdev_prop_uint32, uint32_t); 1116 1117 static bool arm_get_pmu(Object *obj, Error **errp) 1118 { 1119 ARMCPU *cpu = ARM_CPU(obj); 1120 1121 return cpu->has_pmu; 1122 } 1123 1124 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1125 { 1126 ARMCPU *cpu = ARM_CPU(obj); 1127 1128 if (value) { 1129 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1130 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1131 return; 1132 } 1133 set_feature(&cpu->env, ARM_FEATURE_PMU); 1134 } else { 1135 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1136 } 1137 cpu->has_pmu = value; 1138 } 1139 1140 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1141 { 1142 /* 1143 * The exact approach to calculating guest ticks is: 1144 * 1145 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1146 * NANOSECONDS_PER_SECOND); 1147 * 1148 * We don't do that. Rather we intentionally use integer division 1149 * truncation below and in the caller for the conversion of host monotonic 1150 * time to guest ticks to provide the exact inverse for the semantics of 1151 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1152 * it loses precision when representing frequencies where 1153 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1154 * provide an exact inverse leads to scheduling timers with negative 1155 * periods, which in turn leads to sticky behaviour in the guest. 1156 * 1157 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1158 * cannot become zero. 1159 */ 1160 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1161 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1162 } 1163 1164 void arm_cpu_post_init(Object *obj) 1165 { 1166 ARMCPU *cpu = ARM_CPU(obj); 1167 1168 /* M profile implies PMSA. We have to do this here rather than 1169 * in realize with the other feature-implication checks because 1170 * we look at the PMSA bit to see if we should add some properties. 1171 */ 1172 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1173 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1174 } 1175 1176 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1177 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1178 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1179 } 1180 1181 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1182 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1183 } 1184 1185 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1186 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property); 1187 } 1188 1189 #ifndef CONFIG_USER_ONLY 1190 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1191 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1192 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1193 */ 1194 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1195 1196 object_property_add_link(obj, "secure-memory", 1197 TYPE_MEMORY_REGION, 1198 (Object **)&cpu->secure_memory, 1199 qdev_prop_allow_set_link_before_realize, 1200 OBJ_PROP_LINK_STRONG); 1201 } 1202 1203 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1204 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1205 } 1206 #endif 1207 1208 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1209 cpu->has_pmu = true; 1210 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1211 } 1212 1213 /* 1214 * Allow user to turn off VFP and Neon support, but only for TCG -- 1215 * KVM does not currently allow us to lie to the guest about its 1216 * ID/feature registers, so the guest always sees what the host has. 1217 */ 1218 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 1219 ? cpu_isar_feature(aa64_fp_simd, cpu) 1220 : cpu_isar_feature(aa32_vfp, cpu)) { 1221 cpu->has_vfp = true; 1222 if (!kvm_enabled()) { 1223 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1224 } 1225 } 1226 1227 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1228 cpu->has_neon = true; 1229 if (!kvm_enabled()) { 1230 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1231 } 1232 } 1233 1234 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1235 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1236 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1237 } 1238 1239 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1240 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1241 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1242 qdev_property_add_static(DEVICE(obj), 1243 &arm_cpu_pmsav7_dregion_property); 1244 } 1245 } 1246 1247 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1248 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1249 qdev_prop_allow_set_link_before_realize, 1250 OBJ_PROP_LINK_STRONG); 1251 /* 1252 * M profile: initial value of the Secure VTOR. We can't just use 1253 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1254 * the property to be set after realize. 1255 */ 1256 object_property_add_uint32_ptr(obj, "init-svtor", 1257 &cpu->init_svtor, 1258 OBJ_PROP_FLAG_READWRITE); 1259 } 1260 1261 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1262 1263 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1264 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1265 } 1266 1267 if (kvm_enabled()) { 1268 kvm_arm_add_vcpu_properties(obj); 1269 } 1270 1271 #ifndef CONFIG_USER_ONLY 1272 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1273 cpu_isar_feature(aa64_mte, cpu)) { 1274 object_property_add_link(obj, "tag-memory", 1275 TYPE_MEMORY_REGION, 1276 (Object **)&cpu->tag_memory, 1277 qdev_prop_allow_set_link_before_realize, 1278 OBJ_PROP_LINK_STRONG); 1279 1280 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1281 object_property_add_link(obj, "secure-tag-memory", 1282 TYPE_MEMORY_REGION, 1283 (Object **)&cpu->secure_tag_memory, 1284 qdev_prop_allow_set_link_before_realize, 1285 OBJ_PROP_LINK_STRONG); 1286 } 1287 } 1288 #endif 1289 } 1290 1291 static void arm_cpu_finalizefn(Object *obj) 1292 { 1293 ARMCPU *cpu = ARM_CPU(obj); 1294 ARMELChangeHook *hook, *next; 1295 1296 g_hash_table_destroy(cpu->cp_regs); 1297 1298 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1299 QLIST_REMOVE(hook, node); 1300 g_free(hook); 1301 } 1302 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1303 QLIST_REMOVE(hook, node); 1304 g_free(hook); 1305 } 1306 #ifndef CONFIG_USER_ONLY 1307 if (cpu->pmu_timer) { 1308 timer_free(cpu->pmu_timer); 1309 } 1310 #endif 1311 } 1312 1313 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1314 { 1315 Error *local_err = NULL; 1316 1317 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1318 arm_cpu_sve_finalize(cpu, &local_err); 1319 if (local_err != NULL) { 1320 error_propagate(errp, local_err); 1321 return; 1322 } 1323 1324 /* 1325 * KVM does not support modifications to this feature. 1326 * We have not registered the cpu properties when KVM 1327 * is in use, so the user will not be able to set them. 1328 */ 1329 if (!kvm_enabled()) { 1330 arm_cpu_pauth_finalize(cpu, &local_err); 1331 if (local_err != NULL) { 1332 error_propagate(errp, local_err); 1333 return; 1334 } 1335 } 1336 } 1337 1338 if (kvm_enabled()) { 1339 kvm_arm_steal_time_finalize(cpu, &local_err); 1340 if (local_err != NULL) { 1341 error_propagate(errp, local_err); 1342 return; 1343 } 1344 } 1345 } 1346 1347 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1348 { 1349 CPUState *cs = CPU(dev); 1350 ARMCPU *cpu = ARM_CPU(dev); 1351 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1352 CPUARMState *env = &cpu->env; 1353 int pagebits; 1354 Error *local_err = NULL; 1355 bool no_aa32 = false; 1356 1357 /* If we needed to query the host kernel for the CPU features 1358 * then it's possible that might have failed in the initfn, but 1359 * this is the first point where we can report it. 1360 */ 1361 if (cpu->host_cpu_probe_failed) { 1362 if (!kvm_enabled()) { 1363 error_setg(errp, "The 'host' CPU type can only be used with KVM"); 1364 } else { 1365 error_setg(errp, "Failed to retrieve host CPU features"); 1366 } 1367 return; 1368 } 1369 1370 #ifndef CONFIG_USER_ONLY 1371 /* The NVIC and M-profile CPU are two halves of a single piece of 1372 * hardware; trying to use one without the other is a command line 1373 * error and will result in segfaults if not caught here. 1374 */ 1375 if (arm_feature(env, ARM_FEATURE_M)) { 1376 if (!env->nvic) { 1377 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1378 return; 1379 } 1380 } else { 1381 if (env->nvic) { 1382 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1383 return; 1384 } 1385 } 1386 1387 { 1388 uint64_t scale; 1389 1390 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1391 if (!cpu->gt_cntfrq_hz) { 1392 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1393 cpu->gt_cntfrq_hz); 1394 return; 1395 } 1396 scale = gt_cntfrq_period_ns(cpu); 1397 } else { 1398 scale = GTIMER_SCALE; 1399 } 1400 1401 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1402 arm_gt_ptimer_cb, cpu); 1403 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1404 arm_gt_vtimer_cb, cpu); 1405 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1406 arm_gt_htimer_cb, cpu); 1407 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1408 arm_gt_stimer_cb, cpu); 1409 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1410 arm_gt_hvtimer_cb, cpu); 1411 } 1412 #endif 1413 1414 cpu_exec_realizefn(cs, &local_err); 1415 if (local_err != NULL) { 1416 error_propagate(errp, local_err); 1417 return; 1418 } 1419 1420 arm_cpu_finalize_features(cpu, &local_err); 1421 if (local_err != NULL) { 1422 error_propagate(errp, local_err); 1423 return; 1424 } 1425 1426 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1427 cpu->has_vfp != cpu->has_neon) { 1428 /* 1429 * This is an architectural requirement for AArch64; AArch32 is 1430 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1431 */ 1432 error_setg(errp, 1433 "AArch64 CPUs must have both VFP and Neon or neither"); 1434 return; 1435 } 1436 1437 if (!cpu->has_vfp) { 1438 uint64_t t; 1439 uint32_t u; 1440 1441 t = cpu->isar.id_aa64isar1; 1442 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1443 cpu->isar.id_aa64isar1 = t; 1444 1445 t = cpu->isar.id_aa64pfr0; 1446 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1447 cpu->isar.id_aa64pfr0 = t; 1448 1449 u = cpu->isar.id_isar6; 1450 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1451 cpu->isar.id_isar6 = u; 1452 1453 u = cpu->isar.mvfr0; 1454 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1455 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1456 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1457 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1458 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1459 if (!arm_feature(env, ARM_FEATURE_M)) { 1460 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1461 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1462 } 1463 cpu->isar.mvfr0 = u; 1464 1465 u = cpu->isar.mvfr1; 1466 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1467 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1468 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1469 if (arm_feature(env, ARM_FEATURE_M)) { 1470 u = FIELD_DP32(u, MVFR1, FP16, 0); 1471 } 1472 cpu->isar.mvfr1 = u; 1473 1474 u = cpu->isar.mvfr2; 1475 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1476 cpu->isar.mvfr2 = u; 1477 } 1478 1479 if (!cpu->has_neon) { 1480 uint64_t t; 1481 uint32_t u; 1482 1483 unset_feature(env, ARM_FEATURE_NEON); 1484 1485 t = cpu->isar.id_aa64isar0; 1486 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1487 cpu->isar.id_aa64isar0 = t; 1488 1489 t = cpu->isar.id_aa64isar1; 1490 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1491 cpu->isar.id_aa64isar1 = t; 1492 1493 t = cpu->isar.id_aa64pfr0; 1494 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1495 cpu->isar.id_aa64pfr0 = t; 1496 1497 u = cpu->isar.id_isar5; 1498 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1499 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1500 cpu->isar.id_isar5 = u; 1501 1502 u = cpu->isar.id_isar6; 1503 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1504 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1505 cpu->isar.id_isar6 = u; 1506 1507 if (!arm_feature(env, ARM_FEATURE_M)) { 1508 u = cpu->isar.mvfr1; 1509 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1510 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1511 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1512 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1513 cpu->isar.mvfr1 = u; 1514 1515 u = cpu->isar.mvfr2; 1516 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1517 cpu->isar.mvfr2 = u; 1518 } 1519 } 1520 1521 if (!cpu->has_neon && !cpu->has_vfp) { 1522 uint64_t t; 1523 uint32_t u; 1524 1525 t = cpu->isar.id_aa64isar0; 1526 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1527 cpu->isar.id_aa64isar0 = t; 1528 1529 t = cpu->isar.id_aa64isar1; 1530 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1531 cpu->isar.id_aa64isar1 = t; 1532 1533 u = cpu->isar.mvfr0; 1534 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1535 cpu->isar.mvfr0 = u; 1536 1537 /* Despite the name, this field covers both VFP and Neon */ 1538 u = cpu->isar.mvfr1; 1539 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1540 cpu->isar.mvfr1 = u; 1541 } 1542 1543 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1544 uint32_t u; 1545 1546 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1547 1548 u = cpu->isar.id_isar1; 1549 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1550 cpu->isar.id_isar1 = u; 1551 1552 u = cpu->isar.id_isar2; 1553 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1554 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1555 cpu->isar.id_isar2 = u; 1556 1557 u = cpu->isar.id_isar3; 1558 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1559 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1560 cpu->isar.id_isar3 = u; 1561 } 1562 1563 /* Some features automatically imply others: */ 1564 if (arm_feature(env, ARM_FEATURE_V8)) { 1565 if (arm_feature(env, ARM_FEATURE_M)) { 1566 set_feature(env, ARM_FEATURE_V7); 1567 } else { 1568 set_feature(env, ARM_FEATURE_V7VE); 1569 } 1570 } 1571 1572 /* 1573 * There exist AArch64 cpus without AArch32 support. When KVM 1574 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1575 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1576 * As a general principle, we also do not make ID register 1577 * consistency checks anywhere unless using TCG, because only 1578 * for TCG would a consistency-check failure be a QEMU bug. 1579 */ 1580 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1581 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1582 } 1583 1584 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1585 /* v7 Virtualization Extensions. In real hardware this implies 1586 * EL2 and also the presence of the Security Extensions. 1587 * For QEMU, for backwards-compatibility we implement some 1588 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1589 * include the various other features that V7VE implies. 1590 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1591 * Security Extensions is ARM_FEATURE_EL3. 1592 */ 1593 assert(!tcg_enabled() || no_aa32 || 1594 cpu_isar_feature(aa32_arm_div, cpu)); 1595 set_feature(env, ARM_FEATURE_LPAE); 1596 set_feature(env, ARM_FEATURE_V7); 1597 } 1598 if (arm_feature(env, ARM_FEATURE_V7)) { 1599 set_feature(env, ARM_FEATURE_VAPA); 1600 set_feature(env, ARM_FEATURE_THUMB2); 1601 set_feature(env, ARM_FEATURE_MPIDR); 1602 if (!arm_feature(env, ARM_FEATURE_M)) { 1603 set_feature(env, ARM_FEATURE_V6K); 1604 } else { 1605 set_feature(env, ARM_FEATURE_V6); 1606 } 1607 1608 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1609 * non-EL3 configs. This is needed by some legacy boards. 1610 */ 1611 set_feature(env, ARM_FEATURE_VBAR); 1612 } 1613 if (arm_feature(env, ARM_FEATURE_V6K)) { 1614 set_feature(env, ARM_FEATURE_V6); 1615 set_feature(env, ARM_FEATURE_MVFR); 1616 } 1617 if (arm_feature(env, ARM_FEATURE_V6)) { 1618 set_feature(env, ARM_FEATURE_V5); 1619 if (!arm_feature(env, ARM_FEATURE_M)) { 1620 assert(!tcg_enabled() || no_aa32 || 1621 cpu_isar_feature(aa32_jazelle, cpu)); 1622 set_feature(env, ARM_FEATURE_AUXCR); 1623 } 1624 } 1625 if (arm_feature(env, ARM_FEATURE_V5)) { 1626 set_feature(env, ARM_FEATURE_V4T); 1627 } 1628 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1629 set_feature(env, ARM_FEATURE_V7MP); 1630 } 1631 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1632 set_feature(env, ARM_FEATURE_CBAR); 1633 } 1634 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1635 !arm_feature(env, ARM_FEATURE_M)) { 1636 set_feature(env, ARM_FEATURE_THUMB_DSP); 1637 } 1638 1639 /* 1640 * We rely on no XScale CPU having VFP so we can use the same bits in the 1641 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1642 */ 1643 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1644 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1645 !arm_feature(env, ARM_FEATURE_XSCALE)); 1646 1647 if (arm_feature(env, ARM_FEATURE_V7) && 1648 !arm_feature(env, ARM_FEATURE_M) && 1649 !arm_feature(env, ARM_FEATURE_PMSA)) { 1650 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1651 * can use 4K pages. 1652 */ 1653 pagebits = 12; 1654 } else { 1655 /* For CPUs which might have tiny 1K pages, or which have an 1656 * MPU and might have small region sizes, stick with 1K pages. 1657 */ 1658 pagebits = 10; 1659 } 1660 if (!set_preferred_target_page_bits(pagebits)) { 1661 /* This can only ever happen for hotplugging a CPU, or if 1662 * the board code incorrectly creates a CPU which it has 1663 * promised via minimum_page_size that it will not. 1664 */ 1665 error_setg(errp, "This CPU requires a smaller page size than the " 1666 "system is using"); 1667 return; 1668 } 1669 1670 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1671 * We don't support setting cluster ID ([16..23]) (known as Aff2 1672 * in later ARM ARM versions), or any of the higher affinity level fields, 1673 * so these bits always RAZ. 1674 */ 1675 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1676 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1677 ARM_DEFAULT_CPUS_PER_CLUSTER); 1678 } 1679 1680 if (cpu->reset_hivecs) { 1681 cpu->reset_sctlr |= (1 << 13); 1682 } 1683 1684 if (cpu->cfgend) { 1685 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1686 cpu->reset_sctlr |= SCTLR_EE; 1687 } else { 1688 cpu->reset_sctlr |= SCTLR_B; 1689 } 1690 } 1691 1692 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 1693 /* If the has_el3 CPU property is disabled then we need to disable the 1694 * feature. 1695 */ 1696 unset_feature(env, ARM_FEATURE_EL3); 1697 1698 /* Disable the security extension feature bits in the processor feature 1699 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 1700 */ 1701 cpu->isar.id_pfr1 &= ~0xf0; 1702 cpu->isar.id_aa64pfr0 &= ~0xf000; 1703 } 1704 1705 if (!cpu->has_el2) { 1706 unset_feature(env, ARM_FEATURE_EL2); 1707 } 1708 1709 if (!cpu->has_pmu) { 1710 unset_feature(env, ARM_FEATURE_PMU); 1711 } 1712 if (arm_feature(env, ARM_FEATURE_PMU)) { 1713 pmu_init(cpu); 1714 1715 if (!kvm_enabled()) { 1716 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1717 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1718 } 1719 1720 #ifndef CONFIG_USER_ONLY 1721 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1722 cpu); 1723 #endif 1724 } else { 1725 cpu->isar.id_aa64dfr0 = 1726 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 1727 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 1728 cpu->pmceid0 = 0; 1729 cpu->pmceid1 = 0; 1730 } 1731 1732 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1733 /* Disable the hypervisor feature bits in the processor feature 1734 * registers if we don't have EL2. These are id_pfr1[15:12] and 1735 * id_aa64pfr0_el1[11:8]. 1736 */ 1737 cpu->isar.id_aa64pfr0 &= ~0xf00; 1738 cpu->isar.id_pfr1 &= ~0xf000; 1739 } 1740 1741 #ifndef CONFIG_USER_ONLY 1742 if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { 1743 /* 1744 * Disable the MTE feature bits if we do not have tag-memory 1745 * provided by the machine. 1746 */ 1747 cpu->isar.id_aa64pfr1 = 1748 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 1749 } 1750 #endif 1751 1752 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1753 * to false or by setting pmsav7-dregion to 0. 1754 */ 1755 if (!cpu->has_mpu) { 1756 cpu->pmsav7_dregion = 0; 1757 } 1758 if (cpu->pmsav7_dregion == 0) { 1759 cpu->has_mpu = false; 1760 } 1761 1762 if (arm_feature(env, ARM_FEATURE_PMSA) && 1763 arm_feature(env, ARM_FEATURE_V7)) { 1764 uint32_t nr = cpu->pmsav7_dregion; 1765 1766 if (nr > 0xff) { 1767 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1768 return; 1769 } 1770 1771 if (nr) { 1772 if (arm_feature(env, ARM_FEATURE_V8)) { 1773 /* PMSAv8 */ 1774 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1775 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1776 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1777 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1778 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1779 } 1780 } else { 1781 env->pmsav7.drbar = g_new0(uint32_t, nr); 1782 env->pmsav7.drsr = g_new0(uint32_t, nr); 1783 env->pmsav7.dracr = g_new0(uint32_t, nr); 1784 } 1785 } 1786 } 1787 1788 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1789 uint32_t nr = cpu->sau_sregion; 1790 1791 if (nr > 0xff) { 1792 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1793 return; 1794 } 1795 1796 if (nr) { 1797 env->sau.rbar = g_new0(uint32_t, nr); 1798 env->sau.rlar = g_new0(uint32_t, nr); 1799 } 1800 } 1801 1802 if (arm_feature(env, ARM_FEATURE_EL3)) { 1803 set_feature(env, ARM_FEATURE_VBAR); 1804 } 1805 1806 register_cp_regs_for_features(cpu); 1807 arm_cpu_register_gdb_regs_for_features(cpu); 1808 1809 init_cpreg_list(cpu); 1810 1811 #ifndef CONFIG_USER_ONLY 1812 MachineState *ms = MACHINE(qdev_get_machine()); 1813 unsigned int smp_cpus = ms->smp.cpus; 1814 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 1815 1816 /* 1817 * We must set cs->num_ases to the final value before 1818 * the first call to cpu_address_space_init. 1819 */ 1820 if (cpu->tag_memory != NULL) { 1821 cs->num_ases = 3 + has_secure; 1822 } else { 1823 cs->num_ases = 1 + has_secure; 1824 } 1825 1826 if (has_secure) { 1827 if (!cpu->secure_memory) { 1828 cpu->secure_memory = cs->memory; 1829 } 1830 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1831 cpu->secure_memory); 1832 } 1833 1834 if (cpu->tag_memory != NULL) { 1835 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 1836 cpu->tag_memory); 1837 if (has_secure) { 1838 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 1839 cpu->secure_tag_memory); 1840 } 1841 } 1842 1843 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1844 1845 /* No core_count specified, default to smp_cpus. */ 1846 if (cpu->core_count == -1) { 1847 cpu->core_count = smp_cpus; 1848 } 1849 #endif 1850 1851 if (tcg_enabled()) { 1852 int dcz_blocklen = 4 << cpu->dcz_blocksize; 1853 1854 /* 1855 * We only support DCZ blocklen that fits on one page. 1856 * 1857 * Architectually this is always true. However TARGET_PAGE_SIZE 1858 * is variable and, for compatibility with -machine virt-2.7, 1859 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 1860 * But even then, while the largest architectural DCZ blocklen 1861 * is 2KiB, no cpu actually uses such a large blocklen. 1862 */ 1863 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 1864 1865 /* 1866 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 1867 * both nibbles of each byte storing tag data may be written at once. 1868 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 1869 */ 1870 if (cpu_isar_feature(aa64_mte, cpu)) { 1871 assert(dcz_blocklen >= 2 * TAG_GRANULE); 1872 } 1873 } 1874 1875 qemu_init_vcpu(cs); 1876 cpu_reset(cs); 1877 1878 acc->parent_realize(dev, errp); 1879 } 1880 1881 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1882 { 1883 ObjectClass *oc; 1884 char *typename; 1885 char **cpuname; 1886 const char *cpunamestr; 1887 1888 cpuname = g_strsplit(cpu_model, ",", 1); 1889 cpunamestr = cpuname[0]; 1890 #ifdef CONFIG_USER_ONLY 1891 /* For backwards compatibility usermode emulation allows "-cpu any", 1892 * which has the same semantics as "-cpu max". 1893 */ 1894 if (!strcmp(cpunamestr, "any")) { 1895 cpunamestr = "max"; 1896 } 1897 #endif 1898 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 1899 oc = object_class_by_name(typename); 1900 g_strfreev(cpuname); 1901 g_free(typename); 1902 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 1903 object_class_is_abstract(oc)) { 1904 return NULL; 1905 } 1906 return oc; 1907 } 1908 1909 /* CPU models. These are not needed for the AArch64 linux-user build. */ 1910 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1911 1912 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1913 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1914 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1915 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1916 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1917 REGINFO_SENTINEL 1918 }; 1919 1920 static void cortex_a8_initfn(Object *obj) 1921 { 1922 ARMCPU *cpu = ARM_CPU(obj); 1923 1924 cpu->dtb_compatible = "arm,cortex-a8"; 1925 set_feature(&cpu->env, ARM_FEATURE_V7); 1926 set_feature(&cpu->env, ARM_FEATURE_NEON); 1927 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1928 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1929 set_feature(&cpu->env, ARM_FEATURE_EL3); 1930 cpu->midr = 0x410fc080; 1931 cpu->reset_fpsid = 0x410330c0; 1932 cpu->isar.mvfr0 = 0x11110222; 1933 cpu->isar.mvfr1 = 0x00011111; 1934 cpu->ctr = 0x82048004; 1935 cpu->reset_sctlr = 0x00c50078; 1936 cpu->isar.id_pfr0 = 0x1031; 1937 cpu->isar.id_pfr1 = 0x11; 1938 cpu->isar.id_dfr0 = 0x400; 1939 cpu->id_afr0 = 0; 1940 cpu->isar.id_mmfr0 = 0x31100003; 1941 cpu->isar.id_mmfr1 = 0x20000000; 1942 cpu->isar.id_mmfr2 = 0x01202000; 1943 cpu->isar.id_mmfr3 = 0x11; 1944 cpu->isar.id_isar0 = 0x00101111; 1945 cpu->isar.id_isar1 = 0x12112111; 1946 cpu->isar.id_isar2 = 0x21232031; 1947 cpu->isar.id_isar3 = 0x11112131; 1948 cpu->isar.id_isar4 = 0x00111142; 1949 cpu->isar.dbgdidr = 0x15141000; 1950 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1951 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1952 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1953 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1954 cpu->reset_auxcr = 2; 1955 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1956 } 1957 1958 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1959 /* power_control should be set to maximum latency. Again, 1960 * default to 0 and set by private hook 1961 */ 1962 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1963 .access = PL1_RW, .resetvalue = 0, 1964 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1965 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1966 .access = PL1_RW, .resetvalue = 0, 1967 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1968 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1969 .access = PL1_RW, .resetvalue = 0, 1970 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1971 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1972 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1973 /* TLB lockdown control */ 1974 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1975 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1976 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1977 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1978 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1979 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1980 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1981 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1982 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1983 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1984 REGINFO_SENTINEL 1985 }; 1986 1987 static void cortex_a9_initfn(Object *obj) 1988 { 1989 ARMCPU *cpu = ARM_CPU(obj); 1990 1991 cpu->dtb_compatible = "arm,cortex-a9"; 1992 set_feature(&cpu->env, ARM_FEATURE_V7); 1993 set_feature(&cpu->env, ARM_FEATURE_NEON); 1994 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1995 set_feature(&cpu->env, ARM_FEATURE_EL3); 1996 /* Note that A9 supports the MP extensions even for 1997 * A9UP and single-core A9MP (which are both different 1998 * and valid configurations; we don't model A9UP). 1999 */ 2000 set_feature(&cpu->env, ARM_FEATURE_V7MP); 2001 set_feature(&cpu->env, ARM_FEATURE_CBAR); 2002 cpu->midr = 0x410fc090; 2003 cpu->reset_fpsid = 0x41033090; 2004 cpu->isar.mvfr0 = 0x11110222; 2005 cpu->isar.mvfr1 = 0x01111111; 2006 cpu->ctr = 0x80038003; 2007 cpu->reset_sctlr = 0x00c50078; 2008 cpu->isar.id_pfr0 = 0x1031; 2009 cpu->isar.id_pfr1 = 0x11; 2010 cpu->isar.id_dfr0 = 0x000; 2011 cpu->id_afr0 = 0; 2012 cpu->isar.id_mmfr0 = 0x00100103; 2013 cpu->isar.id_mmfr1 = 0x20000000; 2014 cpu->isar.id_mmfr2 = 0x01230000; 2015 cpu->isar.id_mmfr3 = 0x00002111; 2016 cpu->isar.id_isar0 = 0x00101111; 2017 cpu->isar.id_isar1 = 0x13112111; 2018 cpu->isar.id_isar2 = 0x21232041; 2019 cpu->isar.id_isar3 = 0x11112131; 2020 cpu->isar.id_isar4 = 0x00111142; 2021 cpu->isar.dbgdidr = 0x35141000; 2022 cpu->clidr = (1 << 27) | (1 << 24) | 3; 2023 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 2024 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 2025 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 2026 } 2027 2028 #ifndef CONFIG_USER_ONLY 2029 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2030 { 2031 MachineState *ms = MACHINE(qdev_get_machine()); 2032 2033 /* Linux wants the number of processors from here. 2034 * Might as well set the interrupt-controller bit too. 2035 */ 2036 return ((ms->smp.cpus - 1) << 24) | (1 << 23); 2037 } 2038 #endif 2039 2040 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 2041 #ifndef CONFIG_USER_ONLY 2042 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 2043 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 2044 .writefn = arm_cp_write_ignore, }, 2045 #endif 2046 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 2047 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 2048 REGINFO_SENTINEL 2049 }; 2050 2051 static void cortex_a7_initfn(Object *obj) 2052 { 2053 ARMCPU *cpu = ARM_CPU(obj); 2054 2055 cpu->dtb_compatible = "arm,cortex-a7"; 2056 set_feature(&cpu->env, ARM_FEATURE_V7VE); 2057 set_feature(&cpu->env, ARM_FEATURE_NEON); 2058 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2059 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 2060 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2061 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 2062 set_feature(&cpu->env, ARM_FEATURE_EL2); 2063 set_feature(&cpu->env, ARM_FEATURE_EL3); 2064 set_feature(&cpu->env, ARM_FEATURE_PMU); 2065 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 2066 cpu->midr = 0x410fc075; 2067 cpu->reset_fpsid = 0x41023075; 2068 cpu->isar.mvfr0 = 0x10110222; 2069 cpu->isar.mvfr1 = 0x11111111; 2070 cpu->ctr = 0x84448003; 2071 cpu->reset_sctlr = 0x00c50078; 2072 cpu->isar.id_pfr0 = 0x00001131; 2073 cpu->isar.id_pfr1 = 0x00011011; 2074 cpu->isar.id_dfr0 = 0x02010555; 2075 cpu->id_afr0 = 0x00000000; 2076 cpu->isar.id_mmfr0 = 0x10101105; 2077 cpu->isar.id_mmfr1 = 0x40000000; 2078 cpu->isar.id_mmfr2 = 0x01240000; 2079 cpu->isar.id_mmfr3 = 0x02102211; 2080 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but 2081 * table 4-41 gives 0x02101110, which includes the arm div insns. 2082 */ 2083 cpu->isar.id_isar0 = 0x02101110; 2084 cpu->isar.id_isar1 = 0x13112111; 2085 cpu->isar.id_isar2 = 0x21232041; 2086 cpu->isar.id_isar3 = 0x11112131; 2087 cpu->isar.id_isar4 = 0x10011142; 2088 cpu->isar.dbgdidr = 0x3515f005; 2089 cpu->clidr = 0x0a200023; 2090 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 2091 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 2092 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 2093 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 2094 } 2095 2096 static void cortex_a15_initfn(Object *obj) 2097 { 2098 ARMCPU *cpu = ARM_CPU(obj); 2099 2100 cpu->dtb_compatible = "arm,cortex-a15"; 2101 set_feature(&cpu->env, ARM_FEATURE_V7VE); 2102 set_feature(&cpu->env, ARM_FEATURE_NEON); 2103 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2104 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 2105 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2106 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 2107 set_feature(&cpu->env, ARM_FEATURE_EL2); 2108 set_feature(&cpu->env, ARM_FEATURE_EL3); 2109 set_feature(&cpu->env, ARM_FEATURE_PMU); 2110 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 2111 cpu->midr = 0x412fc0f1; 2112 cpu->reset_fpsid = 0x410430f0; 2113 cpu->isar.mvfr0 = 0x10110222; 2114 cpu->isar.mvfr1 = 0x11111111; 2115 cpu->ctr = 0x8444c004; 2116 cpu->reset_sctlr = 0x00c50078; 2117 cpu->isar.id_pfr0 = 0x00001131; 2118 cpu->isar.id_pfr1 = 0x00011011; 2119 cpu->isar.id_dfr0 = 0x02010555; 2120 cpu->id_afr0 = 0x00000000; 2121 cpu->isar.id_mmfr0 = 0x10201105; 2122 cpu->isar.id_mmfr1 = 0x20000000; 2123 cpu->isar.id_mmfr2 = 0x01240000; 2124 cpu->isar.id_mmfr3 = 0x02102211; 2125 cpu->isar.id_isar0 = 0x02101110; 2126 cpu->isar.id_isar1 = 0x13112111; 2127 cpu->isar.id_isar2 = 0x21232041; 2128 cpu->isar.id_isar3 = 0x11112131; 2129 cpu->isar.id_isar4 = 0x10011142; 2130 cpu->isar.dbgdidr = 0x3515f021; 2131 cpu->clidr = 0x0a200023; 2132 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 2133 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 2134 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 2135 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 2136 } 2137 2138 #ifndef TARGET_AARCH64 2139 /* 2140 * -cpu max: a CPU with as many features enabled as our emulation supports. 2141 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; 2142 * this only needs to handle 32 bits, and need not care about KVM. 2143 */ 2144 static void arm_max_initfn(Object *obj) 2145 { 2146 ARMCPU *cpu = ARM_CPU(obj); 2147 2148 cortex_a15_initfn(obj); 2149 2150 /* old-style VFP short-vector support */ 2151 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 2152 2153 #ifdef CONFIG_USER_ONLY 2154 /* 2155 * We don't set these in system emulation mode for the moment, 2156 * since we don't correctly set (all of) the ID registers to 2157 * advertise them. 2158 */ 2159 set_feature(&cpu->env, ARM_FEATURE_V8); 2160 { 2161 uint32_t t; 2162 2163 t = cpu->isar.id_isar5; 2164 t = FIELD_DP32(t, ID_ISAR5, AES, 2); 2165 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); 2166 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); 2167 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); 2168 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); 2169 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); 2170 cpu->isar.id_isar5 = t; 2171 2172 t = cpu->isar.id_isar6; 2173 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); 2174 t = FIELD_DP32(t, ID_ISAR6, DP, 1); 2175 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); 2176 t = FIELD_DP32(t, ID_ISAR6, SB, 1); 2177 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); 2178 cpu->isar.id_isar6 = t; 2179 2180 t = cpu->isar.mvfr1; 2181 t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ 2182 t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ 2183 cpu->isar.mvfr1 = t; 2184 2185 t = cpu->isar.mvfr2; 2186 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ 2187 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ 2188 cpu->isar.mvfr2 = t; 2189 2190 t = cpu->isar.id_mmfr3; 2191 t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ 2192 cpu->isar.id_mmfr3 = t; 2193 2194 t = cpu->isar.id_mmfr4; 2195 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ 2196 t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ 2197 t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ 2198 t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ 2199 cpu->isar.id_mmfr4 = t; 2200 } 2201 #endif 2202 } 2203 #endif 2204 2205 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 2206 2207 static const ARMCPUInfo arm_cpus[] = { 2208 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 2209 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 2210 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 2211 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 2212 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 2213 #ifndef TARGET_AARCH64 2214 { .name = "max", .initfn = arm_max_initfn }, 2215 #endif 2216 #ifdef CONFIG_USER_ONLY 2217 { .name = "any", .initfn = arm_max_initfn }, 2218 #endif 2219 #endif 2220 }; 2221 2222 static Property arm_cpu_properties[] = { 2223 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 2224 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2225 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2226 mp_affinity, ARM64_AFFINITY_INVALID), 2227 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2228 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2229 DEFINE_PROP_END_OF_LIST() 2230 }; 2231 2232 static gchar *arm_gdb_arch_name(CPUState *cs) 2233 { 2234 ARMCPU *cpu = ARM_CPU(cs); 2235 CPUARMState *env = &cpu->env; 2236 2237 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2238 return g_strdup("iwmmxt"); 2239 } 2240 return g_strdup("arm"); 2241 } 2242 2243 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2244 { 2245 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2246 CPUClass *cc = CPU_CLASS(acc); 2247 DeviceClass *dc = DEVICE_CLASS(oc); 2248 2249 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2250 &acc->parent_realize); 2251 2252 device_class_set_props(dc, arm_cpu_properties); 2253 device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); 2254 2255 cc->class_by_name = arm_cpu_class_by_name; 2256 cc->has_work = arm_cpu_has_work; 2257 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 2258 cc->dump_state = arm_cpu_dump_state; 2259 cc->set_pc = arm_cpu_set_pc; 2260 cc->synchronize_from_tb = arm_cpu_synchronize_from_tb; 2261 cc->gdb_read_register = arm_cpu_gdb_read_register; 2262 cc->gdb_write_register = arm_cpu_gdb_write_register; 2263 #ifndef CONFIG_USER_ONLY 2264 cc->do_interrupt = arm_cpu_do_interrupt; 2265 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 2266 cc->asidx_from_attrs = arm_asidx_from_attrs; 2267 cc->vmsd = &vmstate_arm_cpu; 2268 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 2269 cc->write_elf64_note = arm_cpu_write_elf64_note; 2270 cc->write_elf32_note = arm_cpu_write_elf32_note; 2271 #endif 2272 cc->gdb_num_core_regs = 26; 2273 cc->gdb_core_xml_file = "arm-core.xml"; 2274 cc->gdb_arch_name = arm_gdb_arch_name; 2275 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2276 cc->gdb_stop_before_watchpoint = true; 2277 cc->disas_set_info = arm_disas_set_info; 2278 #ifdef CONFIG_TCG 2279 cc->tcg_initialize = arm_translate_init; 2280 cc->tlb_fill = arm_cpu_tlb_fill; 2281 cc->debug_excp_handler = arm_debug_excp_handler; 2282 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 2283 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 2284 #if !defined(CONFIG_USER_ONLY) 2285 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 2286 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 2287 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 2288 #endif 2289 } 2290 2291 #ifdef CONFIG_KVM 2292 static void arm_host_initfn(Object *obj) 2293 { 2294 ARMCPU *cpu = ARM_CPU(obj); 2295 2296 kvm_arm_set_cpu_features_from_host(cpu); 2297 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 2298 aarch64_add_sve_properties(obj); 2299 } 2300 arm_cpu_post_init(obj); 2301 } 2302 2303 static const TypeInfo host_arm_cpu_type_info = { 2304 .name = TYPE_ARM_HOST_CPU, 2305 .parent = TYPE_AARCH64_CPU, 2306 .instance_init = arm_host_initfn, 2307 }; 2308 2309 #endif 2310 2311 static void arm_cpu_instance_init(Object *obj) 2312 { 2313 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2314 2315 acc->info->initfn(obj); 2316 arm_cpu_post_init(obj); 2317 } 2318 2319 static void cpu_register_class_init(ObjectClass *oc, void *data) 2320 { 2321 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2322 2323 acc->info = data; 2324 } 2325 2326 void arm_cpu_register(const ARMCPUInfo *info) 2327 { 2328 TypeInfo type_info = { 2329 .parent = TYPE_ARM_CPU, 2330 .instance_size = sizeof(ARMCPU), 2331 .instance_align = __alignof__(ARMCPU), 2332 .instance_init = arm_cpu_instance_init, 2333 .class_size = sizeof(ARMCPUClass), 2334 .class_init = info->class_init ?: cpu_register_class_init, 2335 .class_data = (void *)info, 2336 }; 2337 2338 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2339 type_register(&type_info); 2340 g_free((void *)type_info.name); 2341 } 2342 2343 static const TypeInfo arm_cpu_type_info = { 2344 .name = TYPE_ARM_CPU, 2345 .parent = TYPE_CPU, 2346 .instance_size = sizeof(ARMCPU), 2347 .instance_align = __alignof__(ARMCPU), 2348 .instance_init = arm_cpu_initfn, 2349 .instance_finalize = arm_cpu_finalizefn, 2350 .abstract = true, 2351 .class_size = sizeof(ARMCPUClass), 2352 .class_init = arm_cpu_class_init, 2353 }; 2354 2355 static const TypeInfo idau_interface_type_info = { 2356 .name = TYPE_IDAU_INTERFACE, 2357 .parent = TYPE_INTERFACE, 2358 .class_size = sizeof(IDAUInterfaceClass), 2359 }; 2360 2361 static void arm_cpu_register_types(void) 2362 { 2363 const size_t cpu_count = ARRAY_SIZE(arm_cpus); 2364 2365 type_register_static(&arm_cpu_type_info); 2366 2367 #ifdef CONFIG_KVM 2368 type_register_static(&host_arm_cpu_type_info); 2369 #endif 2370 2371 if (cpu_count) { 2372 size_t i; 2373 2374 type_register_static(&idau_interface_type_info); 2375 for (i = 0; i < cpu_count; ++i) { 2376 arm_cpu_register(&arm_cpus[i]); 2377 } 2378 } 2379 } 2380 2381 type_init(arm_cpu_register_types) 2382