1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu-common.h" 24 #include "target/arm/idau.h" 25 #include "qemu/module.h" 26 #include "qapi/error.h" 27 #include "qapi/visitor.h" 28 #include "cpu.h" 29 #include "internals.h" 30 #include "exec/exec-all.h" 31 #include "hw/qdev-properties.h" 32 #if !defined(CONFIG_USER_ONLY) 33 #include "hw/loader.h" 34 #endif 35 #include "sysemu/sysemu.h" 36 #include "sysemu/tcg.h" 37 #include "sysemu/hw_accel.h" 38 #include "kvm_arm.h" 39 #include "disas/capstone.h" 40 #include "fpu/softfloat.h" 41 42 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 43 { 44 ARMCPU *cpu = ARM_CPU(cs); 45 CPUARMState *env = &cpu->env; 46 47 if (is_a64(env)) { 48 env->pc = value; 49 env->thumb = 0; 50 } else { 51 env->regs[15] = value & ~1; 52 env->thumb = value & 1; 53 } 54 } 55 56 static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 57 { 58 ARMCPU *cpu = ARM_CPU(cs); 59 CPUARMState *env = &cpu->env; 60 61 /* 62 * It's OK to look at env for the current mode here, because it's 63 * never possible for an AArch64 TB to chain to an AArch32 TB. 64 */ 65 if (is_a64(env)) { 66 env->pc = tb->pc; 67 } else { 68 env->regs[15] = tb->pc; 69 } 70 } 71 72 static bool arm_cpu_has_work(CPUState *cs) 73 { 74 ARMCPU *cpu = ARM_CPU(cs); 75 76 return (cpu->power_state != PSCI_OFF) 77 && cs->interrupt_request & 78 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 79 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 80 | CPU_INTERRUPT_EXITTB); 81 } 82 83 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 84 void *opaque) 85 { 86 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 87 88 entry->hook = hook; 89 entry->opaque = opaque; 90 91 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 92 } 93 94 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 95 void *opaque) 96 { 97 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 98 99 entry->hook = hook; 100 entry->opaque = opaque; 101 102 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 103 } 104 105 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 106 { 107 /* Reset a single ARMCPRegInfo register */ 108 ARMCPRegInfo *ri = value; 109 ARMCPU *cpu = opaque; 110 111 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 112 return; 113 } 114 115 if (ri->resetfn) { 116 ri->resetfn(&cpu->env, ri); 117 return; 118 } 119 120 /* A zero offset is never possible as it would be regs[0] 121 * so we use it to indicate that reset is being handled elsewhere. 122 * This is basically only used for fields in non-core coprocessors 123 * (like the pxa2xx ones). 124 */ 125 if (!ri->fieldoffset) { 126 return; 127 } 128 129 if (cpreg_field_is_64bit(ri)) { 130 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 131 } else { 132 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 133 } 134 } 135 136 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 137 { 138 /* Purely an assertion check: we've already done reset once, 139 * so now check that running the reset for the cpreg doesn't 140 * change its value. This traps bugs where two different cpregs 141 * both try to reset the same state field but to different values. 142 */ 143 ARMCPRegInfo *ri = value; 144 ARMCPU *cpu = opaque; 145 uint64_t oldvalue, newvalue; 146 147 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 148 return; 149 } 150 151 oldvalue = read_raw_cp_reg(&cpu->env, ri); 152 cp_reg_reset(key, value, opaque); 153 newvalue = read_raw_cp_reg(&cpu->env, ri); 154 assert(oldvalue == newvalue); 155 } 156 157 /* CPUClass::reset() */ 158 static void arm_cpu_reset(CPUState *s) 159 { 160 ARMCPU *cpu = ARM_CPU(s); 161 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 162 CPUARMState *env = &cpu->env; 163 164 acc->parent_reset(s); 165 166 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 167 168 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 169 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 170 171 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 172 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 173 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 174 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 175 176 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 177 s->halted = cpu->start_powered_off; 178 179 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 180 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 181 } 182 183 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 184 /* 64 bit CPUs always start in 64 bit mode */ 185 env->aarch64 = 1; 186 #if defined(CONFIG_USER_ONLY) 187 env->pstate = PSTATE_MODE_EL0t; 188 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 189 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 190 /* Enable all PAC keys. */ 191 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 192 SCTLR_EnDA | SCTLR_EnDB); 193 /* Enable all PAC instructions */ 194 env->cp15.hcr_el2 |= HCR_API; 195 env->cp15.scr_el3 |= SCR_API; 196 /* and to the FP/Neon instructions */ 197 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 198 /* and to the SVE instructions */ 199 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 200 env->cp15.cptr_el[3] |= CPTR_EZ; 201 /* with maximum vector length */ 202 env->vfp.zcr_el[1] = cpu->sve_max_vq - 1; 203 env->vfp.zcr_el[2] = env->vfp.zcr_el[1]; 204 env->vfp.zcr_el[3] = env->vfp.zcr_el[1]; 205 /* 206 * Enable TBI0 and TBI1. While the real kernel only enables TBI0, 207 * turning on both here will produce smaller code and otherwise 208 * make no difference to the user-level emulation. 209 */ 210 env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); 211 #else 212 /* Reset into the highest available EL */ 213 if (arm_feature(env, ARM_FEATURE_EL3)) { 214 env->pstate = PSTATE_MODE_EL3h; 215 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 216 env->pstate = PSTATE_MODE_EL2h; 217 } else { 218 env->pstate = PSTATE_MODE_EL1h; 219 } 220 env->pc = cpu->rvbar; 221 #endif 222 } else { 223 #if defined(CONFIG_USER_ONLY) 224 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 225 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 226 #endif 227 } 228 229 #if defined(CONFIG_USER_ONLY) 230 env->uncached_cpsr = ARM_CPU_MODE_USR; 231 /* For user mode we must enable access to coprocessors */ 232 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 233 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 234 env->cp15.c15_cpar = 3; 235 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 236 env->cp15.c15_cpar = 1; 237 } 238 #else 239 240 /* 241 * If the highest available EL is EL2, AArch32 will start in Hyp 242 * mode; otherwise it starts in SVC. Note that if we start in 243 * AArch64 then these values in the uncached_cpsr will be ignored. 244 */ 245 if (arm_feature(env, ARM_FEATURE_EL2) && 246 !arm_feature(env, ARM_FEATURE_EL3)) { 247 env->uncached_cpsr = ARM_CPU_MODE_HYP; 248 } else { 249 env->uncached_cpsr = ARM_CPU_MODE_SVC; 250 } 251 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 252 253 if (arm_feature(env, ARM_FEATURE_M)) { 254 uint32_t initial_msp; /* Loaded from 0x0 */ 255 uint32_t initial_pc; /* Loaded from 0x4 */ 256 uint8_t *rom; 257 uint32_t vecbase; 258 259 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 260 env->v7m.secure = true; 261 } else { 262 /* This bit resets to 0 if security is supported, but 1 if 263 * it is not. The bit is not present in v7M, but we set it 264 * here so we can avoid having to make checks on it conditional 265 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 266 */ 267 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 268 } 269 270 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 271 * that it resets to 1, so QEMU always does that rather than making 272 * it dependent on CPU model. In v8M it is RES1. 273 */ 274 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 275 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 276 if (arm_feature(env, ARM_FEATURE_V8)) { 277 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 278 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 279 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 280 } 281 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 282 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 283 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 284 } 285 286 if (arm_feature(env, ARM_FEATURE_VFP)) { 287 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 288 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 289 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 290 } 291 /* Unlike A/R profile, M profile defines the reset LR value */ 292 env->regs[14] = 0xffffffff; 293 294 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 295 296 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 297 vecbase = env->v7m.vecbase[env->v7m.secure]; 298 rom = rom_ptr(vecbase, 8); 299 if (rom) { 300 /* Address zero is covered by ROM which hasn't yet been 301 * copied into physical memory. 302 */ 303 initial_msp = ldl_p(rom); 304 initial_pc = ldl_p(rom + 4); 305 } else { 306 /* Address zero not covered by a ROM blob, or the ROM blob 307 * is in non-modifiable memory and this is a second reset after 308 * it got copied into memory. In the latter case, rom_ptr 309 * will return a NULL pointer and we should use ldl_phys instead. 310 */ 311 initial_msp = ldl_phys(s->as, vecbase); 312 initial_pc = ldl_phys(s->as, vecbase + 4); 313 } 314 315 env->regs[13] = initial_msp & 0xFFFFFFFC; 316 env->regs[15] = initial_pc & ~1; 317 env->thumb = initial_pc & 1; 318 } 319 320 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 321 * executing as AArch32 then check if highvecs are enabled and 322 * adjust the PC accordingly. 323 */ 324 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 325 env->regs[15] = 0xFFFF0000; 326 } 327 328 /* M profile requires that reset clears the exclusive monitor; 329 * A profile does not, but clearing it makes more sense than having it 330 * set with an exclusive access on address zero. 331 */ 332 arm_clear_exclusive(env); 333 334 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 335 #endif 336 337 if (arm_feature(env, ARM_FEATURE_PMSA)) { 338 if (cpu->pmsav7_dregion > 0) { 339 if (arm_feature(env, ARM_FEATURE_V8)) { 340 memset(env->pmsav8.rbar[M_REG_NS], 0, 341 sizeof(*env->pmsav8.rbar[M_REG_NS]) 342 * cpu->pmsav7_dregion); 343 memset(env->pmsav8.rlar[M_REG_NS], 0, 344 sizeof(*env->pmsav8.rlar[M_REG_NS]) 345 * cpu->pmsav7_dregion); 346 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 347 memset(env->pmsav8.rbar[M_REG_S], 0, 348 sizeof(*env->pmsav8.rbar[M_REG_S]) 349 * cpu->pmsav7_dregion); 350 memset(env->pmsav8.rlar[M_REG_S], 0, 351 sizeof(*env->pmsav8.rlar[M_REG_S]) 352 * cpu->pmsav7_dregion); 353 } 354 } else if (arm_feature(env, ARM_FEATURE_V7)) { 355 memset(env->pmsav7.drbar, 0, 356 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 357 memset(env->pmsav7.drsr, 0, 358 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 359 memset(env->pmsav7.dracr, 0, 360 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 361 } 362 } 363 env->pmsav7.rnr[M_REG_NS] = 0; 364 env->pmsav7.rnr[M_REG_S] = 0; 365 env->pmsav8.mair0[M_REG_NS] = 0; 366 env->pmsav8.mair0[M_REG_S] = 0; 367 env->pmsav8.mair1[M_REG_NS] = 0; 368 env->pmsav8.mair1[M_REG_S] = 0; 369 } 370 371 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 372 if (cpu->sau_sregion > 0) { 373 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 374 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 375 } 376 env->sau.rnr = 0; 377 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 378 * the Cortex-M33 does. 379 */ 380 env->sau.ctrl = 0; 381 } 382 383 set_flush_to_zero(1, &env->vfp.standard_fp_status); 384 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 385 set_default_nan_mode(1, &env->vfp.standard_fp_status); 386 set_float_detect_tininess(float_tininess_before_rounding, 387 &env->vfp.fp_status); 388 set_float_detect_tininess(float_tininess_before_rounding, 389 &env->vfp.standard_fp_status); 390 set_float_detect_tininess(float_tininess_before_rounding, 391 &env->vfp.fp_status_f16); 392 #ifndef CONFIG_USER_ONLY 393 if (kvm_enabled()) { 394 kvm_arm_reset_vcpu(cpu); 395 } 396 #endif 397 398 hw_breakpoint_update_all(cpu); 399 hw_watchpoint_update_all(cpu); 400 } 401 402 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 403 { 404 CPUClass *cc = CPU_GET_CLASS(cs); 405 CPUARMState *env = cs->env_ptr; 406 uint32_t cur_el = arm_current_el(env); 407 bool secure = arm_is_secure(env); 408 uint32_t target_el; 409 uint32_t excp_idx; 410 bool ret = false; 411 412 if (interrupt_request & CPU_INTERRUPT_FIQ) { 413 excp_idx = EXCP_FIQ; 414 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 415 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 416 cs->exception_index = excp_idx; 417 env->exception.target_el = target_el; 418 cc->do_interrupt(cs); 419 ret = true; 420 } 421 } 422 if (interrupt_request & CPU_INTERRUPT_HARD) { 423 excp_idx = EXCP_IRQ; 424 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 425 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 426 cs->exception_index = excp_idx; 427 env->exception.target_el = target_el; 428 cc->do_interrupt(cs); 429 ret = true; 430 } 431 } 432 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 433 excp_idx = EXCP_VIRQ; 434 target_el = 1; 435 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 436 cs->exception_index = excp_idx; 437 env->exception.target_el = target_el; 438 cc->do_interrupt(cs); 439 ret = true; 440 } 441 } 442 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 443 excp_idx = EXCP_VFIQ; 444 target_el = 1; 445 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 446 cs->exception_index = excp_idx; 447 env->exception.target_el = target_el; 448 cc->do_interrupt(cs); 449 ret = true; 450 } 451 } 452 453 return ret; 454 } 455 456 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 457 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 458 { 459 CPUClass *cc = CPU_GET_CLASS(cs); 460 ARMCPU *cpu = ARM_CPU(cs); 461 CPUARMState *env = &cpu->env; 462 bool ret = false; 463 464 /* ARMv7-M interrupt masking works differently than -A or -R. 465 * There is no FIQ/IRQ distinction. Instead of I and F bits 466 * masking FIQ and IRQ interrupts, an exception is taken only 467 * if it is higher priority than the current execution priority 468 * (which depends on state like BASEPRI, FAULTMASK and the 469 * currently active exception). 470 */ 471 if (interrupt_request & CPU_INTERRUPT_HARD 472 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 473 cs->exception_index = EXCP_IRQ; 474 cc->do_interrupt(cs); 475 ret = true; 476 } 477 return ret; 478 } 479 #endif 480 481 void arm_cpu_update_virq(ARMCPU *cpu) 482 { 483 /* 484 * Update the interrupt level for VIRQ, which is the logical OR of 485 * the HCR_EL2.VI bit and the input line level from the GIC. 486 */ 487 CPUARMState *env = &cpu->env; 488 CPUState *cs = CPU(cpu); 489 490 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 491 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 492 493 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 494 if (new_state) { 495 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 496 } else { 497 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 498 } 499 } 500 } 501 502 void arm_cpu_update_vfiq(ARMCPU *cpu) 503 { 504 /* 505 * Update the interrupt level for VFIQ, which is the logical OR of 506 * the HCR_EL2.VF bit and the input line level from the GIC. 507 */ 508 CPUARMState *env = &cpu->env; 509 CPUState *cs = CPU(cpu); 510 511 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 512 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 513 514 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 515 if (new_state) { 516 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 517 } else { 518 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 519 } 520 } 521 } 522 523 #ifndef CONFIG_USER_ONLY 524 static void arm_cpu_set_irq(void *opaque, int irq, int level) 525 { 526 ARMCPU *cpu = opaque; 527 CPUARMState *env = &cpu->env; 528 CPUState *cs = CPU(cpu); 529 static const int mask[] = { 530 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 531 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 532 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 533 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 534 }; 535 536 if (level) { 537 env->irq_line_state |= mask[irq]; 538 } else { 539 env->irq_line_state &= ~mask[irq]; 540 } 541 542 switch (irq) { 543 case ARM_CPU_VIRQ: 544 assert(arm_feature(env, ARM_FEATURE_EL2)); 545 arm_cpu_update_virq(cpu); 546 break; 547 case ARM_CPU_VFIQ: 548 assert(arm_feature(env, ARM_FEATURE_EL2)); 549 arm_cpu_update_vfiq(cpu); 550 break; 551 case ARM_CPU_IRQ: 552 case ARM_CPU_FIQ: 553 if (level) { 554 cpu_interrupt(cs, mask[irq]); 555 } else { 556 cpu_reset_interrupt(cs, mask[irq]); 557 } 558 break; 559 default: 560 g_assert_not_reached(); 561 } 562 } 563 564 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 565 { 566 #ifdef CONFIG_KVM 567 ARMCPU *cpu = opaque; 568 CPUARMState *env = &cpu->env; 569 CPUState *cs = CPU(cpu); 570 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 571 uint32_t linestate_bit; 572 573 switch (irq) { 574 case ARM_CPU_IRQ: 575 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 576 linestate_bit = CPU_INTERRUPT_HARD; 577 break; 578 case ARM_CPU_FIQ: 579 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 580 linestate_bit = CPU_INTERRUPT_FIQ; 581 break; 582 default: 583 g_assert_not_reached(); 584 } 585 586 if (level) { 587 env->irq_line_state |= linestate_bit; 588 } else { 589 env->irq_line_state &= ~linestate_bit; 590 } 591 592 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 593 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 594 #endif 595 } 596 597 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 598 { 599 ARMCPU *cpu = ARM_CPU(cs); 600 CPUARMState *env = &cpu->env; 601 602 cpu_synchronize_state(cs); 603 return arm_cpu_data_is_big_endian(env); 604 } 605 606 #endif 607 608 static inline void set_feature(CPUARMState *env, int feature) 609 { 610 env->features |= 1ULL << feature; 611 } 612 613 static inline void unset_feature(CPUARMState *env, int feature) 614 { 615 env->features &= ~(1ULL << feature); 616 } 617 618 static int 619 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 620 { 621 return print_insn_arm(pc | 1, info); 622 } 623 624 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 625 { 626 ARMCPU *ac = ARM_CPU(cpu); 627 CPUARMState *env = &ac->env; 628 bool sctlr_b; 629 630 if (is_a64(env)) { 631 /* We might not be compiled with the A64 disassembler 632 * because it needs a C++ compiler. Leave print_insn 633 * unset in this case to use the caller default behaviour. 634 */ 635 #if defined(CONFIG_ARM_A64_DIS) 636 info->print_insn = print_insn_arm_a64; 637 #endif 638 info->cap_arch = CS_ARCH_ARM64; 639 info->cap_insn_unit = 4; 640 info->cap_insn_split = 4; 641 } else { 642 int cap_mode; 643 if (env->thumb) { 644 info->print_insn = print_insn_thumb1; 645 info->cap_insn_unit = 2; 646 info->cap_insn_split = 4; 647 cap_mode = CS_MODE_THUMB; 648 } else { 649 info->print_insn = print_insn_arm; 650 info->cap_insn_unit = 4; 651 info->cap_insn_split = 4; 652 cap_mode = CS_MODE_ARM; 653 } 654 if (arm_feature(env, ARM_FEATURE_V8)) { 655 cap_mode |= CS_MODE_V8; 656 } 657 if (arm_feature(env, ARM_FEATURE_M)) { 658 cap_mode |= CS_MODE_MCLASS; 659 } 660 info->cap_arch = CS_ARCH_ARM; 661 info->cap_mode = cap_mode; 662 } 663 664 sctlr_b = arm_sctlr_b(env); 665 if (bswap_code(sctlr_b)) { 666 #ifdef TARGET_WORDS_BIGENDIAN 667 info->endian = BFD_ENDIAN_LITTLE; 668 #else 669 info->endian = BFD_ENDIAN_BIG; 670 #endif 671 } 672 info->flags &= ~INSN_ARM_BE32; 673 #ifndef CONFIG_USER_ONLY 674 if (sctlr_b) { 675 info->flags |= INSN_ARM_BE32; 676 } 677 #endif 678 } 679 680 #ifdef TARGET_AARCH64 681 682 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 683 { 684 ARMCPU *cpu = ARM_CPU(cs); 685 CPUARMState *env = &cpu->env; 686 uint32_t psr = pstate_read(env); 687 int i; 688 int el = arm_current_el(env); 689 const char *ns_status; 690 691 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 692 for (i = 0; i < 32; i++) { 693 if (i == 31) { 694 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 695 } else { 696 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 697 (i + 2) % 3 ? " " : "\n"); 698 } 699 } 700 701 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 702 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 703 } else { 704 ns_status = ""; 705 } 706 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 707 psr, 708 psr & PSTATE_N ? 'N' : '-', 709 psr & PSTATE_Z ? 'Z' : '-', 710 psr & PSTATE_C ? 'C' : '-', 711 psr & PSTATE_V ? 'V' : '-', 712 ns_status, 713 el, 714 psr & PSTATE_SP ? 'h' : 't'); 715 716 if (cpu_isar_feature(aa64_bti, cpu)) { 717 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 718 } 719 if (!(flags & CPU_DUMP_FPU)) { 720 qemu_fprintf(f, "\n"); 721 return; 722 } 723 if (fp_exception_el(env, el) != 0) { 724 qemu_fprintf(f, " FPU disabled\n"); 725 return; 726 } 727 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 728 vfp_get_fpcr(env), vfp_get_fpsr(env)); 729 730 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { 731 int j, zcr_len = sve_zcr_len_for_el(env, el); 732 733 for (i = 0; i <= FFR_PRED_NUM; i++) { 734 bool eol; 735 if (i == FFR_PRED_NUM) { 736 qemu_fprintf(f, "FFR="); 737 /* It's last, so end the line. */ 738 eol = true; 739 } else { 740 qemu_fprintf(f, "P%02d=", i); 741 switch (zcr_len) { 742 case 0: 743 eol = i % 8 == 7; 744 break; 745 case 1: 746 eol = i % 6 == 5; 747 break; 748 case 2: 749 case 3: 750 eol = i % 3 == 2; 751 break; 752 default: 753 /* More than one quadword per predicate. */ 754 eol = true; 755 break; 756 } 757 } 758 for (j = zcr_len / 4; j >= 0; j--) { 759 int digits; 760 if (j * 4 + 4 <= zcr_len + 1) { 761 digits = 16; 762 } else { 763 digits = (zcr_len % 4 + 1) * 4; 764 } 765 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 766 env->vfp.pregs[i].p[j], 767 j ? ":" : eol ? "\n" : " "); 768 } 769 } 770 771 for (i = 0; i < 32; i++) { 772 if (zcr_len == 0) { 773 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 774 i, env->vfp.zregs[i].d[1], 775 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 776 } else if (zcr_len == 1) { 777 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 778 ":%016" PRIx64 ":%016" PRIx64 "\n", 779 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 780 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 781 } else { 782 for (j = zcr_len; j >= 0; j--) { 783 bool odd = (zcr_len - j) % 2 != 0; 784 if (j == zcr_len) { 785 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 786 } else if (!odd) { 787 if (j > 0) { 788 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 789 } else { 790 qemu_fprintf(f, " [%x]=", j); 791 } 792 } 793 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 794 env->vfp.zregs[i].d[j * 2 + 1], 795 env->vfp.zregs[i].d[j * 2], 796 odd || j == 0 ? "\n" : ":"); 797 } 798 } 799 } 800 } else { 801 for (i = 0; i < 32; i++) { 802 uint64_t *q = aa64_vfp_qreg(env, i); 803 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 804 i, q[1], q[0], (i & 1 ? "\n" : " ")); 805 } 806 } 807 } 808 809 #else 810 811 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 812 { 813 g_assert_not_reached(); 814 } 815 816 #endif 817 818 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 819 { 820 ARMCPU *cpu = ARM_CPU(cs); 821 CPUARMState *env = &cpu->env; 822 int i; 823 824 if (is_a64(env)) { 825 aarch64_cpu_dump_state(cs, f, flags); 826 return; 827 } 828 829 for (i = 0; i < 16; i++) { 830 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 831 if ((i % 4) == 3) { 832 qemu_fprintf(f, "\n"); 833 } else { 834 qemu_fprintf(f, " "); 835 } 836 } 837 838 if (arm_feature(env, ARM_FEATURE_M)) { 839 uint32_t xpsr = xpsr_read(env); 840 const char *mode; 841 const char *ns_status = ""; 842 843 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 844 ns_status = env->v7m.secure ? "S " : "NS "; 845 } 846 847 if (xpsr & XPSR_EXCP) { 848 mode = "handler"; 849 } else { 850 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 851 mode = "unpriv-thread"; 852 } else { 853 mode = "priv-thread"; 854 } 855 } 856 857 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 858 xpsr, 859 xpsr & XPSR_N ? 'N' : '-', 860 xpsr & XPSR_Z ? 'Z' : '-', 861 xpsr & XPSR_C ? 'C' : '-', 862 xpsr & XPSR_V ? 'V' : '-', 863 xpsr & XPSR_T ? 'T' : 'A', 864 ns_status, 865 mode); 866 } else { 867 uint32_t psr = cpsr_read(env); 868 const char *ns_status = ""; 869 870 if (arm_feature(env, ARM_FEATURE_EL3) && 871 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 872 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 873 } 874 875 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 876 psr, 877 psr & CPSR_N ? 'N' : '-', 878 psr & CPSR_Z ? 'Z' : '-', 879 psr & CPSR_C ? 'C' : '-', 880 psr & CPSR_V ? 'V' : '-', 881 psr & CPSR_T ? 'T' : 'A', 882 ns_status, 883 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 884 } 885 886 if (flags & CPU_DUMP_FPU) { 887 int numvfpregs = 0; 888 if (arm_feature(env, ARM_FEATURE_VFP)) { 889 numvfpregs += 16; 890 } 891 if (arm_feature(env, ARM_FEATURE_VFP3)) { 892 numvfpregs += 16; 893 } 894 for (i = 0; i < numvfpregs; i++) { 895 uint64_t v = *aa32_vfp_dreg(env, i); 896 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 897 i * 2, (uint32_t)v, 898 i * 2 + 1, (uint32_t)(v >> 32), 899 i, v); 900 } 901 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 902 } 903 } 904 905 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 906 { 907 uint32_t Aff1 = idx / clustersz; 908 uint32_t Aff0 = idx % clustersz; 909 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 910 } 911 912 static void cpreg_hashtable_data_destroy(gpointer data) 913 { 914 /* 915 * Destroy function for cpu->cp_regs hashtable data entries. 916 * We must free the name string because it was g_strdup()ed in 917 * add_cpreg_to_hashtable(). It's OK to cast away the 'const' 918 * from r->name because we know we definitely allocated it. 919 */ 920 ARMCPRegInfo *r = data; 921 922 g_free((void *)r->name); 923 g_free(r); 924 } 925 926 static void arm_cpu_initfn(Object *obj) 927 { 928 ARMCPU *cpu = ARM_CPU(obj); 929 930 cpu_set_cpustate_pointers(cpu); 931 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 932 g_free, cpreg_hashtable_data_destroy); 933 934 QLIST_INIT(&cpu->pre_el_change_hooks); 935 QLIST_INIT(&cpu->el_change_hooks); 936 937 #ifndef CONFIG_USER_ONLY 938 /* Our inbound IRQ and FIQ lines */ 939 if (kvm_enabled()) { 940 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 941 * the same interface as non-KVM CPUs. 942 */ 943 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 944 } else { 945 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 946 } 947 948 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 949 ARRAY_SIZE(cpu->gt_timer_outputs)); 950 951 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 952 "gicv3-maintenance-interrupt", 1); 953 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 954 "pmu-interrupt", 1); 955 #endif 956 957 /* DTB consumers generally don't in fact care what the 'compatible' 958 * string is, so always provide some string and trust that a hypothetical 959 * picky DTB consumer will also provide a helpful error message. 960 */ 961 cpu->dtb_compatible = "qemu,unknown"; 962 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 963 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 964 965 if (tcg_enabled()) { 966 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 967 } 968 } 969 970 static Property arm_cpu_reset_cbar_property = 971 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 972 973 static Property arm_cpu_reset_hivecs_property = 974 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 975 976 static Property arm_cpu_rvbar_property = 977 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 978 979 static Property arm_cpu_has_el2_property = 980 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 981 982 static Property arm_cpu_has_el3_property = 983 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 984 985 static Property arm_cpu_cfgend_property = 986 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 987 988 /* use property name "pmu" to match other archs and virt tools */ 989 static Property arm_cpu_has_pmu_property = 990 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 991 992 static Property arm_cpu_has_vfp_property = 993 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 994 995 static Property arm_cpu_has_neon_property = 996 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 997 998 static Property arm_cpu_has_dsp_property = 999 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1000 1001 static Property arm_cpu_has_mpu_property = 1002 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1003 1004 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1005 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1006 * the right value for that particular CPU type, and we don't want 1007 * to override that with an incorrect constant value. 1008 */ 1009 static Property arm_cpu_pmsav7_dregion_property = 1010 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1011 pmsav7_dregion, 1012 qdev_prop_uint32, uint32_t); 1013 1014 static void arm_get_init_svtor(Object *obj, Visitor *v, const char *name, 1015 void *opaque, Error **errp) 1016 { 1017 ARMCPU *cpu = ARM_CPU(obj); 1018 1019 visit_type_uint32(v, name, &cpu->init_svtor, errp); 1020 } 1021 1022 static void arm_set_init_svtor(Object *obj, Visitor *v, const char *name, 1023 void *opaque, Error **errp) 1024 { 1025 ARMCPU *cpu = ARM_CPU(obj); 1026 1027 visit_type_uint32(v, name, &cpu->init_svtor, errp); 1028 } 1029 1030 void arm_cpu_post_init(Object *obj) 1031 { 1032 ARMCPU *cpu = ARM_CPU(obj); 1033 1034 /* M profile implies PMSA. We have to do this here rather than 1035 * in realize with the other feature-implication checks because 1036 * we look at the PMSA bit to see if we should add some properties. 1037 */ 1038 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1039 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1040 } 1041 /* Similarly for the VFP feature bits */ 1042 if (arm_feature(&cpu->env, ARM_FEATURE_VFP4)) { 1043 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1044 } 1045 if (arm_feature(&cpu->env, ARM_FEATURE_VFP3)) { 1046 set_feature(&cpu->env, ARM_FEATURE_VFP); 1047 } 1048 1049 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1050 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1051 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 1052 &error_abort); 1053 } 1054 1055 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1056 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 1057 &error_abort); 1058 } 1059 1060 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1061 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 1062 &error_abort); 1063 } 1064 1065 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1066 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1067 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1068 */ 1069 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 1070 &error_abort); 1071 1072 #ifndef CONFIG_USER_ONLY 1073 object_property_add_link(obj, "secure-memory", 1074 TYPE_MEMORY_REGION, 1075 (Object **)&cpu->secure_memory, 1076 qdev_prop_allow_set_link_before_realize, 1077 OBJ_PROP_LINK_STRONG, 1078 &error_abort); 1079 #endif 1080 } 1081 1082 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1083 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 1084 &error_abort); 1085 } 1086 1087 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1088 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 1089 &error_abort); 1090 } 1091 1092 /* 1093 * Allow user to turn off VFP and Neon support, but only for TCG -- 1094 * KVM does not currently allow us to lie to the guest about its 1095 * ID/feature registers, so the guest always sees what the host has. 1096 */ 1097 if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { 1098 cpu->has_vfp = true; 1099 if (!kvm_enabled()) { 1100 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property, 1101 &error_abort); 1102 } 1103 } 1104 1105 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1106 cpu->has_neon = true; 1107 if (!kvm_enabled()) { 1108 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property, 1109 &error_abort); 1110 } 1111 } 1112 1113 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1114 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1115 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property, 1116 &error_abort); 1117 } 1118 1119 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1120 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 1121 &error_abort); 1122 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1123 qdev_property_add_static(DEVICE(obj), 1124 &arm_cpu_pmsav7_dregion_property, 1125 &error_abort); 1126 } 1127 } 1128 1129 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1130 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1131 qdev_prop_allow_set_link_before_realize, 1132 OBJ_PROP_LINK_STRONG, 1133 &error_abort); 1134 /* 1135 * M profile: initial value of the Secure VTOR. We can't just use 1136 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1137 * the property to be set after realize. 1138 */ 1139 object_property_add(obj, "init-svtor", "uint32", 1140 arm_get_init_svtor, arm_set_init_svtor, 1141 NULL, NULL, &error_abort); 1142 } 1143 1144 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 1145 &error_abort); 1146 } 1147 1148 static void arm_cpu_finalizefn(Object *obj) 1149 { 1150 ARMCPU *cpu = ARM_CPU(obj); 1151 ARMELChangeHook *hook, *next; 1152 1153 g_hash_table_destroy(cpu->cp_regs); 1154 1155 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1156 QLIST_REMOVE(hook, node); 1157 g_free(hook); 1158 } 1159 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1160 QLIST_REMOVE(hook, node); 1161 g_free(hook); 1162 } 1163 #ifndef CONFIG_USER_ONLY 1164 if (cpu->pmu_timer) { 1165 timer_del(cpu->pmu_timer); 1166 timer_deinit(cpu->pmu_timer); 1167 timer_free(cpu->pmu_timer); 1168 } 1169 #endif 1170 } 1171 1172 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1173 { 1174 CPUState *cs = CPU(dev); 1175 ARMCPU *cpu = ARM_CPU(dev); 1176 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1177 CPUARMState *env = &cpu->env; 1178 int pagebits; 1179 Error *local_err = NULL; 1180 bool no_aa32 = false; 1181 1182 /* If we needed to query the host kernel for the CPU features 1183 * then it's possible that might have failed in the initfn, but 1184 * this is the first point where we can report it. 1185 */ 1186 if (cpu->host_cpu_probe_failed) { 1187 if (!kvm_enabled()) { 1188 error_setg(errp, "The 'host' CPU type can only be used with KVM"); 1189 } else { 1190 error_setg(errp, "Failed to retrieve host CPU features"); 1191 } 1192 return; 1193 } 1194 1195 #ifndef CONFIG_USER_ONLY 1196 /* The NVIC and M-profile CPU are two halves of a single piece of 1197 * hardware; trying to use one without the other is a command line 1198 * error and will result in segfaults if not caught here. 1199 */ 1200 if (arm_feature(env, ARM_FEATURE_M)) { 1201 if (!env->nvic) { 1202 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1203 return; 1204 } 1205 } else { 1206 if (env->nvic) { 1207 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1208 return; 1209 } 1210 } 1211 1212 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 1213 arm_gt_ptimer_cb, cpu); 1214 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 1215 arm_gt_vtimer_cb, cpu); 1216 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 1217 arm_gt_htimer_cb, cpu); 1218 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 1219 arm_gt_stimer_cb, cpu); 1220 #endif 1221 1222 cpu_exec_realizefn(cs, &local_err); 1223 if (local_err != NULL) { 1224 error_propagate(errp, local_err); 1225 return; 1226 } 1227 1228 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1229 cpu->has_vfp != cpu->has_neon) { 1230 /* 1231 * This is an architectural requirement for AArch64; AArch32 is 1232 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1233 */ 1234 error_setg(errp, 1235 "AArch64 CPUs must have both VFP and Neon or neither"); 1236 return; 1237 } 1238 1239 if (!cpu->has_vfp) { 1240 uint64_t t; 1241 uint32_t u; 1242 1243 unset_feature(env, ARM_FEATURE_VFP); 1244 unset_feature(env, ARM_FEATURE_VFP3); 1245 unset_feature(env, ARM_FEATURE_VFP4); 1246 1247 t = cpu->isar.id_aa64isar1; 1248 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1249 cpu->isar.id_aa64isar1 = t; 1250 1251 t = cpu->isar.id_aa64pfr0; 1252 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1253 cpu->isar.id_aa64pfr0 = t; 1254 1255 u = cpu->isar.id_isar6; 1256 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1257 cpu->isar.id_isar6 = u; 1258 1259 u = cpu->isar.mvfr0; 1260 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1261 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1262 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1263 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1264 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1265 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1266 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1267 cpu->isar.mvfr0 = u; 1268 1269 u = cpu->isar.mvfr1; 1270 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1271 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1272 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1273 cpu->isar.mvfr1 = u; 1274 1275 u = cpu->isar.mvfr2; 1276 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1277 cpu->isar.mvfr2 = u; 1278 } 1279 1280 if (!cpu->has_neon) { 1281 uint64_t t; 1282 uint32_t u; 1283 1284 unset_feature(env, ARM_FEATURE_NEON); 1285 1286 t = cpu->isar.id_aa64isar0; 1287 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1288 cpu->isar.id_aa64isar0 = t; 1289 1290 t = cpu->isar.id_aa64isar1; 1291 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1292 cpu->isar.id_aa64isar1 = t; 1293 1294 t = cpu->isar.id_aa64pfr0; 1295 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1296 cpu->isar.id_aa64pfr0 = t; 1297 1298 u = cpu->isar.id_isar5; 1299 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1300 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1301 cpu->isar.id_isar5 = u; 1302 1303 u = cpu->isar.id_isar6; 1304 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1305 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1306 cpu->isar.id_isar6 = u; 1307 1308 u = cpu->isar.mvfr1; 1309 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1310 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1311 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1312 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1313 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1314 cpu->isar.mvfr1 = u; 1315 1316 u = cpu->isar.mvfr2; 1317 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1318 cpu->isar.mvfr2 = u; 1319 } 1320 1321 if (!cpu->has_neon && !cpu->has_vfp) { 1322 uint64_t t; 1323 uint32_t u; 1324 1325 t = cpu->isar.id_aa64isar0; 1326 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1327 cpu->isar.id_aa64isar0 = t; 1328 1329 t = cpu->isar.id_aa64isar1; 1330 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1331 cpu->isar.id_aa64isar1 = t; 1332 1333 u = cpu->isar.mvfr0; 1334 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1335 cpu->isar.mvfr0 = u; 1336 } 1337 1338 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1339 uint32_t u; 1340 1341 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1342 1343 u = cpu->isar.id_isar1; 1344 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1345 cpu->isar.id_isar1 = u; 1346 1347 u = cpu->isar.id_isar2; 1348 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1349 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1350 cpu->isar.id_isar2 = u; 1351 1352 u = cpu->isar.id_isar3; 1353 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1354 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1355 cpu->isar.id_isar3 = u; 1356 } 1357 1358 /* Some features automatically imply others: */ 1359 if (arm_feature(env, ARM_FEATURE_V8)) { 1360 if (arm_feature(env, ARM_FEATURE_M)) { 1361 set_feature(env, ARM_FEATURE_V7); 1362 } else { 1363 set_feature(env, ARM_FEATURE_V7VE); 1364 } 1365 } 1366 1367 /* 1368 * There exist AArch64 cpus without AArch32 support. When KVM 1369 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1370 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1371 */ 1372 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1373 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1374 } 1375 1376 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1377 /* v7 Virtualization Extensions. In real hardware this implies 1378 * EL2 and also the presence of the Security Extensions. 1379 * For QEMU, for backwards-compatibility we implement some 1380 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1381 * include the various other features that V7VE implies. 1382 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1383 * Security Extensions is ARM_FEATURE_EL3. 1384 */ 1385 assert(no_aa32 || cpu_isar_feature(arm_div, cpu)); 1386 set_feature(env, ARM_FEATURE_LPAE); 1387 set_feature(env, ARM_FEATURE_V7); 1388 } 1389 if (arm_feature(env, ARM_FEATURE_V7)) { 1390 set_feature(env, ARM_FEATURE_VAPA); 1391 set_feature(env, ARM_FEATURE_THUMB2); 1392 set_feature(env, ARM_FEATURE_MPIDR); 1393 if (!arm_feature(env, ARM_FEATURE_M)) { 1394 set_feature(env, ARM_FEATURE_V6K); 1395 } else { 1396 set_feature(env, ARM_FEATURE_V6); 1397 } 1398 1399 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1400 * non-EL3 configs. This is needed by some legacy boards. 1401 */ 1402 set_feature(env, ARM_FEATURE_VBAR); 1403 } 1404 if (arm_feature(env, ARM_FEATURE_V6K)) { 1405 set_feature(env, ARM_FEATURE_V6); 1406 set_feature(env, ARM_FEATURE_MVFR); 1407 } 1408 if (arm_feature(env, ARM_FEATURE_V6)) { 1409 set_feature(env, ARM_FEATURE_V5); 1410 if (!arm_feature(env, ARM_FEATURE_M)) { 1411 assert(no_aa32 || cpu_isar_feature(jazelle, cpu)); 1412 set_feature(env, ARM_FEATURE_AUXCR); 1413 } 1414 } 1415 if (arm_feature(env, ARM_FEATURE_V5)) { 1416 set_feature(env, ARM_FEATURE_V4T); 1417 } 1418 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1419 set_feature(env, ARM_FEATURE_V7MP); 1420 set_feature(env, ARM_FEATURE_PXN); 1421 } 1422 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1423 set_feature(env, ARM_FEATURE_CBAR); 1424 } 1425 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1426 !arm_feature(env, ARM_FEATURE_M)) { 1427 set_feature(env, ARM_FEATURE_THUMB_DSP); 1428 } 1429 1430 /* 1431 * We rely on no XScale CPU having VFP so we can use the same bits in the 1432 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1433 */ 1434 assert(!(arm_feature(env, ARM_FEATURE_VFP) && 1435 arm_feature(env, ARM_FEATURE_XSCALE))); 1436 1437 if (arm_feature(env, ARM_FEATURE_V7) && 1438 !arm_feature(env, ARM_FEATURE_M) && 1439 !arm_feature(env, ARM_FEATURE_PMSA)) { 1440 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1441 * can use 4K pages. 1442 */ 1443 pagebits = 12; 1444 } else { 1445 /* For CPUs which might have tiny 1K pages, or which have an 1446 * MPU and might have small region sizes, stick with 1K pages. 1447 */ 1448 pagebits = 10; 1449 } 1450 if (!set_preferred_target_page_bits(pagebits)) { 1451 /* This can only ever happen for hotplugging a CPU, or if 1452 * the board code incorrectly creates a CPU which it has 1453 * promised via minimum_page_size that it will not. 1454 */ 1455 error_setg(errp, "This CPU requires a smaller page size than the " 1456 "system is using"); 1457 return; 1458 } 1459 1460 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1461 * We don't support setting cluster ID ([16..23]) (known as Aff2 1462 * in later ARM ARM versions), or any of the higher affinity level fields, 1463 * so these bits always RAZ. 1464 */ 1465 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1466 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1467 ARM_DEFAULT_CPUS_PER_CLUSTER); 1468 } 1469 1470 if (cpu->reset_hivecs) { 1471 cpu->reset_sctlr |= (1 << 13); 1472 } 1473 1474 if (cpu->cfgend) { 1475 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1476 cpu->reset_sctlr |= SCTLR_EE; 1477 } else { 1478 cpu->reset_sctlr |= SCTLR_B; 1479 } 1480 } 1481 1482 if (!cpu->has_el3) { 1483 /* If the has_el3 CPU property is disabled then we need to disable the 1484 * feature. 1485 */ 1486 unset_feature(env, ARM_FEATURE_EL3); 1487 1488 /* Disable the security extension feature bits in the processor feature 1489 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 1490 */ 1491 cpu->id_pfr1 &= ~0xf0; 1492 cpu->isar.id_aa64pfr0 &= ~0xf000; 1493 } 1494 1495 if (!cpu->has_el2) { 1496 unset_feature(env, ARM_FEATURE_EL2); 1497 } 1498 1499 if (!cpu->has_pmu) { 1500 unset_feature(env, ARM_FEATURE_PMU); 1501 } 1502 if (arm_feature(env, ARM_FEATURE_PMU)) { 1503 pmu_init(cpu); 1504 1505 if (!kvm_enabled()) { 1506 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1507 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1508 } 1509 1510 #ifndef CONFIG_USER_ONLY 1511 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1512 cpu); 1513 #endif 1514 } else { 1515 cpu->id_aa64dfr0 &= ~0xf00; 1516 cpu->id_dfr0 &= ~(0xf << 24); 1517 cpu->pmceid0 = 0; 1518 cpu->pmceid1 = 0; 1519 } 1520 1521 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1522 /* Disable the hypervisor feature bits in the processor feature 1523 * registers if we don't have EL2. These are id_pfr1[15:12] and 1524 * id_aa64pfr0_el1[11:8]. 1525 */ 1526 cpu->isar.id_aa64pfr0 &= ~0xf00; 1527 cpu->id_pfr1 &= ~0xf000; 1528 } 1529 1530 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1531 * to false or by setting pmsav7-dregion to 0. 1532 */ 1533 if (!cpu->has_mpu) { 1534 cpu->pmsav7_dregion = 0; 1535 } 1536 if (cpu->pmsav7_dregion == 0) { 1537 cpu->has_mpu = false; 1538 } 1539 1540 if (arm_feature(env, ARM_FEATURE_PMSA) && 1541 arm_feature(env, ARM_FEATURE_V7)) { 1542 uint32_t nr = cpu->pmsav7_dregion; 1543 1544 if (nr > 0xff) { 1545 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1546 return; 1547 } 1548 1549 if (nr) { 1550 if (arm_feature(env, ARM_FEATURE_V8)) { 1551 /* PMSAv8 */ 1552 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1553 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1554 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1555 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1556 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1557 } 1558 } else { 1559 env->pmsav7.drbar = g_new0(uint32_t, nr); 1560 env->pmsav7.drsr = g_new0(uint32_t, nr); 1561 env->pmsav7.dracr = g_new0(uint32_t, nr); 1562 } 1563 } 1564 } 1565 1566 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1567 uint32_t nr = cpu->sau_sregion; 1568 1569 if (nr > 0xff) { 1570 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1571 return; 1572 } 1573 1574 if (nr) { 1575 env->sau.rbar = g_new0(uint32_t, nr); 1576 env->sau.rlar = g_new0(uint32_t, nr); 1577 } 1578 } 1579 1580 if (arm_feature(env, ARM_FEATURE_EL3)) { 1581 set_feature(env, ARM_FEATURE_VBAR); 1582 } 1583 1584 register_cp_regs_for_features(cpu); 1585 arm_cpu_register_gdb_regs_for_features(cpu); 1586 1587 init_cpreg_list(cpu); 1588 1589 #ifndef CONFIG_USER_ONLY 1590 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1591 cs->num_ases = 2; 1592 1593 if (!cpu->secure_memory) { 1594 cpu->secure_memory = cs->memory; 1595 } 1596 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1597 cpu->secure_memory); 1598 } else { 1599 cs->num_ases = 1; 1600 } 1601 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1602 1603 /* No core_count specified, default to smp_cpus. */ 1604 if (cpu->core_count == -1) { 1605 cpu->core_count = smp_cpus; 1606 } 1607 #endif 1608 1609 qemu_init_vcpu(cs); 1610 cpu_reset(cs); 1611 1612 acc->parent_realize(dev, errp); 1613 } 1614 1615 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1616 { 1617 ObjectClass *oc; 1618 char *typename; 1619 char **cpuname; 1620 const char *cpunamestr; 1621 1622 cpuname = g_strsplit(cpu_model, ",", 1); 1623 cpunamestr = cpuname[0]; 1624 #ifdef CONFIG_USER_ONLY 1625 /* For backwards compatibility usermode emulation allows "-cpu any", 1626 * which has the same semantics as "-cpu max". 1627 */ 1628 if (!strcmp(cpunamestr, "any")) { 1629 cpunamestr = "max"; 1630 } 1631 #endif 1632 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 1633 oc = object_class_by_name(typename); 1634 g_strfreev(cpuname); 1635 g_free(typename); 1636 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 1637 object_class_is_abstract(oc)) { 1638 return NULL; 1639 } 1640 return oc; 1641 } 1642 1643 /* CPU models. These are not needed for the AArch64 linux-user build. */ 1644 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1645 1646 static void arm926_initfn(Object *obj) 1647 { 1648 ARMCPU *cpu = ARM_CPU(obj); 1649 1650 cpu->dtb_compatible = "arm,arm926"; 1651 set_feature(&cpu->env, ARM_FEATURE_V5); 1652 set_feature(&cpu->env, ARM_FEATURE_VFP); 1653 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1654 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1655 cpu->midr = 0x41069265; 1656 cpu->reset_fpsid = 0x41011090; 1657 cpu->ctr = 0x1dd20d2; 1658 cpu->reset_sctlr = 0x00090078; 1659 1660 /* 1661 * ARMv5 does not have the ID_ISAR registers, but we can still 1662 * set the field to indicate Jazelle support within QEMU. 1663 */ 1664 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 1665 } 1666 1667 static void arm946_initfn(Object *obj) 1668 { 1669 ARMCPU *cpu = ARM_CPU(obj); 1670 1671 cpu->dtb_compatible = "arm,arm946"; 1672 set_feature(&cpu->env, ARM_FEATURE_V5); 1673 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1674 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1675 cpu->midr = 0x41059461; 1676 cpu->ctr = 0x0f004006; 1677 cpu->reset_sctlr = 0x00000078; 1678 } 1679 1680 static void arm1026_initfn(Object *obj) 1681 { 1682 ARMCPU *cpu = ARM_CPU(obj); 1683 1684 cpu->dtb_compatible = "arm,arm1026"; 1685 set_feature(&cpu->env, ARM_FEATURE_V5); 1686 set_feature(&cpu->env, ARM_FEATURE_VFP); 1687 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 1688 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1689 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1690 cpu->midr = 0x4106a262; 1691 cpu->reset_fpsid = 0x410110a0; 1692 cpu->ctr = 0x1dd20d2; 1693 cpu->reset_sctlr = 0x00090078; 1694 cpu->reset_auxcr = 1; 1695 1696 /* 1697 * ARMv5 does not have the ID_ISAR registers, but we can still 1698 * set the field to indicate Jazelle support within QEMU. 1699 */ 1700 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 1701 1702 { 1703 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 1704 ARMCPRegInfo ifar = { 1705 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 1706 .access = PL1_RW, 1707 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 1708 .resetvalue = 0 1709 }; 1710 define_one_arm_cp_reg(cpu, &ifar); 1711 } 1712 } 1713 1714 static void arm1136_r2_initfn(Object *obj) 1715 { 1716 ARMCPU *cpu = ARM_CPU(obj); 1717 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 1718 * older core than plain "arm1136". In particular this does not 1719 * have the v6K features. 1720 * These ID register values are correct for 1136 but may be wrong 1721 * for 1136_r2 (in particular r0p2 does not actually implement most 1722 * of the ID registers). 1723 */ 1724 1725 cpu->dtb_compatible = "arm,arm1136"; 1726 set_feature(&cpu->env, ARM_FEATURE_V6); 1727 set_feature(&cpu->env, ARM_FEATURE_VFP); 1728 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1729 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1730 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1731 cpu->midr = 0x4107b362; 1732 cpu->reset_fpsid = 0x410120b4; 1733 cpu->isar.mvfr0 = 0x11111111; 1734 cpu->isar.mvfr1 = 0x00000000; 1735 cpu->ctr = 0x1dd20d2; 1736 cpu->reset_sctlr = 0x00050078; 1737 cpu->id_pfr0 = 0x111; 1738 cpu->id_pfr1 = 0x1; 1739 cpu->id_dfr0 = 0x2; 1740 cpu->id_afr0 = 0x3; 1741 cpu->id_mmfr0 = 0x01130003; 1742 cpu->id_mmfr1 = 0x10030302; 1743 cpu->id_mmfr2 = 0x01222110; 1744 cpu->isar.id_isar0 = 0x00140011; 1745 cpu->isar.id_isar1 = 0x12002111; 1746 cpu->isar.id_isar2 = 0x11231111; 1747 cpu->isar.id_isar3 = 0x01102131; 1748 cpu->isar.id_isar4 = 0x141; 1749 cpu->reset_auxcr = 7; 1750 } 1751 1752 static void arm1136_initfn(Object *obj) 1753 { 1754 ARMCPU *cpu = ARM_CPU(obj); 1755 1756 cpu->dtb_compatible = "arm,arm1136"; 1757 set_feature(&cpu->env, ARM_FEATURE_V6K); 1758 set_feature(&cpu->env, ARM_FEATURE_V6); 1759 set_feature(&cpu->env, ARM_FEATURE_VFP); 1760 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1761 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1762 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1763 cpu->midr = 0x4117b363; 1764 cpu->reset_fpsid = 0x410120b4; 1765 cpu->isar.mvfr0 = 0x11111111; 1766 cpu->isar.mvfr1 = 0x00000000; 1767 cpu->ctr = 0x1dd20d2; 1768 cpu->reset_sctlr = 0x00050078; 1769 cpu->id_pfr0 = 0x111; 1770 cpu->id_pfr1 = 0x1; 1771 cpu->id_dfr0 = 0x2; 1772 cpu->id_afr0 = 0x3; 1773 cpu->id_mmfr0 = 0x01130003; 1774 cpu->id_mmfr1 = 0x10030302; 1775 cpu->id_mmfr2 = 0x01222110; 1776 cpu->isar.id_isar0 = 0x00140011; 1777 cpu->isar.id_isar1 = 0x12002111; 1778 cpu->isar.id_isar2 = 0x11231111; 1779 cpu->isar.id_isar3 = 0x01102131; 1780 cpu->isar.id_isar4 = 0x141; 1781 cpu->reset_auxcr = 7; 1782 } 1783 1784 static void arm1176_initfn(Object *obj) 1785 { 1786 ARMCPU *cpu = ARM_CPU(obj); 1787 1788 cpu->dtb_compatible = "arm,arm1176"; 1789 set_feature(&cpu->env, ARM_FEATURE_V6K); 1790 set_feature(&cpu->env, ARM_FEATURE_VFP); 1791 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1792 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1793 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1794 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1795 set_feature(&cpu->env, ARM_FEATURE_EL3); 1796 cpu->midr = 0x410fb767; 1797 cpu->reset_fpsid = 0x410120b5; 1798 cpu->isar.mvfr0 = 0x11111111; 1799 cpu->isar.mvfr1 = 0x00000000; 1800 cpu->ctr = 0x1dd20d2; 1801 cpu->reset_sctlr = 0x00050078; 1802 cpu->id_pfr0 = 0x111; 1803 cpu->id_pfr1 = 0x11; 1804 cpu->id_dfr0 = 0x33; 1805 cpu->id_afr0 = 0; 1806 cpu->id_mmfr0 = 0x01130003; 1807 cpu->id_mmfr1 = 0x10030302; 1808 cpu->id_mmfr2 = 0x01222100; 1809 cpu->isar.id_isar0 = 0x0140011; 1810 cpu->isar.id_isar1 = 0x12002111; 1811 cpu->isar.id_isar2 = 0x11231121; 1812 cpu->isar.id_isar3 = 0x01102131; 1813 cpu->isar.id_isar4 = 0x01141; 1814 cpu->reset_auxcr = 7; 1815 } 1816 1817 static void arm11mpcore_initfn(Object *obj) 1818 { 1819 ARMCPU *cpu = ARM_CPU(obj); 1820 1821 cpu->dtb_compatible = "arm,arm11mpcore"; 1822 set_feature(&cpu->env, ARM_FEATURE_V6K); 1823 set_feature(&cpu->env, ARM_FEATURE_VFP); 1824 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1825 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1826 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1827 cpu->midr = 0x410fb022; 1828 cpu->reset_fpsid = 0x410120b4; 1829 cpu->isar.mvfr0 = 0x11111111; 1830 cpu->isar.mvfr1 = 0x00000000; 1831 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1832 cpu->id_pfr0 = 0x111; 1833 cpu->id_pfr1 = 0x1; 1834 cpu->id_dfr0 = 0; 1835 cpu->id_afr0 = 0x2; 1836 cpu->id_mmfr0 = 0x01100103; 1837 cpu->id_mmfr1 = 0x10020302; 1838 cpu->id_mmfr2 = 0x01222000; 1839 cpu->isar.id_isar0 = 0x00100011; 1840 cpu->isar.id_isar1 = 0x12002111; 1841 cpu->isar.id_isar2 = 0x11221011; 1842 cpu->isar.id_isar3 = 0x01102131; 1843 cpu->isar.id_isar4 = 0x141; 1844 cpu->reset_auxcr = 1; 1845 } 1846 1847 static void cortex_m0_initfn(Object *obj) 1848 { 1849 ARMCPU *cpu = ARM_CPU(obj); 1850 set_feature(&cpu->env, ARM_FEATURE_V6); 1851 set_feature(&cpu->env, ARM_FEATURE_M); 1852 1853 cpu->midr = 0x410cc200; 1854 } 1855 1856 static void cortex_m3_initfn(Object *obj) 1857 { 1858 ARMCPU *cpu = ARM_CPU(obj); 1859 set_feature(&cpu->env, ARM_FEATURE_V7); 1860 set_feature(&cpu->env, ARM_FEATURE_M); 1861 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1862 cpu->midr = 0x410fc231; 1863 cpu->pmsav7_dregion = 8; 1864 cpu->id_pfr0 = 0x00000030; 1865 cpu->id_pfr1 = 0x00000200; 1866 cpu->id_dfr0 = 0x00100000; 1867 cpu->id_afr0 = 0x00000000; 1868 cpu->id_mmfr0 = 0x00000030; 1869 cpu->id_mmfr1 = 0x00000000; 1870 cpu->id_mmfr2 = 0x00000000; 1871 cpu->id_mmfr3 = 0x00000000; 1872 cpu->isar.id_isar0 = 0x01141110; 1873 cpu->isar.id_isar1 = 0x02111000; 1874 cpu->isar.id_isar2 = 0x21112231; 1875 cpu->isar.id_isar3 = 0x01111110; 1876 cpu->isar.id_isar4 = 0x01310102; 1877 cpu->isar.id_isar5 = 0x00000000; 1878 cpu->isar.id_isar6 = 0x00000000; 1879 } 1880 1881 static void cortex_m4_initfn(Object *obj) 1882 { 1883 ARMCPU *cpu = ARM_CPU(obj); 1884 1885 set_feature(&cpu->env, ARM_FEATURE_V7); 1886 set_feature(&cpu->env, ARM_FEATURE_M); 1887 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1888 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1889 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1890 cpu->midr = 0x410fc240; /* r0p0 */ 1891 cpu->pmsav7_dregion = 8; 1892 cpu->isar.mvfr0 = 0x10110021; 1893 cpu->isar.mvfr1 = 0x11000011; 1894 cpu->isar.mvfr2 = 0x00000000; 1895 cpu->id_pfr0 = 0x00000030; 1896 cpu->id_pfr1 = 0x00000200; 1897 cpu->id_dfr0 = 0x00100000; 1898 cpu->id_afr0 = 0x00000000; 1899 cpu->id_mmfr0 = 0x00000030; 1900 cpu->id_mmfr1 = 0x00000000; 1901 cpu->id_mmfr2 = 0x00000000; 1902 cpu->id_mmfr3 = 0x00000000; 1903 cpu->isar.id_isar0 = 0x01141110; 1904 cpu->isar.id_isar1 = 0x02111000; 1905 cpu->isar.id_isar2 = 0x21112231; 1906 cpu->isar.id_isar3 = 0x01111110; 1907 cpu->isar.id_isar4 = 0x01310102; 1908 cpu->isar.id_isar5 = 0x00000000; 1909 cpu->isar.id_isar6 = 0x00000000; 1910 } 1911 1912 static void cortex_m33_initfn(Object *obj) 1913 { 1914 ARMCPU *cpu = ARM_CPU(obj); 1915 1916 set_feature(&cpu->env, ARM_FEATURE_V8); 1917 set_feature(&cpu->env, ARM_FEATURE_M); 1918 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1919 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); 1920 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1921 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1922 cpu->midr = 0x410fd213; /* r0p3 */ 1923 cpu->pmsav7_dregion = 16; 1924 cpu->sau_sregion = 8; 1925 cpu->isar.mvfr0 = 0x10110021; 1926 cpu->isar.mvfr1 = 0x11000011; 1927 cpu->isar.mvfr2 = 0x00000040; 1928 cpu->id_pfr0 = 0x00000030; 1929 cpu->id_pfr1 = 0x00000210; 1930 cpu->id_dfr0 = 0x00200000; 1931 cpu->id_afr0 = 0x00000000; 1932 cpu->id_mmfr0 = 0x00101F40; 1933 cpu->id_mmfr1 = 0x00000000; 1934 cpu->id_mmfr2 = 0x01000000; 1935 cpu->id_mmfr3 = 0x00000000; 1936 cpu->isar.id_isar0 = 0x01101110; 1937 cpu->isar.id_isar1 = 0x02212000; 1938 cpu->isar.id_isar2 = 0x20232232; 1939 cpu->isar.id_isar3 = 0x01111131; 1940 cpu->isar.id_isar4 = 0x01310132; 1941 cpu->isar.id_isar5 = 0x00000000; 1942 cpu->isar.id_isar6 = 0x00000000; 1943 cpu->clidr = 0x00000000; 1944 cpu->ctr = 0x8000c000; 1945 } 1946 1947 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1948 { 1949 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1950 CPUClass *cc = CPU_CLASS(oc); 1951 1952 acc->info = data; 1953 #ifndef CONFIG_USER_ONLY 1954 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1955 #endif 1956 1957 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1958 } 1959 1960 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1961 /* Dummy the TCM region regs for the moment */ 1962 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1963 .access = PL1_RW, .type = ARM_CP_CONST }, 1964 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1965 .access = PL1_RW, .type = ARM_CP_CONST }, 1966 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 1967 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 1968 REGINFO_SENTINEL 1969 }; 1970 1971 static void cortex_r5_initfn(Object *obj) 1972 { 1973 ARMCPU *cpu = ARM_CPU(obj); 1974 1975 set_feature(&cpu->env, ARM_FEATURE_V7); 1976 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1977 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1978 cpu->midr = 0x411fc153; /* r1p3 */ 1979 cpu->id_pfr0 = 0x0131; 1980 cpu->id_pfr1 = 0x001; 1981 cpu->id_dfr0 = 0x010400; 1982 cpu->id_afr0 = 0x0; 1983 cpu->id_mmfr0 = 0x0210030; 1984 cpu->id_mmfr1 = 0x00000000; 1985 cpu->id_mmfr2 = 0x01200000; 1986 cpu->id_mmfr3 = 0x0211; 1987 cpu->isar.id_isar0 = 0x02101111; 1988 cpu->isar.id_isar1 = 0x13112111; 1989 cpu->isar.id_isar2 = 0x21232141; 1990 cpu->isar.id_isar3 = 0x01112131; 1991 cpu->isar.id_isar4 = 0x0010142; 1992 cpu->isar.id_isar5 = 0x0; 1993 cpu->isar.id_isar6 = 0x0; 1994 cpu->mp_is_up = true; 1995 cpu->pmsav7_dregion = 16; 1996 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1997 } 1998 1999 static void cortex_r5f_initfn(Object *obj) 2000 { 2001 ARMCPU *cpu = ARM_CPU(obj); 2002 2003 cortex_r5_initfn(obj); 2004 set_feature(&cpu->env, ARM_FEATURE_VFP3); 2005 cpu->isar.mvfr0 = 0x10110221; 2006 cpu->isar.mvfr1 = 0x00000011; 2007 } 2008 2009 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 2010 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 2011 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 2012 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 2013 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 2014 REGINFO_SENTINEL 2015 }; 2016 2017 static void cortex_a8_initfn(Object *obj) 2018 { 2019 ARMCPU *cpu = ARM_CPU(obj); 2020 2021 cpu->dtb_compatible = "arm,cortex-a8"; 2022 set_feature(&cpu->env, ARM_FEATURE_V7); 2023 set_feature(&cpu->env, ARM_FEATURE_VFP3); 2024 set_feature(&cpu->env, ARM_FEATURE_NEON); 2025 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2026 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2027 set_feature(&cpu->env, ARM_FEATURE_EL3); 2028 cpu->midr = 0x410fc080; 2029 cpu->reset_fpsid = 0x410330c0; 2030 cpu->isar.mvfr0 = 0x11110222; 2031 cpu->isar.mvfr1 = 0x00011111; 2032 cpu->ctr = 0x82048004; 2033 cpu->reset_sctlr = 0x00c50078; 2034 cpu->id_pfr0 = 0x1031; 2035 cpu->id_pfr1 = 0x11; 2036 cpu->id_dfr0 = 0x400; 2037 cpu->id_afr0 = 0; 2038 cpu->id_mmfr0 = 0x31100003; 2039 cpu->id_mmfr1 = 0x20000000; 2040 cpu->id_mmfr2 = 0x01202000; 2041 cpu->id_mmfr3 = 0x11; 2042 cpu->isar.id_isar0 = 0x00101111; 2043 cpu->isar.id_isar1 = 0x12112111; 2044 cpu->isar.id_isar2 = 0x21232031; 2045 cpu->isar.id_isar3 = 0x11112131; 2046 cpu->isar.id_isar4 = 0x00111142; 2047 cpu->dbgdidr = 0x15141000; 2048 cpu->clidr = (1 << 27) | (2 << 24) | 3; 2049 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 2050 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 2051 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 2052 cpu->reset_auxcr = 2; 2053 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 2054 } 2055 2056 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 2057 /* power_control should be set to maximum latency. Again, 2058 * default to 0 and set by private hook 2059 */ 2060 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 2061 .access = PL1_RW, .resetvalue = 0, 2062 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 2063 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 2064 .access = PL1_RW, .resetvalue = 0, 2065 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 2066 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 2067 .access = PL1_RW, .resetvalue = 0, 2068 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 2069 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 2070 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 2071 /* TLB lockdown control */ 2072 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 2073 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 2074 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 2075 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 2076 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 2077 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 2078 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 2079 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 2080 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 2081 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 2082 REGINFO_SENTINEL 2083 }; 2084 2085 static void cortex_a9_initfn(Object *obj) 2086 { 2087 ARMCPU *cpu = ARM_CPU(obj); 2088 2089 cpu->dtb_compatible = "arm,cortex-a9"; 2090 set_feature(&cpu->env, ARM_FEATURE_V7); 2091 set_feature(&cpu->env, ARM_FEATURE_VFP3); 2092 set_feature(&cpu->env, ARM_FEATURE_NEON); 2093 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2094 set_feature(&cpu->env, ARM_FEATURE_EL3); 2095 /* Note that A9 supports the MP extensions even for 2096 * A9UP and single-core A9MP (which are both different 2097 * and valid configurations; we don't model A9UP). 2098 */ 2099 set_feature(&cpu->env, ARM_FEATURE_V7MP); 2100 set_feature(&cpu->env, ARM_FEATURE_CBAR); 2101 cpu->midr = 0x410fc090; 2102 cpu->reset_fpsid = 0x41033090; 2103 cpu->isar.mvfr0 = 0x11110222; 2104 cpu->isar.mvfr1 = 0x01111111; 2105 cpu->ctr = 0x80038003; 2106 cpu->reset_sctlr = 0x00c50078; 2107 cpu->id_pfr0 = 0x1031; 2108 cpu->id_pfr1 = 0x11; 2109 cpu->id_dfr0 = 0x000; 2110 cpu->id_afr0 = 0; 2111 cpu->id_mmfr0 = 0x00100103; 2112 cpu->id_mmfr1 = 0x20000000; 2113 cpu->id_mmfr2 = 0x01230000; 2114 cpu->id_mmfr3 = 0x00002111; 2115 cpu->isar.id_isar0 = 0x00101111; 2116 cpu->isar.id_isar1 = 0x13112111; 2117 cpu->isar.id_isar2 = 0x21232041; 2118 cpu->isar.id_isar3 = 0x11112131; 2119 cpu->isar.id_isar4 = 0x00111142; 2120 cpu->dbgdidr = 0x35141000; 2121 cpu->clidr = (1 << 27) | (1 << 24) | 3; 2122 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 2123 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 2124 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 2125 } 2126 2127 #ifndef CONFIG_USER_ONLY 2128 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2129 { 2130 /* Linux wants the number of processors from here. 2131 * Might as well set the interrupt-controller bit too. 2132 */ 2133 return ((smp_cpus - 1) << 24) | (1 << 23); 2134 } 2135 #endif 2136 2137 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 2138 #ifndef CONFIG_USER_ONLY 2139 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 2140 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 2141 .writefn = arm_cp_write_ignore, }, 2142 #endif 2143 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 2144 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 2145 REGINFO_SENTINEL 2146 }; 2147 2148 static void cortex_a7_initfn(Object *obj) 2149 { 2150 ARMCPU *cpu = ARM_CPU(obj); 2151 2152 cpu->dtb_compatible = "arm,cortex-a7"; 2153 set_feature(&cpu->env, ARM_FEATURE_V7VE); 2154 set_feature(&cpu->env, ARM_FEATURE_VFP4); 2155 set_feature(&cpu->env, ARM_FEATURE_NEON); 2156 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2157 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 2158 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2159 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 2160 set_feature(&cpu->env, ARM_FEATURE_EL2); 2161 set_feature(&cpu->env, ARM_FEATURE_EL3); 2162 set_feature(&cpu->env, ARM_FEATURE_PMU); 2163 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 2164 cpu->midr = 0x410fc075; 2165 cpu->reset_fpsid = 0x41023075; 2166 cpu->isar.mvfr0 = 0x10110222; 2167 cpu->isar.mvfr1 = 0x11111111; 2168 cpu->ctr = 0x84448003; 2169 cpu->reset_sctlr = 0x00c50078; 2170 cpu->id_pfr0 = 0x00001131; 2171 cpu->id_pfr1 = 0x00011011; 2172 cpu->id_dfr0 = 0x02010555; 2173 cpu->id_afr0 = 0x00000000; 2174 cpu->id_mmfr0 = 0x10101105; 2175 cpu->id_mmfr1 = 0x40000000; 2176 cpu->id_mmfr2 = 0x01240000; 2177 cpu->id_mmfr3 = 0x02102211; 2178 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but 2179 * table 4-41 gives 0x02101110, which includes the arm div insns. 2180 */ 2181 cpu->isar.id_isar0 = 0x02101110; 2182 cpu->isar.id_isar1 = 0x13112111; 2183 cpu->isar.id_isar2 = 0x21232041; 2184 cpu->isar.id_isar3 = 0x11112131; 2185 cpu->isar.id_isar4 = 0x10011142; 2186 cpu->dbgdidr = 0x3515f005; 2187 cpu->clidr = 0x0a200023; 2188 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 2189 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 2190 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 2191 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 2192 } 2193 2194 static void cortex_a15_initfn(Object *obj) 2195 { 2196 ARMCPU *cpu = ARM_CPU(obj); 2197 2198 cpu->dtb_compatible = "arm,cortex-a15"; 2199 set_feature(&cpu->env, ARM_FEATURE_V7VE); 2200 set_feature(&cpu->env, ARM_FEATURE_VFP4); 2201 set_feature(&cpu->env, ARM_FEATURE_NEON); 2202 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2203 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 2204 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2205 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 2206 set_feature(&cpu->env, ARM_FEATURE_EL2); 2207 set_feature(&cpu->env, ARM_FEATURE_EL3); 2208 set_feature(&cpu->env, ARM_FEATURE_PMU); 2209 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 2210 cpu->midr = 0x412fc0f1; 2211 cpu->reset_fpsid = 0x410430f0; 2212 cpu->isar.mvfr0 = 0x10110222; 2213 cpu->isar.mvfr1 = 0x11111111; 2214 cpu->ctr = 0x8444c004; 2215 cpu->reset_sctlr = 0x00c50078; 2216 cpu->id_pfr0 = 0x00001131; 2217 cpu->id_pfr1 = 0x00011011; 2218 cpu->id_dfr0 = 0x02010555; 2219 cpu->id_afr0 = 0x00000000; 2220 cpu->id_mmfr0 = 0x10201105; 2221 cpu->id_mmfr1 = 0x20000000; 2222 cpu->id_mmfr2 = 0x01240000; 2223 cpu->id_mmfr3 = 0x02102211; 2224 cpu->isar.id_isar0 = 0x02101110; 2225 cpu->isar.id_isar1 = 0x13112111; 2226 cpu->isar.id_isar2 = 0x21232041; 2227 cpu->isar.id_isar3 = 0x11112131; 2228 cpu->isar.id_isar4 = 0x10011142; 2229 cpu->dbgdidr = 0x3515f021; 2230 cpu->clidr = 0x0a200023; 2231 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 2232 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 2233 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 2234 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 2235 } 2236 2237 static void ti925t_initfn(Object *obj) 2238 { 2239 ARMCPU *cpu = ARM_CPU(obj); 2240 set_feature(&cpu->env, ARM_FEATURE_V4T); 2241 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 2242 cpu->midr = ARM_CPUID_TI925T; 2243 cpu->ctr = 0x5109149; 2244 cpu->reset_sctlr = 0x00000070; 2245 } 2246 2247 static void sa1100_initfn(Object *obj) 2248 { 2249 ARMCPU *cpu = ARM_CPU(obj); 2250 2251 cpu->dtb_compatible = "intel,sa1100"; 2252 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 2253 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2254 cpu->midr = 0x4401A11B; 2255 cpu->reset_sctlr = 0x00000070; 2256 } 2257 2258 static void sa1110_initfn(Object *obj) 2259 { 2260 ARMCPU *cpu = ARM_CPU(obj); 2261 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 2262 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2263 cpu->midr = 0x6901B119; 2264 cpu->reset_sctlr = 0x00000070; 2265 } 2266 2267 static void pxa250_initfn(Object *obj) 2268 { 2269 ARMCPU *cpu = ARM_CPU(obj); 2270 2271 cpu->dtb_compatible = "marvell,xscale"; 2272 set_feature(&cpu->env, ARM_FEATURE_V5); 2273 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2274 cpu->midr = 0x69052100; 2275 cpu->ctr = 0xd172172; 2276 cpu->reset_sctlr = 0x00000078; 2277 } 2278 2279 static void pxa255_initfn(Object *obj) 2280 { 2281 ARMCPU *cpu = ARM_CPU(obj); 2282 2283 cpu->dtb_compatible = "marvell,xscale"; 2284 set_feature(&cpu->env, ARM_FEATURE_V5); 2285 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2286 cpu->midr = 0x69052d00; 2287 cpu->ctr = 0xd172172; 2288 cpu->reset_sctlr = 0x00000078; 2289 } 2290 2291 static void pxa260_initfn(Object *obj) 2292 { 2293 ARMCPU *cpu = ARM_CPU(obj); 2294 2295 cpu->dtb_compatible = "marvell,xscale"; 2296 set_feature(&cpu->env, ARM_FEATURE_V5); 2297 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2298 cpu->midr = 0x69052903; 2299 cpu->ctr = 0xd172172; 2300 cpu->reset_sctlr = 0x00000078; 2301 } 2302 2303 static void pxa261_initfn(Object *obj) 2304 { 2305 ARMCPU *cpu = ARM_CPU(obj); 2306 2307 cpu->dtb_compatible = "marvell,xscale"; 2308 set_feature(&cpu->env, ARM_FEATURE_V5); 2309 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2310 cpu->midr = 0x69052d05; 2311 cpu->ctr = 0xd172172; 2312 cpu->reset_sctlr = 0x00000078; 2313 } 2314 2315 static void pxa262_initfn(Object *obj) 2316 { 2317 ARMCPU *cpu = ARM_CPU(obj); 2318 2319 cpu->dtb_compatible = "marvell,xscale"; 2320 set_feature(&cpu->env, ARM_FEATURE_V5); 2321 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2322 cpu->midr = 0x69052d06; 2323 cpu->ctr = 0xd172172; 2324 cpu->reset_sctlr = 0x00000078; 2325 } 2326 2327 static void pxa270a0_initfn(Object *obj) 2328 { 2329 ARMCPU *cpu = ARM_CPU(obj); 2330 2331 cpu->dtb_compatible = "marvell,xscale"; 2332 set_feature(&cpu->env, ARM_FEATURE_V5); 2333 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2334 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2335 cpu->midr = 0x69054110; 2336 cpu->ctr = 0xd172172; 2337 cpu->reset_sctlr = 0x00000078; 2338 } 2339 2340 static void pxa270a1_initfn(Object *obj) 2341 { 2342 ARMCPU *cpu = ARM_CPU(obj); 2343 2344 cpu->dtb_compatible = "marvell,xscale"; 2345 set_feature(&cpu->env, ARM_FEATURE_V5); 2346 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2347 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2348 cpu->midr = 0x69054111; 2349 cpu->ctr = 0xd172172; 2350 cpu->reset_sctlr = 0x00000078; 2351 } 2352 2353 static void pxa270b0_initfn(Object *obj) 2354 { 2355 ARMCPU *cpu = ARM_CPU(obj); 2356 2357 cpu->dtb_compatible = "marvell,xscale"; 2358 set_feature(&cpu->env, ARM_FEATURE_V5); 2359 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2360 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2361 cpu->midr = 0x69054112; 2362 cpu->ctr = 0xd172172; 2363 cpu->reset_sctlr = 0x00000078; 2364 } 2365 2366 static void pxa270b1_initfn(Object *obj) 2367 { 2368 ARMCPU *cpu = ARM_CPU(obj); 2369 2370 cpu->dtb_compatible = "marvell,xscale"; 2371 set_feature(&cpu->env, ARM_FEATURE_V5); 2372 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2373 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2374 cpu->midr = 0x69054113; 2375 cpu->ctr = 0xd172172; 2376 cpu->reset_sctlr = 0x00000078; 2377 } 2378 2379 static void pxa270c0_initfn(Object *obj) 2380 { 2381 ARMCPU *cpu = ARM_CPU(obj); 2382 2383 cpu->dtb_compatible = "marvell,xscale"; 2384 set_feature(&cpu->env, ARM_FEATURE_V5); 2385 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2386 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2387 cpu->midr = 0x69054114; 2388 cpu->ctr = 0xd172172; 2389 cpu->reset_sctlr = 0x00000078; 2390 } 2391 2392 static void pxa270c5_initfn(Object *obj) 2393 { 2394 ARMCPU *cpu = ARM_CPU(obj); 2395 2396 cpu->dtb_compatible = "marvell,xscale"; 2397 set_feature(&cpu->env, ARM_FEATURE_V5); 2398 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2399 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2400 cpu->midr = 0x69054117; 2401 cpu->ctr = 0xd172172; 2402 cpu->reset_sctlr = 0x00000078; 2403 } 2404 2405 #ifndef TARGET_AARCH64 2406 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 2407 * otherwise, a CPU with as many features enabled as our emulation supports. 2408 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; 2409 * this only needs to handle 32 bits. 2410 */ 2411 static void arm_max_initfn(Object *obj) 2412 { 2413 ARMCPU *cpu = ARM_CPU(obj); 2414 2415 if (kvm_enabled()) { 2416 kvm_arm_set_cpu_features_from_host(cpu); 2417 } else { 2418 cortex_a15_initfn(obj); 2419 2420 /* old-style VFP short-vector support */ 2421 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 2422 2423 #ifdef CONFIG_USER_ONLY 2424 /* We don't set these in system emulation mode for the moment, 2425 * since we don't correctly set (all of) the ID registers to 2426 * advertise them. 2427 */ 2428 set_feature(&cpu->env, ARM_FEATURE_V8); 2429 { 2430 uint32_t t; 2431 2432 t = cpu->isar.id_isar5; 2433 t = FIELD_DP32(t, ID_ISAR5, AES, 2); 2434 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); 2435 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); 2436 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); 2437 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); 2438 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); 2439 cpu->isar.id_isar5 = t; 2440 2441 t = cpu->isar.id_isar6; 2442 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); 2443 t = FIELD_DP32(t, ID_ISAR6, DP, 1); 2444 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); 2445 t = FIELD_DP32(t, ID_ISAR6, SB, 1); 2446 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); 2447 cpu->isar.id_isar6 = t; 2448 2449 t = cpu->isar.mvfr2; 2450 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ 2451 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ 2452 cpu->isar.mvfr2 = t; 2453 2454 t = cpu->id_mmfr4; 2455 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ 2456 cpu->id_mmfr4 = t; 2457 } 2458 #endif 2459 } 2460 } 2461 #endif 2462 2463 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 2464 2465 struct ARMCPUInfo { 2466 const char *name; 2467 void (*initfn)(Object *obj); 2468 void (*class_init)(ObjectClass *oc, void *data); 2469 }; 2470 2471 static const ARMCPUInfo arm_cpus[] = { 2472 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 2473 { .name = "arm926", .initfn = arm926_initfn }, 2474 { .name = "arm946", .initfn = arm946_initfn }, 2475 { .name = "arm1026", .initfn = arm1026_initfn }, 2476 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 2477 * older core than plain "arm1136". In particular this does not 2478 * have the v6K features. 2479 */ 2480 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 2481 { .name = "arm1136", .initfn = arm1136_initfn }, 2482 { .name = "arm1176", .initfn = arm1176_initfn }, 2483 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 2484 { .name = "cortex-m0", .initfn = cortex_m0_initfn, 2485 .class_init = arm_v7m_class_init }, 2486 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 2487 .class_init = arm_v7m_class_init }, 2488 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 2489 .class_init = arm_v7m_class_init }, 2490 { .name = "cortex-m33", .initfn = cortex_m33_initfn, 2491 .class_init = arm_v7m_class_init }, 2492 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 2493 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, 2494 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 2495 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 2496 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 2497 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 2498 { .name = "ti925t", .initfn = ti925t_initfn }, 2499 { .name = "sa1100", .initfn = sa1100_initfn }, 2500 { .name = "sa1110", .initfn = sa1110_initfn }, 2501 { .name = "pxa250", .initfn = pxa250_initfn }, 2502 { .name = "pxa255", .initfn = pxa255_initfn }, 2503 { .name = "pxa260", .initfn = pxa260_initfn }, 2504 { .name = "pxa261", .initfn = pxa261_initfn }, 2505 { .name = "pxa262", .initfn = pxa262_initfn }, 2506 /* "pxa270" is an alias for "pxa270-a0" */ 2507 { .name = "pxa270", .initfn = pxa270a0_initfn }, 2508 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 2509 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 2510 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 2511 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 2512 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 2513 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 2514 #ifndef TARGET_AARCH64 2515 { .name = "max", .initfn = arm_max_initfn }, 2516 #endif 2517 #ifdef CONFIG_USER_ONLY 2518 { .name = "any", .initfn = arm_max_initfn }, 2519 #endif 2520 #endif 2521 { .name = NULL } 2522 }; 2523 2524 static Property arm_cpu_properties[] = { 2525 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 2526 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 2527 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 2528 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2529 mp_affinity, ARM64_AFFINITY_INVALID), 2530 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2531 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2532 DEFINE_PROP_END_OF_LIST() 2533 }; 2534 2535 static gchar *arm_gdb_arch_name(CPUState *cs) 2536 { 2537 ARMCPU *cpu = ARM_CPU(cs); 2538 CPUARMState *env = &cpu->env; 2539 2540 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2541 return g_strdup("iwmmxt"); 2542 } 2543 return g_strdup("arm"); 2544 } 2545 2546 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2547 { 2548 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2549 CPUClass *cc = CPU_CLASS(acc); 2550 DeviceClass *dc = DEVICE_CLASS(oc); 2551 2552 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2553 &acc->parent_realize); 2554 dc->props = arm_cpu_properties; 2555 2556 acc->parent_reset = cc->reset; 2557 cc->reset = arm_cpu_reset; 2558 2559 cc->class_by_name = arm_cpu_class_by_name; 2560 cc->has_work = arm_cpu_has_work; 2561 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 2562 cc->dump_state = arm_cpu_dump_state; 2563 cc->set_pc = arm_cpu_set_pc; 2564 cc->synchronize_from_tb = arm_cpu_synchronize_from_tb; 2565 cc->gdb_read_register = arm_cpu_gdb_read_register; 2566 cc->gdb_write_register = arm_cpu_gdb_write_register; 2567 #ifndef CONFIG_USER_ONLY 2568 cc->do_interrupt = arm_cpu_do_interrupt; 2569 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 2570 cc->asidx_from_attrs = arm_asidx_from_attrs; 2571 cc->vmsd = &vmstate_arm_cpu; 2572 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 2573 cc->write_elf64_note = arm_cpu_write_elf64_note; 2574 cc->write_elf32_note = arm_cpu_write_elf32_note; 2575 #endif 2576 cc->gdb_num_core_regs = 26; 2577 cc->gdb_core_xml_file = "arm-core.xml"; 2578 cc->gdb_arch_name = arm_gdb_arch_name; 2579 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2580 cc->gdb_stop_before_watchpoint = true; 2581 cc->disas_set_info = arm_disas_set_info; 2582 #ifdef CONFIG_TCG 2583 cc->tcg_initialize = arm_translate_init; 2584 cc->tlb_fill = arm_cpu_tlb_fill; 2585 cc->debug_excp_handler = arm_debug_excp_handler; 2586 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 2587 #if !defined(CONFIG_USER_ONLY) 2588 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 2589 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 2590 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 2591 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 2592 #endif 2593 } 2594 2595 #ifdef CONFIG_KVM 2596 static void arm_host_initfn(Object *obj) 2597 { 2598 ARMCPU *cpu = ARM_CPU(obj); 2599 2600 kvm_arm_set_cpu_features_from_host(cpu); 2601 arm_cpu_post_init(obj); 2602 } 2603 2604 static const TypeInfo host_arm_cpu_type_info = { 2605 .name = TYPE_ARM_HOST_CPU, 2606 #ifdef TARGET_AARCH64 2607 .parent = TYPE_AARCH64_CPU, 2608 #else 2609 .parent = TYPE_ARM_CPU, 2610 #endif 2611 .instance_init = arm_host_initfn, 2612 }; 2613 2614 #endif 2615 2616 static void arm_cpu_instance_init(Object *obj) 2617 { 2618 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2619 2620 acc->info->initfn(obj); 2621 arm_cpu_post_init(obj); 2622 } 2623 2624 static void cpu_register_class_init(ObjectClass *oc, void *data) 2625 { 2626 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2627 2628 acc->info = data; 2629 } 2630 2631 static void cpu_register(const ARMCPUInfo *info) 2632 { 2633 TypeInfo type_info = { 2634 .parent = TYPE_ARM_CPU, 2635 .instance_size = sizeof(ARMCPU), 2636 .instance_init = arm_cpu_instance_init, 2637 .class_size = sizeof(ARMCPUClass), 2638 .class_init = info->class_init ?: cpu_register_class_init, 2639 .class_data = (void *)info, 2640 }; 2641 2642 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2643 type_register(&type_info); 2644 g_free((void *)type_info.name); 2645 } 2646 2647 static const TypeInfo arm_cpu_type_info = { 2648 .name = TYPE_ARM_CPU, 2649 .parent = TYPE_CPU, 2650 .instance_size = sizeof(ARMCPU), 2651 .instance_init = arm_cpu_initfn, 2652 .instance_finalize = arm_cpu_finalizefn, 2653 .abstract = true, 2654 .class_size = sizeof(ARMCPUClass), 2655 .class_init = arm_cpu_class_init, 2656 }; 2657 2658 static const TypeInfo idau_interface_type_info = { 2659 .name = TYPE_IDAU_INTERFACE, 2660 .parent = TYPE_INTERFACE, 2661 .class_size = sizeof(IDAUInterfaceClass), 2662 }; 2663 2664 static void arm_cpu_register_types(void) 2665 { 2666 const ARMCPUInfo *info = arm_cpus; 2667 2668 type_register_static(&arm_cpu_type_info); 2669 type_register_static(&idau_interface_type_info); 2670 2671 while (info->name) { 2672 cpu_register(info); 2673 info++; 2674 } 2675 2676 #ifdef CONFIG_KVM 2677 type_register_static(&host_arm_cpu_type_info); 2678 #endif 2679 } 2680 2681 type_init(arm_cpu_register_types) 2682