1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu/timer.h" 24 #include "qemu/log.h" 25 #include "exec/page-vary.h" 26 #include "exec/tswap.h" 27 #include "target/arm/idau.h" 28 #include "qemu/module.h" 29 #include "qapi/error.h" 30 #include "cpu.h" 31 #ifdef CONFIG_TCG 32 #include "exec/translation-block.h" 33 #include "accel/tcg/cpu-ops.h" 34 #endif /* CONFIG_TCG */ 35 #include "internals.h" 36 #include "cpu-features.h" 37 #include "exec/target_page.h" 38 #include "hw/qdev-properties.h" 39 #if !defined(CONFIG_USER_ONLY) 40 #include "hw/loader.h" 41 #include "hw/boards.h" 42 #ifdef CONFIG_TCG 43 #include "hw/intc/armv7m_nvic.h" 44 #endif /* CONFIG_TCG */ 45 #endif /* !CONFIG_USER_ONLY */ 46 #include "system/tcg.h" 47 #include "system/qtest.h" 48 #include "system/hw_accel.h" 49 #include "kvm_arm.h" 50 #include "disas/capstone.h" 51 #include "fpu/softfloat.h" 52 #include "cpregs.h" 53 #include "target/arm/cpu-qom.h" 54 #include "target/arm/gtimer.h" 55 56 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 57 { 58 ARMCPU *cpu = ARM_CPU(cs); 59 CPUARMState *env = &cpu->env; 60 61 if (is_a64(env)) { 62 env->pc = value; 63 env->thumb = false; 64 } else { 65 env->regs[15] = value & ~1; 66 env->thumb = value & 1; 67 } 68 } 69 70 static vaddr arm_cpu_get_pc(CPUState *cs) 71 { 72 ARMCPU *cpu = ARM_CPU(cs); 73 CPUARMState *env = &cpu->env; 74 75 if (is_a64(env)) { 76 return env->pc; 77 } else { 78 return env->regs[15]; 79 } 80 } 81 82 #ifdef CONFIG_TCG 83 void arm_cpu_synchronize_from_tb(CPUState *cs, 84 const TranslationBlock *tb) 85 { 86 /* The program counter is always up to date with CF_PCREL. */ 87 if (!(tb_cflags(tb) & CF_PCREL)) { 88 CPUARMState *env = cpu_env(cs); 89 /* 90 * It's OK to look at env for the current mode here, because it's 91 * never possible for an AArch64 TB to chain to an AArch32 TB. 92 */ 93 if (is_a64(env)) { 94 env->pc = tb->pc; 95 } else { 96 env->regs[15] = tb->pc; 97 } 98 } 99 } 100 101 void arm_restore_state_to_opc(CPUState *cs, 102 const TranslationBlock *tb, 103 const uint64_t *data) 104 { 105 CPUARMState *env = cpu_env(cs); 106 107 if (is_a64(env)) { 108 if (tb_cflags(tb) & CF_PCREL) { 109 env->pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 110 } else { 111 env->pc = data[0]; 112 } 113 env->condexec_bits = 0; 114 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 115 } else { 116 if (tb_cflags(tb) & CF_PCREL) { 117 env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0]; 118 } else { 119 env->regs[15] = data[0]; 120 } 121 env->condexec_bits = data[1]; 122 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 123 } 124 } 125 126 int arm_cpu_mmu_index(CPUState *cs, bool ifetch) 127 { 128 return arm_env_mmu_index(cpu_env(cs)); 129 } 130 131 #endif /* CONFIG_TCG */ 132 133 #ifndef CONFIG_USER_ONLY 134 /* 135 * With SCTLR_ELx.NMI == 0, IRQ with Superpriority is masked identically with 136 * IRQ without Superpriority. Moreover, if the GIC is configured so that 137 * FEAT_GICv3_NMI is only set if FEAT_NMI is set, then we won't ever see 138 * CPU_INTERRUPT_*NMI anyway. So we might as well accept NMI here 139 * unconditionally. 140 */ 141 static bool arm_cpu_has_work(CPUState *cs) 142 { 143 ARMCPU *cpu = ARM_CPU(cs); 144 145 return (cpu->power_state != PSCI_OFF) 146 && cs->interrupt_request & 147 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 148 | CPU_INTERRUPT_NMI | CPU_INTERRUPT_VINMI | CPU_INTERRUPT_VFNMI 149 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR 150 | CPU_INTERRUPT_EXITTB); 151 } 152 #endif /* !CONFIG_USER_ONLY */ 153 154 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 155 void *opaque) 156 { 157 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 158 159 entry->hook = hook; 160 entry->opaque = opaque; 161 162 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 163 } 164 165 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 166 void *opaque) 167 { 168 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 169 170 entry->hook = hook; 171 entry->opaque = opaque; 172 173 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 174 } 175 176 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 177 { 178 /* Reset a single ARMCPRegInfo register */ 179 ARMCPRegInfo *ri = value; 180 ARMCPU *cpu = opaque; 181 182 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { 183 return; 184 } 185 186 if (ri->resetfn) { 187 ri->resetfn(&cpu->env, ri); 188 return; 189 } 190 191 /* A zero offset is never possible as it would be regs[0] 192 * so we use it to indicate that reset is being handled elsewhere. 193 * This is basically only used for fields in non-core coprocessors 194 * (like the pxa2xx ones). 195 */ 196 if (!ri->fieldoffset) { 197 return; 198 } 199 200 if (cpreg_field_is_64bit(ri)) { 201 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 202 } else { 203 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 204 } 205 } 206 207 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 208 { 209 /* Purely an assertion check: we've already done reset once, 210 * so now check that running the reset for the cpreg doesn't 211 * change its value. This traps bugs where two different cpregs 212 * both try to reset the same state field but to different values. 213 */ 214 ARMCPRegInfo *ri = value; 215 ARMCPU *cpu = opaque; 216 uint64_t oldvalue, newvalue; 217 218 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 219 return; 220 } 221 222 oldvalue = read_raw_cp_reg(&cpu->env, ri); 223 cp_reg_reset(key, value, opaque); 224 newvalue = read_raw_cp_reg(&cpu->env, ri); 225 assert(oldvalue == newvalue); 226 } 227 228 static void arm_cpu_reset_hold(Object *obj, ResetType type) 229 { 230 CPUState *cs = CPU(obj); 231 ARMCPU *cpu = ARM_CPU(cs); 232 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 233 CPUARMState *env = &cpu->env; 234 235 if (acc->parent_phases.hold) { 236 acc->parent_phases.hold(obj, type); 237 } 238 239 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 240 241 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 242 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 243 244 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 245 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 246 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 247 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 248 249 cpu->power_state = cs->start_powered_off ? PSCI_OFF : PSCI_ON; 250 251 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 252 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 253 } 254 255 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 256 /* 64 bit CPUs always start in 64 bit mode */ 257 env->aarch64 = true; 258 #if defined(CONFIG_USER_ONLY) 259 env->pstate = PSTATE_MODE_EL0t; 260 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 261 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 262 /* Enable all PAC keys. */ 263 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 264 SCTLR_EnDA | SCTLR_EnDB); 265 /* Trap on btype=3 for PACIxSP. */ 266 env->cp15.sctlr_el[1] |= SCTLR_BT0; 267 /* Trap on implementation defined registers. */ 268 if (cpu_isar_feature(aa64_tidcp1, cpu)) { 269 env->cp15.sctlr_el[1] |= SCTLR_TIDCP; 270 } 271 /* and to the FP/Neon instructions */ 272 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 273 CPACR_EL1, FPEN, 3); 274 /* and to the SVE instructions, with default vector length */ 275 if (cpu_isar_feature(aa64_sve, cpu)) { 276 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 277 CPACR_EL1, ZEN, 3); 278 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; 279 } 280 /* and for SME instructions, with default vector length, and TPIDR2 */ 281 if (cpu_isar_feature(aa64_sme, cpu)) { 282 env->cp15.sctlr_el[1] |= SCTLR_EnTP2; 283 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 284 CPACR_EL1, SMEN, 3); 285 env->vfp.smcr_el[1] = cpu->sme_default_vq - 1; 286 if (cpu_isar_feature(aa64_sme_fa64, cpu)) { 287 env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1], 288 SMCR, FA64, 1); 289 } 290 } 291 /* 292 * Enable 48-bit address space (TODO: take reserved_va into account). 293 * Enable TBI0 but not TBI1. 294 * Note that this must match useronly_clean_ptr. 295 */ 296 env->cp15.tcr_el[1] = 5 | (1ULL << 37); 297 298 /* Enable MTE */ 299 if (cpu_isar_feature(aa64_mte, cpu)) { 300 /* Enable tag access, but leave TCF0 as No Effect (0). */ 301 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 302 /* 303 * Exclude all tags, so that tag 0 is always used. 304 * This corresponds to Linux current->thread.gcr_incl = 0. 305 * 306 * Set RRND, so that helper_irg() will generate a seed later. 307 * Here in cpu_reset(), the crypto subsystem has not yet been 308 * initialized. 309 */ 310 env->cp15.gcr_el1 = 0x1ffff; 311 } 312 /* 313 * Disable access to SCXTNUM_EL0 from CSV2_1p2. 314 * This is not yet exposed from the Linux kernel in any way. 315 */ 316 env->cp15.sctlr_el[1] |= SCTLR_TSCXT; 317 /* Disable access to Debug Communication Channel (DCC). */ 318 env->cp15.mdscr_el1 |= 1 << 12; 319 /* Enable FEAT_MOPS */ 320 env->cp15.sctlr_el[1] |= SCTLR_MSCEN; 321 #else 322 /* Reset into the highest available EL */ 323 if (arm_feature(env, ARM_FEATURE_EL3)) { 324 env->pstate = PSTATE_MODE_EL3h; 325 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 326 env->pstate = PSTATE_MODE_EL2h; 327 } else { 328 env->pstate = PSTATE_MODE_EL1h; 329 } 330 331 /* Sample rvbar at reset. */ 332 env->cp15.rvbar = cpu->rvbar_prop; 333 env->pc = env->cp15.rvbar; 334 #endif 335 } else { 336 #if defined(CONFIG_USER_ONLY) 337 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 338 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 339 CPACR, CP10, 3); 340 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 341 CPACR, CP11, 3); 342 #endif 343 if (arm_feature(env, ARM_FEATURE_V8)) { 344 env->cp15.rvbar = cpu->rvbar_prop; 345 env->regs[15] = cpu->rvbar_prop; 346 } 347 } 348 349 #if defined(CONFIG_USER_ONLY) 350 env->uncached_cpsr = ARM_CPU_MODE_USR; 351 /* For user mode we must enable access to coprocessors */ 352 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 353 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 354 env->cp15.c15_cpar = 3; 355 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 356 env->cp15.c15_cpar = 1; 357 } 358 #else 359 360 /* 361 * If the highest available EL is EL2, AArch32 will start in Hyp 362 * mode; otherwise it starts in SVC. Note that if we start in 363 * AArch64 then these values in the uncached_cpsr will be ignored. 364 */ 365 if (arm_feature(env, ARM_FEATURE_EL2) && 366 !arm_feature(env, ARM_FEATURE_EL3)) { 367 env->uncached_cpsr = ARM_CPU_MODE_HYP; 368 } else { 369 env->uncached_cpsr = ARM_CPU_MODE_SVC; 370 } 371 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 372 373 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 374 * executing as AArch32 then check if highvecs are enabled and 375 * adjust the PC accordingly. 376 */ 377 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 378 env->regs[15] = 0xFFFF0000; 379 } 380 381 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 382 #endif 383 384 if (arm_feature(env, ARM_FEATURE_M)) { 385 #ifndef CONFIG_USER_ONLY 386 uint32_t initial_msp; /* Loaded from 0x0 */ 387 uint32_t initial_pc; /* Loaded from 0x4 */ 388 uint8_t *rom; 389 uint32_t vecbase; 390 #endif 391 392 if (cpu_isar_feature(aa32_lob, cpu)) { 393 /* 394 * LTPSIZE is constant 4 if MVE not implemented, and resets 395 * to an UNKNOWN value if MVE is implemented. We choose to 396 * always reset to 4. 397 */ 398 env->v7m.ltpsize = 4; 399 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 400 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 401 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 402 } 403 404 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 405 env->v7m.secure = true; 406 } else { 407 /* This bit resets to 0 if security is supported, but 1 if 408 * it is not. The bit is not present in v7M, but we set it 409 * here so we can avoid having to make checks on it conditional 410 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 411 */ 412 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 413 /* 414 * Set NSACR to indicate "NS access permitted to everything"; 415 * this avoids having to have all the tests of it being 416 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 417 * v8.1M the guest-visible value of NSACR in a CPU without the 418 * Security Extension is 0xcff. 419 */ 420 env->v7m.nsacr = 0xcff; 421 } 422 423 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 424 * that it resets to 1, so QEMU always does that rather than making 425 * it dependent on CPU model. In v8M it is RES1. 426 */ 427 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 428 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 429 if (arm_feature(env, ARM_FEATURE_V8)) { 430 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 431 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 432 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 433 } 434 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 435 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 436 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 437 } 438 439 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 440 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 441 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 442 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 443 } 444 445 #ifndef CONFIG_USER_ONLY 446 /* Unlike A/R profile, M profile defines the reset LR value */ 447 env->regs[14] = 0xffffffff; 448 449 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 450 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 451 452 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 453 vecbase = env->v7m.vecbase[env->v7m.secure]; 454 rom = rom_ptr_for_as(cs->as, vecbase, 8); 455 if (rom) { 456 /* Address zero is covered by ROM which hasn't yet been 457 * copied into physical memory. 458 */ 459 initial_msp = ldl_p(rom); 460 initial_pc = ldl_p(rom + 4); 461 } else { 462 /* Address zero not covered by a ROM blob, or the ROM blob 463 * is in non-modifiable memory and this is a second reset after 464 * it got copied into memory. In the latter case, rom_ptr 465 * will return a NULL pointer and we should use ldl_phys instead. 466 */ 467 initial_msp = ldl_phys(cs->as, vecbase); 468 initial_pc = ldl_phys(cs->as, vecbase + 4); 469 } 470 471 qemu_log_mask(CPU_LOG_INT, 472 "Loaded reset SP 0x%x PC 0x%x from vector table\n", 473 initial_msp, initial_pc); 474 475 env->regs[13] = initial_msp & 0xFFFFFFFC; 476 env->regs[15] = initial_pc & ~1; 477 env->thumb = initial_pc & 1; 478 #else 479 /* 480 * For user mode we run non-secure and with access to the FPU. 481 * The FPU context is active (ie does not need further setup) 482 * and is owned by non-secure. 483 */ 484 env->v7m.secure = false; 485 env->v7m.nsacr = 0xcff; 486 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 487 env->v7m.fpccr[M_REG_S] &= 488 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 489 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 490 #endif 491 } 492 493 /* M profile requires that reset clears the exclusive monitor; 494 * A profile does not, but clearing it makes more sense than having it 495 * set with an exclusive access on address zero. 496 */ 497 arm_clear_exclusive(env); 498 499 if (arm_feature(env, ARM_FEATURE_PMSA)) { 500 if (cpu->pmsav7_dregion > 0) { 501 if (arm_feature(env, ARM_FEATURE_V8)) { 502 memset(env->pmsav8.rbar[M_REG_NS], 0, 503 sizeof(*env->pmsav8.rbar[M_REG_NS]) 504 * cpu->pmsav7_dregion); 505 memset(env->pmsav8.rlar[M_REG_NS], 0, 506 sizeof(*env->pmsav8.rlar[M_REG_NS]) 507 * cpu->pmsav7_dregion); 508 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 509 memset(env->pmsav8.rbar[M_REG_S], 0, 510 sizeof(*env->pmsav8.rbar[M_REG_S]) 511 * cpu->pmsav7_dregion); 512 memset(env->pmsav8.rlar[M_REG_S], 0, 513 sizeof(*env->pmsav8.rlar[M_REG_S]) 514 * cpu->pmsav7_dregion); 515 } 516 } else if (arm_feature(env, ARM_FEATURE_V7)) { 517 memset(env->pmsav7.drbar, 0, 518 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 519 memset(env->pmsav7.drsr, 0, 520 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 521 memset(env->pmsav7.dracr, 0, 522 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 523 } 524 } 525 526 if (cpu->pmsav8r_hdregion > 0) { 527 memset(env->pmsav8.hprbar, 0, 528 sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion); 529 memset(env->pmsav8.hprlar, 0, 530 sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion); 531 } 532 533 env->pmsav7.rnr[M_REG_NS] = 0; 534 env->pmsav7.rnr[M_REG_S] = 0; 535 env->pmsav8.mair0[M_REG_NS] = 0; 536 env->pmsav8.mair0[M_REG_S] = 0; 537 env->pmsav8.mair1[M_REG_NS] = 0; 538 env->pmsav8.mair1[M_REG_S] = 0; 539 } 540 541 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 542 if (cpu->sau_sregion > 0) { 543 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 544 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 545 } 546 env->sau.rnr = 0; 547 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 548 * the Cortex-M33 does. 549 */ 550 env->sau.ctrl = 0; 551 } 552 553 set_flush_to_zero(1, &env->vfp.fp_status[FPST_STD]); 554 set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_STD]); 555 set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD]); 556 set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD_F16]); 557 set_default_nan_mode(1, &env->vfp.fp_status[FPST_ZA]); 558 set_default_nan_mode(1, &env->vfp.fp_status[FPST_ZA_F16]); 559 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32]); 560 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64]); 561 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_ZA]); 562 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD]); 563 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32_F16]); 564 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]); 565 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_ZA_F16]); 566 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD_F16]); 567 arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH]); 568 set_flush_to_zero(1, &env->vfp.fp_status[FPST_AH]); 569 set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_AH]); 570 arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH_F16]); 571 572 #ifndef CONFIG_USER_ONLY 573 if (kvm_enabled()) { 574 kvm_arm_reset_vcpu(cpu); 575 } 576 #endif 577 578 if (tcg_enabled()) { 579 hw_breakpoint_update_all(cpu); 580 hw_watchpoint_update_all(cpu); 581 582 arm_rebuild_hflags(env); 583 } 584 } 585 586 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el) 587 { 588 ARMCPU *cpu = ARM_CPU(cpustate); 589 CPUARMState *env = &cpu->env; 590 bool have_el3 = arm_feature(env, ARM_FEATURE_EL3); 591 bool have_el2 = arm_feature(env, ARM_FEATURE_EL2); 592 593 /* 594 * Check we have the EL we're aiming for. If that is the 595 * highest implemented EL, then cpu_reset has already done 596 * all the work. 597 */ 598 switch (target_el) { 599 case 3: 600 assert(have_el3); 601 return; 602 case 2: 603 assert(have_el2); 604 if (!have_el3) { 605 return; 606 } 607 break; 608 case 1: 609 if (!have_el3 && !have_el2) { 610 return; 611 } 612 break; 613 default: 614 g_assert_not_reached(); 615 } 616 617 if (have_el3) { 618 /* 619 * Set the EL3 state so code can run at EL2. This should match 620 * the requirements set by Linux in its booting spec. 621 */ 622 if (env->aarch64) { 623 env->cp15.scr_el3 |= SCR_RW; 624 if (cpu_isar_feature(aa64_pauth, cpu)) { 625 env->cp15.scr_el3 |= SCR_API | SCR_APK; 626 } 627 if (cpu_isar_feature(aa64_mte, cpu)) { 628 env->cp15.scr_el3 |= SCR_ATA; 629 } 630 if (cpu_isar_feature(aa64_sve, cpu)) { 631 env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK; 632 env->vfp.zcr_el[3] = 0xf; 633 } 634 if (cpu_isar_feature(aa64_sme, cpu)) { 635 env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK; 636 env->cp15.scr_el3 |= SCR_ENTP2; 637 env->vfp.smcr_el[3] = 0xf; 638 if (cpu_isar_feature(aa64_sme2, cpu)) { 639 env->vfp.smcr_el[3] |= R_SMCR_EZT0_MASK; 640 } 641 } 642 if (cpu_isar_feature(aa64_hcx, cpu)) { 643 env->cp15.scr_el3 |= SCR_HXEN; 644 } 645 if (cpu_isar_feature(aa64_fgt, cpu)) { 646 env->cp15.scr_el3 |= SCR_FGTEN; 647 } 648 } 649 650 if (target_el == 2) { 651 /* If the guest is at EL2 then Linux expects the HVC insn to work */ 652 env->cp15.scr_el3 |= SCR_HCE; 653 } 654 655 /* Put CPU into non-secure state */ 656 env->cp15.scr_el3 |= SCR_NS; 657 /* Set NSACR.{CP11,CP10} so NS can access the FPU */ 658 env->cp15.nsacr |= 3 << 10; 659 } 660 661 if (have_el2 && target_el < 2) { 662 /* Set EL2 state so code can run at EL1. */ 663 if (env->aarch64) { 664 env->cp15.hcr_el2 |= HCR_RW; 665 } 666 } 667 668 /* Set the CPU to the desired state */ 669 if (env->aarch64) { 670 env->pstate = aarch64_pstate_mode(target_el, true); 671 } else { 672 static const uint32_t mode_for_el[] = { 673 0, 674 ARM_CPU_MODE_SVC, 675 ARM_CPU_MODE_HYP, 676 ARM_CPU_MODE_SVC, 677 }; 678 679 cpsr_write(env, mode_for_el[target_el], CPSR_M, CPSRWriteRaw); 680 } 681 } 682 683 684 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 685 686 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 687 unsigned int target_el, 688 unsigned int cur_el, bool secure, 689 uint64_t hcr_el2) 690 { 691 CPUARMState *env = cpu_env(cs); 692 bool pstate_unmasked; 693 bool unmasked = false; 694 bool allIntMask = false; 695 696 /* 697 * Don't take exceptions if they target a lower EL. 698 * This check should catch any exceptions that would not be taken 699 * but left pending. 700 */ 701 if (cur_el > target_el) { 702 return false; 703 } 704 705 if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) && 706 env->cp15.sctlr_el[target_el] & SCTLR_NMI && cur_el == target_el) { 707 allIntMask = env->pstate & PSTATE_ALLINT || 708 ((env->cp15.sctlr_el[target_el] & SCTLR_SPINTMASK) && 709 (env->pstate & PSTATE_SP)); 710 } 711 712 switch (excp_idx) { 713 case EXCP_NMI: 714 pstate_unmasked = !allIntMask; 715 break; 716 717 case EXCP_VINMI: 718 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 719 /* VINMIs are only taken when hypervized. */ 720 return false; 721 } 722 return !allIntMask; 723 case EXCP_VFNMI: 724 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 725 /* VFNMIs are only taken when hypervized. */ 726 return false; 727 } 728 return !allIntMask; 729 case EXCP_FIQ: 730 pstate_unmasked = (!(env->daif & PSTATE_F)) && (!allIntMask); 731 break; 732 733 case EXCP_IRQ: 734 pstate_unmasked = (!(env->daif & PSTATE_I)) && (!allIntMask); 735 break; 736 737 case EXCP_VFIQ: 738 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 739 /* VFIQs are only taken when hypervized. */ 740 return false; 741 } 742 return !(env->daif & PSTATE_F) && (!allIntMask); 743 case EXCP_VIRQ: 744 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 745 /* VIRQs are only taken when hypervized. */ 746 return false; 747 } 748 return !(env->daif & PSTATE_I) && (!allIntMask); 749 case EXCP_VSERR: 750 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { 751 /* VIRQs are only taken when hypervized. */ 752 return false; 753 } 754 return !(env->daif & PSTATE_A); 755 default: 756 g_assert_not_reached(); 757 } 758 759 /* 760 * Use the target EL, current execution state and SCR/HCR settings to 761 * determine whether the corresponding CPSR bit is used to mask the 762 * interrupt. 763 */ 764 if ((target_el > cur_el) && (target_el != 1)) { 765 /* Exceptions targeting a higher EL may not be maskable */ 766 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 767 switch (target_el) { 768 case 2: 769 /* 770 * According to ARM DDI 0487H.a, an interrupt can be masked 771 * when HCR_E2H and HCR_TGE are both set regardless of the 772 * current Security state. Note that we need to revisit this 773 * part again once we need to support NMI. 774 */ 775 if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { 776 unmasked = true; 777 } 778 break; 779 case 3: 780 /* Interrupt cannot be masked when the target EL is 3 */ 781 unmasked = true; 782 break; 783 default: 784 g_assert_not_reached(); 785 } 786 } else { 787 /* 788 * The old 32-bit-only environment has a more complicated 789 * masking setup. HCR and SCR bits not only affect interrupt 790 * routing but also change the behaviour of masking. 791 */ 792 bool hcr, scr; 793 794 switch (excp_idx) { 795 case EXCP_FIQ: 796 /* 797 * If FIQs are routed to EL3 or EL2 then there are cases where 798 * we override the CPSR.F in determining if the exception is 799 * masked or not. If neither of these are set then we fall back 800 * to the CPSR.F setting otherwise we further assess the state 801 * below. 802 */ 803 hcr = hcr_el2 & HCR_FMO; 804 scr = (env->cp15.scr_el3 & SCR_FIQ); 805 806 /* 807 * When EL3 is 32-bit, the SCR.FW bit controls whether the 808 * CPSR.F bit masks FIQ interrupts when taken in non-secure 809 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 810 * when non-secure but only when FIQs are only routed to EL3. 811 */ 812 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 813 break; 814 case EXCP_IRQ: 815 /* 816 * When EL3 execution state is 32-bit, if HCR.IMO is set then 817 * we may override the CPSR.I masking when in non-secure state. 818 * The SCR.IRQ setting has already been taken into consideration 819 * when setting the target EL, so it does not have a further 820 * affect here. 821 */ 822 hcr = hcr_el2 & HCR_IMO; 823 scr = false; 824 break; 825 default: 826 g_assert_not_reached(); 827 } 828 829 if ((scr || hcr) && !secure) { 830 unmasked = true; 831 } 832 } 833 } 834 835 /* 836 * The PSTATE bits only mask the interrupt if we have not overridden the 837 * ability above. 838 */ 839 return unmasked || pstate_unmasked; 840 } 841 842 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 843 { 844 CPUARMState *env = cpu_env(cs); 845 uint32_t cur_el = arm_current_el(env); 846 bool secure = arm_is_secure(env); 847 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 848 uint32_t target_el; 849 uint32_t excp_idx; 850 851 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 852 853 if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) && 854 (arm_sctlr(env, cur_el) & SCTLR_NMI)) { 855 if (interrupt_request & CPU_INTERRUPT_NMI) { 856 excp_idx = EXCP_NMI; 857 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 858 if (arm_excp_unmasked(cs, excp_idx, target_el, 859 cur_el, secure, hcr_el2)) { 860 goto found; 861 } 862 } 863 if (interrupt_request & CPU_INTERRUPT_VINMI) { 864 excp_idx = EXCP_VINMI; 865 target_el = 1; 866 if (arm_excp_unmasked(cs, excp_idx, target_el, 867 cur_el, secure, hcr_el2)) { 868 goto found; 869 } 870 } 871 if (interrupt_request & CPU_INTERRUPT_VFNMI) { 872 excp_idx = EXCP_VFNMI; 873 target_el = 1; 874 if (arm_excp_unmasked(cs, excp_idx, target_el, 875 cur_el, secure, hcr_el2)) { 876 goto found; 877 } 878 } 879 } else { 880 /* 881 * NMI disabled: interrupts with superpriority are handled 882 * as if they didn't have it 883 */ 884 if (interrupt_request & CPU_INTERRUPT_NMI) { 885 interrupt_request |= CPU_INTERRUPT_HARD; 886 } 887 if (interrupt_request & CPU_INTERRUPT_VINMI) { 888 interrupt_request |= CPU_INTERRUPT_VIRQ; 889 } 890 if (interrupt_request & CPU_INTERRUPT_VFNMI) { 891 interrupt_request |= CPU_INTERRUPT_VFIQ; 892 } 893 } 894 895 if (interrupt_request & CPU_INTERRUPT_FIQ) { 896 excp_idx = EXCP_FIQ; 897 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 898 if (arm_excp_unmasked(cs, excp_idx, target_el, 899 cur_el, secure, hcr_el2)) { 900 goto found; 901 } 902 } 903 if (interrupt_request & CPU_INTERRUPT_HARD) { 904 excp_idx = EXCP_IRQ; 905 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 906 if (arm_excp_unmasked(cs, excp_idx, target_el, 907 cur_el, secure, hcr_el2)) { 908 goto found; 909 } 910 } 911 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 912 excp_idx = EXCP_VIRQ; 913 target_el = 1; 914 if (arm_excp_unmasked(cs, excp_idx, target_el, 915 cur_el, secure, hcr_el2)) { 916 goto found; 917 } 918 } 919 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 920 excp_idx = EXCP_VFIQ; 921 target_el = 1; 922 if (arm_excp_unmasked(cs, excp_idx, target_el, 923 cur_el, secure, hcr_el2)) { 924 goto found; 925 } 926 } 927 if (interrupt_request & CPU_INTERRUPT_VSERR) { 928 excp_idx = EXCP_VSERR; 929 target_el = 1; 930 if (arm_excp_unmasked(cs, excp_idx, target_el, 931 cur_el, secure, hcr_el2)) { 932 /* Taking a virtual abort clears HCR_EL2.VSE */ 933 env->cp15.hcr_el2 &= ~HCR_VSE; 934 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 935 goto found; 936 } 937 } 938 return false; 939 940 found: 941 cs->exception_index = excp_idx; 942 env->exception.target_el = target_el; 943 cs->cc->tcg_ops->do_interrupt(cs); 944 return true; 945 } 946 947 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 948 949 void arm_cpu_update_virq(ARMCPU *cpu) 950 { 951 /* 952 * Update the interrupt level for VIRQ, which is the logical OR of 953 * the HCR_EL2.VI bit and the input line level from the GIC. 954 */ 955 CPUARMState *env = &cpu->env; 956 CPUState *cs = CPU(cpu); 957 958 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VI) && 959 !(arm_hcrx_el2_eff(env) & HCRX_VINMI)) || 960 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 961 962 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 963 if (new_state) { 964 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 965 } else { 966 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 967 } 968 } 969 } 970 971 void arm_cpu_update_vfiq(ARMCPU *cpu) 972 { 973 /* 974 * Update the interrupt level for VFIQ, which is the logical OR of 975 * the HCR_EL2.VF bit and the input line level from the GIC. 976 */ 977 CPUARMState *env = &cpu->env; 978 CPUState *cs = CPU(cpu); 979 980 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VF) && 981 !(arm_hcrx_el2_eff(env) & HCRX_VFNMI)) || 982 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 983 984 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 985 if (new_state) { 986 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 987 } else { 988 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 989 } 990 } 991 } 992 993 void arm_cpu_update_vinmi(ARMCPU *cpu) 994 { 995 /* 996 * Update the interrupt level for VINMI, which is the logical OR of 997 * the HCRX_EL2.VINMI bit and the input line level from the GIC. 998 */ 999 CPUARMState *env = &cpu->env; 1000 CPUState *cs = CPU(cpu); 1001 1002 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VI) && 1003 (arm_hcrx_el2_eff(env) & HCRX_VINMI)) || 1004 (env->irq_line_state & CPU_INTERRUPT_VINMI); 1005 1006 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VINMI) != 0)) { 1007 if (new_state) { 1008 cpu_interrupt(cs, CPU_INTERRUPT_VINMI); 1009 } else { 1010 cpu_reset_interrupt(cs, CPU_INTERRUPT_VINMI); 1011 } 1012 } 1013 } 1014 1015 void arm_cpu_update_vfnmi(ARMCPU *cpu) 1016 { 1017 /* 1018 * Update the interrupt level for VFNMI, which is the HCRX_EL2.VFNMI bit. 1019 */ 1020 CPUARMState *env = &cpu->env; 1021 CPUState *cs = CPU(cpu); 1022 1023 bool new_state = (arm_hcr_el2_eff(env) & HCR_VF) && 1024 (arm_hcrx_el2_eff(env) & HCRX_VFNMI); 1025 1026 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFNMI) != 0)) { 1027 if (new_state) { 1028 cpu_interrupt(cs, CPU_INTERRUPT_VFNMI); 1029 } else { 1030 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFNMI); 1031 } 1032 } 1033 } 1034 1035 void arm_cpu_update_vserr(ARMCPU *cpu) 1036 { 1037 /* 1038 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. 1039 */ 1040 CPUARMState *env = &cpu->env; 1041 CPUState *cs = CPU(cpu); 1042 1043 bool new_state = env->cp15.hcr_el2 & HCR_VSE; 1044 1045 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { 1046 if (new_state) { 1047 cpu_interrupt(cs, CPU_INTERRUPT_VSERR); 1048 } else { 1049 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 1050 } 1051 } 1052 } 1053 1054 #ifndef CONFIG_USER_ONLY 1055 static void arm_cpu_set_irq(void *opaque, int irq, int level) 1056 { 1057 ARMCPU *cpu = opaque; 1058 CPUARMState *env = &cpu->env; 1059 CPUState *cs = CPU(cpu); 1060 static const int mask[] = { 1061 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 1062 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 1063 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 1064 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ, 1065 [ARM_CPU_NMI] = CPU_INTERRUPT_NMI, 1066 [ARM_CPU_VINMI] = CPU_INTERRUPT_VINMI, 1067 }; 1068 1069 if (!arm_feature(env, ARM_FEATURE_EL2) && 1070 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { 1071 /* 1072 * The GIC might tell us about VIRQ and VFIQ state, but if we don't 1073 * have EL2 support we don't care. (Unless the guest is doing something 1074 * silly this will only be calls saying "level is still 0".) 1075 */ 1076 return; 1077 } 1078 1079 if (level) { 1080 env->irq_line_state |= mask[irq]; 1081 } else { 1082 env->irq_line_state &= ~mask[irq]; 1083 } 1084 1085 switch (irq) { 1086 case ARM_CPU_VIRQ: 1087 arm_cpu_update_virq(cpu); 1088 break; 1089 case ARM_CPU_VFIQ: 1090 arm_cpu_update_vfiq(cpu); 1091 break; 1092 case ARM_CPU_VINMI: 1093 arm_cpu_update_vinmi(cpu); 1094 break; 1095 case ARM_CPU_IRQ: 1096 case ARM_CPU_FIQ: 1097 case ARM_CPU_NMI: 1098 if (level) { 1099 cpu_interrupt(cs, mask[irq]); 1100 } else { 1101 cpu_reset_interrupt(cs, mask[irq]); 1102 } 1103 break; 1104 default: 1105 g_assert_not_reached(); 1106 } 1107 } 1108 1109 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 1110 { 1111 ARMCPU *cpu = ARM_CPU(cs); 1112 CPUARMState *env = &cpu->env; 1113 1114 cpu_synchronize_state(cs); 1115 return arm_cpu_data_is_big_endian(env); 1116 } 1117 1118 #ifdef CONFIG_TCG 1119 bool arm_cpu_exec_halt(CPUState *cs) 1120 { 1121 bool leave_halt = cpu_has_work(cs); 1122 1123 if (leave_halt) { 1124 /* We're about to come out of WFI/WFE: disable the WFxT timer */ 1125 ARMCPU *cpu = ARM_CPU(cs); 1126 if (cpu->wfxt_timer) { 1127 timer_del(cpu->wfxt_timer); 1128 } 1129 } 1130 return leave_halt; 1131 } 1132 #endif 1133 1134 static void arm_wfxt_timer_cb(void *opaque) 1135 { 1136 ARMCPU *cpu = opaque; 1137 CPUState *cs = CPU(cpu); 1138 1139 /* 1140 * We expect the CPU to be halted; this will cause arm_cpu_is_work() 1141 * to return true (so we will come out of halt even with no other 1142 * pending interrupt), and the TCG accelerator's cpu_exec_interrupt() 1143 * function auto-clears the CPU_INTERRUPT_EXITTB flag for us. 1144 */ 1145 cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); 1146 } 1147 #endif 1148 1149 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 1150 { 1151 ARMCPU *ac = ARM_CPU(cpu); 1152 CPUARMState *env = &ac->env; 1153 bool sctlr_b = arm_sctlr_b(env); 1154 1155 if (is_a64(env)) { 1156 info->cap_arch = CS_ARCH_ARM64; 1157 info->cap_insn_unit = 4; 1158 info->cap_insn_split = 4; 1159 } else { 1160 int cap_mode; 1161 if (env->thumb) { 1162 info->cap_insn_unit = 2; 1163 info->cap_insn_split = 4; 1164 cap_mode = CS_MODE_THUMB; 1165 } else { 1166 info->cap_insn_unit = 4; 1167 info->cap_insn_split = 4; 1168 cap_mode = CS_MODE_ARM; 1169 } 1170 if (arm_feature(env, ARM_FEATURE_V8)) { 1171 cap_mode |= CS_MODE_V8; 1172 } 1173 if (arm_feature(env, ARM_FEATURE_M)) { 1174 cap_mode |= CS_MODE_MCLASS; 1175 } 1176 info->cap_arch = CS_ARCH_ARM; 1177 info->cap_mode = cap_mode; 1178 } 1179 1180 info->endian = BFD_ENDIAN_LITTLE; 1181 if (bswap_code(sctlr_b)) { 1182 info->endian = target_big_endian() ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 1183 } 1184 info->flags &= ~INSN_ARM_BE32; 1185 #ifndef CONFIG_USER_ONLY 1186 if (sctlr_b) { 1187 info->flags |= INSN_ARM_BE32; 1188 } 1189 #endif 1190 } 1191 1192 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1193 { 1194 ARMCPU *cpu = ARM_CPU(cs); 1195 CPUARMState *env = &cpu->env; 1196 uint32_t psr = pstate_read(env); 1197 int i, j; 1198 int el = arm_current_el(env); 1199 uint64_t hcr = arm_hcr_el2_eff(env); 1200 const char *ns_status; 1201 bool sve; 1202 1203 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 1204 for (i = 0; i < 32; i++) { 1205 if (i == 31) { 1206 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 1207 } else { 1208 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 1209 (i + 2) % 3 ? " " : "\n"); 1210 } 1211 } 1212 1213 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 1214 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1215 } else { 1216 ns_status = ""; 1217 } 1218 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 1219 psr, 1220 psr & PSTATE_N ? 'N' : '-', 1221 psr & PSTATE_Z ? 'Z' : '-', 1222 psr & PSTATE_C ? 'C' : '-', 1223 psr & PSTATE_V ? 'V' : '-', 1224 ns_status, 1225 el, 1226 psr & PSTATE_SP ? 'h' : 't'); 1227 1228 if (cpu_isar_feature(aa64_sme, cpu)) { 1229 qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c", 1230 env->svcr, 1231 (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), 1232 (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); 1233 } 1234 if (cpu_isar_feature(aa64_bti, cpu)) { 1235 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 1236 } 1237 qemu_fprintf(f, "%s%s%s", 1238 (hcr & HCR_NV) ? " NV" : "", 1239 (hcr & HCR_NV1) ? " NV1" : "", 1240 (hcr & HCR_NV2) ? " NV2" : ""); 1241 if (!(flags & CPU_DUMP_FPU)) { 1242 qemu_fprintf(f, "\n"); 1243 return; 1244 } 1245 if (fp_exception_el(env, el) != 0) { 1246 qemu_fprintf(f, " FPU disabled\n"); 1247 return; 1248 } 1249 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 1250 vfp_get_fpcr(env), vfp_get_fpsr(env)); 1251 1252 if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) { 1253 sve = sme_exception_el(env, el) == 0; 1254 } else if (cpu_isar_feature(aa64_sve, cpu)) { 1255 sve = sve_exception_el(env, el) == 0; 1256 } else { 1257 sve = false; 1258 } 1259 1260 if (sve) { 1261 int zcr_len = sve_vqm1_for_el(env, el); 1262 1263 for (i = 0; i <= FFR_PRED_NUM; i++) { 1264 bool eol; 1265 if (i == FFR_PRED_NUM) { 1266 qemu_fprintf(f, "FFR="); 1267 /* It's last, so end the line. */ 1268 eol = true; 1269 } else { 1270 qemu_fprintf(f, "P%02d=", i); 1271 switch (zcr_len) { 1272 case 0: 1273 eol = i % 8 == 7; 1274 break; 1275 case 1: 1276 eol = i % 6 == 5; 1277 break; 1278 case 2: 1279 case 3: 1280 eol = i % 3 == 2; 1281 break; 1282 default: 1283 /* More than one quadword per predicate. */ 1284 eol = true; 1285 break; 1286 } 1287 } 1288 for (j = zcr_len / 4; j >= 0; j--) { 1289 int digits; 1290 if (j * 4 + 4 <= zcr_len + 1) { 1291 digits = 16; 1292 } else { 1293 digits = (zcr_len % 4 + 1) * 4; 1294 } 1295 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 1296 env->vfp.pregs[i].p[j], 1297 j ? ":" : eol ? "\n" : " "); 1298 } 1299 } 1300 1301 if (zcr_len == 0) { 1302 /* 1303 * With vl=16, there are only 37 columns per register, 1304 * so output two registers per line. 1305 */ 1306 for (i = 0; i < 32; i++) { 1307 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1308 i, env->vfp.zregs[i].d[1], 1309 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 1310 } 1311 } else { 1312 for (i = 0; i < 32; i++) { 1313 qemu_fprintf(f, "Z%02d=", i); 1314 for (j = zcr_len; j >= 0; j--) { 1315 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 1316 env->vfp.zregs[i].d[j * 2 + 1], 1317 env->vfp.zregs[i].d[j * 2 + 0], 1318 j ? ":" : "\n"); 1319 } 1320 } 1321 } 1322 } else { 1323 for (i = 0; i < 32; i++) { 1324 uint64_t *q = aa64_vfp_qreg(env, i); 1325 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1326 i, q[1], q[0], (i & 1 ? "\n" : " ")); 1327 } 1328 } 1329 1330 if (cpu_isar_feature(aa64_sme, cpu) && 1331 FIELD_EX64(env->svcr, SVCR, ZA) && 1332 sme_exception_el(env, el) == 0) { 1333 int zcr_len = sve_vqm1_for_el_sm(env, el, true); 1334 int svl = (zcr_len + 1) * 16; 1335 int svl_lg10 = svl < 100 ? 2 : 3; 1336 1337 for (i = 0; i < svl; i++) { 1338 qemu_fprintf(f, "ZA[%0*d]=", svl_lg10, i); 1339 for (j = zcr_len; j >= 0; --j) { 1340 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%c", 1341 env->za_state.za[i].d[2 * j + 1], 1342 env->za_state.za[i].d[2 * j], 1343 j ? ':' : '\n'); 1344 } 1345 } 1346 } 1347 } 1348 1349 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1350 { 1351 ARMCPU *cpu = ARM_CPU(cs); 1352 CPUARMState *env = &cpu->env; 1353 int i; 1354 1355 if (is_a64(env)) { 1356 aarch64_cpu_dump_state(cs, f, flags); 1357 return; 1358 } 1359 1360 for (i = 0; i < 16; i++) { 1361 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 1362 if ((i % 4) == 3) { 1363 qemu_fprintf(f, "\n"); 1364 } else { 1365 qemu_fprintf(f, " "); 1366 } 1367 } 1368 1369 if (arm_feature(env, ARM_FEATURE_M)) { 1370 uint32_t xpsr = xpsr_read(env); 1371 const char *mode; 1372 const char *ns_status = ""; 1373 1374 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1375 ns_status = env->v7m.secure ? "S " : "NS "; 1376 } 1377 1378 if (xpsr & XPSR_EXCP) { 1379 mode = "handler"; 1380 } else { 1381 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 1382 mode = "unpriv-thread"; 1383 } else { 1384 mode = "priv-thread"; 1385 } 1386 } 1387 1388 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 1389 xpsr, 1390 xpsr & XPSR_N ? 'N' : '-', 1391 xpsr & XPSR_Z ? 'Z' : '-', 1392 xpsr & XPSR_C ? 'C' : '-', 1393 xpsr & XPSR_V ? 'V' : '-', 1394 xpsr & XPSR_T ? 'T' : 'A', 1395 ns_status, 1396 mode); 1397 } else { 1398 uint32_t psr = cpsr_read(env); 1399 const char *ns_status = ""; 1400 1401 if (arm_feature(env, ARM_FEATURE_EL3) && 1402 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1403 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1404 } 1405 1406 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1407 psr, 1408 psr & CPSR_N ? 'N' : '-', 1409 psr & CPSR_Z ? 'Z' : '-', 1410 psr & CPSR_C ? 'C' : '-', 1411 psr & CPSR_V ? 'V' : '-', 1412 psr & CPSR_T ? 'T' : 'A', 1413 ns_status, 1414 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1415 } 1416 1417 if (flags & CPU_DUMP_FPU) { 1418 int numvfpregs = 0; 1419 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1420 numvfpregs = 32; 1421 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1422 numvfpregs = 16; 1423 } 1424 for (i = 0; i < numvfpregs; i++) { 1425 uint64_t v = *aa32_vfp_dreg(env, i); 1426 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1427 i * 2, (uint32_t)v, 1428 i * 2 + 1, (uint32_t)(v >> 32), 1429 i, v); 1430 } 1431 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1432 if (cpu_isar_feature(aa32_mve, cpu)) { 1433 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1434 } 1435 } 1436 } 1437 1438 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz) 1439 { 1440 uint32_t Aff1 = idx / clustersz; 1441 uint32_t Aff0 = idx % clustersz; 1442 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1443 } 1444 1445 uint64_t arm_cpu_mp_affinity(ARMCPU *cpu) 1446 { 1447 return cpu->mp_affinity; 1448 } 1449 1450 static void arm_cpu_initfn(Object *obj) 1451 { 1452 ARMCPU *cpu = ARM_CPU(obj); 1453 1454 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, 1455 NULL, g_free); 1456 1457 QLIST_INIT(&cpu->pre_el_change_hooks); 1458 QLIST_INIT(&cpu->el_change_hooks); 1459 1460 #ifdef CONFIG_USER_ONLY 1461 # ifdef TARGET_AARCH64 1462 /* 1463 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME. 1464 * These values were chosen to fit within the default signal frame. 1465 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length, 1466 * and our corresponding cpu property. 1467 */ 1468 cpu->sve_default_vq = 4; 1469 cpu->sme_default_vq = 2; 1470 # endif 1471 #else 1472 /* Our inbound IRQ and FIQ lines */ 1473 if (kvm_enabled()) { 1474 /* 1475 * VIRQ, VFIQ, NMI, VINMI are unused with KVM but we add 1476 * them to maintain the same interface as non-KVM CPUs. 1477 */ 1478 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 6); 1479 } else { 1480 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 6); 1481 } 1482 1483 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1484 ARRAY_SIZE(cpu->gt_timer_outputs)); 1485 1486 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1487 "gicv3-maintenance-interrupt", 1); 1488 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1489 "pmu-interrupt", 1); 1490 #endif 1491 1492 /* DTB consumers generally don't in fact care what the 'compatible' 1493 * string is, so always provide some string and trust that a hypothetical 1494 * picky DTB consumer will also provide a helpful error message. 1495 */ 1496 cpu->dtb_compatible = "qemu,unknown"; 1497 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ 1498 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1499 1500 if (tcg_enabled() || hvf_enabled()) { 1501 /* TCG and HVF implement PSCI 1.1 */ 1502 cpu->psci_version = QEMU_PSCI_VERSION_1_1; 1503 } 1504 } 1505 1506 /* 1507 * 0 means "unset, use the default value". That default might vary depending 1508 * on the CPU type, and is set in the realize fn. 1509 */ 1510 #ifndef CONFIG_USER_ONLY 1511 static const Property arm_cpu_gt_cntfrq_property = 1512 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 0); 1513 1514 static const Property arm_cpu_reset_cbar_property = 1515 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1516 1517 static const Property arm_cpu_reset_hivecs_property = 1518 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1519 1520 static const Property arm_cpu_has_el2_property = 1521 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1522 1523 static const Property arm_cpu_has_el3_property = 1524 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1525 #endif 1526 1527 static const Property arm_cpu_cfgend_property = 1528 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1529 1530 static const Property arm_cpu_has_vfp_property = 1531 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1532 1533 static const Property arm_cpu_has_vfp_d32_property = 1534 DEFINE_PROP_BOOL("vfp-d32", ARMCPU, has_vfp_d32, true); 1535 1536 static const Property arm_cpu_has_neon_property = 1537 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1538 1539 static const Property arm_cpu_has_dsp_property = 1540 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1541 1542 #ifndef CONFIG_USER_ONLY 1543 static const Property arm_cpu_has_mpu_property = 1544 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1545 1546 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1547 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1548 * the right value for that particular CPU type, and we don't want 1549 * to override that with an incorrect constant value. 1550 */ 1551 static const Property arm_cpu_pmsav7_dregion_property = 1552 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1553 pmsav7_dregion, 1554 qdev_prop_uint32, uint32_t); 1555 #endif 1556 1557 static bool arm_get_pmu(Object *obj, Error **errp) 1558 { 1559 ARMCPU *cpu = ARM_CPU(obj); 1560 1561 return cpu->has_pmu; 1562 } 1563 1564 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1565 { 1566 ARMCPU *cpu = ARM_CPU(obj); 1567 1568 if (value) { 1569 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1570 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1571 return; 1572 } 1573 set_feature(&cpu->env, ARM_FEATURE_PMU); 1574 } else { 1575 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1576 } 1577 cpu->has_pmu = value; 1578 } 1579 1580 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) 1581 { 1582 ARMCPU *cpu = ARM_CPU(obj); 1583 1584 return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); 1585 } 1586 1587 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) 1588 { 1589 ARMCPU *cpu = ARM_CPU(obj); 1590 1591 /* 1592 * At this time, this property is only allowed if KVM is enabled. This 1593 * restriction allows us to avoid fixing up functionality that assumes a 1594 * uniform execution state like do_interrupt. 1595 */ 1596 if (value == false) { 1597 if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { 1598 error_setg(errp, "'aarch64' feature cannot be disabled " 1599 "unless KVM is enabled and 32-bit EL1 " 1600 "is supported"); 1601 return; 1602 } 1603 unset_feature(&cpu->env, ARM_FEATURE_AARCH64); 1604 } else { 1605 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 1606 } 1607 } 1608 1609 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1610 { 1611 /* 1612 * The exact approach to calculating guest ticks is: 1613 * 1614 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1615 * NANOSECONDS_PER_SECOND); 1616 * 1617 * We don't do that. Rather we intentionally use integer division 1618 * truncation below and in the caller for the conversion of host monotonic 1619 * time to guest ticks to provide the exact inverse for the semantics of 1620 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1621 * it loses precision when representing frequencies where 1622 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1623 * provide an exact inverse leads to scheduling timers with negative 1624 * periods, which in turn leads to sticky behaviour in the guest. 1625 * 1626 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1627 * cannot become zero. 1628 */ 1629 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1630 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1631 } 1632 1633 static void arm_cpu_propagate_feature_implications(ARMCPU *cpu) 1634 { 1635 CPUARMState *env = &cpu->env; 1636 bool no_aa32 = false; 1637 1638 /* 1639 * Some features automatically imply others: set the feature 1640 * bits explicitly for these cases. 1641 */ 1642 1643 if (arm_feature(env, ARM_FEATURE_M)) { 1644 set_feature(env, ARM_FEATURE_PMSA); 1645 } 1646 1647 if (arm_feature(env, ARM_FEATURE_V8)) { 1648 if (arm_feature(env, ARM_FEATURE_M)) { 1649 set_feature(env, ARM_FEATURE_V7); 1650 } else { 1651 set_feature(env, ARM_FEATURE_V7VE); 1652 } 1653 } 1654 1655 /* 1656 * There exist AArch64 cpus without AArch32 support. When KVM 1657 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1658 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1659 * As a general principle, we also do not make ID register 1660 * consistency checks anywhere unless using TCG, because only 1661 * for TCG would a consistency-check failure be a QEMU bug. 1662 */ 1663 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1664 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1665 } 1666 1667 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1668 /* 1669 * v7 Virtualization Extensions. In real hardware this implies 1670 * EL2 and also the presence of the Security Extensions. 1671 * For QEMU, for backwards-compatibility we implement some 1672 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1673 * include the various other features that V7VE implies. 1674 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1675 * Security Extensions is ARM_FEATURE_EL3. 1676 */ 1677 assert(!tcg_enabled() || no_aa32 || 1678 cpu_isar_feature(aa32_arm_div, cpu)); 1679 set_feature(env, ARM_FEATURE_LPAE); 1680 set_feature(env, ARM_FEATURE_V7); 1681 } 1682 if (arm_feature(env, ARM_FEATURE_V7)) { 1683 set_feature(env, ARM_FEATURE_VAPA); 1684 set_feature(env, ARM_FEATURE_THUMB2); 1685 set_feature(env, ARM_FEATURE_MPIDR); 1686 if (!arm_feature(env, ARM_FEATURE_M)) { 1687 set_feature(env, ARM_FEATURE_V6K); 1688 } else { 1689 set_feature(env, ARM_FEATURE_V6); 1690 } 1691 1692 /* 1693 * Always define VBAR for V7 CPUs even if it doesn't exist in 1694 * non-EL3 configs. This is needed by some legacy boards. 1695 */ 1696 set_feature(env, ARM_FEATURE_VBAR); 1697 } 1698 if (arm_feature(env, ARM_FEATURE_V6K)) { 1699 set_feature(env, ARM_FEATURE_V6); 1700 set_feature(env, ARM_FEATURE_MVFR); 1701 } 1702 if (arm_feature(env, ARM_FEATURE_V6)) { 1703 set_feature(env, ARM_FEATURE_V5); 1704 if (!arm_feature(env, ARM_FEATURE_M)) { 1705 assert(!tcg_enabled() || no_aa32 || 1706 cpu_isar_feature(aa32_jazelle, cpu)); 1707 set_feature(env, ARM_FEATURE_AUXCR); 1708 } 1709 } 1710 if (arm_feature(env, ARM_FEATURE_V5)) { 1711 set_feature(env, ARM_FEATURE_V4T); 1712 } 1713 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1714 set_feature(env, ARM_FEATURE_V7MP); 1715 } 1716 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1717 set_feature(env, ARM_FEATURE_CBAR); 1718 } 1719 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1720 !arm_feature(env, ARM_FEATURE_M)) { 1721 set_feature(env, ARM_FEATURE_THUMB_DSP); 1722 } 1723 } 1724 1725 static void arm_cpu_post_init(Object *obj) 1726 { 1727 ARMCPU *cpu = ARM_CPU(obj); 1728 1729 /* 1730 * Some features imply others. Figure this out now, because we 1731 * are going to look at the feature bits in deciding which 1732 * properties to add. 1733 */ 1734 arm_cpu_propagate_feature_implications(cpu); 1735 1736 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1737 object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64, 1738 aarch64_cpu_set_aarch64); 1739 object_property_set_description(obj, "aarch64", 1740 "Set on/off to enable/disable aarch64 " 1741 "execution state "); 1742 } 1743 #ifndef CONFIG_USER_ONLY 1744 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1745 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1746 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1747 } 1748 1749 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1750 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1751 } 1752 1753 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1754 object_property_add_uint64_ptr(obj, "rvbar", 1755 &cpu->rvbar_prop, 1756 OBJ_PROP_FLAG_READWRITE); 1757 } 1758 1759 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1760 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1761 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1762 */ 1763 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1764 1765 object_property_add_link(obj, "secure-memory", 1766 TYPE_MEMORY_REGION, 1767 (Object **)&cpu->secure_memory, 1768 qdev_prop_allow_set_link_before_realize, 1769 OBJ_PROP_LINK_STRONG); 1770 } 1771 1772 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1773 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1774 } 1775 #endif 1776 1777 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1778 cpu->has_pmu = true; 1779 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1780 } 1781 1782 /* 1783 * Allow user to turn off VFP and Neon support, but only for TCG -- 1784 * KVM does not currently allow us to lie to the guest about its 1785 * ID/feature registers, so the guest always sees what the host has. 1786 */ 1787 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1788 if (cpu_isar_feature(aa64_fp_simd, cpu)) { 1789 cpu->has_vfp = true; 1790 cpu->has_vfp_d32 = true; 1791 if (tcg_enabled() || qtest_enabled()) { 1792 qdev_property_add_static(DEVICE(obj), 1793 &arm_cpu_has_vfp_property); 1794 } 1795 } 1796 } else if (cpu_isar_feature(aa32_vfp, cpu)) { 1797 cpu->has_vfp = true; 1798 if (tcg_enabled() || qtest_enabled()) { 1799 qdev_property_add_static(DEVICE(obj), 1800 &arm_cpu_has_vfp_property); 1801 } 1802 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1803 cpu->has_vfp_d32 = true; 1804 /* 1805 * The permitted values of the SIMDReg bits [3:0] on 1806 * Armv8-A are either 0b0000 and 0b0010. On such CPUs, 1807 * make sure that has_vfp_d32 can not be set to false. 1808 */ 1809 if ((tcg_enabled() || qtest_enabled()) 1810 && !(arm_feature(&cpu->env, ARM_FEATURE_V8) 1811 && !arm_feature(&cpu->env, ARM_FEATURE_M))) { 1812 qdev_property_add_static(DEVICE(obj), 1813 &arm_cpu_has_vfp_d32_property); 1814 } 1815 } 1816 } 1817 1818 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1819 cpu->has_neon = true; 1820 if (!kvm_enabled()) { 1821 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1822 } 1823 } 1824 1825 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1826 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1827 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1828 } 1829 1830 #ifndef CONFIG_USER_ONLY 1831 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1832 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1833 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1834 qdev_property_add_static(DEVICE(obj), 1835 &arm_cpu_pmsav7_dregion_property); 1836 } 1837 } 1838 1839 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1840 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1841 qdev_prop_allow_set_link_before_realize, 1842 OBJ_PROP_LINK_STRONG); 1843 /* 1844 * M profile: initial value of the Secure VTOR. We can't just use 1845 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1846 * the property to be set after realize. 1847 */ 1848 object_property_add_uint32_ptr(obj, "init-svtor", 1849 &cpu->init_svtor, 1850 OBJ_PROP_FLAG_READWRITE); 1851 } 1852 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1853 /* 1854 * Initial value of the NS VTOR (for cores without the Security 1855 * extension, this is the only VTOR) 1856 */ 1857 object_property_add_uint32_ptr(obj, "init-nsvtor", 1858 &cpu->init_nsvtor, 1859 OBJ_PROP_FLAG_READWRITE); 1860 } 1861 1862 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ 1863 object_property_add_uint32_ptr(obj, "psci-conduit", 1864 &cpu->psci_conduit, 1865 OBJ_PROP_FLAG_READWRITE); 1866 1867 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1868 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1869 } 1870 1871 if (kvm_enabled()) { 1872 kvm_arm_add_vcpu_properties(cpu); 1873 } 1874 1875 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1876 cpu_isar_feature(aa64_mte, cpu)) { 1877 object_property_add_link(obj, "tag-memory", 1878 TYPE_MEMORY_REGION, 1879 (Object **)&cpu->tag_memory, 1880 qdev_prop_allow_set_link_before_realize, 1881 OBJ_PROP_LINK_STRONG); 1882 1883 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1884 object_property_add_link(obj, "secure-tag-memory", 1885 TYPE_MEMORY_REGION, 1886 (Object **)&cpu->secure_tag_memory, 1887 qdev_prop_allow_set_link_before_realize, 1888 OBJ_PROP_LINK_STRONG); 1889 } 1890 } 1891 #endif 1892 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1893 } 1894 1895 static void arm_cpu_finalizefn(Object *obj) 1896 { 1897 ARMCPU *cpu = ARM_CPU(obj); 1898 ARMELChangeHook *hook, *next; 1899 1900 g_hash_table_destroy(cpu->cp_regs); 1901 1902 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1903 QLIST_REMOVE(hook, node); 1904 g_free(hook); 1905 } 1906 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1907 QLIST_REMOVE(hook, node); 1908 g_free(hook); 1909 } 1910 #ifndef CONFIG_USER_ONLY 1911 if (cpu->pmu_timer) { 1912 timer_free(cpu->pmu_timer); 1913 } 1914 if (cpu->wfxt_timer) { 1915 timer_free(cpu->wfxt_timer); 1916 } 1917 #endif 1918 } 1919 1920 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1921 { 1922 Error *local_err = NULL; 1923 1924 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1925 arm_cpu_sve_finalize(cpu, &local_err); 1926 if (local_err != NULL) { 1927 error_propagate(errp, local_err); 1928 return; 1929 } 1930 1931 /* 1932 * FEAT_SME is not architecturally dependent on FEAT_SVE (unless 1933 * FEAT_SME_FA64 is present). However our implementation currently 1934 * assumes it, so if the user asked for sve=off then turn off SME also. 1935 * (KVM doesn't currently support SME at all.) 1936 */ 1937 if (cpu_isar_feature(aa64_sme, cpu) && !cpu_isar_feature(aa64_sve, cpu)) { 1938 object_property_set_bool(OBJECT(cpu), "sme", false, &error_abort); 1939 } 1940 1941 arm_cpu_sme_finalize(cpu, &local_err); 1942 if (local_err != NULL) { 1943 error_propagate(errp, local_err); 1944 return; 1945 } 1946 1947 arm_cpu_pauth_finalize(cpu, &local_err); 1948 if (local_err != NULL) { 1949 error_propagate(errp, local_err); 1950 return; 1951 } 1952 1953 arm_cpu_lpa2_finalize(cpu, &local_err); 1954 if (local_err != NULL) { 1955 error_propagate(errp, local_err); 1956 return; 1957 } 1958 } 1959 1960 if (kvm_enabled()) { 1961 kvm_arm_steal_time_finalize(cpu, &local_err); 1962 if (local_err != NULL) { 1963 error_propagate(errp, local_err); 1964 return; 1965 } 1966 } 1967 } 1968 1969 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1970 { 1971 CPUState *cs = CPU(dev); 1972 ARMCPU *cpu = ARM_CPU(dev); 1973 ARMISARegisters *isar = &cpu->isar; 1974 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1975 CPUARMState *env = &cpu->env; 1976 Error *local_err = NULL; 1977 1978 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 1979 /* Use pc-relative instructions in system-mode */ 1980 tcg_cflags_set(cs, CF_PCREL); 1981 #endif 1982 1983 /* If we needed to query the host kernel for the CPU features 1984 * then it's possible that might have failed in the initfn, but 1985 * this is the first point where we can report it. 1986 */ 1987 if (cpu->host_cpu_probe_failed) { 1988 if (!kvm_enabled() && !hvf_enabled()) { 1989 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1990 } else { 1991 error_setg(errp, "Failed to retrieve host CPU features"); 1992 } 1993 return; 1994 } 1995 1996 if (!cpu->gt_cntfrq_hz) { 1997 /* 1998 * 0 means "the board didn't set a value, use the default". (We also 1999 * get here for the CONFIG_USER_ONLY case.) 2000 * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before 2001 * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz, 2002 * which gives a 16ns tick period. 2003 * 2004 * We will use the back-compat value: 2005 * - for QEMU CPU types added before we standardized on 1GHz 2006 * - for versioned machine types with a version of 9.0 or earlier 2007 */ 2008 if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) || 2009 cpu->backcompat_cntfrq) { 2010 cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ; 2011 } else { 2012 cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ; 2013 } 2014 } 2015 2016 #ifndef CONFIG_USER_ONLY 2017 /* The NVIC and M-profile CPU are two halves of a single piece of 2018 * hardware; trying to use one without the other is a command line 2019 * error and will result in segfaults if not caught here. 2020 */ 2021 if (arm_feature(env, ARM_FEATURE_M)) { 2022 if (!env->nvic) { 2023 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 2024 return; 2025 } 2026 } else { 2027 if (env->nvic) { 2028 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 2029 return; 2030 } 2031 } 2032 2033 if (!tcg_enabled() && !qtest_enabled()) { 2034 /* 2035 * We assume that no accelerator except TCG (and the "not really an 2036 * accelerator" qtest) can handle these features, because Arm hardware 2037 * virtualization can't virtualize them. 2038 * 2039 * Catch all the cases which might cause us to create more than one 2040 * address space for the CPU (otherwise we will assert() later in 2041 * cpu_address_space_init()). 2042 */ 2043 if (arm_feature(env, ARM_FEATURE_M)) { 2044 error_setg(errp, 2045 "Cannot enable %s when using an M-profile guest CPU", 2046 current_accel_name()); 2047 return; 2048 } 2049 if (cpu->has_el3) { 2050 error_setg(errp, 2051 "Cannot enable %s when guest CPU has EL3 enabled", 2052 current_accel_name()); 2053 return; 2054 } 2055 if (cpu->tag_memory) { 2056 error_setg(errp, 2057 "Cannot enable %s when guest CPUs has MTE enabled", 2058 current_accel_name()); 2059 return; 2060 } 2061 } 2062 2063 { 2064 uint64_t scale = gt_cntfrq_period_ns(cpu); 2065 2066 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2067 arm_gt_ptimer_cb, cpu); 2068 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2069 arm_gt_vtimer_cb, cpu); 2070 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2071 arm_gt_htimer_cb, cpu); 2072 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2073 arm_gt_stimer_cb, cpu); 2074 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2075 arm_gt_hvtimer_cb, cpu); 2076 cpu->gt_timer[GTIMER_S_EL2_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2077 arm_gt_sel2timer_cb, cpu); 2078 cpu->gt_timer[GTIMER_S_EL2_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2079 arm_gt_sel2vtimer_cb, cpu); 2080 } 2081 #endif 2082 2083 cpu_exec_realizefn(cs, &local_err); 2084 if (local_err != NULL) { 2085 error_propagate(errp, local_err); 2086 return; 2087 } 2088 2089 arm_cpu_finalize_features(cpu, &local_err); 2090 if (local_err != NULL) { 2091 error_propagate(errp, local_err); 2092 return; 2093 } 2094 2095 #ifdef CONFIG_USER_ONLY 2096 /* 2097 * User mode relies on IC IVAU instructions to catch modification of 2098 * dual-mapped code. 2099 * 2100 * Clear CTR_EL0.DIC to ensure that software that honors these flags uses 2101 * IC IVAU even if the emulated processor does not normally require it. 2102 */ 2103 cpu->ctr = FIELD_DP64(cpu->ctr, CTR_EL0, DIC, 0); 2104 #endif 2105 2106 if (arm_feature(env, ARM_FEATURE_AARCH64) && 2107 cpu->has_vfp != cpu->has_neon) { 2108 /* 2109 * This is an architectural requirement for AArch64; AArch32 is 2110 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 2111 */ 2112 error_setg(errp, 2113 "AArch64 CPUs must have both VFP and Neon or neither"); 2114 return; 2115 } 2116 2117 if (cpu->has_vfp_d32 != cpu->has_neon) { 2118 error_setg(errp, "ARM CPUs must have both VFP-D32 and Neon or neither"); 2119 return; 2120 } 2121 2122 if (!cpu->has_vfp_d32) { 2123 uint32_t u; 2124 2125 u = cpu->isar.mvfr0; 2126 u = FIELD_DP32(u, MVFR0, SIMDREG, 1); /* 16 registers */ 2127 cpu->isar.mvfr0 = u; 2128 } 2129 2130 if (!cpu->has_vfp) { 2131 uint32_t u; 2132 2133 FIELD_DP64_IDREG(isar, ID_AA64ISAR1, JSCVT, 0); 2134 2135 FIELD_DP64_IDREG(isar, ID_AA64PFR0, FP, 0xf); 2136 2137 u = GET_IDREG(isar, ID_ISAR6); 2138 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 2139 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 2140 SET_IDREG(isar, ID_ISAR6, u); 2141 2142 u = cpu->isar.mvfr0; 2143 u = FIELD_DP32(u, MVFR0, FPSP, 0); 2144 u = FIELD_DP32(u, MVFR0, FPDP, 0); 2145 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 2146 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 2147 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 2148 if (!arm_feature(env, ARM_FEATURE_M)) { 2149 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 2150 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 2151 } 2152 cpu->isar.mvfr0 = u; 2153 2154 u = cpu->isar.mvfr1; 2155 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 2156 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 2157 u = FIELD_DP32(u, MVFR1, FPHP, 0); 2158 if (arm_feature(env, ARM_FEATURE_M)) { 2159 u = FIELD_DP32(u, MVFR1, FP16, 0); 2160 } 2161 cpu->isar.mvfr1 = u; 2162 2163 u = cpu->isar.mvfr2; 2164 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 2165 cpu->isar.mvfr2 = u; 2166 } 2167 2168 if (!cpu->has_neon) { 2169 uint64_t t; 2170 uint32_t u; 2171 2172 unset_feature(env, ARM_FEATURE_NEON); 2173 2174 t = GET_IDREG(isar, ID_AA64ISAR0); 2175 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); 2176 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); 2177 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); 2178 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); 2179 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); 2180 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); 2181 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 2182 SET_IDREG(isar, ID_AA64ISAR0, t); 2183 2184 t = GET_IDREG(isar, ID_AA64ISAR1); 2185 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 2186 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 2187 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 2188 SET_IDREG(isar, ID_AA64ISAR1, t); 2189 2190 FIELD_DP64_IDREG(isar, ID_AA64PFR0, ADVSIMD, 0xf); 2191 2192 u = GET_IDREG(isar, ID_ISAR5); 2193 u = FIELD_DP32(u, ID_ISAR5, AES, 0); 2194 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); 2195 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); 2196 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 2197 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 2198 SET_IDREG(isar, ID_ISAR5, u); 2199 2200 u = GET_IDREG(isar, ID_ISAR6); 2201 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 2202 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 2203 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 2204 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 2205 SET_IDREG(isar, ID_ISAR6, u); 2206 2207 if (!arm_feature(env, ARM_FEATURE_M)) { 2208 u = cpu->isar.mvfr1; 2209 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 2210 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 2211 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 2212 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 2213 cpu->isar.mvfr1 = u; 2214 2215 u = cpu->isar.mvfr2; 2216 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 2217 cpu->isar.mvfr2 = u; 2218 } 2219 } 2220 2221 if (!cpu->has_neon && !cpu->has_vfp) { 2222 uint32_t u; 2223 2224 FIELD_DP64_IDREG(isar, ID_AA64ISAR0, FHM, 0); 2225 2226 FIELD_DP64_IDREG(isar, ID_AA64ISAR1, FRINTTS, 0); 2227 2228 u = cpu->isar.mvfr0; 2229 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 2230 cpu->isar.mvfr0 = u; 2231 2232 /* Despite the name, this field covers both VFP and Neon */ 2233 u = cpu->isar.mvfr1; 2234 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 2235 cpu->isar.mvfr1 = u; 2236 } 2237 2238 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 2239 uint32_t u; 2240 2241 unset_feature(env, ARM_FEATURE_THUMB_DSP); 2242 2243 FIELD_DP32_IDREG(isar, ID_ISAR1, EXTEND, 1); 2244 2245 u = GET_IDREG(isar, ID_ISAR2); 2246 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 2247 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 2248 SET_IDREG(isar, ID_ISAR2, u); 2249 2250 u = GET_IDREG(isar, ID_ISAR3); 2251 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 2252 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 2253 SET_IDREG(isar, ID_ISAR3, u); 2254 } 2255 2256 2257 /* 2258 * We rely on no XScale CPU having VFP so we can use the same bits in the 2259 * TB flags field for VECSTRIDE and XSCALE_CPAR. 2260 */ 2261 assert(arm_feature(env, ARM_FEATURE_AARCH64) || 2262 !cpu_isar_feature(aa32_vfp_simd, cpu) || 2263 !arm_feature(env, ARM_FEATURE_XSCALE)); 2264 2265 #ifndef CONFIG_USER_ONLY 2266 { 2267 int pagebits; 2268 if (arm_feature(env, ARM_FEATURE_V7) && 2269 !arm_feature(env, ARM_FEATURE_M) && 2270 !arm_feature(env, ARM_FEATURE_PMSA)) { 2271 /* 2272 * v7VMSA drops support for the old ARMv5 tiny pages, 2273 * so we can use 4K pages. 2274 */ 2275 pagebits = 12; 2276 } else { 2277 /* 2278 * For CPUs which might have tiny 1K pages, or which have an 2279 * MPU and might have small region sizes, stick with 1K pages. 2280 */ 2281 pagebits = 10; 2282 } 2283 if (!set_preferred_target_page_bits(pagebits)) { 2284 /* 2285 * This can only ever happen for hotplugging a CPU, or if 2286 * the board code incorrectly creates a CPU which it has 2287 * promised via minimum_page_size that it will not. 2288 */ 2289 error_setg(errp, "This CPU requires a smaller page size " 2290 "than the system is using"); 2291 return; 2292 } 2293 } 2294 #endif 2295 2296 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 2297 * We don't support setting cluster ID ([16..23]) (known as Aff2 2298 * in later ARM ARM versions), or any of the higher affinity level fields, 2299 * so these bits always RAZ. 2300 */ 2301 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 2302 cpu->mp_affinity = arm_build_mp_affinity(cs->cpu_index, 2303 ARM_DEFAULT_CPUS_PER_CLUSTER); 2304 } 2305 2306 if (cpu->reset_hivecs) { 2307 cpu->reset_sctlr |= (1 << 13); 2308 } 2309 2310 if (cpu->cfgend) { 2311 if (arm_feature(env, ARM_FEATURE_V7)) { 2312 cpu->reset_sctlr |= SCTLR_EE; 2313 } else { 2314 cpu->reset_sctlr |= SCTLR_B; 2315 } 2316 } 2317 2318 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 2319 /* If the has_el3 CPU property is disabled then we need to disable the 2320 * feature. 2321 */ 2322 unset_feature(env, ARM_FEATURE_EL3); 2323 2324 /* 2325 * Disable the security extension feature bits in the processor 2326 * feature registers as well. 2327 */ 2328 FIELD_DP32_IDREG(isar, ID_PFR1, SECURITY, 0); 2329 FIELD_DP32_IDREG(isar, ID_DFR0, COPSDBG, 0); 2330 FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL3, 0); 2331 2332 /* Disable the realm management extension, which requires EL3. */ 2333 FIELD_DP64_IDREG(isar, ID_AA64PFR0, RME, 0); 2334 } 2335 2336 if (!cpu->has_el2) { 2337 unset_feature(env, ARM_FEATURE_EL2); 2338 } 2339 2340 if (!cpu->has_pmu) { 2341 unset_feature(env, ARM_FEATURE_PMU); 2342 } 2343 if (arm_feature(env, ARM_FEATURE_PMU)) { 2344 pmu_init(cpu); 2345 2346 if (!kvm_enabled()) { 2347 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 2348 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 2349 } 2350 2351 #ifndef CONFIG_USER_ONLY 2352 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 2353 cpu); 2354 #endif 2355 } else { 2356 FIELD_DP64_IDREG(isar, ID_AA64DFR0, PMUVER, 0); 2357 FIELD_DP32_IDREG(isar, ID_DFR0, PERFMON, 0); 2358 cpu->pmceid0 = 0; 2359 cpu->pmceid1 = 0; 2360 } 2361 2362 if (!arm_feature(env, ARM_FEATURE_EL2)) { 2363 /* 2364 * Disable the hypervisor feature bits in the processor feature 2365 * registers if we don't have EL2. 2366 */ 2367 FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL2, 0); 2368 FIELD_DP32_IDREG(isar, ID_PFR1, VIRTUALIZATION, 0); 2369 } 2370 2371 if (cpu_isar_feature(aa64_mte, cpu)) { 2372 /* 2373 * The architectural range of GM blocksize is 2-6, however qemu 2374 * doesn't support blocksize of 2 (see HELPER(ldgm)). 2375 */ 2376 if (tcg_enabled()) { 2377 assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6); 2378 } 2379 2380 #ifndef CONFIG_USER_ONLY 2381 /* 2382 * If we run with TCG and do not have tag-memory provided by 2383 * the machine, then reduce MTE support to instructions enabled at EL0. 2384 * This matches Cortex-A710 BROADCASTMTE input being LOW. 2385 */ 2386 if (tcg_enabled() && cpu->tag_memory == NULL) { 2387 FIELD_DP64_IDREG(isar, ID_AA64PFR1, MTE, 1); 2388 } 2389 2390 /* 2391 * If MTE is supported by the host, however it should not be 2392 * enabled on the guest (i.e mte=off), clear guest's MTE bits." 2393 */ 2394 if (kvm_enabled() && !cpu->kvm_mte) { 2395 FIELD_DP64_IDREG(isar, ID_AA64PFR1, MTE, 0); 2396 } 2397 #endif 2398 } 2399 2400 #ifndef CONFIG_USER_ONLY 2401 if (tcg_enabled() && cpu_isar_feature(aa64_wfxt, cpu)) { 2402 cpu->wfxt_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 2403 arm_wfxt_timer_cb, cpu); 2404 } 2405 #endif 2406 2407 if (tcg_enabled()) { 2408 /* 2409 * Don't report some architectural features in the ID registers 2410 * where TCG does not yet implement it (not even a minimal 2411 * stub version). This avoids guests falling over when they 2412 * try to access the non-existent system registers for them. 2413 */ 2414 /* FEAT_SPE (Statistical Profiling Extension) */ 2415 FIELD_DP64_IDREG(isar, ID_AA64DFR0, PMSVER, 0); 2416 /* FEAT_TRBE (Trace Buffer Extension) */ 2417 FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEBUFFER, 0); 2418 /* FEAT_TRF (Self-hosted Trace Extension) */ 2419 FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEFILT, 0); 2420 FIELD_DP32_IDREG(isar, ID_DFR0, TRACEFILT, 0); 2421 /* Trace Macrocell system register access */ 2422 FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEVER, 0); 2423 FIELD_DP32_IDREG(isar, ID_DFR0, COPTRC, 0); 2424 /* Memory mapped trace */ 2425 FIELD_DP32_IDREG(isar, ID_DFR0, MMAPTRC, 0); 2426 /* FEAT_AMU (Activity Monitors Extension) */ 2427 FIELD_DP64_IDREG(isar, ID_AA64PFR0, AMU, 0); 2428 FIELD_DP32_IDREG(isar, ID_PFR0, AMU, 0); 2429 /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ 2430 FIELD_DP64_IDREG(isar, ID_AA64PFR0, MPAM, 0); 2431 } 2432 2433 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 2434 * to false or by setting pmsav7-dregion to 0. 2435 */ 2436 if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) { 2437 cpu->has_mpu = false; 2438 cpu->pmsav7_dregion = 0; 2439 cpu->pmsav8r_hdregion = 0; 2440 } 2441 2442 if (arm_feature(env, ARM_FEATURE_PMSA) && 2443 arm_feature(env, ARM_FEATURE_V7)) { 2444 uint32_t nr = cpu->pmsav7_dregion; 2445 2446 if (nr > 0xff) { 2447 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 2448 return; 2449 } 2450 2451 if (nr) { 2452 if (arm_feature(env, ARM_FEATURE_V8)) { 2453 /* PMSAv8 */ 2454 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 2455 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 2456 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2457 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 2458 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 2459 } 2460 } else { 2461 env->pmsav7.drbar = g_new0(uint32_t, nr); 2462 env->pmsav7.drsr = g_new0(uint32_t, nr); 2463 env->pmsav7.dracr = g_new0(uint32_t, nr); 2464 } 2465 } 2466 2467 if (cpu->pmsav8r_hdregion > 0xff) { 2468 error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32, 2469 cpu->pmsav8r_hdregion); 2470 return; 2471 } 2472 2473 if (cpu->pmsav8r_hdregion) { 2474 env->pmsav8.hprbar = g_new0(uint32_t, 2475 cpu->pmsav8r_hdregion); 2476 env->pmsav8.hprlar = g_new0(uint32_t, 2477 cpu->pmsav8r_hdregion); 2478 } 2479 } 2480 2481 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2482 uint32_t nr = cpu->sau_sregion; 2483 2484 if (nr > 0xff) { 2485 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 2486 return; 2487 } 2488 2489 if (nr) { 2490 env->sau.rbar = g_new0(uint32_t, nr); 2491 env->sau.rlar = g_new0(uint32_t, nr); 2492 } 2493 } 2494 2495 if (arm_feature(env, ARM_FEATURE_EL3)) { 2496 set_feature(env, ARM_FEATURE_VBAR); 2497 } 2498 2499 #ifndef CONFIG_USER_ONLY 2500 if (tcg_enabled() && cpu_isar_feature(aa64_rme, cpu)) { 2501 arm_register_el_change_hook(cpu, >_rme_post_el_change, 0); 2502 } 2503 #endif 2504 2505 register_cp_regs_for_features(cpu); 2506 arm_cpu_register_gdb_regs_for_features(cpu); 2507 arm_cpu_register_gdb_commands(cpu); 2508 2509 init_cpreg_list(cpu); 2510 2511 #ifndef CONFIG_USER_ONLY 2512 MachineState *ms = MACHINE(qdev_get_machine()); 2513 unsigned int smp_cpus = ms->smp.cpus; 2514 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 2515 2516 /* 2517 * We must set cs->num_ases to the final value before 2518 * the first call to cpu_address_space_init. 2519 */ 2520 if (cpu->tag_memory != NULL) { 2521 cs->num_ases = 3 + has_secure; 2522 } else { 2523 cs->num_ases = 1 + has_secure; 2524 } 2525 2526 if (has_secure) { 2527 if (!cpu->secure_memory) { 2528 cpu->secure_memory = cs->memory; 2529 } 2530 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 2531 cpu->secure_memory); 2532 } 2533 2534 if (cpu->tag_memory != NULL) { 2535 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 2536 cpu->tag_memory); 2537 if (has_secure) { 2538 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 2539 cpu->secure_tag_memory); 2540 } 2541 } 2542 2543 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 2544 2545 /* No core_count specified, default to smp_cpus. */ 2546 if (cpu->core_count == -1) { 2547 cpu->core_count = smp_cpus; 2548 } 2549 #endif 2550 2551 if (tcg_enabled()) { 2552 int dcz_blocklen = 4 << cpu->dcz_blocksize; 2553 2554 /* 2555 * We only support DCZ blocklen that fits on one page. 2556 * 2557 * Architectually this is always true. However TARGET_PAGE_SIZE 2558 * is variable and, for compatibility with -machine virt-2.7, 2559 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 2560 * But even then, while the largest architectural DCZ blocklen 2561 * is 2KiB, no cpu actually uses such a large blocklen. 2562 */ 2563 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 2564 2565 /* 2566 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 2567 * both nibbles of each byte storing tag data may be written at once. 2568 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 2569 */ 2570 if (cpu_isar_feature(aa64_mte, cpu)) { 2571 assert(dcz_blocklen >= 2 * TAG_GRANULE); 2572 } 2573 } 2574 2575 qemu_init_vcpu(cs); 2576 cpu_reset(cs); 2577 2578 acc->parent_realize(dev, errp); 2579 } 2580 2581 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 2582 { 2583 ObjectClass *oc; 2584 char *typename; 2585 char **cpuname; 2586 const char *cpunamestr; 2587 2588 cpuname = g_strsplit(cpu_model, ",", 1); 2589 cpunamestr = cpuname[0]; 2590 #ifdef CONFIG_USER_ONLY 2591 /* For backwards compatibility usermode emulation allows "-cpu any", 2592 * which has the same semantics as "-cpu max". 2593 */ 2594 if (!strcmp(cpunamestr, "any")) { 2595 cpunamestr = "max"; 2596 } 2597 #endif 2598 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 2599 oc = object_class_by_name(typename); 2600 g_strfreev(cpuname); 2601 g_free(typename); 2602 2603 return oc; 2604 } 2605 2606 static const Property arm_cpu_properties[] = { 2607 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2608 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2609 mp_affinity, ARM64_AFFINITY_INVALID), 2610 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2611 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2612 /* True to default to the backward-compat old CNTFRQ rather than 1Ghz */ 2613 DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false), 2614 DEFINE_PROP_BOOL("backcompat-pauth-default-use-qarma5", ARMCPU, 2615 backcompat_pauth_default_use_qarma5, false), 2616 }; 2617 2618 static const gchar *arm_gdb_arch_name(CPUState *cs) 2619 { 2620 ARMCPU *cpu = ARM_CPU(cs); 2621 CPUARMState *env = &cpu->env; 2622 2623 if (arm_gdbstub_is_aarch64(cpu)) { 2624 return "aarch64"; 2625 } 2626 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2627 return "iwmmxt"; 2628 } 2629 return "arm"; 2630 } 2631 2632 static const char *arm_gdb_get_core_xml_file(CPUState *cs) 2633 { 2634 ARMCPU *cpu = ARM_CPU(cs); 2635 CPUARMState *env = &cpu->env; 2636 2637 if (arm_gdbstub_is_aarch64(cpu)) { 2638 return "aarch64-core.xml"; 2639 } 2640 if (arm_feature(env, ARM_FEATURE_M)) { 2641 return "arm-m-profile.xml"; 2642 } 2643 return "arm-core.xml"; 2644 } 2645 2646 #ifdef CONFIG_USER_ONLY 2647 /** 2648 * aarch64_untagged_addr: 2649 * 2650 * Remove any address tag from @x. This is explicitly related to the 2651 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 2652 * 2653 * There should be a better place to put this, but we need this in 2654 * include/accel/tcg/cpu-ldst.h, and not some place linux-user specific. 2655 * 2656 * Note that arm-*-user will never set tagged_addr_enable. 2657 */ 2658 static vaddr aarch64_untagged_addr(CPUState *cs, vaddr x) 2659 { 2660 CPUARMState *env = cpu_env(cs); 2661 if (env->tagged_addr_enable) { 2662 /* 2663 * TBI is enabled for userspace but not kernelspace addresses. 2664 * Only clear the tag if bit 55 is clear. 2665 */ 2666 x &= sextract64(x, 0, 56); 2667 } 2668 return x; 2669 } 2670 #else 2671 #include "hw/core/sysemu-cpu-ops.h" 2672 2673 static const struct SysemuCPUOps arm_sysemu_ops = { 2674 .has_work = arm_cpu_has_work, 2675 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2676 .asidx_from_attrs = arm_asidx_from_attrs, 2677 .write_elf32_note = arm_cpu_write_elf32_note, 2678 .write_elf64_note = arm_cpu_write_elf64_note, 2679 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2680 .legacy_vmsd = &vmstate_arm_cpu, 2681 }; 2682 #endif 2683 2684 #ifdef CONFIG_TCG 2685 #ifndef CONFIG_USER_ONLY 2686 static vaddr aprofile_pointer_wrap(CPUState *cs, int mmu_idx, 2687 vaddr result, vaddr base) 2688 { 2689 /* 2690 * The Stage2 and Phys indexes are only used for ptw on arm32, 2691 * and all pte's are aligned, so we never produce a wrap for these. 2692 * Double check that we're not truncating a 40-bit physical address. 2693 */ 2694 assert((unsigned)mmu_idx < (ARMMMUIdx_Stage2_S & ARM_MMU_IDX_COREIDX_MASK)); 2695 2696 if (!is_a64(cpu_env(cs))) { 2697 return (uint32_t)result; 2698 } 2699 2700 /* 2701 * TODO: For FEAT_CPA2, decide how to we want to resolve 2702 * Unpredictable_CPACHECK in AddressIncrement. 2703 */ 2704 return result; 2705 } 2706 #endif /* !CONFIG_USER_ONLY */ 2707 2708 static const TCGCPUOps arm_tcg_ops = { 2709 .mttcg_supported = true, 2710 /* ARM processors have a weak memory model */ 2711 .guest_default_memory_order = 0, 2712 2713 .initialize = arm_translate_init, 2714 .translate_code = arm_translate_code, 2715 .get_tb_cpu_state = arm_get_tb_cpu_state, 2716 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2717 .debug_excp_handler = arm_debug_excp_handler, 2718 .restore_state_to_opc = arm_restore_state_to_opc, 2719 .mmu_index = arm_cpu_mmu_index, 2720 2721 #ifdef CONFIG_USER_ONLY 2722 .record_sigsegv = arm_cpu_record_sigsegv, 2723 .record_sigbus = arm_cpu_record_sigbus, 2724 .untagged_addr = aarch64_untagged_addr, 2725 #else 2726 .tlb_fill_align = arm_cpu_tlb_fill_align, 2727 .pointer_wrap = aprofile_pointer_wrap, 2728 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2729 .cpu_exec_halt = arm_cpu_exec_halt, 2730 .cpu_exec_reset = cpu_reset, 2731 .do_interrupt = arm_cpu_do_interrupt, 2732 .do_transaction_failed = arm_cpu_do_transaction_failed, 2733 .do_unaligned_access = arm_cpu_do_unaligned_access, 2734 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2735 .debug_check_watchpoint = arm_debug_check_watchpoint, 2736 .debug_check_breakpoint = arm_debug_check_breakpoint, 2737 #endif /* !CONFIG_USER_ONLY */ 2738 }; 2739 #endif /* CONFIG_TCG */ 2740 2741 static void arm_cpu_class_init(ObjectClass *oc, const void *data) 2742 { 2743 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2744 CPUClass *cc = CPU_CLASS(acc); 2745 DeviceClass *dc = DEVICE_CLASS(oc); 2746 ResettableClass *rc = RESETTABLE_CLASS(oc); 2747 2748 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2749 &acc->parent_realize); 2750 2751 device_class_set_props(dc, arm_cpu_properties); 2752 2753 resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL, 2754 &acc->parent_phases); 2755 2756 cc->class_by_name = arm_cpu_class_by_name; 2757 cc->dump_state = arm_cpu_dump_state; 2758 cc->set_pc = arm_cpu_set_pc; 2759 cc->get_pc = arm_cpu_get_pc; 2760 cc->gdb_read_register = arm_cpu_gdb_read_register; 2761 cc->gdb_write_register = arm_cpu_gdb_write_register; 2762 #ifndef CONFIG_USER_ONLY 2763 cc->sysemu_ops = &arm_sysemu_ops; 2764 #endif 2765 cc->gdb_arch_name = arm_gdb_arch_name; 2766 cc->gdb_get_core_xml_file = arm_gdb_get_core_xml_file; 2767 cc->gdb_stop_before_watchpoint = true; 2768 cc->disas_set_info = arm_disas_set_info; 2769 2770 #ifdef CONFIG_TCG 2771 cc->tcg_ops = &arm_tcg_ops; 2772 #endif /* CONFIG_TCG */ 2773 } 2774 2775 static void arm_cpu_instance_init(Object *obj) 2776 { 2777 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2778 2779 acc->info->initfn(obj); 2780 arm_cpu_post_init(obj); 2781 } 2782 2783 static void cpu_register_class_init(ObjectClass *oc, const void *data) 2784 { 2785 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2786 CPUClass *cc = CPU_CLASS(acc); 2787 2788 acc->info = data; 2789 if (acc->info->deprecation_note) { 2790 cc->deprecation_note = acc->info->deprecation_note; 2791 } 2792 } 2793 2794 void arm_cpu_register(const ARMCPUInfo *info) 2795 { 2796 TypeInfo type_info = { 2797 .parent = TYPE_ARM_CPU, 2798 .instance_init = arm_cpu_instance_init, 2799 .class_init = info->class_init ?: cpu_register_class_init, 2800 .class_data = info, 2801 }; 2802 2803 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2804 type_register_static(&type_info); 2805 g_free((void *)type_info.name); 2806 } 2807 2808 static const TypeInfo arm_cpu_type_info = { 2809 .name = TYPE_ARM_CPU, 2810 .parent = TYPE_CPU, 2811 .instance_size = sizeof(ARMCPU), 2812 .instance_align = __alignof__(ARMCPU), 2813 .instance_init = arm_cpu_initfn, 2814 .instance_finalize = arm_cpu_finalizefn, 2815 .abstract = true, 2816 .class_size = sizeof(ARMCPUClass), 2817 .class_init = arm_cpu_class_init, 2818 }; 2819 2820 static void arm_cpu_register_types(void) 2821 { 2822 type_register_static(&arm_cpu_type_info); 2823 } 2824 2825 type_init(arm_cpu_register_types) 2826