1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu/timer.h" 24 #include "qemu/log.h" 25 #include "exec/page-vary.h" 26 #include "target/arm/idau.h" 27 #include "qemu/module.h" 28 #include "qapi/error.h" 29 #include "cpu.h" 30 #ifdef CONFIG_TCG 31 #include "exec/translation-block.h" 32 #include "accel/tcg/cpu-ops.h" 33 #endif /* CONFIG_TCG */ 34 #include "internals.h" 35 #include "cpu-features.h" 36 #include "exec/target_page.h" 37 #include "hw/qdev-properties.h" 38 #if !defined(CONFIG_USER_ONLY) 39 #include "hw/loader.h" 40 #include "hw/boards.h" 41 #ifdef CONFIG_TCG 42 #include "hw/intc/armv7m_nvic.h" 43 #endif /* CONFIG_TCG */ 44 #endif /* !CONFIG_USER_ONLY */ 45 #include "system/tcg.h" 46 #include "system/qtest.h" 47 #include "system/hw_accel.h" 48 #include "kvm_arm.h" 49 #include "disas/capstone.h" 50 #include "fpu/softfloat.h" 51 #include "cpregs.h" 52 #include "target/arm/cpu-qom.h" 53 #include "target/arm/gtimer.h" 54 55 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 56 { 57 ARMCPU *cpu = ARM_CPU(cs); 58 CPUARMState *env = &cpu->env; 59 60 if (is_a64(env)) { 61 env->pc = value; 62 env->thumb = false; 63 } else { 64 env->regs[15] = value & ~1; 65 env->thumb = value & 1; 66 } 67 } 68 69 static vaddr arm_cpu_get_pc(CPUState *cs) 70 { 71 ARMCPU *cpu = ARM_CPU(cs); 72 CPUARMState *env = &cpu->env; 73 74 if (is_a64(env)) { 75 return env->pc; 76 } else { 77 return env->regs[15]; 78 } 79 } 80 81 #ifdef CONFIG_TCG 82 void arm_cpu_synchronize_from_tb(CPUState *cs, 83 const TranslationBlock *tb) 84 { 85 /* The program counter is always up to date with CF_PCREL. */ 86 if (!(tb_cflags(tb) & CF_PCREL)) { 87 CPUARMState *env = cpu_env(cs); 88 /* 89 * It's OK to look at env for the current mode here, because it's 90 * never possible for an AArch64 TB to chain to an AArch32 TB. 91 */ 92 if (is_a64(env)) { 93 env->pc = tb->pc; 94 } else { 95 env->regs[15] = tb->pc; 96 } 97 } 98 } 99 100 void arm_restore_state_to_opc(CPUState *cs, 101 const TranslationBlock *tb, 102 const uint64_t *data) 103 { 104 CPUARMState *env = cpu_env(cs); 105 106 if (is_a64(env)) { 107 if (tb_cflags(tb) & CF_PCREL) { 108 env->pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 109 } else { 110 env->pc = data[0]; 111 } 112 env->condexec_bits = 0; 113 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 114 } else { 115 if (tb_cflags(tb) & CF_PCREL) { 116 env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0]; 117 } else { 118 env->regs[15] = data[0]; 119 } 120 env->condexec_bits = data[1]; 121 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 122 } 123 } 124 125 int arm_cpu_mmu_index(CPUState *cs, bool ifetch) 126 { 127 return arm_env_mmu_index(cpu_env(cs)); 128 } 129 130 #endif /* CONFIG_TCG */ 131 132 #ifndef CONFIG_USER_ONLY 133 /* 134 * With SCTLR_ELx.NMI == 0, IRQ with Superpriority is masked identically with 135 * IRQ without Superpriority. Moreover, if the GIC is configured so that 136 * FEAT_GICv3_NMI is only set if FEAT_NMI is set, then we won't ever see 137 * CPU_INTERRUPT_*NMI anyway. So we might as well accept NMI here 138 * unconditionally. 139 */ 140 static bool arm_cpu_has_work(CPUState *cs) 141 { 142 ARMCPU *cpu = ARM_CPU(cs); 143 144 return (cpu->power_state != PSCI_OFF) 145 && cs->interrupt_request & 146 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 147 | CPU_INTERRUPT_NMI | CPU_INTERRUPT_VINMI | CPU_INTERRUPT_VFNMI 148 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR 149 | CPU_INTERRUPT_EXITTB); 150 } 151 #endif /* !CONFIG_USER_ONLY */ 152 153 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 154 void *opaque) 155 { 156 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 157 158 entry->hook = hook; 159 entry->opaque = opaque; 160 161 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 162 } 163 164 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 165 void *opaque) 166 { 167 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 168 169 entry->hook = hook; 170 entry->opaque = opaque; 171 172 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 173 } 174 175 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 176 { 177 /* Reset a single ARMCPRegInfo register */ 178 ARMCPRegInfo *ri = value; 179 ARMCPU *cpu = opaque; 180 181 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { 182 return; 183 } 184 185 if (ri->resetfn) { 186 ri->resetfn(&cpu->env, ri); 187 return; 188 } 189 190 /* A zero offset is never possible as it would be regs[0] 191 * so we use it to indicate that reset is being handled elsewhere. 192 * This is basically only used for fields in non-core coprocessors 193 * (like the pxa2xx ones). 194 */ 195 if (!ri->fieldoffset) { 196 return; 197 } 198 199 if (cpreg_field_is_64bit(ri)) { 200 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 201 } else { 202 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 203 } 204 } 205 206 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 207 { 208 /* Purely an assertion check: we've already done reset once, 209 * so now check that running the reset for the cpreg doesn't 210 * change its value. This traps bugs where two different cpregs 211 * both try to reset the same state field but to different values. 212 */ 213 ARMCPRegInfo *ri = value; 214 ARMCPU *cpu = opaque; 215 uint64_t oldvalue, newvalue; 216 217 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 218 return; 219 } 220 221 oldvalue = read_raw_cp_reg(&cpu->env, ri); 222 cp_reg_reset(key, value, opaque); 223 newvalue = read_raw_cp_reg(&cpu->env, ri); 224 assert(oldvalue == newvalue); 225 } 226 227 static void arm_cpu_reset_hold(Object *obj, ResetType type) 228 { 229 CPUState *cs = CPU(obj); 230 ARMCPU *cpu = ARM_CPU(cs); 231 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 232 CPUARMState *env = &cpu->env; 233 234 if (acc->parent_phases.hold) { 235 acc->parent_phases.hold(obj, type); 236 } 237 238 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 239 240 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 241 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 242 243 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 244 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 245 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 246 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 247 248 cpu->power_state = cs->start_powered_off ? PSCI_OFF : PSCI_ON; 249 250 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 251 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 252 } 253 254 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 255 /* 64 bit CPUs always start in 64 bit mode */ 256 env->aarch64 = true; 257 #if defined(CONFIG_USER_ONLY) 258 env->pstate = PSTATE_MODE_EL0t; 259 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 260 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 261 /* Enable all PAC keys. */ 262 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 263 SCTLR_EnDA | SCTLR_EnDB); 264 /* Trap on btype=3 for PACIxSP. */ 265 env->cp15.sctlr_el[1] |= SCTLR_BT0; 266 /* Trap on implementation defined registers. */ 267 if (cpu_isar_feature(aa64_tidcp1, cpu)) { 268 env->cp15.sctlr_el[1] |= SCTLR_TIDCP; 269 } 270 /* and to the FP/Neon instructions */ 271 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 272 CPACR_EL1, FPEN, 3); 273 /* and to the SVE instructions, with default vector length */ 274 if (cpu_isar_feature(aa64_sve, cpu)) { 275 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 276 CPACR_EL1, ZEN, 3); 277 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; 278 } 279 /* and for SME instructions, with default vector length, and TPIDR2 */ 280 if (cpu_isar_feature(aa64_sme, cpu)) { 281 env->cp15.sctlr_el[1] |= SCTLR_EnTP2; 282 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 283 CPACR_EL1, SMEN, 3); 284 env->vfp.smcr_el[1] = cpu->sme_default_vq - 1; 285 if (cpu_isar_feature(aa64_sme_fa64, cpu)) { 286 env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1], 287 SMCR, FA64, 1); 288 } 289 } 290 /* 291 * Enable 48-bit address space (TODO: take reserved_va into account). 292 * Enable TBI0 but not TBI1. 293 * Note that this must match useronly_clean_ptr. 294 */ 295 env->cp15.tcr_el[1] = 5 | (1ULL << 37); 296 297 /* Enable MTE */ 298 if (cpu_isar_feature(aa64_mte, cpu)) { 299 /* Enable tag access, but leave TCF0 as No Effect (0). */ 300 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 301 /* 302 * Exclude all tags, so that tag 0 is always used. 303 * This corresponds to Linux current->thread.gcr_incl = 0. 304 * 305 * Set RRND, so that helper_irg() will generate a seed later. 306 * Here in cpu_reset(), the crypto subsystem has not yet been 307 * initialized. 308 */ 309 env->cp15.gcr_el1 = 0x1ffff; 310 } 311 /* 312 * Disable access to SCXTNUM_EL0 from CSV2_1p2. 313 * This is not yet exposed from the Linux kernel in any way. 314 */ 315 env->cp15.sctlr_el[1] |= SCTLR_TSCXT; 316 /* Disable access to Debug Communication Channel (DCC). */ 317 env->cp15.mdscr_el1 |= 1 << 12; 318 /* Enable FEAT_MOPS */ 319 env->cp15.sctlr_el[1] |= SCTLR_MSCEN; 320 #else 321 /* Reset into the highest available EL */ 322 if (arm_feature(env, ARM_FEATURE_EL3)) { 323 env->pstate = PSTATE_MODE_EL3h; 324 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 325 env->pstate = PSTATE_MODE_EL2h; 326 } else { 327 env->pstate = PSTATE_MODE_EL1h; 328 } 329 330 /* Sample rvbar at reset. */ 331 env->cp15.rvbar = cpu->rvbar_prop; 332 env->pc = env->cp15.rvbar; 333 #endif 334 } else { 335 #if defined(CONFIG_USER_ONLY) 336 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 337 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 338 CPACR, CP10, 3); 339 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 340 CPACR, CP11, 3); 341 #endif 342 if (arm_feature(env, ARM_FEATURE_V8)) { 343 env->cp15.rvbar = cpu->rvbar_prop; 344 env->regs[15] = cpu->rvbar_prop; 345 } 346 } 347 348 #if defined(CONFIG_USER_ONLY) 349 env->uncached_cpsr = ARM_CPU_MODE_USR; 350 /* For user mode we must enable access to coprocessors */ 351 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 352 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 353 env->cp15.c15_cpar = 3; 354 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 355 env->cp15.c15_cpar = 1; 356 } 357 #else 358 359 /* 360 * If the highest available EL is EL2, AArch32 will start in Hyp 361 * mode; otherwise it starts in SVC. Note that if we start in 362 * AArch64 then these values in the uncached_cpsr will be ignored. 363 */ 364 if (arm_feature(env, ARM_FEATURE_EL2) && 365 !arm_feature(env, ARM_FEATURE_EL3)) { 366 env->uncached_cpsr = ARM_CPU_MODE_HYP; 367 } else { 368 env->uncached_cpsr = ARM_CPU_MODE_SVC; 369 } 370 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 371 372 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 373 * executing as AArch32 then check if highvecs are enabled and 374 * adjust the PC accordingly. 375 */ 376 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 377 env->regs[15] = 0xFFFF0000; 378 } 379 380 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 381 #endif 382 383 if (arm_feature(env, ARM_FEATURE_M)) { 384 #ifndef CONFIG_USER_ONLY 385 uint32_t initial_msp; /* Loaded from 0x0 */ 386 uint32_t initial_pc; /* Loaded from 0x4 */ 387 uint8_t *rom; 388 uint32_t vecbase; 389 #endif 390 391 if (cpu_isar_feature(aa32_lob, cpu)) { 392 /* 393 * LTPSIZE is constant 4 if MVE not implemented, and resets 394 * to an UNKNOWN value if MVE is implemented. We choose to 395 * always reset to 4. 396 */ 397 env->v7m.ltpsize = 4; 398 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 399 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 400 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 401 } 402 403 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 404 env->v7m.secure = true; 405 } else { 406 /* This bit resets to 0 if security is supported, but 1 if 407 * it is not. The bit is not present in v7M, but we set it 408 * here so we can avoid having to make checks on it conditional 409 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 410 */ 411 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 412 /* 413 * Set NSACR to indicate "NS access permitted to everything"; 414 * this avoids having to have all the tests of it being 415 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 416 * v8.1M the guest-visible value of NSACR in a CPU without the 417 * Security Extension is 0xcff. 418 */ 419 env->v7m.nsacr = 0xcff; 420 } 421 422 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 423 * that it resets to 1, so QEMU always does that rather than making 424 * it dependent on CPU model. In v8M it is RES1. 425 */ 426 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 427 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 428 if (arm_feature(env, ARM_FEATURE_V8)) { 429 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 430 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 431 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 432 } 433 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 434 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 435 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 436 } 437 438 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 439 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 440 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 441 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 442 } 443 444 #ifndef CONFIG_USER_ONLY 445 /* Unlike A/R profile, M profile defines the reset LR value */ 446 env->regs[14] = 0xffffffff; 447 448 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 449 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 450 451 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 452 vecbase = env->v7m.vecbase[env->v7m.secure]; 453 rom = rom_ptr_for_as(cs->as, vecbase, 8); 454 if (rom) { 455 /* Address zero is covered by ROM which hasn't yet been 456 * copied into physical memory. 457 */ 458 initial_msp = ldl_p(rom); 459 initial_pc = ldl_p(rom + 4); 460 } else { 461 /* Address zero not covered by a ROM blob, or the ROM blob 462 * is in non-modifiable memory and this is a second reset after 463 * it got copied into memory. In the latter case, rom_ptr 464 * will return a NULL pointer and we should use ldl_phys instead. 465 */ 466 initial_msp = ldl_phys(cs->as, vecbase); 467 initial_pc = ldl_phys(cs->as, vecbase + 4); 468 } 469 470 qemu_log_mask(CPU_LOG_INT, 471 "Loaded reset SP 0x%x PC 0x%x from vector table\n", 472 initial_msp, initial_pc); 473 474 env->regs[13] = initial_msp & 0xFFFFFFFC; 475 env->regs[15] = initial_pc & ~1; 476 env->thumb = initial_pc & 1; 477 #else 478 /* 479 * For user mode we run non-secure and with access to the FPU. 480 * The FPU context is active (ie does not need further setup) 481 * and is owned by non-secure. 482 */ 483 env->v7m.secure = false; 484 env->v7m.nsacr = 0xcff; 485 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 486 env->v7m.fpccr[M_REG_S] &= 487 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 488 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 489 #endif 490 } 491 492 /* M profile requires that reset clears the exclusive monitor; 493 * A profile does not, but clearing it makes more sense than having it 494 * set with an exclusive access on address zero. 495 */ 496 arm_clear_exclusive(env); 497 498 if (arm_feature(env, ARM_FEATURE_PMSA)) { 499 if (cpu->pmsav7_dregion > 0) { 500 if (arm_feature(env, ARM_FEATURE_V8)) { 501 memset(env->pmsav8.rbar[M_REG_NS], 0, 502 sizeof(*env->pmsav8.rbar[M_REG_NS]) 503 * cpu->pmsav7_dregion); 504 memset(env->pmsav8.rlar[M_REG_NS], 0, 505 sizeof(*env->pmsav8.rlar[M_REG_NS]) 506 * cpu->pmsav7_dregion); 507 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 508 memset(env->pmsav8.rbar[M_REG_S], 0, 509 sizeof(*env->pmsav8.rbar[M_REG_S]) 510 * cpu->pmsav7_dregion); 511 memset(env->pmsav8.rlar[M_REG_S], 0, 512 sizeof(*env->pmsav8.rlar[M_REG_S]) 513 * cpu->pmsav7_dregion); 514 } 515 } else if (arm_feature(env, ARM_FEATURE_V7)) { 516 memset(env->pmsav7.drbar, 0, 517 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 518 memset(env->pmsav7.drsr, 0, 519 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 520 memset(env->pmsav7.dracr, 0, 521 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 522 } 523 } 524 525 if (cpu->pmsav8r_hdregion > 0) { 526 memset(env->pmsav8.hprbar, 0, 527 sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion); 528 memset(env->pmsav8.hprlar, 0, 529 sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion); 530 } 531 532 env->pmsav7.rnr[M_REG_NS] = 0; 533 env->pmsav7.rnr[M_REG_S] = 0; 534 env->pmsav8.mair0[M_REG_NS] = 0; 535 env->pmsav8.mair0[M_REG_S] = 0; 536 env->pmsav8.mair1[M_REG_NS] = 0; 537 env->pmsav8.mair1[M_REG_S] = 0; 538 } 539 540 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 541 if (cpu->sau_sregion > 0) { 542 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 543 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 544 } 545 env->sau.rnr = 0; 546 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 547 * the Cortex-M33 does. 548 */ 549 env->sau.ctrl = 0; 550 } 551 552 set_flush_to_zero(1, &env->vfp.fp_status[FPST_STD]); 553 set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_STD]); 554 set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD]); 555 set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD_F16]); 556 set_default_nan_mode(1, &env->vfp.fp_status[FPST_ZA]); 557 set_default_nan_mode(1, &env->vfp.fp_status[FPST_ZA_F16]); 558 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32]); 559 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64]); 560 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_ZA]); 561 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD]); 562 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32_F16]); 563 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]); 564 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_ZA_F16]); 565 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD_F16]); 566 arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH]); 567 set_flush_to_zero(1, &env->vfp.fp_status[FPST_AH]); 568 set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_AH]); 569 arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH_F16]); 570 571 #ifndef CONFIG_USER_ONLY 572 if (kvm_enabled()) { 573 kvm_arm_reset_vcpu(cpu); 574 } 575 #endif 576 577 if (tcg_enabled()) { 578 hw_breakpoint_update_all(cpu); 579 hw_watchpoint_update_all(cpu); 580 581 arm_rebuild_hflags(env); 582 } 583 } 584 585 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el) 586 { 587 ARMCPU *cpu = ARM_CPU(cpustate); 588 CPUARMState *env = &cpu->env; 589 bool have_el3 = arm_feature(env, ARM_FEATURE_EL3); 590 bool have_el2 = arm_feature(env, ARM_FEATURE_EL2); 591 592 /* 593 * Check we have the EL we're aiming for. If that is the 594 * highest implemented EL, then cpu_reset has already done 595 * all the work. 596 */ 597 switch (target_el) { 598 case 3: 599 assert(have_el3); 600 return; 601 case 2: 602 assert(have_el2); 603 if (!have_el3) { 604 return; 605 } 606 break; 607 case 1: 608 if (!have_el3 && !have_el2) { 609 return; 610 } 611 break; 612 default: 613 g_assert_not_reached(); 614 } 615 616 if (have_el3) { 617 /* 618 * Set the EL3 state so code can run at EL2. This should match 619 * the requirements set by Linux in its booting spec. 620 */ 621 if (env->aarch64) { 622 env->cp15.scr_el3 |= SCR_RW; 623 if (cpu_isar_feature(aa64_pauth, cpu)) { 624 env->cp15.scr_el3 |= SCR_API | SCR_APK; 625 } 626 if (cpu_isar_feature(aa64_mte, cpu)) { 627 env->cp15.scr_el3 |= SCR_ATA; 628 } 629 if (cpu_isar_feature(aa64_sve, cpu)) { 630 env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK; 631 env->vfp.zcr_el[3] = 0xf; 632 } 633 if (cpu_isar_feature(aa64_sme, cpu)) { 634 env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK; 635 env->cp15.scr_el3 |= SCR_ENTP2; 636 env->vfp.smcr_el[3] = 0xf; 637 if (cpu_isar_feature(aa64_sme2, cpu)) { 638 env->vfp.smcr_el[3] |= R_SMCR_EZT0_MASK; 639 } 640 } 641 if (cpu_isar_feature(aa64_hcx, cpu)) { 642 env->cp15.scr_el3 |= SCR_HXEN; 643 } 644 if (cpu_isar_feature(aa64_fgt, cpu)) { 645 env->cp15.scr_el3 |= SCR_FGTEN; 646 } 647 } 648 649 if (target_el == 2) { 650 /* If the guest is at EL2 then Linux expects the HVC insn to work */ 651 env->cp15.scr_el3 |= SCR_HCE; 652 } 653 654 /* Put CPU into non-secure state */ 655 env->cp15.scr_el3 |= SCR_NS; 656 /* Set NSACR.{CP11,CP10} so NS can access the FPU */ 657 env->cp15.nsacr |= 3 << 10; 658 } 659 660 if (have_el2 && target_el < 2) { 661 /* Set EL2 state so code can run at EL1. */ 662 if (env->aarch64) { 663 env->cp15.hcr_el2 |= HCR_RW; 664 } 665 } 666 667 /* Set the CPU to the desired state */ 668 if (env->aarch64) { 669 env->pstate = aarch64_pstate_mode(target_el, true); 670 } else { 671 static const uint32_t mode_for_el[] = { 672 0, 673 ARM_CPU_MODE_SVC, 674 ARM_CPU_MODE_HYP, 675 ARM_CPU_MODE_SVC, 676 }; 677 678 cpsr_write(env, mode_for_el[target_el], CPSR_M, CPSRWriteRaw); 679 } 680 } 681 682 683 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 684 685 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 686 unsigned int target_el, 687 unsigned int cur_el, bool secure, 688 uint64_t hcr_el2) 689 { 690 CPUARMState *env = cpu_env(cs); 691 bool pstate_unmasked; 692 bool unmasked = false; 693 bool allIntMask = false; 694 695 /* 696 * Don't take exceptions if they target a lower EL. 697 * This check should catch any exceptions that would not be taken 698 * but left pending. 699 */ 700 if (cur_el > target_el) { 701 return false; 702 } 703 704 if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) && 705 env->cp15.sctlr_el[target_el] & SCTLR_NMI && cur_el == target_el) { 706 allIntMask = env->pstate & PSTATE_ALLINT || 707 ((env->cp15.sctlr_el[target_el] & SCTLR_SPINTMASK) && 708 (env->pstate & PSTATE_SP)); 709 } 710 711 switch (excp_idx) { 712 case EXCP_NMI: 713 pstate_unmasked = !allIntMask; 714 break; 715 716 case EXCP_VINMI: 717 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 718 /* VINMIs are only taken when hypervized. */ 719 return false; 720 } 721 return !allIntMask; 722 case EXCP_VFNMI: 723 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 724 /* VFNMIs are only taken when hypervized. */ 725 return false; 726 } 727 return !allIntMask; 728 case EXCP_FIQ: 729 pstate_unmasked = (!(env->daif & PSTATE_F)) && (!allIntMask); 730 break; 731 732 case EXCP_IRQ: 733 pstate_unmasked = (!(env->daif & PSTATE_I)) && (!allIntMask); 734 break; 735 736 case EXCP_VFIQ: 737 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 738 /* VFIQs are only taken when hypervized. */ 739 return false; 740 } 741 return !(env->daif & PSTATE_F) && (!allIntMask); 742 case EXCP_VIRQ: 743 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 744 /* VIRQs are only taken when hypervized. */ 745 return false; 746 } 747 return !(env->daif & PSTATE_I) && (!allIntMask); 748 case EXCP_VSERR: 749 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { 750 /* VIRQs are only taken when hypervized. */ 751 return false; 752 } 753 return !(env->daif & PSTATE_A); 754 default: 755 g_assert_not_reached(); 756 } 757 758 /* 759 * Use the target EL, current execution state and SCR/HCR settings to 760 * determine whether the corresponding CPSR bit is used to mask the 761 * interrupt. 762 */ 763 if ((target_el > cur_el) && (target_el != 1)) { 764 /* Exceptions targeting a higher EL may not be maskable */ 765 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 766 switch (target_el) { 767 case 2: 768 /* 769 * According to ARM DDI 0487H.a, an interrupt can be masked 770 * when HCR_E2H and HCR_TGE are both set regardless of the 771 * current Security state. Note that we need to revisit this 772 * part again once we need to support NMI. 773 */ 774 if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { 775 unmasked = true; 776 } 777 break; 778 case 3: 779 /* Interrupt cannot be masked when the target EL is 3 */ 780 unmasked = true; 781 break; 782 default: 783 g_assert_not_reached(); 784 } 785 } else { 786 /* 787 * The old 32-bit-only environment has a more complicated 788 * masking setup. HCR and SCR bits not only affect interrupt 789 * routing but also change the behaviour of masking. 790 */ 791 bool hcr, scr; 792 793 switch (excp_idx) { 794 case EXCP_FIQ: 795 /* 796 * If FIQs are routed to EL3 or EL2 then there are cases where 797 * we override the CPSR.F in determining if the exception is 798 * masked or not. If neither of these are set then we fall back 799 * to the CPSR.F setting otherwise we further assess the state 800 * below. 801 */ 802 hcr = hcr_el2 & HCR_FMO; 803 scr = (env->cp15.scr_el3 & SCR_FIQ); 804 805 /* 806 * When EL3 is 32-bit, the SCR.FW bit controls whether the 807 * CPSR.F bit masks FIQ interrupts when taken in non-secure 808 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 809 * when non-secure but only when FIQs are only routed to EL3. 810 */ 811 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 812 break; 813 case EXCP_IRQ: 814 /* 815 * When EL3 execution state is 32-bit, if HCR.IMO is set then 816 * we may override the CPSR.I masking when in non-secure state. 817 * The SCR.IRQ setting has already been taken into consideration 818 * when setting the target EL, so it does not have a further 819 * affect here. 820 */ 821 hcr = hcr_el2 & HCR_IMO; 822 scr = false; 823 break; 824 default: 825 g_assert_not_reached(); 826 } 827 828 if ((scr || hcr) && !secure) { 829 unmasked = true; 830 } 831 } 832 } 833 834 /* 835 * The PSTATE bits only mask the interrupt if we have not overridden the 836 * ability above. 837 */ 838 return unmasked || pstate_unmasked; 839 } 840 841 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 842 { 843 CPUARMState *env = cpu_env(cs); 844 uint32_t cur_el = arm_current_el(env); 845 bool secure = arm_is_secure(env); 846 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 847 uint32_t target_el; 848 uint32_t excp_idx; 849 850 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 851 852 if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) && 853 (arm_sctlr(env, cur_el) & SCTLR_NMI)) { 854 if (interrupt_request & CPU_INTERRUPT_NMI) { 855 excp_idx = EXCP_NMI; 856 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 857 if (arm_excp_unmasked(cs, excp_idx, target_el, 858 cur_el, secure, hcr_el2)) { 859 goto found; 860 } 861 } 862 if (interrupt_request & CPU_INTERRUPT_VINMI) { 863 excp_idx = EXCP_VINMI; 864 target_el = 1; 865 if (arm_excp_unmasked(cs, excp_idx, target_el, 866 cur_el, secure, hcr_el2)) { 867 goto found; 868 } 869 } 870 if (interrupt_request & CPU_INTERRUPT_VFNMI) { 871 excp_idx = EXCP_VFNMI; 872 target_el = 1; 873 if (arm_excp_unmasked(cs, excp_idx, target_el, 874 cur_el, secure, hcr_el2)) { 875 goto found; 876 } 877 } 878 } else { 879 /* 880 * NMI disabled: interrupts with superpriority are handled 881 * as if they didn't have it 882 */ 883 if (interrupt_request & CPU_INTERRUPT_NMI) { 884 interrupt_request |= CPU_INTERRUPT_HARD; 885 } 886 if (interrupt_request & CPU_INTERRUPT_VINMI) { 887 interrupt_request |= CPU_INTERRUPT_VIRQ; 888 } 889 if (interrupt_request & CPU_INTERRUPT_VFNMI) { 890 interrupt_request |= CPU_INTERRUPT_VFIQ; 891 } 892 } 893 894 if (interrupt_request & CPU_INTERRUPT_FIQ) { 895 excp_idx = EXCP_FIQ; 896 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 897 if (arm_excp_unmasked(cs, excp_idx, target_el, 898 cur_el, secure, hcr_el2)) { 899 goto found; 900 } 901 } 902 if (interrupt_request & CPU_INTERRUPT_HARD) { 903 excp_idx = EXCP_IRQ; 904 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 905 if (arm_excp_unmasked(cs, excp_idx, target_el, 906 cur_el, secure, hcr_el2)) { 907 goto found; 908 } 909 } 910 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 911 excp_idx = EXCP_VIRQ; 912 target_el = 1; 913 if (arm_excp_unmasked(cs, excp_idx, target_el, 914 cur_el, secure, hcr_el2)) { 915 goto found; 916 } 917 } 918 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 919 excp_idx = EXCP_VFIQ; 920 target_el = 1; 921 if (arm_excp_unmasked(cs, excp_idx, target_el, 922 cur_el, secure, hcr_el2)) { 923 goto found; 924 } 925 } 926 if (interrupt_request & CPU_INTERRUPT_VSERR) { 927 excp_idx = EXCP_VSERR; 928 target_el = 1; 929 if (arm_excp_unmasked(cs, excp_idx, target_el, 930 cur_el, secure, hcr_el2)) { 931 /* Taking a virtual abort clears HCR_EL2.VSE */ 932 env->cp15.hcr_el2 &= ~HCR_VSE; 933 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 934 goto found; 935 } 936 } 937 return false; 938 939 found: 940 cs->exception_index = excp_idx; 941 env->exception.target_el = target_el; 942 cs->cc->tcg_ops->do_interrupt(cs); 943 return true; 944 } 945 946 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 947 948 void arm_cpu_update_virq(ARMCPU *cpu) 949 { 950 /* 951 * Update the interrupt level for VIRQ, which is the logical OR of 952 * the HCR_EL2.VI bit and the input line level from the GIC. 953 */ 954 CPUARMState *env = &cpu->env; 955 CPUState *cs = CPU(cpu); 956 957 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VI) && 958 !(arm_hcrx_el2_eff(env) & HCRX_VINMI)) || 959 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 960 961 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 962 if (new_state) { 963 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 964 } else { 965 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 966 } 967 } 968 } 969 970 void arm_cpu_update_vfiq(ARMCPU *cpu) 971 { 972 /* 973 * Update the interrupt level for VFIQ, which is the logical OR of 974 * the HCR_EL2.VF bit and the input line level from the GIC. 975 */ 976 CPUARMState *env = &cpu->env; 977 CPUState *cs = CPU(cpu); 978 979 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VF) && 980 !(arm_hcrx_el2_eff(env) & HCRX_VFNMI)) || 981 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 982 983 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 984 if (new_state) { 985 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 986 } else { 987 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 988 } 989 } 990 } 991 992 void arm_cpu_update_vinmi(ARMCPU *cpu) 993 { 994 /* 995 * Update the interrupt level for VINMI, which is the logical OR of 996 * the HCRX_EL2.VINMI bit and the input line level from the GIC. 997 */ 998 CPUARMState *env = &cpu->env; 999 CPUState *cs = CPU(cpu); 1000 1001 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VI) && 1002 (arm_hcrx_el2_eff(env) & HCRX_VINMI)) || 1003 (env->irq_line_state & CPU_INTERRUPT_VINMI); 1004 1005 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VINMI) != 0)) { 1006 if (new_state) { 1007 cpu_interrupt(cs, CPU_INTERRUPT_VINMI); 1008 } else { 1009 cpu_reset_interrupt(cs, CPU_INTERRUPT_VINMI); 1010 } 1011 } 1012 } 1013 1014 void arm_cpu_update_vfnmi(ARMCPU *cpu) 1015 { 1016 /* 1017 * Update the interrupt level for VFNMI, which is the HCRX_EL2.VFNMI bit. 1018 */ 1019 CPUARMState *env = &cpu->env; 1020 CPUState *cs = CPU(cpu); 1021 1022 bool new_state = (arm_hcr_el2_eff(env) & HCR_VF) && 1023 (arm_hcrx_el2_eff(env) & HCRX_VFNMI); 1024 1025 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFNMI) != 0)) { 1026 if (new_state) { 1027 cpu_interrupt(cs, CPU_INTERRUPT_VFNMI); 1028 } else { 1029 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFNMI); 1030 } 1031 } 1032 } 1033 1034 void arm_cpu_update_vserr(ARMCPU *cpu) 1035 { 1036 /* 1037 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. 1038 */ 1039 CPUARMState *env = &cpu->env; 1040 CPUState *cs = CPU(cpu); 1041 1042 bool new_state = env->cp15.hcr_el2 & HCR_VSE; 1043 1044 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { 1045 if (new_state) { 1046 cpu_interrupt(cs, CPU_INTERRUPT_VSERR); 1047 } else { 1048 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 1049 } 1050 } 1051 } 1052 1053 #ifndef CONFIG_USER_ONLY 1054 static void arm_cpu_set_irq(void *opaque, int irq, int level) 1055 { 1056 ARMCPU *cpu = opaque; 1057 CPUARMState *env = &cpu->env; 1058 CPUState *cs = CPU(cpu); 1059 static const int mask[] = { 1060 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 1061 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 1062 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 1063 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ, 1064 [ARM_CPU_NMI] = CPU_INTERRUPT_NMI, 1065 [ARM_CPU_VINMI] = CPU_INTERRUPT_VINMI, 1066 }; 1067 1068 if (!arm_feature(env, ARM_FEATURE_EL2) && 1069 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { 1070 /* 1071 * The GIC might tell us about VIRQ and VFIQ state, but if we don't 1072 * have EL2 support we don't care. (Unless the guest is doing something 1073 * silly this will only be calls saying "level is still 0".) 1074 */ 1075 return; 1076 } 1077 1078 if (level) { 1079 env->irq_line_state |= mask[irq]; 1080 } else { 1081 env->irq_line_state &= ~mask[irq]; 1082 } 1083 1084 switch (irq) { 1085 case ARM_CPU_VIRQ: 1086 arm_cpu_update_virq(cpu); 1087 break; 1088 case ARM_CPU_VFIQ: 1089 arm_cpu_update_vfiq(cpu); 1090 break; 1091 case ARM_CPU_VINMI: 1092 arm_cpu_update_vinmi(cpu); 1093 break; 1094 case ARM_CPU_IRQ: 1095 case ARM_CPU_FIQ: 1096 case ARM_CPU_NMI: 1097 if (level) { 1098 cpu_interrupt(cs, mask[irq]); 1099 } else { 1100 cpu_reset_interrupt(cs, mask[irq]); 1101 } 1102 break; 1103 default: 1104 g_assert_not_reached(); 1105 } 1106 } 1107 1108 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 1109 { 1110 ARMCPU *cpu = ARM_CPU(cs); 1111 CPUARMState *env = &cpu->env; 1112 1113 cpu_synchronize_state(cs); 1114 return arm_cpu_data_is_big_endian(env); 1115 } 1116 1117 #ifdef CONFIG_TCG 1118 bool arm_cpu_exec_halt(CPUState *cs) 1119 { 1120 bool leave_halt = cpu_has_work(cs); 1121 1122 if (leave_halt) { 1123 /* We're about to come out of WFI/WFE: disable the WFxT timer */ 1124 ARMCPU *cpu = ARM_CPU(cs); 1125 if (cpu->wfxt_timer) { 1126 timer_del(cpu->wfxt_timer); 1127 } 1128 } 1129 return leave_halt; 1130 } 1131 #endif 1132 1133 static void arm_wfxt_timer_cb(void *opaque) 1134 { 1135 ARMCPU *cpu = opaque; 1136 CPUState *cs = CPU(cpu); 1137 1138 /* 1139 * We expect the CPU to be halted; this will cause arm_cpu_is_work() 1140 * to return true (so we will come out of halt even with no other 1141 * pending interrupt), and the TCG accelerator's cpu_exec_interrupt() 1142 * function auto-clears the CPU_INTERRUPT_EXITTB flag for us. 1143 */ 1144 cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); 1145 } 1146 #endif 1147 1148 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 1149 { 1150 ARMCPU *ac = ARM_CPU(cpu); 1151 CPUARMState *env = &ac->env; 1152 bool sctlr_b = arm_sctlr_b(env); 1153 1154 if (is_a64(env)) { 1155 info->cap_arch = CS_ARCH_ARM64; 1156 info->cap_insn_unit = 4; 1157 info->cap_insn_split = 4; 1158 } else { 1159 int cap_mode; 1160 if (env->thumb) { 1161 info->cap_insn_unit = 2; 1162 info->cap_insn_split = 4; 1163 cap_mode = CS_MODE_THUMB; 1164 } else { 1165 info->cap_insn_unit = 4; 1166 info->cap_insn_split = 4; 1167 cap_mode = CS_MODE_ARM; 1168 } 1169 if (arm_feature(env, ARM_FEATURE_V8)) { 1170 cap_mode |= CS_MODE_V8; 1171 } 1172 if (arm_feature(env, ARM_FEATURE_M)) { 1173 cap_mode |= CS_MODE_MCLASS; 1174 } 1175 info->cap_arch = CS_ARCH_ARM; 1176 info->cap_mode = cap_mode; 1177 } 1178 1179 info->endian = BFD_ENDIAN_LITTLE; 1180 if (bswap_code(sctlr_b)) { 1181 info->endian = target_big_endian() ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 1182 } 1183 info->flags &= ~INSN_ARM_BE32; 1184 #ifndef CONFIG_USER_ONLY 1185 if (sctlr_b) { 1186 info->flags |= INSN_ARM_BE32; 1187 } 1188 #endif 1189 } 1190 1191 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1192 { 1193 ARMCPU *cpu = ARM_CPU(cs); 1194 CPUARMState *env = &cpu->env; 1195 uint32_t psr = pstate_read(env); 1196 int i, j; 1197 int el = arm_current_el(env); 1198 uint64_t hcr = arm_hcr_el2_eff(env); 1199 const char *ns_status; 1200 bool sve; 1201 1202 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 1203 for (i = 0; i < 32; i++) { 1204 if (i == 31) { 1205 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 1206 } else { 1207 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 1208 (i + 2) % 3 ? " " : "\n"); 1209 } 1210 } 1211 1212 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 1213 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1214 } else { 1215 ns_status = ""; 1216 } 1217 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 1218 psr, 1219 psr & PSTATE_N ? 'N' : '-', 1220 psr & PSTATE_Z ? 'Z' : '-', 1221 psr & PSTATE_C ? 'C' : '-', 1222 psr & PSTATE_V ? 'V' : '-', 1223 ns_status, 1224 el, 1225 psr & PSTATE_SP ? 'h' : 't'); 1226 1227 if (cpu_isar_feature(aa64_sme, cpu)) { 1228 qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c", 1229 env->svcr, 1230 (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), 1231 (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); 1232 } 1233 if (cpu_isar_feature(aa64_bti, cpu)) { 1234 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 1235 } 1236 qemu_fprintf(f, "%s%s%s", 1237 (hcr & HCR_NV) ? " NV" : "", 1238 (hcr & HCR_NV1) ? " NV1" : "", 1239 (hcr & HCR_NV2) ? " NV2" : ""); 1240 if (!(flags & CPU_DUMP_FPU)) { 1241 qemu_fprintf(f, "\n"); 1242 return; 1243 } 1244 if (fp_exception_el(env, el) != 0) { 1245 qemu_fprintf(f, " FPU disabled\n"); 1246 return; 1247 } 1248 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 1249 vfp_get_fpcr(env), vfp_get_fpsr(env)); 1250 1251 if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) { 1252 sve = sme_exception_el(env, el) == 0; 1253 } else if (cpu_isar_feature(aa64_sve, cpu)) { 1254 sve = sve_exception_el(env, el) == 0; 1255 } else { 1256 sve = false; 1257 } 1258 1259 if (sve) { 1260 int zcr_len = sve_vqm1_for_el(env, el); 1261 1262 for (i = 0; i <= FFR_PRED_NUM; i++) { 1263 bool eol; 1264 if (i == FFR_PRED_NUM) { 1265 qemu_fprintf(f, "FFR="); 1266 /* It's last, so end the line. */ 1267 eol = true; 1268 } else { 1269 qemu_fprintf(f, "P%02d=", i); 1270 switch (zcr_len) { 1271 case 0: 1272 eol = i % 8 == 7; 1273 break; 1274 case 1: 1275 eol = i % 6 == 5; 1276 break; 1277 case 2: 1278 case 3: 1279 eol = i % 3 == 2; 1280 break; 1281 default: 1282 /* More than one quadword per predicate. */ 1283 eol = true; 1284 break; 1285 } 1286 } 1287 for (j = zcr_len / 4; j >= 0; j--) { 1288 int digits; 1289 if (j * 4 + 4 <= zcr_len + 1) { 1290 digits = 16; 1291 } else { 1292 digits = (zcr_len % 4 + 1) * 4; 1293 } 1294 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 1295 env->vfp.pregs[i].p[j], 1296 j ? ":" : eol ? "\n" : " "); 1297 } 1298 } 1299 1300 if (zcr_len == 0) { 1301 /* 1302 * With vl=16, there are only 37 columns per register, 1303 * so output two registers per line. 1304 */ 1305 for (i = 0; i < 32; i++) { 1306 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1307 i, env->vfp.zregs[i].d[1], 1308 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 1309 } 1310 } else { 1311 for (i = 0; i < 32; i++) { 1312 qemu_fprintf(f, "Z%02d=", i); 1313 for (j = zcr_len; j >= 0; j--) { 1314 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 1315 env->vfp.zregs[i].d[j * 2 + 1], 1316 env->vfp.zregs[i].d[j * 2 + 0], 1317 j ? ":" : "\n"); 1318 } 1319 } 1320 } 1321 } else { 1322 for (i = 0; i < 32; i++) { 1323 uint64_t *q = aa64_vfp_qreg(env, i); 1324 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1325 i, q[1], q[0], (i & 1 ? "\n" : " ")); 1326 } 1327 } 1328 1329 if (cpu_isar_feature(aa64_sme, cpu) && 1330 FIELD_EX64(env->svcr, SVCR, ZA) && 1331 sme_exception_el(env, el) == 0) { 1332 int zcr_len = sve_vqm1_for_el_sm(env, el, true); 1333 int svl = (zcr_len + 1) * 16; 1334 int svl_lg10 = svl < 100 ? 2 : 3; 1335 1336 for (i = 0; i < svl; i++) { 1337 qemu_fprintf(f, "ZA[%0*d]=", svl_lg10, i); 1338 for (j = zcr_len; j >= 0; --j) { 1339 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%c", 1340 env->za_state.za[i].d[2 * j + 1], 1341 env->za_state.za[i].d[2 * j], 1342 j ? ':' : '\n'); 1343 } 1344 } 1345 } 1346 } 1347 1348 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1349 { 1350 ARMCPU *cpu = ARM_CPU(cs); 1351 CPUARMState *env = &cpu->env; 1352 int i; 1353 1354 if (is_a64(env)) { 1355 aarch64_cpu_dump_state(cs, f, flags); 1356 return; 1357 } 1358 1359 for (i = 0; i < 16; i++) { 1360 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 1361 if ((i % 4) == 3) { 1362 qemu_fprintf(f, "\n"); 1363 } else { 1364 qemu_fprintf(f, " "); 1365 } 1366 } 1367 1368 if (arm_feature(env, ARM_FEATURE_M)) { 1369 uint32_t xpsr = xpsr_read(env); 1370 const char *mode; 1371 const char *ns_status = ""; 1372 1373 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1374 ns_status = env->v7m.secure ? "S " : "NS "; 1375 } 1376 1377 if (xpsr & XPSR_EXCP) { 1378 mode = "handler"; 1379 } else { 1380 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 1381 mode = "unpriv-thread"; 1382 } else { 1383 mode = "priv-thread"; 1384 } 1385 } 1386 1387 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 1388 xpsr, 1389 xpsr & XPSR_N ? 'N' : '-', 1390 xpsr & XPSR_Z ? 'Z' : '-', 1391 xpsr & XPSR_C ? 'C' : '-', 1392 xpsr & XPSR_V ? 'V' : '-', 1393 xpsr & XPSR_T ? 'T' : 'A', 1394 ns_status, 1395 mode); 1396 } else { 1397 uint32_t psr = cpsr_read(env); 1398 const char *ns_status = ""; 1399 1400 if (arm_feature(env, ARM_FEATURE_EL3) && 1401 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1402 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1403 } 1404 1405 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1406 psr, 1407 psr & CPSR_N ? 'N' : '-', 1408 psr & CPSR_Z ? 'Z' : '-', 1409 psr & CPSR_C ? 'C' : '-', 1410 psr & CPSR_V ? 'V' : '-', 1411 psr & CPSR_T ? 'T' : 'A', 1412 ns_status, 1413 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1414 } 1415 1416 if (flags & CPU_DUMP_FPU) { 1417 int numvfpregs = 0; 1418 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1419 numvfpregs = 32; 1420 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1421 numvfpregs = 16; 1422 } 1423 for (i = 0; i < numvfpregs; i++) { 1424 uint64_t v = *aa32_vfp_dreg(env, i); 1425 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1426 i * 2, (uint32_t)v, 1427 i * 2 + 1, (uint32_t)(v >> 32), 1428 i, v); 1429 } 1430 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1431 if (cpu_isar_feature(aa32_mve, cpu)) { 1432 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1433 } 1434 } 1435 } 1436 1437 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz) 1438 { 1439 uint32_t Aff1 = idx / clustersz; 1440 uint32_t Aff0 = idx % clustersz; 1441 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1442 } 1443 1444 uint64_t arm_cpu_mp_affinity(ARMCPU *cpu) 1445 { 1446 return cpu->mp_affinity; 1447 } 1448 1449 static void arm_cpu_initfn(Object *obj) 1450 { 1451 ARMCPU *cpu = ARM_CPU(obj); 1452 1453 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, 1454 NULL, g_free); 1455 1456 QLIST_INIT(&cpu->pre_el_change_hooks); 1457 QLIST_INIT(&cpu->el_change_hooks); 1458 1459 #ifdef CONFIG_USER_ONLY 1460 # ifdef TARGET_AARCH64 1461 /* 1462 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME. 1463 * These values were chosen to fit within the default signal frame. 1464 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length, 1465 * and our corresponding cpu property. 1466 */ 1467 cpu->sve_default_vq = 4; 1468 cpu->sme_default_vq = 2; 1469 # endif 1470 #else 1471 /* Our inbound IRQ and FIQ lines */ 1472 if (kvm_enabled()) { 1473 /* 1474 * VIRQ, VFIQ, NMI, VINMI are unused with KVM but we add 1475 * them to maintain the same interface as non-KVM CPUs. 1476 */ 1477 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 6); 1478 } else { 1479 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 6); 1480 } 1481 1482 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1483 ARRAY_SIZE(cpu->gt_timer_outputs)); 1484 1485 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1486 "gicv3-maintenance-interrupt", 1); 1487 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1488 "pmu-interrupt", 1); 1489 #endif 1490 1491 /* DTB consumers generally don't in fact care what the 'compatible' 1492 * string is, so always provide some string and trust that a hypothetical 1493 * picky DTB consumer will also provide a helpful error message. 1494 */ 1495 cpu->dtb_compatible = "qemu,unknown"; 1496 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ 1497 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1498 1499 if (tcg_enabled() || hvf_enabled()) { 1500 /* TCG and HVF implement PSCI 1.1 */ 1501 cpu->psci_version = QEMU_PSCI_VERSION_1_1; 1502 } 1503 } 1504 1505 /* 1506 * 0 means "unset, use the default value". That default might vary depending 1507 * on the CPU type, and is set in the realize fn. 1508 */ 1509 #ifndef CONFIG_USER_ONLY 1510 static const Property arm_cpu_gt_cntfrq_property = 1511 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 0); 1512 1513 static const Property arm_cpu_reset_cbar_property = 1514 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1515 1516 static const Property arm_cpu_reset_hivecs_property = 1517 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1518 1519 static const Property arm_cpu_has_el2_property = 1520 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1521 1522 static const Property arm_cpu_has_el3_property = 1523 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1524 #endif 1525 1526 static const Property arm_cpu_cfgend_property = 1527 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1528 1529 static const Property arm_cpu_has_vfp_property = 1530 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1531 1532 static const Property arm_cpu_has_vfp_d32_property = 1533 DEFINE_PROP_BOOL("vfp-d32", ARMCPU, has_vfp_d32, true); 1534 1535 static const Property arm_cpu_has_neon_property = 1536 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1537 1538 static const Property arm_cpu_has_dsp_property = 1539 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1540 1541 #ifndef CONFIG_USER_ONLY 1542 static const Property arm_cpu_has_mpu_property = 1543 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1544 1545 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1546 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1547 * the right value for that particular CPU type, and we don't want 1548 * to override that with an incorrect constant value. 1549 */ 1550 static const Property arm_cpu_pmsav7_dregion_property = 1551 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1552 pmsav7_dregion, 1553 qdev_prop_uint32, uint32_t); 1554 #endif 1555 1556 static bool arm_get_pmu(Object *obj, Error **errp) 1557 { 1558 ARMCPU *cpu = ARM_CPU(obj); 1559 1560 return cpu->has_pmu; 1561 } 1562 1563 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1564 { 1565 ARMCPU *cpu = ARM_CPU(obj); 1566 1567 if (value) { 1568 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1569 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1570 return; 1571 } 1572 set_feature(&cpu->env, ARM_FEATURE_PMU); 1573 } else { 1574 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1575 } 1576 cpu->has_pmu = value; 1577 } 1578 1579 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) 1580 { 1581 ARMCPU *cpu = ARM_CPU(obj); 1582 1583 return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); 1584 } 1585 1586 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) 1587 { 1588 ARMCPU *cpu = ARM_CPU(obj); 1589 1590 /* 1591 * At this time, this property is only allowed if KVM is enabled. This 1592 * restriction allows us to avoid fixing up functionality that assumes a 1593 * uniform execution state like do_interrupt. 1594 */ 1595 if (value == false) { 1596 if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { 1597 error_setg(errp, "'aarch64' feature cannot be disabled " 1598 "unless KVM is enabled and 32-bit EL1 " 1599 "is supported"); 1600 return; 1601 } 1602 unset_feature(&cpu->env, ARM_FEATURE_AARCH64); 1603 } else { 1604 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 1605 } 1606 } 1607 1608 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1609 { 1610 /* 1611 * The exact approach to calculating guest ticks is: 1612 * 1613 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1614 * NANOSECONDS_PER_SECOND); 1615 * 1616 * We don't do that. Rather we intentionally use integer division 1617 * truncation below and in the caller for the conversion of host monotonic 1618 * time to guest ticks to provide the exact inverse for the semantics of 1619 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1620 * it loses precision when representing frequencies where 1621 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1622 * provide an exact inverse leads to scheduling timers with negative 1623 * periods, which in turn leads to sticky behaviour in the guest. 1624 * 1625 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1626 * cannot become zero. 1627 */ 1628 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1629 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1630 } 1631 1632 static void arm_cpu_propagate_feature_implications(ARMCPU *cpu) 1633 { 1634 CPUARMState *env = &cpu->env; 1635 bool no_aa32 = false; 1636 1637 /* 1638 * Some features automatically imply others: set the feature 1639 * bits explicitly for these cases. 1640 */ 1641 1642 if (arm_feature(env, ARM_FEATURE_M)) { 1643 set_feature(env, ARM_FEATURE_PMSA); 1644 } 1645 1646 if (arm_feature(env, ARM_FEATURE_V8)) { 1647 if (arm_feature(env, ARM_FEATURE_M)) { 1648 set_feature(env, ARM_FEATURE_V7); 1649 } else { 1650 set_feature(env, ARM_FEATURE_V7VE); 1651 } 1652 } 1653 1654 /* 1655 * There exist AArch64 cpus without AArch32 support. When KVM 1656 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1657 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1658 * As a general principle, we also do not make ID register 1659 * consistency checks anywhere unless using TCG, because only 1660 * for TCG would a consistency-check failure be a QEMU bug. 1661 */ 1662 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1663 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1664 } 1665 1666 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1667 /* 1668 * v7 Virtualization Extensions. In real hardware this implies 1669 * EL2 and also the presence of the Security Extensions. 1670 * For QEMU, for backwards-compatibility we implement some 1671 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1672 * include the various other features that V7VE implies. 1673 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1674 * Security Extensions is ARM_FEATURE_EL3. 1675 */ 1676 assert(!tcg_enabled() || no_aa32 || 1677 cpu_isar_feature(aa32_arm_div, cpu)); 1678 set_feature(env, ARM_FEATURE_LPAE); 1679 set_feature(env, ARM_FEATURE_V7); 1680 } 1681 if (arm_feature(env, ARM_FEATURE_V7)) { 1682 set_feature(env, ARM_FEATURE_VAPA); 1683 set_feature(env, ARM_FEATURE_THUMB2); 1684 set_feature(env, ARM_FEATURE_MPIDR); 1685 if (!arm_feature(env, ARM_FEATURE_M)) { 1686 set_feature(env, ARM_FEATURE_V6K); 1687 } else { 1688 set_feature(env, ARM_FEATURE_V6); 1689 } 1690 1691 /* 1692 * Always define VBAR for V7 CPUs even if it doesn't exist in 1693 * non-EL3 configs. This is needed by some legacy boards. 1694 */ 1695 set_feature(env, ARM_FEATURE_VBAR); 1696 } 1697 if (arm_feature(env, ARM_FEATURE_V6K)) { 1698 set_feature(env, ARM_FEATURE_V6); 1699 set_feature(env, ARM_FEATURE_MVFR); 1700 } 1701 if (arm_feature(env, ARM_FEATURE_V6)) { 1702 set_feature(env, ARM_FEATURE_V5); 1703 if (!arm_feature(env, ARM_FEATURE_M)) { 1704 assert(!tcg_enabled() || no_aa32 || 1705 cpu_isar_feature(aa32_jazelle, cpu)); 1706 set_feature(env, ARM_FEATURE_AUXCR); 1707 } 1708 } 1709 if (arm_feature(env, ARM_FEATURE_V5)) { 1710 set_feature(env, ARM_FEATURE_V4T); 1711 } 1712 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1713 set_feature(env, ARM_FEATURE_V7MP); 1714 } 1715 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1716 set_feature(env, ARM_FEATURE_CBAR); 1717 } 1718 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1719 !arm_feature(env, ARM_FEATURE_M)) { 1720 set_feature(env, ARM_FEATURE_THUMB_DSP); 1721 } 1722 } 1723 1724 static void arm_cpu_post_init(Object *obj) 1725 { 1726 ARMCPU *cpu = ARM_CPU(obj); 1727 1728 /* 1729 * Some features imply others. Figure this out now, because we 1730 * are going to look at the feature bits in deciding which 1731 * properties to add. 1732 */ 1733 arm_cpu_propagate_feature_implications(cpu); 1734 1735 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1736 object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64, 1737 aarch64_cpu_set_aarch64); 1738 object_property_set_description(obj, "aarch64", 1739 "Set on/off to enable/disable aarch64 " 1740 "execution state "); 1741 } 1742 #ifndef CONFIG_USER_ONLY 1743 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1744 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1745 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1746 } 1747 1748 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1749 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1750 } 1751 1752 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1753 object_property_add_uint64_ptr(obj, "rvbar", 1754 &cpu->rvbar_prop, 1755 OBJ_PROP_FLAG_READWRITE); 1756 } 1757 1758 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1759 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1760 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1761 */ 1762 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1763 1764 object_property_add_link(obj, "secure-memory", 1765 TYPE_MEMORY_REGION, 1766 (Object **)&cpu->secure_memory, 1767 qdev_prop_allow_set_link_before_realize, 1768 OBJ_PROP_LINK_STRONG); 1769 } 1770 1771 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1772 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1773 } 1774 #endif 1775 1776 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1777 cpu->has_pmu = true; 1778 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1779 } 1780 1781 /* 1782 * Allow user to turn off VFP and Neon support, but only for TCG -- 1783 * KVM does not currently allow us to lie to the guest about its 1784 * ID/feature registers, so the guest always sees what the host has. 1785 */ 1786 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1787 if (cpu_isar_feature(aa64_fp_simd, cpu)) { 1788 cpu->has_vfp = true; 1789 cpu->has_vfp_d32 = true; 1790 if (tcg_enabled() || qtest_enabled()) { 1791 qdev_property_add_static(DEVICE(obj), 1792 &arm_cpu_has_vfp_property); 1793 } 1794 } 1795 } else if (cpu_isar_feature(aa32_vfp, cpu)) { 1796 cpu->has_vfp = true; 1797 if (tcg_enabled() || qtest_enabled()) { 1798 qdev_property_add_static(DEVICE(obj), 1799 &arm_cpu_has_vfp_property); 1800 } 1801 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1802 cpu->has_vfp_d32 = true; 1803 /* 1804 * The permitted values of the SIMDReg bits [3:0] on 1805 * Armv8-A are either 0b0000 and 0b0010. On such CPUs, 1806 * make sure that has_vfp_d32 can not be set to false. 1807 */ 1808 if ((tcg_enabled() || qtest_enabled()) 1809 && !(arm_feature(&cpu->env, ARM_FEATURE_V8) 1810 && !arm_feature(&cpu->env, ARM_FEATURE_M))) { 1811 qdev_property_add_static(DEVICE(obj), 1812 &arm_cpu_has_vfp_d32_property); 1813 } 1814 } 1815 } 1816 1817 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1818 cpu->has_neon = true; 1819 if (!kvm_enabled()) { 1820 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1821 } 1822 } 1823 1824 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1825 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1826 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1827 } 1828 1829 #ifndef CONFIG_USER_ONLY 1830 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1831 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1832 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1833 qdev_property_add_static(DEVICE(obj), 1834 &arm_cpu_pmsav7_dregion_property); 1835 } 1836 } 1837 1838 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1839 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1840 qdev_prop_allow_set_link_before_realize, 1841 OBJ_PROP_LINK_STRONG); 1842 /* 1843 * M profile: initial value of the Secure VTOR. We can't just use 1844 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1845 * the property to be set after realize. 1846 */ 1847 object_property_add_uint32_ptr(obj, "init-svtor", 1848 &cpu->init_svtor, 1849 OBJ_PROP_FLAG_READWRITE); 1850 } 1851 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1852 /* 1853 * Initial value of the NS VTOR (for cores without the Security 1854 * extension, this is the only VTOR) 1855 */ 1856 object_property_add_uint32_ptr(obj, "init-nsvtor", 1857 &cpu->init_nsvtor, 1858 OBJ_PROP_FLAG_READWRITE); 1859 } 1860 1861 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ 1862 object_property_add_uint32_ptr(obj, "psci-conduit", 1863 &cpu->psci_conduit, 1864 OBJ_PROP_FLAG_READWRITE); 1865 1866 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1867 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1868 } 1869 1870 if (kvm_enabled()) { 1871 kvm_arm_add_vcpu_properties(cpu); 1872 } 1873 1874 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1875 cpu_isar_feature(aa64_mte, cpu)) { 1876 object_property_add_link(obj, "tag-memory", 1877 TYPE_MEMORY_REGION, 1878 (Object **)&cpu->tag_memory, 1879 qdev_prop_allow_set_link_before_realize, 1880 OBJ_PROP_LINK_STRONG); 1881 1882 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1883 object_property_add_link(obj, "secure-tag-memory", 1884 TYPE_MEMORY_REGION, 1885 (Object **)&cpu->secure_tag_memory, 1886 qdev_prop_allow_set_link_before_realize, 1887 OBJ_PROP_LINK_STRONG); 1888 } 1889 } 1890 #endif 1891 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1892 } 1893 1894 static void arm_cpu_finalizefn(Object *obj) 1895 { 1896 ARMCPU *cpu = ARM_CPU(obj); 1897 ARMELChangeHook *hook, *next; 1898 1899 g_hash_table_destroy(cpu->cp_regs); 1900 1901 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1902 QLIST_REMOVE(hook, node); 1903 g_free(hook); 1904 } 1905 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1906 QLIST_REMOVE(hook, node); 1907 g_free(hook); 1908 } 1909 #ifndef CONFIG_USER_ONLY 1910 if (cpu->pmu_timer) { 1911 timer_free(cpu->pmu_timer); 1912 } 1913 if (cpu->wfxt_timer) { 1914 timer_free(cpu->wfxt_timer); 1915 } 1916 #endif 1917 } 1918 1919 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1920 { 1921 Error *local_err = NULL; 1922 1923 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1924 arm_cpu_sve_finalize(cpu, &local_err); 1925 if (local_err != NULL) { 1926 error_propagate(errp, local_err); 1927 return; 1928 } 1929 1930 /* 1931 * FEAT_SME is not architecturally dependent on FEAT_SVE (unless 1932 * FEAT_SME_FA64 is present). However our implementation currently 1933 * assumes it, so if the user asked for sve=off then turn off SME also. 1934 * (KVM doesn't currently support SME at all.) 1935 */ 1936 if (cpu_isar_feature(aa64_sme, cpu) && !cpu_isar_feature(aa64_sve, cpu)) { 1937 object_property_set_bool(OBJECT(cpu), "sme", false, &error_abort); 1938 } 1939 1940 arm_cpu_sme_finalize(cpu, &local_err); 1941 if (local_err != NULL) { 1942 error_propagate(errp, local_err); 1943 return; 1944 } 1945 1946 arm_cpu_pauth_finalize(cpu, &local_err); 1947 if (local_err != NULL) { 1948 error_propagate(errp, local_err); 1949 return; 1950 } 1951 1952 arm_cpu_lpa2_finalize(cpu, &local_err); 1953 if (local_err != NULL) { 1954 error_propagate(errp, local_err); 1955 return; 1956 } 1957 } 1958 1959 if (kvm_enabled()) { 1960 kvm_arm_steal_time_finalize(cpu, &local_err); 1961 if (local_err != NULL) { 1962 error_propagate(errp, local_err); 1963 return; 1964 } 1965 } 1966 } 1967 1968 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1969 { 1970 CPUState *cs = CPU(dev); 1971 ARMCPU *cpu = ARM_CPU(dev); 1972 ARMISARegisters *isar = &cpu->isar; 1973 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1974 CPUARMState *env = &cpu->env; 1975 Error *local_err = NULL; 1976 1977 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 1978 /* Use pc-relative instructions in system-mode */ 1979 tcg_cflags_set(cs, CF_PCREL); 1980 #endif 1981 1982 /* If we needed to query the host kernel for the CPU features 1983 * then it's possible that might have failed in the initfn, but 1984 * this is the first point where we can report it. 1985 */ 1986 if (cpu->host_cpu_probe_failed) { 1987 if (!kvm_enabled() && !hvf_enabled()) { 1988 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1989 } else { 1990 error_setg(errp, "Failed to retrieve host CPU features"); 1991 } 1992 return; 1993 } 1994 1995 if (!cpu->gt_cntfrq_hz) { 1996 /* 1997 * 0 means "the board didn't set a value, use the default". (We also 1998 * get here for the CONFIG_USER_ONLY case.) 1999 * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before 2000 * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz, 2001 * which gives a 16ns tick period. 2002 * 2003 * We will use the back-compat value: 2004 * - for QEMU CPU types added before we standardized on 1GHz 2005 * - for versioned machine types with a version of 9.0 or earlier 2006 */ 2007 if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) || 2008 cpu->backcompat_cntfrq) { 2009 cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ; 2010 } else { 2011 cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ; 2012 } 2013 } 2014 2015 #ifndef CONFIG_USER_ONLY 2016 /* The NVIC and M-profile CPU are two halves of a single piece of 2017 * hardware; trying to use one without the other is a command line 2018 * error and will result in segfaults if not caught here. 2019 */ 2020 if (arm_feature(env, ARM_FEATURE_M)) { 2021 if (!env->nvic) { 2022 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 2023 return; 2024 } 2025 } else { 2026 if (env->nvic) { 2027 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 2028 return; 2029 } 2030 } 2031 2032 if (!tcg_enabled() && !qtest_enabled()) { 2033 /* 2034 * We assume that no accelerator except TCG (and the "not really an 2035 * accelerator" qtest) can handle these features, because Arm hardware 2036 * virtualization can't virtualize them. 2037 * 2038 * Catch all the cases which might cause us to create more than one 2039 * address space for the CPU (otherwise we will assert() later in 2040 * cpu_address_space_init()). 2041 */ 2042 if (arm_feature(env, ARM_FEATURE_M)) { 2043 error_setg(errp, 2044 "Cannot enable %s when using an M-profile guest CPU", 2045 current_accel_name()); 2046 return; 2047 } 2048 if (cpu->has_el3) { 2049 error_setg(errp, 2050 "Cannot enable %s when guest CPU has EL3 enabled", 2051 current_accel_name()); 2052 return; 2053 } 2054 if (cpu->tag_memory) { 2055 error_setg(errp, 2056 "Cannot enable %s when guest CPUs has MTE enabled", 2057 current_accel_name()); 2058 return; 2059 } 2060 } 2061 2062 { 2063 uint64_t scale = gt_cntfrq_period_ns(cpu); 2064 2065 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2066 arm_gt_ptimer_cb, cpu); 2067 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2068 arm_gt_vtimer_cb, cpu); 2069 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2070 arm_gt_htimer_cb, cpu); 2071 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2072 arm_gt_stimer_cb, cpu); 2073 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2074 arm_gt_hvtimer_cb, cpu); 2075 cpu->gt_timer[GTIMER_S_EL2_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2076 arm_gt_sel2timer_cb, cpu); 2077 cpu->gt_timer[GTIMER_S_EL2_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 2078 arm_gt_sel2vtimer_cb, cpu); 2079 } 2080 #endif 2081 2082 cpu_exec_realizefn(cs, &local_err); 2083 if (local_err != NULL) { 2084 error_propagate(errp, local_err); 2085 return; 2086 } 2087 2088 arm_cpu_finalize_features(cpu, &local_err); 2089 if (local_err != NULL) { 2090 error_propagate(errp, local_err); 2091 return; 2092 } 2093 2094 #ifdef CONFIG_USER_ONLY 2095 /* 2096 * User mode relies on IC IVAU instructions to catch modification of 2097 * dual-mapped code. 2098 * 2099 * Clear CTR_EL0.DIC to ensure that software that honors these flags uses 2100 * IC IVAU even if the emulated processor does not normally require it. 2101 */ 2102 cpu->ctr = FIELD_DP64(cpu->ctr, CTR_EL0, DIC, 0); 2103 #endif 2104 2105 if (arm_feature(env, ARM_FEATURE_AARCH64) && 2106 cpu->has_vfp != cpu->has_neon) { 2107 /* 2108 * This is an architectural requirement for AArch64; AArch32 is 2109 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 2110 */ 2111 error_setg(errp, 2112 "AArch64 CPUs must have both VFP and Neon or neither"); 2113 return; 2114 } 2115 2116 if (cpu->has_vfp_d32 != cpu->has_neon) { 2117 error_setg(errp, "ARM CPUs must have both VFP-D32 and Neon or neither"); 2118 return; 2119 } 2120 2121 if (!cpu->has_vfp_d32) { 2122 uint32_t u; 2123 2124 u = cpu->isar.mvfr0; 2125 u = FIELD_DP32(u, MVFR0, SIMDREG, 1); /* 16 registers */ 2126 cpu->isar.mvfr0 = u; 2127 } 2128 2129 if (!cpu->has_vfp) { 2130 uint32_t u; 2131 2132 FIELD_DP64_IDREG(isar, ID_AA64ISAR1, JSCVT, 0); 2133 2134 FIELD_DP64_IDREG(isar, ID_AA64PFR0, FP, 0xf); 2135 2136 u = GET_IDREG(isar, ID_ISAR6); 2137 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 2138 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 2139 SET_IDREG(isar, ID_ISAR6, u); 2140 2141 u = cpu->isar.mvfr0; 2142 u = FIELD_DP32(u, MVFR0, FPSP, 0); 2143 u = FIELD_DP32(u, MVFR0, FPDP, 0); 2144 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 2145 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 2146 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 2147 if (!arm_feature(env, ARM_FEATURE_M)) { 2148 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 2149 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 2150 } 2151 cpu->isar.mvfr0 = u; 2152 2153 u = cpu->isar.mvfr1; 2154 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 2155 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 2156 u = FIELD_DP32(u, MVFR1, FPHP, 0); 2157 if (arm_feature(env, ARM_FEATURE_M)) { 2158 u = FIELD_DP32(u, MVFR1, FP16, 0); 2159 } 2160 cpu->isar.mvfr1 = u; 2161 2162 u = cpu->isar.mvfr2; 2163 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 2164 cpu->isar.mvfr2 = u; 2165 } 2166 2167 if (!cpu->has_neon) { 2168 uint64_t t; 2169 uint32_t u; 2170 2171 unset_feature(env, ARM_FEATURE_NEON); 2172 2173 t = GET_IDREG(isar, ID_AA64ISAR0); 2174 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); 2175 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); 2176 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); 2177 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); 2178 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); 2179 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); 2180 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 2181 SET_IDREG(isar, ID_AA64ISAR0, t); 2182 2183 t = GET_IDREG(isar, ID_AA64ISAR1); 2184 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 2185 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 2186 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 2187 SET_IDREG(isar, ID_AA64ISAR1, t); 2188 2189 FIELD_DP64_IDREG(isar, ID_AA64PFR0, ADVSIMD, 0xf); 2190 2191 u = GET_IDREG(isar, ID_ISAR5); 2192 u = FIELD_DP32(u, ID_ISAR5, AES, 0); 2193 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); 2194 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); 2195 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 2196 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 2197 SET_IDREG(isar, ID_ISAR5, u); 2198 2199 u = GET_IDREG(isar, ID_ISAR6); 2200 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 2201 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 2202 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 2203 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 2204 SET_IDREG(isar, ID_ISAR6, u); 2205 2206 if (!arm_feature(env, ARM_FEATURE_M)) { 2207 u = cpu->isar.mvfr1; 2208 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 2209 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 2210 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 2211 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 2212 cpu->isar.mvfr1 = u; 2213 2214 u = cpu->isar.mvfr2; 2215 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 2216 cpu->isar.mvfr2 = u; 2217 } 2218 } 2219 2220 if (!cpu->has_neon && !cpu->has_vfp) { 2221 uint32_t u; 2222 2223 FIELD_DP64_IDREG(isar, ID_AA64ISAR0, FHM, 0); 2224 2225 FIELD_DP64_IDREG(isar, ID_AA64ISAR1, FRINTTS, 0); 2226 2227 u = cpu->isar.mvfr0; 2228 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 2229 cpu->isar.mvfr0 = u; 2230 2231 /* Despite the name, this field covers both VFP and Neon */ 2232 u = cpu->isar.mvfr1; 2233 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 2234 cpu->isar.mvfr1 = u; 2235 } 2236 2237 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 2238 uint32_t u; 2239 2240 unset_feature(env, ARM_FEATURE_THUMB_DSP); 2241 2242 FIELD_DP32_IDREG(isar, ID_ISAR1, EXTEND, 1); 2243 2244 u = GET_IDREG(isar, ID_ISAR2); 2245 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 2246 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 2247 SET_IDREG(isar, ID_ISAR2, u); 2248 2249 u = GET_IDREG(isar, ID_ISAR3); 2250 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 2251 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 2252 SET_IDREG(isar, ID_ISAR3, u); 2253 } 2254 2255 2256 /* 2257 * We rely on no XScale CPU having VFP so we can use the same bits in the 2258 * TB flags field for VECSTRIDE and XSCALE_CPAR. 2259 */ 2260 assert(arm_feature(env, ARM_FEATURE_AARCH64) || 2261 !cpu_isar_feature(aa32_vfp_simd, cpu) || 2262 !arm_feature(env, ARM_FEATURE_XSCALE)); 2263 2264 #ifndef CONFIG_USER_ONLY 2265 { 2266 int pagebits; 2267 if (arm_feature(env, ARM_FEATURE_V7) && 2268 !arm_feature(env, ARM_FEATURE_M) && 2269 !arm_feature(env, ARM_FEATURE_PMSA)) { 2270 /* 2271 * v7VMSA drops support for the old ARMv5 tiny pages, 2272 * so we can use 4K pages. 2273 */ 2274 pagebits = 12; 2275 } else { 2276 /* 2277 * For CPUs which might have tiny 1K pages, or which have an 2278 * MPU and might have small region sizes, stick with 1K pages. 2279 */ 2280 pagebits = 10; 2281 } 2282 if (!set_preferred_target_page_bits(pagebits)) { 2283 /* 2284 * This can only ever happen for hotplugging a CPU, or if 2285 * the board code incorrectly creates a CPU which it has 2286 * promised via minimum_page_size that it will not. 2287 */ 2288 error_setg(errp, "This CPU requires a smaller page size " 2289 "than the system is using"); 2290 return; 2291 } 2292 } 2293 #endif 2294 2295 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 2296 * We don't support setting cluster ID ([16..23]) (known as Aff2 2297 * in later ARM ARM versions), or any of the higher affinity level fields, 2298 * so these bits always RAZ. 2299 */ 2300 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 2301 cpu->mp_affinity = arm_build_mp_affinity(cs->cpu_index, 2302 ARM_DEFAULT_CPUS_PER_CLUSTER); 2303 } 2304 2305 if (cpu->reset_hivecs) { 2306 cpu->reset_sctlr |= (1 << 13); 2307 } 2308 2309 if (cpu->cfgend) { 2310 if (arm_feature(env, ARM_FEATURE_V7)) { 2311 cpu->reset_sctlr |= SCTLR_EE; 2312 } else { 2313 cpu->reset_sctlr |= SCTLR_B; 2314 } 2315 } 2316 2317 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 2318 /* If the has_el3 CPU property is disabled then we need to disable the 2319 * feature. 2320 */ 2321 unset_feature(env, ARM_FEATURE_EL3); 2322 2323 /* 2324 * Disable the security extension feature bits in the processor 2325 * feature registers as well. 2326 */ 2327 FIELD_DP32_IDREG(isar, ID_PFR1, SECURITY, 0); 2328 FIELD_DP32_IDREG(isar, ID_DFR0, COPSDBG, 0); 2329 FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL3, 0); 2330 2331 /* Disable the realm management extension, which requires EL3. */ 2332 FIELD_DP64_IDREG(isar, ID_AA64PFR0, RME, 0); 2333 } 2334 2335 if (!cpu->has_el2) { 2336 unset_feature(env, ARM_FEATURE_EL2); 2337 } 2338 2339 if (!cpu->has_pmu) { 2340 unset_feature(env, ARM_FEATURE_PMU); 2341 } 2342 if (arm_feature(env, ARM_FEATURE_PMU)) { 2343 pmu_init(cpu); 2344 2345 if (!kvm_enabled()) { 2346 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 2347 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 2348 } 2349 2350 #ifndef CONFIG_USER_ONLY 2351 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 2352 cpu); 2353 #endif 2354 } else { 2355 FIELD_DP64_IDREG(isar, ID_AA64DFR0, PMUVER, 0); 2356 FIELD_DP32_IDREG(isar, ID_DFR0, PERFMON, 0); 2357 cpu->pmceid0 = 0; 2358 cpu->pmceid1 = 0; 2359 } 2360 2361 if (!arm_feature(env, ARM_FEATURE_EL2)) { 2362 /* 2363 * Disable the hypervisor feature bits in the processor feature 2364 * registers if we don't have EL2. 2365 */ 2366 FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL2, 0); 2367 FIELD_DP32_IDREG(isar, ID_PFR1, VIRTUALIZATION, 0); 2368 } 2369 2370 if (cpu_isar_feature(aa64_mte, cpu)) { 2371 /* 2372 * The architectural range of GM blocksize is 2-6, however qemu 2373 * doesn't support blocksize of 2 (see HELPER(ldgm)). 2374 */ 2375 if (tcg_enabled()) { 2376 assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6); 2377 } 2378 2379 #ifndef CONFIG_USER_ONLY 2380 /* 2381 * If we run with TCG and do not have tag-memory provided by 2382 * the machine, then reduce MTE support to instructions enabled at EL0. 2383 * This matches Cortex-A710 BROADCASTMTE input being LOW. 2384 */ 2385 if (tcg_enabled() && cpu->tag_memory == NULL) { 2386 FIELD_DP64_IDREG(isar, ID_AA64PFR1, MTE, 1); 2387 } 2388 2389 /* 2390 * If MTE is supported by the host, however it should not be 2391 * enabled on the guest (i.e mte=off), clear guest's MTE bits." 2392 */ 2393 if (kvm_enabled() && !cpu->kvm_mte) { 2394 FIELD_DP64_IDREG(isar, ID_AA64PFR1, MTE, 0); 2395 } 2396 #endif 2397 } 2398 2399 #ifndef CONFIG_USER_ONLY 2400 if (tcg_enabled() && cpu_isar_feature(aa64_wfxt, cpu)) { 2401 cpu->wfxt_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 2402 arm_wfxt_timer_cb, cpu); 2403 } 2404 #endif 2405 2406 if (tcg_enabled()) { 2407 /* 2408 * Don't report some architectural features in the ID registers 2409 * where TCG does not yet implement it (not even a minimal 2410 * stub version). This avoids guests falling over when they 2411 * try to access the non-existent system registers for them. 2412 */ 2413 /* FEAT_SPE (Statistical Profiling Extension) */ 2414 FIELD_DP64_IDREG(isar, ID_AA64DFR0, PMSVER, 0); 2415 /* FEAT_TRBE (Trace Buffer Extension) */ 2416 FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEBUFFER, 0); 2417 /* FEAT_TRF (Self-hosted Trace Extension) */ 2418 FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEFILT, 0); 2419 FIELD_DP32_IDREG(isar, ID_DFR0, TRACEFILT, 0); 2420 /* Trace Macrocell system register access */ 2421 FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEVER, 0); 2422 FIELD_DP32_IDREG(isar, ID_DFR0, COPTRC, 0); 2423 /* Memory mapped trace */ 2424 FIELD_DP32_IDREG(isar, ID_DFR0, MMAPTRC, 0); 2425 /* FEAT_AMU (Activity Monitors Extension) */ 2426 FIELD_DP64_IDREG(isar, ID_AA64PFR0, AMU, 0); 2427 FIELD_DP32_IDREG(isar, ID_PFR0, AMU, 0); 2428 /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ 2429 FIELD_DP64_IDREG(isar, ID_AA64PFR0, MPAM, 0); 2430 } 2431 2432 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 2433 * to false or by setting pmsav7-dregion to 0. 2434 */ 2435 if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) { 2436 cpu->has_mpu = false; 2437 cpu->pmsav7_dregion = 0; 2438 cpu->pmsav8r_hdregion = 0; 2439 } 2440 2441 if (arm_feature(env, ARM_FEATURE_PMSA) && 2442 arm_feature(env, ARM_FEATURE_V7)) { 2443 uint32_t nr = cpu->pmsav7_dregion; 2444 2445 if (nr > 0xff) { 2446 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 2447 return; 2448 } 2449 2450 if (nr) { 2451 if (arm_feature(env, ARM_FEATURE_V8)) { 2452 /* PMSAv8 */ 2453 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 2454 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 2455 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2456 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 2457 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 2458 } 2459 } else { 2460 env->pmsav7.drbar = g_new0(uint32_t, nr); 2461 env->pmsav7.drsr = g_new0(uint32_t, nr); 2462 env->pmsav7.dracr = g_new0(uint32_t, nr); 2463 } 2464 } 2465 2466 if (cpu->pmsav8r_hdregion > 0xff) { 2467 error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32, 2468 cpu->pmsav8r_hdregion); 2469 return; 2470 } 2471 2472 if (cpu->pmsav8r_hdregion) { 2473 env->pmsav8.hprbar = g_new0(uint32_t, 2474 cpu->pmsav8r_hdregion); 2475 env->pmsav8.hprlar = g_new0(uint32_t, 2476 cpu->pmsav8r_hdregion); 2477 } 2478 } 2479 2480 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2481 uint32_t nr = cpu->sau_sregion; 2482 2483 if (nr > 0xff) { 2484 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 2485 return; 2486 } 2487 2488 if (nr) { 2489 env->sau.rbar = g_new0(uint32_t, nr); 2490 env->sau.rlar = g_new0(uint32_t, nr); 2491 } 2492 } 2493 2494 if (arm_feature(env, ARM_FEATURE_EL3)) { 2495 set_feature(env, ARM_FEATURE_VBAR); 2496 } 2497 2498 #ifndef CONFIG_USER_ONLY 2499 if (tcg_enabled() && cpu_isar_feature(aa64_rme, cpu)) { 2500 arm_register_el_change_hook(cpu, >_rme_post_el_change, 0); 2501 } 2502 #endif 2503 2504 register_cp_regs_for_features(cpu); 2505 arm_cpu_register_gdb_regs_for_features(cpu); 2506 arm_cpu_register_gdb_commands(cpu); 2507 2508 init_cpreg_list(cpu); 2509 2510 #ifndef CONFIG_USER_ONLY 2511 MachineState *ms = MACHINE(qdev_get_machine()); 2512 unsigned int smp_cpus = ms->smp.cpus; 2513 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 2514 2515 /* 2516 * We must set cs->num_ases to the final value before 2517 * the first call to cpu_address_space_init. 2518 */ 2519 if (cpu->tag_memory != NULL) { 2520 cs->num_ases = 3 + has_secure; 2521 } else { 2522 cs->num_ases = 1 + has_secure; 2523 } 2524 2525 if (has_secure) { 2526 if (!cpu->secure_memory) { 2527 cpu->secure_memory = cs->memory; 2528 } 2529 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 2530 cpu->secure_memory); 2531 } 2532 2533 if (cpu->tag_memory != NULL) { 2534 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 2535 cpu->tag_memory); 2536 if (has_secure) { 2537 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 2538 cpu->secure_tag_memory); 2539 } 2540 } 2541 2542 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 2543 2544 /* No core_count specified, default to smp_cpus. */ 2545 if (cpu->core_count == -1) { 2546 cpu->core_count = smp_cpus; 2547 } 2548 #endif 2549 2550 if (tcg_enabled()) { 2551 int dcz_blocklen = 4 << cpu->dcz_blocksize; 2552 2553 /* 2554 * We only support DCZ blocklen that fits on one page. 2555 * 2556 * Architectually this is always true. However TARGET_PAGE_SIZE 2557 * is variable and, for compatibility with -machine virt-2.7, 2558 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 2559 * But even then, while the largest architectural DCZ blocklen 2560 * is 2KiB, no cpu actually uses such a large blocklen. 2561 */ 2562 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 2563 2564 /* 2565 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 2566 * both nibbles of each byte storing tag data may be written at once. 2567 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 2568 */ 2569 if (cpu_isar_feature(aa64_mte, cpu)) { 2570 assert(dcz_blocklen >= 2 * TAG_GRANULE); 2571 } 2572 } 2573 2574 qemu_init_vcpu(cs); 2575 cpu_reset(cs); 2576 2577 acc->parent_realize(dev, errp); 2578 } 2579 2580 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 2581 { 2582 ObjectClass *oc; 2583 char *typename; 2584 char **cpuname; 2585 const char *cpunamestr; 2586 2587 cpuname = g_strsplit(cpu_model, ",", 1); 2588 cpunamestr = cpuname[0]; 2589 #ifdef CONFIG_USER_ONLY 2590 /* For backwards compatibility usermode emulation allows "-cpu any", 2591 * which has the same semantics as "-cpu max". 2592 */ 2593 if (!strcmp(cpunamestr, "any")) { 2594 cpunamestr = "max"; 2595 } 2596 #endif 2597 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 2598 oc = object_class_by_name(typename); 2599 g_strfreev(cpuname); 2600 g_free(typename); 2601 2602 return oc; 2603 } 2604 2605 static const Property arm_cpu_properties[] = { 2606 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2607 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2608 mp_affinity, ARM64_AFFINITY_INVALID), 2609 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2610 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2611 /* True to default to the backward-compat old CNTFRQ rather than 1Ghz */ 2612 DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false), 2613 DEFINE_PROP_BOOL("backcompat-pauth-default-use-qarma5", ARMCPU, 2614 backcompat_pauth_default_use_qarma5, false), 2615 }; 2616 2617 static const gchar *arm_gdb_arch_name(CPUState *cs) 2618 { 2619 ARMCPU *cpu = ARM_CPU(cs); 2620 CPUARMState *env = &cpu->env; 2621 2622 if (arm_gdbstub_is_aarch64(cpu)) { 2623 return "aarch64"; 2624 } 2625 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2626 return "iwmmxt"; 2627 } 2628 return "arm"; 2629 } 2630 2631 static const char *arm_gdb_get_core_xml_file(CPUState *cs) 2632 { 2633 ARMCPU *cpu = ARM_CPU(cs); 2634 CPUARMState *env = &cpu->env; 2635 2636 if (arm_gdbstub_is_aarch64(cpu)) { 2637 return "aarch64-core.xml"; 2638 } 2639 if (arm_feature(env, ARM_FEATURE_M)) { 2640 return "arm-m-profile.xml"; 2641 } 2642 return "arm-core.xml"; 2643 } 2644 2645 #ifdef CONFIG_USER_ONLY 2646 /** 2647 * aarch64_untagged_addr: 2648 * 2649 * Remove any address tag from @x. This is explicitly related to the 2650 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 2651 * 2652 * There should be a better place to put this, but we need this in 2653 * include/accel/tcg/cpu-ldst.h, and not some place linux-user specific. 2654 * 2655 * Note that arm-*-user will never set tagged_addr_enable. 2656 */ 2657 static vaddr aarch64_untagged_addr(CPUState *cs, vaddr x) 2658 { 2659 CPUARMState *env = cpu_env(cs); 2660 if (env->tagged_addr_enable) { 2661 /* 2662 * TBI is enabled for userspace but not kernelspace addresses. 2663 * Only clear the tag if bit 55 is clear. 2664 */ 2665 x &= sextract64(x, 0, 56); 2666 } 2667 return x; 2668 } 2669 #else 2670 #include "hw/core/sysemu-cpu-ops.h" 2671 2672 static const struct SysemuCPUOps arm_sysemu_ops = { 2673 .has_work = arm_cpu_has_work, 2674 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2675 .asidx_from_attrs = arm_asidx_from_attrs, 2676 .write_elf32_note = arm_cpu_write_elf32_note, 2677 .write_elf64_note = arm_cpu_write_elf64_note, 2678 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2679 .legacy_vmsd = &vmstate_arm_cpu, 2680 }; 2681 #endif 2682 2683 #ifdef CONFIG_TCG 2684 #ifndef CONFIG_USER_ONLY 2685 static vaddr aprofile_pointer_wrap(CPUState *cs, int mmu_idx, 2686 vaddr result, vaddr base) 2687 { 2688 /* 2689 * The Stage2 and Phys indexes are only used for ptw on arm32, 2690 * and all pte's are aligned, so we never produce a wrap for these. 2691 * Double check that we're not truncating a 40-bit physical address. 2692 */ 2693 assert((unsigned)mmu_idx < (ARMMMUIdx_Stage2_S & ARM_MMU_IDX_COREIDX_MASK)); 2694 2695 if (!is_a64(cpu_env(cs))) { 2696 return (uint32_t)result; 2697 } 2698 2699 /* 2700 * TODO: For FEAT_CPA2, decide how to we want to resolve 2701 * Unpredictable_CPACHECK in AddressIncrement. 2702 */ 2703 return result; 2704 } 2705 #endif /* !CONFIG_USER_ONLY */ 2706 2707 static const TCGCPUOps arm_tcg_ops = { 2708 .mttcg_supported = true, 2709 /* ARM processors have a weak memory model */ 2710 .guest_default_memory_order = 0, 2711 2712 .initialize = arm_translate_init, 2713 .translate_code = arm_translate_code, 2714 .get_tb_cpu_state = arm_get_tb_cpu_state, 2715 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2716 .debug_excp_handler = arm_debug_excp_handler, 2717 .restore_state_to_opc = arm_restore_state_to_opc, 2718 .mmu_index = arm_cpu_mmu_index, 2719 2720 #ifdef CONFIG_USER_ONLY 2721 .record_sigsegv = arm_cpu_record_sigsegv, 2722 .record_sigbus = arm_cpu_record_sigbus, 2723 .untagged_addr = aarch64_untagged_addr, 2724 #else 2725 .tlb_fill_align = arm_cpu_tlb_fill_align, 2726 .pointer_wrap = aprofile_pointer_wrap, 2727 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2728 .cpu_exec_halt = arm_cpu_exec_halt, 2729 .cpu_exec_reset = cpu_reset, 2730 .do_interrupt = arm_cpu_do_interrupt, 2731 .do_transaction_failed = arm_cpu_do_transaction_failed, 2732 .do_unaligned_access = arm_cpu_do_unaligned_access, 2733 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2734 .debug_check_watchpoint = arm_debug_check_watchpoint, 2735 .debug_check_breakpoint = arm_debug_check_breakpoint, 2736 #endif /* !CONFIG_USER_ONLY */ 2737 }; 2738 #endif /* CONFIG_TCG */ 2739 2740 static void arm_cpu_class_init(ObjectClass *oc, const void *data) 2741 { 2742 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2743 CPUClass *cc = CPU_CLASS(acc); 2744 DeviceClass *dc = DEVICE_CLASS(oc); 2745 ResettableClass *rc = RESETTABLE_CLASS(oc); 2746 2747 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2748 &acc->parent_realize); 2749 2750 device_class_set_props(dc, arm_cpu_properties); 2751 2752 resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL, 2753 &acc->parent_phases); 2754 2755 cc->class_by_name = arm_cpu_class_by_name; 2756 cc->dump_state = arm_cpu_dump_state; 2757 cc->set_pc = arm_cpu_set_pc; 2758 cc->get_pc = arm_cpu_get_pc; 2759 cc->gdb_read_register = arm_cpu_gdb_read_register; 2760 cc->gdb_write_register = arm_cpu_gdb_write_register; 2761 #ifndef CONFIG_USER_ONLY 2762 cc->sysemu_ops = &arm_sysemu_ops; 2763 #endif 2764 cc->gdb_arch_name = arm_gdb_arch_name; 2765 cc->gdb_get_core_xml_file = arm_gdb_get_core_xml_file; 2766 cc->gdb_stop_before_watchpoint = true; 2767 cc->disas_set_info = arm_disas_set_info; 2768 2769 #ifdef CONFIG_TCG 2770 cc->tcg_ops = &arm_tcg_ops; 2771 #endif /* CONFIG_TCG */ 2772 } 2773 2774 static void arm_cpu_instance_init(Object *obj) 2775 { 2776 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2777 2778 acc->info->initfn(obj); 2779 arm_cpu_post_init(obj); 2780 } 2781 2782 static void cpu_register_class_init(ObjectClass *oc, const void *data) 2783 { 2784 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2785 CPUClass *cc = CPU_CLASS(acc); 2786 2787 acc->info = data; 2788 if (acc->info->deprecation_note) { 2789 cc->deprecation_note = acc->info->deprecation_note; 2790 } 2791 } 2792 2793 void arm_cpu_register(const ARMCPUInfo *info) 2794 { 2795 TypeInfo type_info = { 2796 .parent = TYPE_ARM_CPU, 2797 .instance_init = arm_cpu_instance_init, 2798 .class_init = info->class_init ?: cpu_register_class_init, 2799 .class_data = info, 2800 }; 2801 2802 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2803 type_register_static(&type_info); 2804 g_free((void *)type_info.name); 2805 } 2806 2807 static const TypeInfo arm_cpu_type_info = { 2808 .name = TYPE_ARM_CPU, 2809 .parent = TYPE_CPU, 2810 .instance_size = sizeof(ARMCPU), 2811 .instance_align = __alignof__(ARMCPU), 2812 .instance_init = arm_cpu_initfn, 2813 .instance_finalize = arm_cpu_finalizefn, 2814 .abstract = true, 2815 .class_size = sizeof(ARMCPUClass), 2816 .class_init = arm_cpu_class_init, 2817 }; 2818 2819 static void arm_cpu_register_types(void) 2820 { 2821 type_register_static(&arm_cpu_type_info); 2822 } 2823 2824 type_init(arm_cpu_register_types) 2825