1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/error-report.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "qemu-common.h" 27 #include "exec/exec-all.h" 28 #include "hw/qdev-properties.h" 29 #if !defined(CONFIG_USER_ONLY) 30 #include "hw/loader.h" 31 #endif 32 #include "hw/arm/arm.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/kvm.h" 35 #include "kvm_arm.h" 36 37 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 38 { 39 ARMCPU *cpu = ARM_CPU(cs); 40 41 cpu->env.regs[15] = value; 42 } 43 44 static bool arm_cpu_has_work(CPUState *cs) 45 { 46 ARMCPU *cpu = ARM_CPU(cs); 47 48 return !cpu->powered_off 49 && cs->interrupt_request & 50 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 51 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 52 | CPU_INTERRUPT_EXITTB); 53 } 54 55 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 56 void *opaque) 57 { 58 /* We currently only support registering a single hook function */ 59 assert(!cpu->el_change_hook); 60 cpu->el_change_hook = hook; 61 cpu->el_change_hook_opaque = opaque; 62 } 63 64 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 65 { 66 /* Reset a single ARMCPRegInfo register */ 67 ARMCPRegInfo *ri = value; 68 ARMCPU *cpu = opaque; 69 70 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 71 return; 72 } 73 74 if (ri->resetfn) { 75 ri->resetfn(&cpu->env, ri); 76 return; 77 } 78 79 /* A zero offset is never possible as it would be regs[0] 80 * so we use it to indicate that reset is being handled elsewhere. 81 * This is basically only used for fields in non-core coprocessors 82 * (like the pxa2xx ones). 83 */ 84 if (!ri->fieldoffset) { 85 return; 86 } 87 88 if (cpreg_field_is_64bit(ri)) { 89 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 90 } else { 91 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 92 } 93 } 94 95 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 96 { 97 /* Purely an assertion check: we've already done reset once, 98 * so now check that running the reset for the cpreg doesn't 99 * change its value. This traps bugs where two different cpregs 100 * both try to reset the same state field but to different values. 101 */ 102 ARMCPRegInfo *ri = value; 103 ARMCPU *cpu = opaque; 104 uint64_t oldvalue, newvalue; 105 106 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 107 return; 108 } 109 110 oldvalue = read_raw_cp_reg(&cpu->env, ri); 111 cp_reg_reset(key, value, opaque); 112 newvalue = read_raw_cp_reg(&cpu->env, ri); 113 assert(oldvalue == newvalue); 114 } 115 116 /* CPUClass::reset() */ 117 static void arm_cpu_reset(CPUState *s) 118 { 119 ARMCPU *cpu = ARM_CPU(s); 120 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 121 CPUARMState *env = &cpu->env; 122 123 acc->parent_reset(s); 124 125 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 126 127 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 128 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 129 130 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 131 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; 132 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; 133 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; 134 135 cpu->powered_off = cpu->start_powered_off; 136 s->halted = cpu->start_powered_off; 137 138 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 139 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 140 } 141 142 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 143 /* 64 bit CPUs always start in 64 bit mode */ 144 env->aarch64 = 1; 145 #if defined(CONFIG_USER_ONLY) 146 env->pstate = PSTATE_MODE_EL0t; 147 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 148 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 149 /* and to the FP/Neon instructions */ 150 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 151 #else 152 /* Reset into the highest available EL */ 153 if (arm_feature(env, ARM_FEATURE_EL3)) { 154 env->pstate = PSTATE_MODE_EL3h; 155 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 156 env->pstate = PSTATE_MODE_EL2h; 157 } else { 158 env->pstate = PSTATE_MODE_EL1h; 159 } 160 env->pc = cpu->rvbar; 161 #endif 162 } else { 163 #if defined(CONFIG_USER_ONLY) 164 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 165 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 166 #endif 167 } 168 169 #if defined(CONFIG_USER_ONLY) 170 env->uncached_cpsr = ARM_CPU_MODE_USR; 171 /* For user mode we must enable access to coprocessors */ 172 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 173 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 174 env->cp15.c15_cpar = 3; 175 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 176 env->cp15.c15_cpar = 1; 177 } 178 #else 179 /* SVC mode with interrupts disabled. */ 180 env->uncached_cpsr = ARM_CPU_MODE_SVC; 181 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 182 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is 183 * clear at reset. Initial SP and PC are loaded from ROM. 184 */ 185 if (IS_M(env)) { 186 uint32_t initial_msp; /* Loaded from 0x0 */ 187 uint32_t initial_pc; /* Loaded from 0x4 */ 188 uint8_t *rom; 189 190 env->daif &= ~PSTATE_I; 191 rom = rom_ptr(0); 192 if (rom) { 193 /* Address zero is covered by ROM which hasn't yet been 194 * copied into physical memory. 195 */ 196 initial_msp = ldl_p(rom); 197 initial_pc = ldl_p(rom + 4); 198 } else { 199 /* Address zero not covered by a ROM blob, or the ROM blob 200 * is in non-modifiable memory and this is a second reset after 201 * it got copied into memory. In the latter case, rom_ptr 202 * will return a NULL pointer and we should use ldl_phys instead. 203 */ 204 initial_msp = ldl_phys(s->as, 0); 205 initial_pc = ldl_phys(s->as, 4); 206 } 207 208 env->regs[13] = initial_msp & 0xFFFFFFFC; 209 env->regs[15] = initial_pc & ~1; 210 env->thumb = initial_pc & 1; 211 } 212 213 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 214 * executing as AArch32 then check if highvecs are enabled and 215 * adjust the PC accordingly. 216 */ 217 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 218 env->regs[15] = 0xFFFF0000; 219 } 220 221 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 222 #endif 223 set_flush_to_zero(1, &env->vfp.standard_fp_status); 224 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 225 set_default_nan_mode(1, &env->vfp.standard_fp_status); 226 set_float_detect_tininess(float_tininess_before_rounding, 227 &env->vfp.fp_status); 228 set_float_detect_tininess(float_tininess_before_rounding, 229 &env->vfp.standard_fp_status); 230 #ifndef CONFIG_USER_ONLY 231 if (kvm_enabled()) { 232 kvm_arm_reset_vcpu(cpu); 233 } 234 #endif 235 236 hw_breakpoint_update_all(cpu); 237 hw_watchpoint_update_all(cpu); 238 } 239 240 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 241 { 242 CPUClass *cc = CPU_GET_CLASS(cs); 243 CPUARMState *env = cs->env_ptr; 244 uint32_t cur_el = arm_current_el(env); 245 bool secure = arm_is_secure(env); 246 uint32_t target_el; 247 uint32_t excp_idx; 248 bool ret = false; 249 250 if (interrupt_request & CPU_INTERRUPT_FIQ) { 251 excp_idx = EXCP_FIQ; 252 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 253 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 254 cs->exception_index = excp_idx; 255 env->exception.target_el = target_el; 256 cc->do_interrupt(cs); 257 ret = true; 258 } 259 } 260 if (interrupt_request & CPU_INTERRUPT_HARD) { 261 excp_idx = EXCP_IRQ; 262 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 263 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 264 cs->exception_index = excp_idx; 265 env->exception.target_el = target_el; 266 cc->do_interrupt(cs); 267 ret = true; 268 } 269 } 270 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 271 excp_idx = EXCP_VIRQ; 272 target_el = 1; 273 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 274 cs->exception_index = excp_idx; 275 env->exception.target_el = target_el; 276 cc->do_interrupt(cs); 277 ret = true; 278 } 279 } 280 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 281 excp_idx = EXCP_VFIQ; 282 target_el = 1; 283 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 284 cs->exception_index = excp_idx; 285 env->exception.target_el = target_el; 286 cc->do_interrupt(cs); 287 ret = true; 288 } 289 } 290 291 return ret; 292 } 293 294 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 295 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 296 { 297 CPUClass *cc = CPU_GET_CLASS(cs); 298 ARMCPU *cpu = ARM_CPU(cs); 299 CPUARMState *env = &cpu->env; 300 bool ret = false; 301 302 303 if (interrupt_request & CPU_INTERRUPT_FIQ 304 && !(env->daif & PSTATE_F)) { 305 cs->exception_index = EXCP_FIQ; 306 cc->do_interrupt(cs); 307 ret = true; 308 } 309 /* ARMv7-M interrupt return works by loading a magic value 310 * into the PC. On real hardware the load causes the 311 * return to occur. The qemu implementation performs the 312 * jump normally, then does the exception return when the 313 * CPU tries to execute code at the magic address. 314 * This will cause the magic PC value to be pushed to 315 * the stack if an interrupt occurred at the wrong time. 316 * We avoid this by disabling interrupts when 317 * pc contains a magic address. 318 */ 319 if (interrupt_request & CPU_INTERRUPT_HARD 320 && !(env->daif & PSTATE_I) 321 && (env->regs[15] < 0xfffffff0)) { 322 cs->exception_index = EXCP_IRQ; 323 cc->do_interrupt(cs); 324 ret = true; 325 } 326 return ret; 327 } 328 #endif 329 330 #ifndef CONFIG_USER_ONLY 331 static void arm_cpu_set_irq(void *opaque, int irq, int level) 332 { 333 ARMCPU *cpu = opaque; 334 CPUARMState *env = &cpu->env; 335 CPUState *cs = CPU(cpu); 336 static const int mask[] = { 337 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 338 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 339 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 340 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 341 }; 342 343 switch (irq) { 344 case ARM_CPU_VIRQ: 345 case ARM_CPU_VFIQ: 346 assert(arm_feature(env, ARM_FEATURE_EL2)); 347 /* fall through */ 348 case ARM_CPU_IRQ: 349 case ARM_CPU_FIQ: 350 if (level) { 351 cpu_interrupt(cs, mask[irq]); 352 } else { 353 cpu_reset_interrupt(cs, mask[irq]); 354 } 355 break; 356 default: 357 g_assert_not_reached(); 358 } 359 } 360 361 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 362 { 363 #ifdef CONFIG_KVM 364 ARMCPU *cpu = opaque; 365 CPUState *cs = CPU(cpu); 366 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 367 368 switch (irq) { 369 case ARM_CPU_IRQ: 370 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 371 break; 372 case ARM_CPU_FIQ: 373 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 374 break; 375 default: 376 g_assert_not_reached(); 377 } 378 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 379 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 380 #endif 381 } 382 383 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 384 { 385 ARMCPU *cpu = ARM_CPU(cs); 386 CPUARMState *env = &cpu->env; 387 388 cpu_synchronize_state(cs); 389 return arm_cpu_data_is_big_endian(env); 390 } 391 392 #endif 393 394 static inline void set_feature(CPUARMState *env, int feature) 395 { 396 env->features |= 1ULL << feature; 397 } 398 399 static inline void unset_feature(CPUARMState *env, int feature) 400 { 401 env->features &= ~(1ULL << feature); 402 } 403 404 static int 405 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 406 { 407 return print_insn_arm(pc | 1, info); 408 } 409 410 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 411 { 412 ARMCPU *ac = ARM_CPU(cpu); 413 CPUARMState *env = &ac->env; 414 415 if (is_a64(env)) { 416 /* We might not be compiled with the A64 disassembler 417 * because it needs a C++ compiler. Leave print_insn 418 * unset in this case to use the caller default behaviour. 419 */ 420 #if defined(CONFIG_ARM_A64_DIS) 421 info->print_insn = print_insn_arm_a64; 422 #endif 423 } else if (env->thumb) { 424 info->print_insn = print_insn_thumb1; 425 } else { 426 info->print_insn = print_insn_arm; 427 } 428 if (bswap_code(arm_sctlr_b(env))) { 429 #ifdef TARGET_WORDS_BIGENDIAN 430 info->endian = BFD_ENDIAN_LITTLE; 431 #else 432 info->endian = BFD_ENDIAN_BIG; 433 #endif 434 } 435 } 436 437 static void arm_cpu_initfn(Object *obj) 438 { 439 CPUState *cs = CPU(obj); 440 ARMCPU *cpu = ARM_CPU(obj); 441 static bool inited; 442 443 cs->env_ptr = &cpu->env; 444 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 445 g_free, g_free); 446 447 #ifndef CONFIG_USER_ONLY 448 /* Our inbound IRQ and FIQ lines */ 449 if (kvm_enabled()) { 450 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 451 * the same interface as non-KVM CPUs. 452 */ 453 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 454 } else { 455 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 456 } 457 458 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 459 arm_gt_ptimer_cb, cpu); 460 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 461 arm_gt_vtimer_cb, cpu); 462 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 463 arm_gt_htimer_cb, cpu); 464 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 465 arm_gt_stimer_cb, cpu); 466 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 467 ARRAY_SIZE(cpu->gt_timer_outputs)); 468 469 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 470 "gicv3-maintenance-interrupt", 1); 471 #endif 472 473 /* DTB consumers generally don't in fact care what the 'compatible' 474 * string is, so always provide some string and trust that a hypothetical 475 * picky DTB consumer will also provide a helpful error message. 476 */ 477 cpu->dtb_compatible = "qemu,unknown"; 478 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 479 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 480 481 if (tcg_enabled()) { 482 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 483 if (!inited) { 484 inited = true; 485 arm_translate_init(); 486 } 487 } 488 } 489 490 static Property arm_cpu_reset_cbar_property = 491 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 492 493 static Property arm_cpu_reset_hivecs_property = 494 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 495 496 static Property arm_cpu_rvbar_property = 497 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 498 499 static Property arm_cpu_has_el3_property = 500 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 501 502 /* use property name "pmu" to match other archs and virt tools */ 503 static Property arm_cpu_has_pmu_property = 504 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 505 506 static Property arm_cpu_has_mpu_property = 507 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 508 509 static Property arm_cpu_pmsav7_dregion_property = 510 DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU, pmsav7_dregion, 16); 511 512 static void arm_cpu_post_init(Object *obj) 513 { 514 ARMCPU *cpu = ARM_CPU(obj); 515 516 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 517 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 518 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 519 &error_abort); 520 } 521 522 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 523 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 524 &error_abort); 525 } 526 527 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 528 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 529 &error_abort); 530 } 531 532 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 533 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 534 * prevent "has_el3" from existing on CPUs which cannot support EL3. 535 */ 536 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 537 &error_abort); 538 539 #ifndef CONFIG_USER_ONLY 540 object_property_add_link(obj, "secure-memory", 541 TYPE_MEMORY_REGION, 542 (Object **)&cpu->secure_memory, 543 qdev_prop_allow_set_link_before_realize, 544 OBJ_PROP_LINK_UNREF_ON_RELEASE, 545 &error_abort); 546 #endif 547 } 548 549 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 550 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 551 &error_abort); 552 } 553 554 if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) { 555 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 556 &error_abort); 557 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 558 qdev_property_add_static(DEVICE(obj), 559 &arm_cpu_pmsav7_dregion_property, 560 &error_abort); 561 } 562 } 563 564 } 565 566 static void arm_cpu_finalizefn(Object *obj) 567 { 568 ARMCPU *cpu = ARM_CPU(obj); 569 g_hash_table_destroy(cpu->cp_regs); 570 } 571 572 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 573 { 574 CPUState *cs = CPU(dev); 575 ARMCPU *cpu = ARM_CPU(dev); 576 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 577 CPUARMState *env = &cpu->env; 578 int pagebits; 579 Error *local_err = NULL; 580 581 cpu_exec_realizefn(cs, &local_err); 582 if (local_err != NULL) { 583 error_propagate(errp, local_err); 584 return; 585 } 586 587 /* Some features automatically imply others: */ 588 if (arm_feature(env, ARM_FEATURE_V8)) { 589 set_feature(env, ARM_FEATURE_V7); 590 set_feature(env, ARM_FEATURE_ARM_DIV); 591 set_feature(env, ARM_FEATURE_LPAE); 592 } 593 if (arm_feature(env, ARM_FEATURE_V7)) { 594 set_feature(env, ARM_FEATURE_VAPA); 595 set_feature(env, ARM_FEATURE_THUMB2); 596 set_feature(env, ARM_FEATURE_MPIDR); 597 if (!arm_feature(env, ARM_FEATURE_M)) { 598 set_feature(env, ARM_FEATURE_V6K); 599 } else { 600 set_feature(env, ARM_FEATURE_V6); 601 } 602 603 /* Always define VBAR for V7 CPUs even if it doesn't exist in 604 * non-EL3 configs. This is needed by some legacy boards. 605 */ 606 set_feature(env, ARM_FEATURE_VBAR); 607 } 608 if (arm_feature(env, ARM_FEATURE_V6K)) { 609 set_feature(env, ARM_FEATURE_V6); 610 set_feature(env, ARM_FEATURE_MVFR); 611 } 612 if (arm_feature(env, ARM_FEATURE_V6)) { 613 set_feature(env, ARM_FEATURE_V5); 614 if (!arm_feature(env, ARM_FEATURE_M)) { 615 set_feature(env, ARM_FEATURE_AUXCR); 616 } 617 } 618 if (arm_feature(env, ARM_FEATURE_V5)) { 619 set_feature(env, ARM_FEATURE_V4T); 620 } 621 if (arm_feature(env, ARM_FEATURE_M)) { 622 set_feature(env, ARM_FEATURE_THUMB_DIV); 623 } 624 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { 625 set_feature(env, ARM_FEATURE_THUMB_DIV); 626 } 627 if (arm_feature(env, ARM_FEATURE_VFP4)) { 628 set_feature(env, ARM_FEATURE_VFP3); 629 set_feature(env, ARM_FEATURE_VFP_FP16); 630 } 631 if (arm_feature(env, ARM_FEATURE_VFP3)) { 632 set_feature(env, ARM_FEATURE_VFP); 633 } 634 if (arm_feature(env, ARM_FEATURE_LPAE)) { 635 set_feature(env, ARM_FEATURE_V7MP); 636 set_feature(env, ARM_FEATURE_PXN); 637 } 638 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 639 set_feature(env, ARM_FEATURE_CBAR); 640 } 641 if (arm_feature(env, ARM_FEATURE_THUMB2) && 642 !arm_feature(env, ARM_FEATURE_M)) { 643 set_feature(env, ARM_FEATURE_THUMB_DSP); 644 } 645 646 if (arm_feature(env, ARM_FEATURE_V7) && 647 !arm_feature(env, ARM_FEATURE_M) && 648 !arm_feature(env, ARM_FEATURE_MPU)) { 649 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 650 * can use 4K pages. 651 */ 652 pagebits = 12; 653 } else { 654 /* For CPUs which might have tiny 1K pages, or which have an 655 * MPU and might have small region sizes, stick with 1K pages. 656 */ 657 pagebits = 10; 658 } 659 if (!set_preferred_target_page_bits(pagebits)) { 660 /* This can only ever happen for hotplugging a CPU, or if 661 * the board code incorrectly creates a CPU which it has 662 * promised via minimum_page_size that it will not. 663 */ 664 error_setg(errp, "This CPU requires a smaller page size than the " 665 "system is using"); 666 return; 667 } 668 669 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 670 * We don't support setting cluster ID ([16..23]) (known as Aff2 671 * in later ARM ARM versions), or any of the higher affinity level fields, 672 * so these bits always RAZ. 673 */ 674 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 675 uint32_t Aff1 = cs->cpu_index / ARM_DEFAULT_CPUS_PER_CLUSTER; 676 uint32_t Aff0 = cs->cpu_index % ARM_DEFAULT_CPUS_PER_CLUSTER; 677 cpu->mp_affinity = (Aff1 << ARM_AFF1_SHIFT) | Aff0; 678 } 679 680 if (cpu->reset_hivecs) { 681 cpu->reset_sctlr |= (1 << 13); 682 } 683 684 if (!cpu->has_el3) { 685 /* If the has_el3 CPU property is disabled then we need to disable the 686 * feature. 687 */ 688 unset_feature(env, ARM_FEATURE_EL3); 689 690 /* Disable the security extension feature bits in the processor feature 691 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 692 */ 693 cpu->id_pfr1 &= ~0xf0; 694 cpu->id_aa64pfr0 &= ~0xf000; 695 } 696 697 if (!cpu->has_pmu || !kvm_enabled()) { 698 cpu->has_pmu = false; 699 unset_feature(env, ARM_FEATURE_PMU); 700 } 701 702 if (!arm_feature(env, ARM_FEATURE_EL2)) { 703 /* Disable the hypervisor feature bits in the processor feature 704 * registers if we don't have EL2. These are id_pfr1[15:12] and 705 * id_aa64pfr0_el1[11:8]. 706 */ 707 cpu->id_aa64pfr0 &= ~0xf00; 708 cpu->id_pfr1 &= ~0xf000; 709 } 710 711 if (!cpu->has_mpu) { 712 unset_feature(env, ARM_FEATURE_MPU); 713 } 714 715 if (arm_feature(env, ARM_FEATURE_MPU) && 716 arm_feature(env, ARM_FEATURE_V7)) { 717 uint32_t nr = cpu->pmsav7_dregion; 718 719 if (nr > 0xff) { 720 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 721 return; 722 } 723 724 if (nr) { 725 env->pmsav7.drbar = g_new0(uint32_t, nr); 726 env->pmsav7.drsr = g_new0(uint32_t, nr); 727 env->pmsav7.dracr = g_new0(uint32_t, nr); 728 } 729 } 730 731 if (arm_feature(env, ARM_FEATURE_EL3)) { 732 set_feature(env, ARM_FEATURE_VBAR); 733 } 734 735 register_cp_regs_for_features(cpu); 736 arm_cpu_register_gdb_regs_for_features(cpu); 737 738 init_cpreg_list(cpu); 739 740 #ifndef CONFIG_USER_ONLY 741 if (cpu->has_el3) { 742 cs->num_ases = 2; 743 } else { 744 cs->num_ases = 1; 745 } 746 747 if (cpu->has_el3) { 748 AddressSpace *as; 749 750 if (!cpu->secure_memory) { 751 cpu->secure_memory = cs->memory; 752 } 753 as = address_space_init_shareable(cpu->secure_memory, 754 "cpu-secure-memory"); 755 cpu_address_space_init(cs, as, ARMASIdx_S); 756 } 757 cpu_address_space_init(cs, 758 address_space_init_shareable(cs->memory, 759 "cpu-memory"), 760 ARMASIdx_NS); 761 #endif 762 763 qemu_init_vcpu(cs); 764 cpu_reset(cs); 765 766 acc->parent_realize(dev, errp); 767 } 768 769 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 770 { 771 ObjectClass *oc; 772 char *typename; 773 char **cpuname; 774 775 if (!cpu_model) { 776 return NULL; 777 } 778 779 cpuname = g_strsplit(cpu_model, ",", 1); 780 typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]); 781 oc = object_class_by_name(typename); 782 g_strfreev(cpuname); 783 g_free(typename); 784 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 785 object_class_is_abstract(oc)) { 786 return NULL; 787 } 788 return oc; 789 } 790 791 /* CPU models. These are not needed for the AArch64 linux-user build. */ 792 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 793 794 static void arm926_initfn(Object *obj) 795 { 796 ARMCPU *cpu = ARM_CPU(obj); 797 798 cpu->dtb_compatible = "arm,arm926"; 799 set_feature(&cpu->env, ARM_FEATURE_V5); 800 set_feature(&cpu->env, ARM_FEATURE_VFP); 801 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 802 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 803 cpu->midr = 0x41069265; 804 cpu->reset_fpsid = 0x41011090; 805 cpu->ctr = 0x1dd20d2; 806 cpu->reset_sctlr = 0x00090078; 807 } 808 809 static void arm946_initfn(Object *obj) 810 { 811 ARMCPU *cpu = ARM_CPU(obj); 812 813 cpu->dtb_compatible = "arm,arm946"; 814 set_feature(&cpu->env, ARM_FEATURE_V5); 815 set_feature(&cpu->env, ARM_FEATURE_MPU); 816 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 817 cpu->midr = 0x41059461; 818 cpu->ctr = 0x0f004006; 819 cpu->reset_sctlr = 0x00000078; 820 } 821 822 static void arm1026_initfn(Object *obj) 823 { 824 ARMCPU *cpu = ARM_CPU(obj); 825 826 cpu->dtb_compatible = "arm,arm1026"; 827 set_feature(&cpu->env, ARM_FEATURE_V5); 828 set_feature(&cpu->env, ARM_FEATURE_VFP); 829 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 830 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 831 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 832 cpu->midr = 0x4106a262; 833 cpu->reset_fpsid = 0x410110a0; 834 cpu->ctr = 0x1dd20d2; 835 cpu->reset_sctlr = 0x00090078; 836 cpu->reset_auxcr = 1; 837 { 838 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 839 ARMCPRegInfo ifar = { 840 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 841 .access = PL1_RW, 842 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 843 .resetvalue = 0 844 }; 845 define_one_arm_cp_reg(cpu, &ifar); 846 } 847 } 848 849 static void arm1136_r2_initfn(Object *obj) 850 { 851 ARMCPU *cpu = ARM_CPU(obj); 852 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 853 * older core than plain "arm1136". In particular this does not 854 * have the v6K features. 855 * These ID register values are correct for 1136 but may be wrong 856 * for 1136_r2 (in particular r0p2 does not actually implement most 857 * of the ID registers). 858 */ 859 860 cpu->dtb_compatible = "arm,arm1136"; 861 set_feature(&cpu->env, ARM_FEATURE_V6); 862 set_feature(&cpu->env, ARM_FEATURE_VFP); 863 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 864 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 865 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 866 cpu->midr = 0x4107b362; 867 cpu->reset_fpsid = 0x410120b4; 868 cpu->mvfr0 = 0x11111111; 869 cpu->mvfr1 = 0x00000000; 870 cpu->ctr = 0x1dd20d2; 871 cpu->reset_sctlr = 0x00050078; 872 cpu->id_pfr0 = 0x111; 873 cpu->id_pfr1 = 0x1; 874 cpu->id_dfr0 = 0x2; 875 cpu->id_afr0 = 0x3; 876 cpu->id_mmfr0 = 0x01130003; 877 cpu->id_mmfr1 = 0x10030302; 878 cpu->id_mmfr2 = 0x01222110; 879 cpu->id_isar0 = 0x00140011; 880 cpu->id_isar1 = 0x12002111; 881 cpu->id_isar2 = 0x11231111; 882 cpu->id_isar3 = 0x01102131; 883 cpu->id_isar4 = 0x141; 884 cpu->reset_auxcr = 7; 885 } 886 887 static void arm1136_initfn(Object *obj) 888 { 889 ARMCPU *cpu = ARM_CPU(obj); 890 891 cpu->dtb_compatible = "arm,arm1136"; 892 set_feature(&cpu->env, ARM_FEATURE_V6K); 893 set_feature(&cpu->env, ARM_FEATURE_V6); 894 set_feature(&cpu->env, ARM_FEATURE_VFP); 895 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 896 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 897 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 898 cpu->midr = 0x4117b363; 899 cpu->reset_fpsid = 0x410120b4; 900 cpu->mvfr0 = 0x11111111; 901 cpu->mvfr1 = 0x00000000; 902 cpu->ctr = 0x1dd20d2; 903 cpu->reset_sctlr = 0x00050078; 904 cpu->id_pfr0 = 0x111; 905 cpu->id_pfr1 = 0x1; 906 cpu->id_dfr0 = 0x2; 907 cpu->id_afr0 = 0x3; 908 cpu->id_mmfr0 = 0x01130003; 909 cpu->id_mmfr1 = 0x10030302; 910 cpu->id_mmfr2 = 0x01222110; 911 cpu->id_isar0 = 0x00140011; 912 cpu->id_isar1 = 0x12002111; 913 cpu->id_isar2 = 0x11231111; 914 cpu->id_isar3 = 0x01102131; 915 cpu->id_isar4 = 0x141; 916 cpu->reset_auxcr = 7; 917 } 918 919 static void arm1176_initfn(Object *obj) 920 { 921 ARMCPU *cpu = ARM_CPU(obj); 922 923 cpu->dtb_compatible = "arm,arm1176"; 924 set_feature(&cpu->env, ARM_FEATURE_V6K); 925 set_feature(&cpu->env, ARM_FEATURE_VFP); 926 set_feature(&cpu->env, ARM_FEATURE_VAPA); 927 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 928 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 929 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 930 set_feature(&cpu->env, ARM_FEATURE_EL3); 931 cpu->midr = 0x410fb767; 932 cpu->reset_fpsid = 0x410120b5; 933 cpu->mvfr0 = 0x11111111; 934 cpu->mvfr1 = 0x00000000; 935 cpu->ctr = 0x1dd20d2; 936 cpu->reset_sctlr = 0x00050078; 937 cpu->id_pfr0 = 0x111; 938 cpu->id_pfr1 = 0x11; 939 cpu->id_dfr0 = 0x33; 940 cpu->id_afr0 = 0; 941 cpu->id_mmfr0 = 0x01130003; 942 cpu->id_mmfr1 = 0x10030302; 943 cpu->id_mmfr2 = 0x01222100; 944 cpu->id_isar0 = 0x0140011; 945 cpu->id_isar1 = 0x12002111; 946 cpu->id_isar2 = 0x11231121; 947 cpu->id_isar3 = 0x01102131; 948 cpu->id_isar4 = 0x01141; 949 cpu->reset_auxcr = 7; 950 } 951 952 static void arm11mpcore_initfn(Object *obj) 953 { 954 ARMCPU *cpu = ARM_CPU(obj); 955 956 cpu->dtb_compatible = "arm,arm11mpcore"; 957 set_feature(&cpu->env, ARM_FEATURE_V6K); 958 set_feature(&cpu->env, ARM_FEATURE_VFP); 959 set_feature(&cpu->env, ARM_FEATURE_VAPA); 960 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 961 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 962 cpu->midr = 0x410fb022; 963 cpu->reset_fpsid = 0x410120b4; 964 cpu->mvfr0 = 0x11111111; 965 cpu->mvfr1 = 0x00000000; 966 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 967 cpu->id_pfr0 = 0x111; 968 cpu->id_pfr1 = 0x1; 969 cpu->id_dfr0 = 0; 970 cpu->id_afr0 = 0x2; 971 cpu->id_mmfr0 = 0x01100103; 972 cpu->id_mmfr1 = 0x10020302; 973 cpu->id_mmfr2 = 0x01222000; 974 cpu->id_isar0 = 0x00100011; 975 cpu->id_isar1 = 0x12002111; 976 cpu->id_isar2 = 0x11221011; 977 cpu->id_isar3 = 0x01102131; 978 cpu->id_isar4 = 0x141; 979 cpu->reset_auxcr = 1; 980 } 981 982 static void cortex_m3_initfn(Object *obj) 983 { 984 ARMCPU *cpu = ARM_CPU(obj); 985 set_feature(&cpu->env, ARM_FEATURE_V7); 986 set_feature(&cpu->env, ARM_FEATURE_M); 987 cpu->midr = 0x410fc231; 988 } 989 990 static void cortex_m4_initfn(Object *obj) 991 { 992 ARMCPU *cpu = ARM_CPU(obj); 993 994 set_feature(&cpu->env, ARM_FEATURE_V7); 995 set_feature(&cpu->env, ARM_FEATURE_M); 996 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 997 cpu->midr = 0x410fc240; /* r0p0 */ 998 } 999 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1000 { 1001 CPUClass *cc = CPU_CLASS(oc); 1002 1003 #ifndef CONFIG_USER_ONLY 1004 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1005 #endif 1006 1007 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1008 } 1009 1010 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1011 /* Dummy the TCM region regs for the moment */ 1012 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1013 .access = PL1_RW, .type = ARM_CP_CONST }, 1014 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1015 .access = PL1_RW, .type = ARM_CP_CONST }, 1016 REGINFO_SENTINEL 1017 }; 1018 1019 static void cortex_r5_initfn(Object *obj) 1020 { 1021 ARMCPU *cpu = ARM_CPU(obj); 1022 1023 set_feature(&cpu->env, ARM_FEATURE_V7); 1024 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); 1025 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1026 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1027 set_feature(&cpu->env, ARM_FEATURE_MPU); 1028 cpu->midr = 0x411fc153; /* r1p3 */ 1029 cpu->id_pfr0 = 0x0131; 1030 cpu->id_pfr1 = 0x001; 1031 cpu->id_dfr0 = 0x010400; 1032 cpu->id_afr0 = 0x0; 1033 cpu->id_mmfr0 = 0x0210030; 1034 cpu->id_mmfr1 = 0x00000000; 1035 cpu->id_mmfr2 = 0x01200000; 1036 cpu->id_mmfr3 = 0x0211; 1037 cpu->id_isar0 = 0x2101111; 1038 cpu->id_isar1 = 0x13112111; 1039 cpu->id_isar2 = 0x21232141; 1040 cpu->id_isar3 = 0x01112131; 1041 cpu->id_isar4 = 0x0010142; 1042 cpu->id_isar5 = 0x0; 1043 cpu->mp_is_up = true; 1044 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1045 } 1046 1047 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1048 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1049 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1050 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1051 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1052 REGINFO_SENTINEL 1053 }; 1054 1055 static void cortex_a8_initfn(Object *obj) 1056 { 1057 ARMCPU *cpu = ARM_CPU(obj); 1058 1059 cpu->dtb_compatible = "arm,cortex-a8"; 1060 set_feature(&cpu->env, ARM_FEATURE_V7); 1061 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1062 set_feature(&cpu->env, ARM_FEATURE_NEON); 1063 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1064 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1065 set_feature(&cpu->env, ARM_FEATURE_EL3); 1066 cpu->midr = 0x410fc080; 1067 cpu->reset_fpsid = 0x410330c0; 1068 cpu->mvfr0 = 0x11110222; 1069 cpu->mvfr1 = 0x00011111; 1070 cpu->ctr = 0x82048004; 1071 cpu->reset_sctlr = 0x00c50078; 1072 cpu->id_pfr0 = 0x1031; 1073 cpu->id_pfr1 = 0x11; 1074 cpu->id_dfr0 = 0x400; 1075 cpu->id_afr0 = 0; 1076 cpu->id_mmfr0 = 0x31100003; 1077 cpu->id_mmfr1 = 0x20000000; 1078 cpu->id_mmfr2 = 0x01202000; 1079 cpu->id_mmfr3 = 0x11; 1080 cpu->id_isar0 = 0x00101111; 1081 cpu->id_isar1 = 0x12112111; 1082 cpu->id_isar2 = 0x21232031; 1083 cpu->id_isar3 = 0x11112131; 1084 cpu->id_isar4 = 0x00111142; 1085 cpu->dbgdidr = 0x15141000; 1086 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1087 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1088 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1089 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1090 cpu->reset_auxcr = 2; 1091 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1092 } 1093 1094 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1095 /* power_control should be set to maximum latency. Again, 1096 * default to 0 and set by private hook 1097 */ 1098 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1099 .access = PL1_RW, .resetvalue = 0, 1100 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1101 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1102 .access = PL1_RW, .resetvalue = 0, 1103 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1104 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1105 .access = PL1_RW, .resetvalue = 0, 1106 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1107 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1108 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1109 /* TLB lockdown control */ 1110 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1111 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1112 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1113 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1114 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1115 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1116 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1117 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1118 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1119 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1120 REGINFO_SENTINEL 1121 }; 1122 1123 static void cortex_a9_initfn(Object *obj) 1124 { 1125 ARMCPU *cpu = ARM_CPU(obj); 1126 1127 cpu->dtb_compatible = "arm,cortex-a9"; 1128 set_feature(&cpu->env, ARM_FEATURE_V7); 1129 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1130 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); 1131 set_feature(&cpu->env, ARM_FEATURE_NEON); 1132 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1133 set_feature(&cpu->env, ARM_FEATURE_EL3); 1134 /* Note that A9 supports the MP extensions even for 1135 * A9UP and single-core A9MP (which are both different 1136 * and valid configurations; we don't model A9UP). 1137 */ 1138 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1139 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1140 cpu->midr = 0x410fc090; 1141 cpu->reset_fpsid = 0x41033090; 1142 cpu->mvfr0 = 0x11110222; 1143 cpu->mvfr1 = 0x01111111; 1144 cpu->ctr = 0x80038003; 1145 cpu->reset_sctlr = 0x00c50078; 1146 cpu->id_pfr0 = 0x1031; 1147 cpu->id_pfr1 = 0x11; 1148 cpu->id_dfr0 = 0x000; 1149 cpu->id_afr0 = 0; 1150 cpu->id_mmfr0 = 0x00100103; 1151 cpu->id_mmfr1 = 0x20000000; 1152 cpu->id_mmfr2 = 0x01230000; 1153 cpu->id_mmfr3 = 0x00002111; 1154 cpu->id_isar0 = 0x00101111; 1155 cpu->id_isar1 = 0x13112111; 1156 cpu->id_isar2 = 0x21232041; 1157 cpu->id_isar3 = 0x11112131; 1158 cpu->id_isar4 = 0x00111142; 1159 cpu->dbgdidr = 0x35141000; 1160 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1161 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1162 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1163 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1164 } 1165 1166 #ifndef CONFIG_USER_ONLY 1167 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1168 { 1169 /* Linux wants the number of processors from here. 1170 * Might as well set the interrupt-controller bit too. 1171 */ 1172 return ((smp_cpus - 1) << 24) | (1 << 23); 1173 } 1174 #endif 1175 1176 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1177 #ifndef CONFIG_USER_ONLY 1178 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1179 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1180 .writefn = arm_cp_write_ignore, }, 1181 #endif 1182 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1183 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1184 REGINFO_SENTINEL 1185 }; 1186 1187 static void cortex_a7_initfn(Object *obj) 1188 { 1189 ARMCPU *cpu = ARM_CPU(obj); 1190 1191 cpu->dtb_compatible = "arm,cortex-a7"; 1192 set_feature(&cpu->env, ARM_FEATURE_V7); 1193 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1194 set_feature(&cpu->env, ARM_FEATURE_NEON); 1195 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1196 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1197 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1198 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1199 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1200 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1201 set_feature(&cpu->env, ARM_FEATURE_EL3); 1202 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1203 cpu->midr = 0x410fc075; 1204 cpu->reset_fpsid = 0x41023075; 1205 cpu->mvfr0 = 0x10110222; 1206 cpu->mvfr1 = 0x11111111; 1207 cpu->ctr = 0x84448003; 1208 cpu->reset_sctlr = 0x00c50078; 1209 cpu->id_pfr0 = 0x00001131; 1210 cpu->id_pfr1 = 0x00011011; 1211 cpu->id_dfr0 = 0x02010555; 1212 cpu->pmceid0 = 0x00000000; 1213 cpu->pmceid1 = 0x00000000; 1214 cpu->id_afr0 = 0x00000000; 1215 cpu->id_mmfr0 = 0x10101105; 1216 cpu->id_mmfr1 = 0x40000000; 1217 cpu->id_mmfr2 = 0x01240000; 1218 cpu->id_mmfr3 = 0x02102211; 1219 cpu->id_isar0 = 0x01101110; 1220 cpu->id_isar1 = 0x13112111; 1221 cpu->id_isar2 = 0x21232041; 1222 cpu->id_isar3 = 0x11112131; 1223 cpu->id_isar4 = 0x10011142; 1224 cpu->dbgdidr = 0x3515f005; 1225 cpu->clidr = 0x0a200023; 1226 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1227 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1228 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1229 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1230 } 1231 1232 static void cortex_a15_initfn(Object *obj) 1233 { 1234 ARMCPU *cpu = ARM_CPU(obj); 1235 1236 cpu->dtb_compatible = "arm,cortex-a15"; 1237 set_feature(&cpu->env, ARM_FEATURE_V7); 1238 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1239 set_feature(&cpu->env, ARM_FEATURE_NEON); 1240 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1241 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1242 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1243 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1244 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1245 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1246 set_feature(&cpu->env, ARM_FEATURE_EL3); 1247 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1248 cpu->midr = 0x412fc0f1; 1249 cpu->reset_fpsid = 0x410430f0; 1250 cpu->mvfr0 = 0x10110222; 1251 cpu->mvfr1 = 0x11111111; 1252 cpu->ctr = 0x8444c004; 1253 cpu->reset_sctlr = 0x00c50078; 1254 cpu->id_pfr0 = 0x00001131; 1255 cpu->id_pfr1 = 0x00011011; 1256 cpu->id_dfr0 = 0x02010555; 1257 cpu->pmceid0 = 0x0000000; 1258 cpu->pmceid1 = 0x00000000; 1259 cpu->id_afr0 = 0x00000000; 1260 cpu->id_mmfr0 = 0x10201105; 1261 cpu->id_mmfr1 = 0x20000000; 1262 cpu->id_mmfr2 = 0x01240000; 1263 cpu->id_mmfr3 = 0x02102211; 1264 cpu->id_isar0 = 0x02101110; 1265 cpu->id_isar1 = 0x13112111; 1266 cpu->id_isar2 = 0x21232041; 1267 cpu->id_isar3 = 0x11112131; 1268 cpu->id_isar4 = 0x10011142; 1269 cpu->dbgdidr = 0x3515f021; 1270 cpu->clidr = 0x0a200023; 1271 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1272 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1273 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1274 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 1275 } 1276 1277 static void ti925t_initfn(Object *obj) 1278 { 1279 ARMCPU *cpu = ARM_CPU(obj); 1280 set_feature(&cpu->env, ARM_FEATURE_V4T); 1281 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 1282 cpu->midr = ARM_CPUID_TI925T; 1283 cpu->ctr = 0x5109149; 1284 cpu->reset_sctlr = 0x00000070; 1285 } 1286 1287 static void sa1100_initfn(Object *obj) 1288 { 1289 ARMCPU *cpu = ARM_CPU(obj); 1290 1291 cpu->dtb_compatible = "intel,sa1100"; 1292 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1293 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1294 cpu->midr = 0x4401A11B; 1295 cpu->reset_sctlr = 0x00000070; 1296 } 1297 1298 static void sa1110_initfn(Object *obj) 1299 { 1300 ARMCPU *cpu = ARM_CPU(obj); 1301 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1302 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1303 cpu->midr = 0x6901B119; 1304 cpu->reset_sctlr = 0x00000070; 1305 } 1306 1307 static void pxa250_initfn(Object *obj) 1308 { 1309 ARMCPU *cpu = ARM_CPU(obj); 1310 1311 cpu->dtb_compatible = "marvell,xscale"; 1312 set_feature(&cpu->env, ARM_FEATURE_V5); 1313 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1314 cpu->midr = 0x69052100; 1315 cpu->ctr = 0xd172172; 1316 cpu->reset_sctlr = 0x00000078; 1317 } 1318 1319 static void pxa255_initfn(Object *obj) 1320 { 1321 ARMCPU *cpu = ARM_CPU(obj); 1322 1323 cpu->dtb_compatible = "marvell,xscale"; 1324 set_feature(&cpu->env, ARM_FEATURE_V5); 1325 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1326 cpu->midr = 0x69052d00; 1327 cpu->ctr = 0xd172172; 1328 cpu->reset_sctlr = 0x00000078; 1329 } 1330 1331 static void pxa260_initfn(Object *obj) 1332 { 1333 ARMCPU *cpu = ARM_CPU(obj); 1334 1335 cpu->dtb_compatible = "marvell,xscale"; 1336 set_feature(&cpu->env, ARM_FEATURE_V5); 1337 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1338 cpu->midr = 0x69052903; 1339 cpu->ctr = 0xd172172; 1340 cpu->reset_sctlr = 0x00000078; 1341 } 1342 1343 static void pxa261_initfn(Object *obj) 1344 { 1345 ARMCPU *cpu = ARM_CPU(obj); 1346 1347 cpu->dtb_compatible = "marvell,xscale"; 1348 set_feature(&cpu->env, ARM_FEATURE_V5); 1349 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1350 cpu->midr = 0x69052d05; 1351 cpu->ctr = 0xd172172; 1352 cpu->reset_sctlr = 0x00000078; 1353 } 1354 1355 static void pxa262_initfn(Object *obj) 1356 { 1357 ARMCPU *cpu = ARM_CPU(obj); 1358 1359 cpu->dtb_compatible = "marvell,xscale"; 1360 set_feature(&cpu->env, ARM_FEATURE_V5); 1361 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1362 cpu->midr = 0x69052d06; 1363 cpu->ctr = 0xd172172; 1364 cpu->reset_sctlr = 0x00000078; 1365 } 1366 1367 static void pxa270a0_initfn(Object *obj) 1368 { 1369 ARMCPU *cpu = ARM_CPU(obj); 1370 1371 cpu->dtb_compatible = "marvell,xscale"; 1372 set_feature(&cpu->env, ARM_FEATURE_V5); 1373 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1374 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1375 cpu->midr = 0x69054110; 1376 cpu->ctr = 0xd172172; 1377 cpu->reset_sctlr = 0x00000078; 1378 } 1379 1380 static void pxa270a1_initfn(Object *obj) 1381 { 1382 ARMCPU *cpu = ARM_CPU(obj); 1383 1384 cpu->dtb_compatible = "marvell,xscale"; 1385 set_feature(&cpu->env, ARM_FEATURE_V5); 1386 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1387 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1388 cpu->midr = 0x69054111; 1389 cpu->ctr = 0xd172172; 1390 cpu->reset_sctlr = 0x00000078; 1391 } 1392 1393 static void pxa270b0_initfn(Object *obj) 1394 { 1395 ARMCPU *cpu = ARM_CPU(obj); 1396 1397 cpu->dtb_compatible = "marvell,xscale"; 1398 set_feature(&cpu->env, ARM_FEATURE_V5); 1399 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1400 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1401 cpu->midr = 0x69054112; 1402 cpu->ctr = 0xd172172; 1403 cpu->reset_sctlr = 0x00000078; 1404 } 1405 1406 static void pxa270b1_initfn(Object *obj) 1407 { 1408 ARMCPU *cpu = ARM_CPU(obj); 1409 1410 cpu->dtb_compatible = "marvell,xscale"; 1411 set_feature(&cpu->env, ARM_FEATURE_V5); 1412 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1413 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1414 cpu->midr = 0x69054113; 1415 cpu->ctr = 0xd172172; 1416 cpu->reset_sctlr = 0x00000078; 1417 } 1418 1419 static void pxa270c0_initfn(Object *obj) 1420 { 1421 ARMCPU *cpu = ARM_CPU(obj); 1422 1423 cpu->dtb_compatible = "marvell,xscale"; 1424 set_feature(&cpu->env, ARM_FEATURE_V5); 1425 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1426 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1427 cpu->midr = 0x69054114; 1428 cpu->ctr = 0xd172172; 1429 cpu->reset_sctlr = 0x00000078; 1430 } 1431 1432 static void pxa270c5_initfn(Object *obj) 1433 { 1434 ARMCPU *cpu = ARM_CPU(obj); 1435 1436 cpu->dtb_compatible = "marvell,xscale"; 1437 set_feature(&cpu->env, ARM_FEATURE_V5); 1438 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1439 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1440 cpu->midr = 0x69054117; 1441 cpu->ctr = 0xd172172; 1442 cpu->reset_sctlr = 0x00000078; 1443 } 1444 1445 #ifdef CONFIG_USER_ONLY 1446 static void arm_any_initfn(Object *obj) 1447 { 1448 ARMCPU *cpu = ARM_CPU(obj); 1449 set_feature(&cpu->env, ARM_FEATURE_V8); 1450 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1451 set_feature(&cpu->env, ARM_FEATURE_NEON); 1452 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1453 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 1454 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 1455 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 1456 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 1457 set_feature(&cpu->env, ARM_FEATURE_CRC); 1458 cpu->midr = 0xffffffff; 1459 } 1460 #endif 1461 1462 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 1463 1464 typedef struct ARMCPUInfo { 1465 const char *name; 1466 void (*initfn)(Object *obj); 1467 void (*class_init)(ObjectClass *oc, void *data); 1468 } ARMCPUInfo; 1469 1470 static const ARMCPUInfo arm_cpus[] = { 1471 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1472 { .name = "arm926", .initfn = arm926_initfn }, 1473 { .name = "arm946", .initfn = arm946_initfn }, 1474 { .name = "arm1026", .initfn = arm1026_initfn }, 1475 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1476 * older core than plain "arm1136". In particular this does not 1477 * have the v6K features. 1478 */ 1479 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1480 { .name = "arm1136", .initfn = arm1136_initfn }, 1481 { .name = "arm1176", .initfn = arm1176_initfn }, 1482 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1483 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 1484 .class_init = arm_v7m_class_init }, 1485 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 1486 .class_init = arm_v7m_class_init }, 1487 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1488 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1489 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1490 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1491 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1492 { .name = "ti925t", .initfn = ti925t_initfn }, 1493 { .name = "sa1100", .initfn = sa1100_initfn }, 1494 { .name = "sa1110", .initfn = sa1110_initfn }, 1495 { .name = "pxa250", .initfn = pxa250_initfn }, 1496 { .name = "pxa255", .initfn = pxa255_initfn }, 1497 { .name = "pxa260", .initfn = pxa260_initfn }, 1498 { .name = "pxa261", .initfn = pxa261_initfn }, 1499 { .name = "pxa262", .initfn = pxa262_initfn }, 1500 /* "pxa270" is an alias for "pxa270-a0" */ 1501 { .name = "pxa270", .initfn = pxa270a0_initfn }, 1502 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 1503 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 1504 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 1505 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 1506 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 1507 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 1508 #ifdef CONFIG_USER_ONLY 1509 { .name = "any", .initfn = arm_any_initfn }, 1510 #endif 1511 #endif 1512 { .name = NULL } 1513 }; 1514 1515 static Property arm_cpu_properties[] = { 1516 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 1517 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 1518 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 1519 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 1520 mp_affinity, ARM64_AFFINITY_INVALID), 1521 DEFINE_PROP_END_OF_LIST() 1522 }; 1523 1524 #ifdef CONFIG_USER_ONLY 1525 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, 1526 int mmu_idx) 1527 { 1528 ARMCPU *cpu = ARM_CPU(cs); 1529 CPUARMState *env = &cpu->env; 1530 1531 env->exception.vaddress = address; 1532 if (rw == 2) { 1533 cs->exception_index = EXCP_PREFETCH_ABORT; 1534 } else { 1535 cs->exception_index = EXCP_DATA_ABORT; 1536 } 1537 return 1; 1538 } 1539 #endif 1540 1541 static gchar *arm_gdb_arch_name(CPUState *cs) 1542 { 1543 ARMCPU *cpu = ARM_CPU(cs); 1544 CPUARMState *env = &cpu->env; 1545 1546 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 1547 return g_strdup("iwmmxt"); 1548 } 1549 return g_strdup("arm"); 1550 } 1551 1552 static void arm_cpu_class_init(ObjectClass *oc, void *data) 1553 { 1554 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1555 CPUClass *cc = CPU_CLASS(acc); 1556 DeviceClass *dc = DEVICE_CLASS(oc); 1557 1558 acc->parent_realize = dc->realize; 1559 dc->realize = arm_cpu_realizefn; 1560 dc->props = arm_cpu_properties; 1561 1562 acc->parent_reset = cc->reset; 1563 cc->reset = arm_cpu_reset; 1564 1565 cc->class_by_name = arm_cpu_class_by_name; 1566 cc->has_work = arm_cpu_has_work; 1567 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 1568 cc->dump_state = arm_cpu_dump_state; 1569 cc->set_pc = arm_cpu_set_pc; 1570 cc->gdb_read_register = arm_cpu_gdb_read_register; 1571 cc->gdb_write_register = arm_cpu_gdb_write_register; 1572 #ifdef CONFIG_USER_ONLY 1573 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; 1574 #else 1575 cc->do_interrupt = arm_cpu_do_interrupt; 1576 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 1577 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 1578 cc->asidx_from_attrs = arm_asidx_from_attrs; 1579 cc->vmsd = &vmstate_arm_cpu; 1580 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 1581 cc->write_elf64_note = arm_cpu_write_elf64_note; 1582 cc->write_elf32_note = arm_cpu_write_elf32_note; 1583 #endif 1584 cc->gdb_num_core_regs = 26; 1585 cc->gdb_core_xml_file = "arm-core.xml"; 1586 cc->gdb_arch_name = arm_gdb_arch_name; 1587 cc->gdb_stop_before_watchpoint = true; 1588 cc->debug_excp_handler = arm_debug_excp_handler; 1589 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 1590 1591 cc->disas_set_info = arm_disas_set_info; 1592 } 1593 1594 static void cpu_register(const ARMCPUInfo *info) 1595 { 1596 TypeInfo type_info = { 1597 .parent = TYPE_ARM_CPU, 1598 .instance_size = sizeof(ARMCPU), 1599 .instance_init = info->initfn, 1600 .class_size = sizeof(ARMCPUClass), 1601 .class_init = info->class_init, 1602 }; 1603 1604 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 1605 type_register(&type_info); 1606 g_free((void *)type_info.name); 1607 } 1608 1609 static const TypeInfo arm_cpu_type_info = { 1610 .name = TYPE_ARM_CPU, 1611 .parent = TYPE_CPU, 1612 .instance_size = sizeof(ARMCPU), 1613 .instance_init = arm_cpu_initfn, 1614 .instance_post_init = arm_cpu_post_init, 1615 .instance_finalize = arm_cpu_finalizefn, 1616 .abstract = true, 1617 .class_size = sizeof(ARMCPUClass), 1618 .class_init = arm_cpu_class_init, 1619 }; 1620 1621 static void arm_cpu_register_types(void) 1622 { 1623 const ARMCPUInfo *info = arm_cpus; 1624 1625 type_register_static(&arm_cpu_type_info); 1626 1627 while (info->name) { 1628 cpu_register(info); 1629 info++; 1630 } 1631 } 1632 1633 type_init(arm_cpu_register_types) 1634