1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu-common.h" 24 #include "target/arm/idau.h" 25 #include "qemu/module.h" 26 #include "qapi/error.h" 27 #include "qapi/visitor.h" 28 #include "cpu.h" 29 #include "internals.h" 30 #include "exec/exec-all.h" 31 #include "hw/qdev-properties.h" 32 #if !defined(CONFIG_USER_ONLY) 33 #include "hw/loader.h" 34 #include "hw/boards.h" 35 #endif 36 #include "sysemu/sysemu.h" 37 #include "sysemu/tcg.h" 38 #include "sysemu/hw_accel.h" 39 #include "kvm_arm.h" 40 #include "disas/capstone.h" 41 #include "fpu/softfloat.h" 42 43 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 44 { 45 ARMCPU *cpu = ARM_CPU(cs); 46 CPUARMState *env = &cpu->env; 47 48 if (is_a64(env)) { 49 env->pc = value; 50 env->thumb = 0; 51 } else { 52 env->regs[15] = value & ~1; 53 env->thumb = value & 1; 54 } 55 } 56 57 static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 58 { 59 ARMCPU *cpu = ARM_CPU(cs); 60 CPUARMState *env = &cpu->env; 61 62 /* 63 * It's OK to look at env for the current mode here, because it's 64 * never possible for an AArch64 TB to chain to an AArch32 TB. 65 */ 66 if (is_a64(env)) { 67 env->pc = tb->pc; 68 } else { 69 env->regs[15] = tb->pc; 70 } 71 } 72 73 static bool arm_cpu_has_work(CPUState *cs) 74 { 75 ARMCPU *cpu = ARM_CPU(cs); 76 77 return (cpu->power_state != PSCI_OFF) 78 && cs->interrupt_request & 79 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 80 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 81 | CPU_INTERRUPT_EXITTB); 82 } 83 84 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 85 void *opaque) 86 { 87 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 88 89 entry->hook = hook; 90 entry->opaque = opaque; 91 92 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 93 } 94 95 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 96 void *opaque) 97 { 98 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 99 100 entry->hook = hook; 101 entry->opaque = opaque; 102 103 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 104 } 105 106 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 107 { 108 /* Reset a single ARMCPRegInfo register */ 109 ARMCPRegInfo *ri = value; 110 ARMCPU *cpu = opaque; 111 112 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 113 return; 114 } 115 116 if (ri->resetfn) { 117 ri->resetfn(&cpu->env, ri); 118 return; 119 } 120 121 /* A zero offset is never possible as it would be regs[0] 122 * so we use it to indicate that reset is being handled elsewhere. 123 * This is basically only used for fields in non-core coprocessors 124 * (like the pxa2xx ones). 125 */ 126 if (!ri->fieldoffset) { 127 return; 128 } 129 130 if (cpreg_field_is_64bit(ri)) { 131 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 132 } else { 133 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 134 } 135 } 136 137 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 138 { 139 /* Purely an assertion check: we've already done reset once, 140 * so now check that running the reset for the cpreg doesn't 141 * change its value. This traps bugs where two different cpregs 142 * both try to reset the same state field but to different values. 143 */ 144 ARMCPRegInfo *ri = value; 145 ARMCPU *cpu = opaque; 146 uint64_t oldvalue, newvalue; 147 148 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 149 return; 150 } 151 152 oldvalue = read_raw_cp_reg(&cpu->env, ri); 153 cp_reg_reset(key, value, opaque); 154 newvalue = read_raw_cp_reg(&cpu->env, ri); 155 assert(oldvalue == newvalue); 156 } 157 158 static void arm_cpu_reset(DeviceState *dev) 159 { 160 CPUState *s = CPU(dev); 161 ARMCPU *cpu = ARM_CPU(s); 162 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 163 CPUARMState *env = &cpu->env; 164 165 acc->parent_reset(dev); 166 167 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 168 169 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 170 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 171 172 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 173 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 174 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 175 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 176 177 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 178 s->halted = cpu->start_powered_off; 179 180 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 181 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 182 } 183 184 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 185 /* 64 bit CPUs always start in 64 bit mode */ 186 env->aarch64 = 1; 187 #if defined(CONFIG_USER_ONLY) 188 env->pstate = PSTATE_MODE_EL0t; 189 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 190 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 191 /* Enable all PAC keys. */ 192 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 193 SCTLR_EnDA | SCTLR_EnDB); 194 /* and to the FP/Neon instructions */ 195 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 196 /* and to the SVE instructions */ 197 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 198 /* with reasonable vector length */ 199 if (cpu_isar_feature(aa64_sve, cpu)) { 200 env->vfp.zcr_el[1] = MIN(cpu->sve_max_vq - 1, 3); 201 } 202 /* 203 * Enable TBI0 and TBI1. While the real kernel only enables TBI0, 204 * turning on both here will produce smaller code and otherwise 205 * make no difference to the user-level emulation. 206 */ 207 env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); 208 #else 209 /* Reset into the highest available EL */ 210 if (arm_feature(env, ARM_FEATURE_EL3)) { 211 env->pstate = PSTATE_MODE_EL3h; 212 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 213 env->pstate = PSTATE_MODE_EL2h; 214 } else { 215 env->pstate = PSTATE_MODE_EL1h; 216 } 217 env->pc = cpu->rvbar; 218 #endif 219 } else { 220 #if defined(CONFIG_USER_ONLY) 221 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 222 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 223 #endif 224 } 225 226 #if defined(CONFIG_USER_ONLY) 227 env->uncached_cpsr = ARM_CPU_MODE_USR; 228 /* For user mode we must enable access to coprocessors */ 229 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 230 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 231 env->cp15.c15_cpar = 3; 232 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 233 env->cp15.c15_cpar = 1; 234 } 235 #else 236 237 /* 238 * If the highest available EL is EL2, AArch32 will start in Hyp 239 * mode; otherwise it starts in SVC. Note that if we start in 240 * AArch64 then these values in the uncached_cpsr will be ignored. 241 */ 242 if (arm_feature(env, ARM_FEATURE_EL2) && 243 !arm_feature(env, ARM_FEATURE_EL3)) { 244 env->uncached_cpsr = ARM_CPU_MODE_HYP; 245 } else { 246 env->uncached_cpsr = ARM_CPU_MODE_SVC; 247 } 248 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 249 250 if (arm_feature(env, ARM_FEATURE_M)) { 251 uint32_t initial_msp; /* Loaded from 0x0 */ 252 uint32_t initial_pc; /* Loaded from 0x4 */ 253 uint8_t *rom; 254 uint32_t vecbase; 255 256 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 257 env->v7m.secure = true; 258 } else { 259 /* This bit resets to 0 if security is supported, but 1 if 260 * it is not. The bit is not present in v7M, but we set it 261 * here so we can avoid having to make checks on it conditional 262 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 263 */ 264 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 265 /* 266 * Set NSACR to indicate "NS access permitted to everything"; 267 * this avoids having to have all the tests of it being 268 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 269 * v8.1M the guest-visible value of NSACR in a CPU without the 270 * Security Extension is 0xcff. 271 */ 272 env->v7m.nsacr = 0xcff; 273 } 274 275 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 276 * that it resets to 1, so QEMU always does that rather than making 277 * it dependent on CPU model. In v8M it is RES1. 278 */ 279 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 280 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 281 if (arm_feature(env, ARM_FEATURE_V8)) { 282 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 283 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 284 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 285 } 286 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 287 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 288 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 289 } 290 291 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 292 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 293 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 294 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 295 } 296 /* Unlike A/R profile, M profile defines the reset LR value */ 297 env->regs[14] = 0xffffffff; 298 299 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 300 301 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 302 vecbase = env->v7m.vecbase[env->v7m.secure]; 303 rom = rom_ptr(vecbase, 8); 304 if (rom) { 305 /* Address zero is covered by ROM which hasn't yet been 306 * copied into physical memory. 307 */ 308 initial_msp = ldl_p(rom); 309 initial_pc = ldl_p(rom + 4); 310 } else { 311 /* Address zero not covered by a ROM blob, or the ROM blob 312 * is in non-modifiable memory and this is a second reset after 313 * it got copied into memory. In the latter case, rom_ptr 314 * will return a NULL pointer and we should use ldl_phys instead. 315 */ 316 initial_msp = ldl_phys(s->as, vecbase); 317 initial_pc = ldl_phys(s->as, vecbase + 4); 318 } 319 320 env->regs[13] = initial_msp & 0xFFFFFFFC; 321 env->regs[15] = initial_pc & ~1; 322 env->thumb = initial_pc & 1; 323 } 324 325 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 326 * executing as AArch32 then check if highvecs are enabled and 327 * adjust the PC accordingly. 328 */ 329 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 330 env->regs[15] = 0xFFFF0000; 331 } 332 333 /* M profile requires that reset clears the exclusive monitor; 334 * A profile does not, but clearing it makes more sense than having it 335 * set with an exclusive access on address zero. 336 */ 337 arm_clear_exclusive(env); 338 339 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 340 #endif 341 342 if (arm_feature(env, ARM_FEATURE_PMSA)) { 343 if (cpu->pmsav7_dregion > 0) { 344 if (arm_feature(env, ARM_FEATURE_V8)) { 345 memset(env->pmsav8.rbar[M_REG_NS], 0, 346 sizeof(*env->pmsav8.rbar[M_REG_NS]) 347 * cpu->pmsav7_dregion); 348 memset(env->pmsav8.rlar[M_REG_NS], 0, 349 sizeof(*env->pmsav8.rlar[M_REG_NS]) 350 * cpu->pmsav7_dregion); 351 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 352 memset(env->pmsav8.rbar[M_REG_S], 0, 353 sizeof(*env->pmsav8.rbar[M_REG_S]) 354 * cpu->pmsav7_dregion); 355 memset(env->pmsav8.rlar[M_REG_S], 0, 356 sizeof(*env->pmsav8.rlar[M_REG_S]) 357 * cpu->pmsav7_dregion); 358 } 359 } else if (arm_feature(env, ARM_FEATURE_V7)) { 360 memset(env->pmsav7.drbar, 0, 361 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 362 memset(env->pmsav7.drsr, 0, 363 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 364 memset(env->pmsav7.dracr, 0, 365 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 366 } 367 } 368 env->pmsav7.rnr[M_REG_NS] = 0; 369 env->pmsav7.rnr[M_REG_S] = 0; 370 env->pmsav8.mair0[M_REG_NS] = 0; 371 env->pmsav8.mair0[M_REG_S] = 0; 372 env->pmsav8.mair1[M_REG_NS] = 0; 373 env->pmsav8.mair1[M_REG_S] = 0; 374 } 375 376 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 377 if (cpu->sau_sregion > 0) { 378 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 379 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 380 } 381 env->sau.rnr = 0; 382 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 383 * the Cortex-M33 does. 384 */ 385 env->sau.ctrl = 0; 386 } 387 388 set_flush_to_zero(1, &env->vfp.standard_fp_status); 389 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 390 set_default_nan_mode(1, &env->vfp.standard_fp_status); 391 set_float_detect_tininess(float_tininess_before_rounding, 392 &env->vfp.fp_status); 393 set_float_detect_tininess(float_tininess_before_rounding, 394 &env->vfp.standard_fp_status); 395 set_float_detect_tininess(float_tininess_before_rounding, 396 &env->vfp.fp_status_f16); 397 #ifndef CONFIG_USER_ONLY 398 if (kvm_enabled()) { 399 kvm_arm_reset_vcpu(cpu); 400 } 401 #endif 402 403 hw_breakpoint_update_all(cpu); 404 hw_watchpoint_update_all(cpu); 405 arm_rebuild_hflags(env); 406 } 407 408 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 409 unsigned int target_el, 410 unsigned int cur_el, bool secure, 411 uint64_t hcr_el2) 412 { 413 CPUARMState *env = cs->env_ptr; 414 bool pstate_unmasked; 415 bool unmasked = false; 416 417 /* 418 * Don't take exceptions if they target a lower EL. 419 * This check should catch any exceptions that would not be taken 420 * but left pending. 421 */ 422 if (cur_el > target_el) { 423 return false; 424 } 425 426 switch (excp_idx) { 427 case EXCP_FIQ: 428 pstate_unmasked = !(env->daif & PSTATE_F); 429 break; 430 431 case EXCP_IRQ: 432 pstate_unmasked = !(env->daif & PSTATE_I); 433 break; 434 435 case EXCP_VFIQ: 436 if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 437 /* VFIQs are only taken when hypervized and non-secure. */ 438 return false; 439 } 440 return !(env->daif & PSTATE_F); 441 case EXCP_VIRQ: 442 if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 443 /* VIRQs are only taken when hypervized and non-secure. */ 444 return false; 445 } 446 return !(env->daif & PSTATE_I); 447 default: 448 g_assert_not_reached(); 449 } 450 451 /* 452 * Use the target EL, current execution state and SCR/HCR settings to 453 * determine whether the corresponding CPSR bit is used to mask the 454 * interrupt. 455 */ 456 if ((target_el > cur_el) && (target_el != 1)) { 457 /* Exceptions targeting a higher EL may not be maskable */ 458 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 459 /* 460 * 64-bit masking rules are simple: exceptions to EL3 461 * can't be masked, and exceptions to EL2 can only be 462 * masked from Secure state. The HCR and SCR settings 463 * don't affect the masking logic, only the interrupt routing. 464 */ 465 if (target_el == 3 || !secure) { 466 unmasked = true; 467 } 468 } else { 469 /* 470 * The old 32-bit-only environment has a more complicated 471 * masking setup. HCR and SCR bits not only affect interrupt 472 * routing but also change the behaviour of masking. 473 */ 474 bool hcr, scr; 475 476 switch (excp_idx) { 477 case EXCP_FIQ: 478 /* 479 * If FIQs are routed to EL3 or EL2 then there are cases where 480 * we override the CPSR.F in determining if the exception is 481 * masked or not. If neither of these are set then we fall back 482 * to the CPSR.F setting otherwise we further assess the state 483 * below. 484 */ 485 hcr = hcr_el2 & HCR_FMO; 486 scr = (env->cp15.scr_el3 & SCR_FIQ); 487 488 /* 489 * When EL3 is 32-bit, the SCR.FW bit controls whether the 490 * CPSR.F bit masks FIQ interrupts when taken in non-secure 491 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 492 * when non-secure but only when FIQs are only routed to EL3. 493 */ 494 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 495 break; 496 case EXCP_IRQ: 497 /* 498 * When EL3 execution state is 32-bit, if HCR.IMO is set then 499 * we may override the CPSR.I masking when in non-secure state. 500 * The SCR.IRQ setting has already been taken into consideration 501 * when setting the target EL, so it does not have a further 502 * affect here. 503 */ 504 hcr = hcr_el2 & HCR_IMO; 505 scr = false; 506 break; 507 default: 508 g_assert_not_reached(); 509 } 510 511 if ((scr || hcr) && !secure) { 512 unmasked = true; 513 } 514 } 515 } 516 517 /* 518 * The PSTATE bits only mask the interrupt if we have not overriden the 519 * ability above. 520 */ 521 return unmasked || pstate_unmasked; 522 } 523 524 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 525 { 526 CPUClass *cc = CPU_GET_CLASS(cs); 527 CPUARMState *env = cs->env_ptr; 528 uint32_t cur_el = arm_current_el(env); 529 bool secure = arm_is_secure(env); 530 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 531 uint32_t target_el; 532 uint32_t excp_idx; 533 534 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 535 536 if (interrupt_request & CPU_INTERRUPT_FIQ) { 537 excp_idx = EXCP_FIQ; 538 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 539 if (arm_excp_unmasked(cs, excp_idx, target_el, 540 cur_el, secure, hcr_el2)) { 541 goto found; 542 } 543 } 544 if (interrupt_request & CPU_INTERRUPT_HARD) { 545 excp_idx = EXCP_IRQ; 546 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 547 if (arm_excp_unmasked(cs, excp_idx, target_el, 548 cur_el, secure, hcr_el2)) { 549 goto found; 550 } 551 } 552 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 553 excp_idx = EXCP_VIRQ; 554 target_el = 1; 555 if (arm_excp_unmasked(cs, excp_idx, target_el, 556 cur_el, secure, hcr_el2)) { 557 goto found; 558 } 559 } 560 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 561 excp_idx = EXCP_VFIQ; 562 target_el = 1; 563 if (arm_excp_unmasked(cs, excp_idx, target_el, 564 cur_el, secure, hcr_el2)) { 565 goto found; 566 } 567 } 568 return false; 569 570 found: 571 cs->exception_index = excp_idx; 572 env->exception.target_el = target_el; 573 cc->do_interrupt(cs); 574 return true; 575 } 576 577 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 578 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 579 { 580 CPUClass *cc = CPU_GET_CLASS(cs); 581 ARMCPU *cpu = ARM_CPU(cs); 582 CPUARMState *env = &cpu->env; 583 bool ret = false; 584 585 /* ARMv7-M interrupt masking works differently than -A or -R. 586 * There is no FIQ/IRQ distinction. Instead of I and F bits 587 * masking FIQ and IRQ interrupts, an exception is taken only 588 * if it is higher priority than the current execution priority 589 * (which depends on state like BASEPRI, FAULTMASK and the 590 * currently active exception). 591 */ 592 if (interrupt_request & CPU_INTERRUPT_HARD 593 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 594 cs->exception_index = EXCP_IRQ; 595 cc->do_interrupt(cs); 596 ret = true; 597 } 598 return ret; 599 } 600 #endif 601 602 void arm_cpu_update_virq(ARMCPU *cpu) 603 { 604 /* 605 * Update the interrupt level for VIRQ, which is the logical OR of 606 * the HCR_EL2.VI bit and the input line level from the GIC. 607 */ 608 CPUARMState *env = &cpu->env; 609 CPUState *cs = CPU(cpu); 610 611 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 612 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 613 614 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 615 if (new_state) { 616 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 617 } else { 618 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 619 } 620 } 621 } 622 623 void arm_cpu_update_vfiq(ARMCPU *cpu) 624 { 625 /* 626 * Update the interrupt level for VFIQ, which is the logical OR of 627 * the HCR_EL2.VF bit and the input line level from the GIC. 628 */ 629 CPUARMState *env = &cpu->env; 630 CPUState *cs = CPU(cpu); 631 632 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 633 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 634 635 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 636 if (new_state) { 637 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 638 } else { 639 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 640 } 641 } 642 } 643 644 #ifndef CONFIG_USER_ONLY 645 static void arm_cpu_set_irq(void *opaque, int irq, int level) 646 { 647 ARMCPU *cpu = opaque; 648 CPUARMState *env = &cpu->env; 649 CPUState *cs = CPU(cpu); 650 static const int mask[] = { 651 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 652 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 653 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 654 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 655 }; 656 657 if (level) { 658 env->irq_line_state |= mask[irq]; 659 } else { 660 env->irq_line_state &= ~mask[irq]; 661 } 662 663 switch (irq) { 664 case ARM_CPU_VIRQ: 665 assert(arm_feature(env, ARM_FEATURE_EL2)); 666 arm_cpu_update_virq(cpu); 667 break; 668 case ARM_CPU_VFIQ: 669 assert(arm_feature(env, ARM_FEATURE_EL2)); 670 arm_cpu_update_vfiq(cpu); 671 break; 672 case ARM_CPU_IRQ: 673 case ARM_CPU_FIQ: 674 if (level) { 675 cpu_interrupt(cs, mask[irq]); 676 } else { 677 cpu_reset_interrupt(cs, mask[irq]); 678 } 679 break; 680 default: 681 g_assert_not_reached(); 682 } 683 } 684 685 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 686 { 687 #ifdef CONFIG_KVM 688 ARMCPU *cpu = opaque; 689 CPUARMState *env = &cpu->env; 690 CPUState *cs = CPU(cpu); 691 uint32_t linestate_bit; 692 int irq_id; 693 694 switch (irq) { 695 case ARM_CPU_IRQ: 696 irq_id = KVM_ARM_IRQ_CPU_IRQ; 697 linestate_bit = CPU_INTERRUPT_HARD; 698 break; 699 case ARM_CPU_FIQ: 700 irq_id = KVM_ARM_IRQ_CPU_FIQ; 701 linestate_bit = CPU_INTERRUPT_FIQ; 702 break; 703 default: 704 g_assert_not_reached(); 705 } 706 707 if (level) { 708 env->irq_line_state |= linestate_bit; 709 } else { 710 env->irq_line_state &= ~linestate_bit; 711 } 712 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 713 #endif 714 } 715 716 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 717 { 718 ARMCPU *cpu = ARM_CPU(cs); 719 CPUARMState *env = &cpu->env; 720 721 cpu_synchronize_state(cs); 722 return arm_cpu_data_is_big_endian(env); 723 } 724 725 #endif 726 727 static inline void set_feature(CPUARMState *env, int feature) 728 { 729 env->features |= 1ULL << feature; 730 } 731 732 static inline void unset_feature(CPUARMState *env, int feature) 733 { 734 env->features &= ~(1ULL << feature); 735 } 736 737 static int 738 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 739 { 740 return print_insn_arm(pc | 1, info); 741 } 742 743 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 744 { 745 ARMCPU *ac = ARM_CPU(cpu); 746 CPUARMState *env = &ac->env; 747 bool sctlr_b; 748 749 if (is_a64(env)) { 750 /* We might not be compiled with the A64 disassembler 751 * because it needs a C++ compiler. Leave print_insn 752 * unset in this case to use the caller default behaviour. 753 */ 754 #if defined(CONFIG_ARM_A64_DIS) 755 info->print_insn = print_insn_arm_a64; 756 #endif 757 info->cap_arch = CS_ARCH_ARM64; 758 info->cap_insn_unit = 4; 759 info->cap_insn_split = 4; 760 } else { 761 int cap_mode; 762 if (env->thumb) { 763 info->print_insn = print_insn_thumb1; 764 info->cap_insn_unit = 2; 765 info->cap_insn_split = 4; 766 cap_mode = CS_MODE_THUMB; 767 } else { 768 info->print_insn = print_insn_arm; 769 info->cap_insn_unit = 4; 770 info->cap_insn_split = 4; 771 cap_mode = CS_MODE_ARM; 772 } 773 if (arm_feature(env, ARM_FEATURE_V8)) { 774 cap_mode |= CS_MODE_V8; 775 } 776 if (arm_feature(env, ARM_FEATURE_M)) { 777 cap_mode |= CS_MODE_MCLASS; 778 } 779 info->cap_arch = CS_ARCH_ARM; 780 info->cap_mode = cap_mode; 781 } 782 783 sctlr_b = arm_sctlr_b(env); 784 if (bswap_code(sctlr_b)) { 785 #ifdef TARGET_WORDS_BIGENDIAN 786 info->endian = BFD_ENDIAN_LITTLE; 787 #else 788 info->endian = BFD_ENDIAN_BIG; 789 #endif 790 } 791 info->flags &= ~INSN_ARM_BE32; 792 #ifndef CONFIG_USER_ONLY 793 if (sctlr_b) { 794 info->flags |= INSN_ARM_BE32; 795 } 796 #endif 797 } 798 799 #ifdef TARGET_AARCH64 800 801 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 802 { 803 ARMCPU *cpu = ARM_CPU(cs); 804 CPUARMState *env = &cpu->env; 805 uint32_t psr = pstate_read(env); 806 int i; 807 int el = arm_current_el(env); 808 const char *ns_status; 809 810 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 811 for (i = 0; i < 32; i++) { 812 if (i == 31) { 813 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 814 } else { 815 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 816 (i + 2) % 3 ? " " : "\n"); 817 } 818 } 819 820 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 821 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 822 } else { 823 ns_status = ""; 824 } 825 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 826 psr, 827 psr & PSTATE_N ? 'N' : '-', 828 psr & PSTATE_Z ? 'Z' : '-', 829 psr & PSTATE_C ? 'C' : '-', 830 psr & PSTATE_V ? 'V' : '-', 831 ns_status, 832 el, 833 psr & PSTATE_SP ? 'h' : 't'); 834 835 if (cpu_isar_feature(aa64_bti, cpu)) { 836 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 837 } 838 if (!(flags & CPU_DUMP_FPU)) { 839 qemu_fprintf(f, "\n"); 840 return; 841 } 842 if (fp_exception_el(env, el) != 0) { 843 qemu_fprintf(f, " FPU disabled\n"); 844 return; 845 } 846 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 847 vfp_get_fpcr(env), vfp_get_fpsr(env)); 848 849 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { 850 int j, zcr_len = sve_zcr_len_for_el(env, el); 851 852 for (i = 0; i <= FFR_PRED_NUM; i++) { 853 bool eol; 854 if (i == FFR_PRED_NUM) { 855 qemu_fprintf(f, "FFR="); 856 /* It's last, so end the line. */ 857 eol = true; 858 } else { 859 qemu_fprintf(f, "P%02d=", i); 860 switch (zcr_len) { 861 case 0: 862 eol = i % 8 == 7; 863 break; 864 case 1: 865 eol = i % 6 == 5; 866 break; 867 case 2: 868 case 3: 869 eol = i % 3 == 2; 870 break; 871 default: 872 /* More than one quadword per predicate. */ 873 eol = true; 874 break; 875 } 876 } 877 for (j = zcr_len / 4; j >= 0; j--) { 878 int digits; 879 if (j * 4 + 4 <= zcr_len + 1) { 880 digits = 16; 881 } else { 882 digits = (zcr_len % 4 + 1) * 4; 883 } 884 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 885 env->vfp.pregs[i].p[j], 886 j ? ":" : eol ? "\n" : " "); 887 } 888 } 889 890 for (i = 0; i < 32; i++) { 891 if (zcr_len == 0) { 892 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 893 i, env->vfp.zregs[i].d[1], 894 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 895 } else if (zcr_len == 1) { 896 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 897 ":%016" PRIx64 ":%016" PRIx64 "\n", 898 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 899 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 900 } else { 901 for (j = zcr_len; j >= 0; j--) { 902 bool odd = (zcr_len - j) % 2 != 0; 903 if (j == zcr_len) { 904 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 905 } else if (!odd) { 906 if (j > 0) { 907 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 908 } else { 909 qemu_fprintf(f, " [%x]=", j); 910 } 911 } 912 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 913 env->vfp.zregs[i].d[j * 2 + 1], 914 env->vfp.zregs[i].d[j * 2], 915 odd || j == 0 ? "\n" : ":"); 916 } 917 } 918 } 919 } else { 920 for (i = 0; i < 32; i++) { 921 uint64_t *q = aa64_vfp_qreg(env, i); 922 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 923 i, q[1], q[0], (i & 1 ? "\n" : " ")); 924 } 925 } 926 } 927 928 #else 929 930 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 931 { 932 g_assert_not_reached(); 933 } 934 935 #endif 936 937 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 938 { 939 ARMCPU *cpu = ARM_CPU(cs); 940 CPUARMState *env = &cpu->env; 941 int i; 942 943 if (is_a64(env)) { 944 aarch64_cpu_dump_state(cs, f, flags); 945 return; 946 } 947 948 for (i = 0; i < 16; i++) { 949 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 950 if ((i % 4) == 3) { 951 qemu_fprintf(f, "\n"); 952 } else { 953 qemu_fprintf(f, " "); 954 } 955 } 956 957 if (arm_feature(env, ARM_FEATURE_M)) { 958 uint32_t xpsr = xpsr_read(env); 959 const char *mode; 960 const char *ns_status = ""; 961 962 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 963 ns_status = env->v7m.secure ? "S " : "NS "; 964 } 965 966 if (xpsr & XPSR_EXCP) { 967 mode = "handler"; 968 } else { 969 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 970 mode = "unpriv-thread"; 971 } else { 972 mode = "priv-thread"; 973 } 974 } 975 976 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 977 xpsr, 978 xpsr & XPSR_N ? 'N' : '-', 979 xpsr & XPSR_Z ? 'Z' : '-', 980 xpsr & XPSR_C ? 'C' : '-', 981 xpsr & XPSR_V ? 'V' : '-', 982 xpsr & XPSR_T ? 'T' : 'A', 983 ns_status, 984 mode); 985 } else { 986 uint32_t psr = cpsr_read(env); 987 const char *ns_status = ""; 988 989 if (arm_feature(env, ARM_FEATURE_EL3) && 990 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 991 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 992 } 993 994 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 995 psr, 996 psr & CPSR_N ? 'N' : '-', 997 psr & CPSR_Z ? 'Z' : '-', 998 psr & CPSR_C ? 'C' : '-', 999 psr & CPSR_V ? 'V' : '-', 1000 psr & CPSR_T ? 'T' : 'A', 1001 ns_status, 1002 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1003 } 1004 1005 if (flags & CPU_DUMP_FPU) { 1006 int numvfpregs = 0; 1007 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1008 numvfpregs = 32; 1009 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1010 numvfpregs = 16; 1011 } 1012 for (i = 0; i < numvfpregs; i++) { 1013 uint64_t v = *aa32_vfp_dreg(env, i); 1014 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1015 i * 2, (uint32_t)v, 1016 i * 2 + 1, (uint32_t)(v >> 32), 1017 i, v); 1018 } 1019 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1020 } 1021 } 1022 1023 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 1024 { 1025 uint32_t Aff1 = idx / clustersz; 1026 uint32_t Aff0 = idx % clustersz; 1027 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1028 } 1029 1030 static void cpreg_hashtable_data_destroy(gpointer data) 1031 { 1032 /* 1033 * Destroy function for cpu->cp_regs hashtable data entries. 1034 * We must free the name string because it was g_strdup()ed in 1035 * add_cpreg_to_hashtable(). It's OK to cast away the 'const' 1036 * from r->name because we know we definitely allocated it. 1037 */ 1038 ARMCPRegInfo *r = data; 1039 1040 g_free((void *)r->name); 1041 g_free(r); 1042 } 1043 1044 static void arm_cpu_initfn(Object *obj) 1045 { 1046 ARMCPU *cpu = ARM_CPU(obj); 1047 1048 cpu_set_cpustate_pointers(cpu); 1049 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 1050 g_free, cpreg_hashtable_data_destroy); 1051 1052 QLIST_INIT(&cpu->pre_el_change_hooks); 1053 QLIST_INIT(&cpu->el_change_hooks); 1054 1055 #ifndef CONFIG_USER_ONLY 1056 /* Our inbound IRQ and FIQ lines */ 1057 if (kvm_enabled()) { 1058 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1059 * the same interface as non-KVM CPUs. 1060 */ 1061 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1062 } else { 1063 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1064 } 1065 1066 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1067 ARRAY_SIZE(cpu->gt_timer_outputs)); 1068 1069 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1070 "gicv3-maintenance-interrupt", 1); 1071 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1072 "pmu-interrupt", 1); 1073 #endif 1074 1075 /* DTB consumers generally don't in fact care what the 'compatible' 1076 * string is, so always provide some string and trust that a hypothetical 1077 * picky DTB consumer will also provide a helpful error message. 1078 */ 1079 cpu->dtb_compatible = "qemu,unknown"; 1080 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 1081 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1082 1083 if (tcg_enabled()) { 1084 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 1085 } 1086 } 1087 1088 static Property arm_cpu_gt_cntfrq_property = 1089 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1090 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1091 1092 static Property arm_cpu_reset_cbar_property = 1093 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1094 1095 static Property arm_cpu_reset_hivecs_property = 1096 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1097 1098 static Property arm_cpu_rvbar_property = 1099 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 1100 1101 #ifndef CONFIG_USER_ONLY 1102 static Property arm_cpu_has_el2_property = 1103 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1104 1105 static Property arm_cpu_has_el3_property = 1106 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1107 #endif 1108 1109 static Property arm_cpu_cfgend_property = 1110 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1111 1112 static Property arm_cpu_has_vfp_property = 1113 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1114 1115 static Property arm_cpu_has_neon_property = 1116 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1117 1118 static Property arm_cpu_has_dsp_property = 1119 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1120 1121 static Property arm_cpu_has_mpu_property = 1122 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1123 1124 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1125 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1126 * the right value for that particular CPU type, and we don't want 1127 * to override that with an incorrect constant value. 1128 */ 1129 static Property arm_cpu_pmsav7_dregion_property = 1130 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1131 pmsav7_dregion, 1132 qdev_prop_uint32, uint32_t); 1133 1134 static bool arm_get_pmu(Object *obj, Error **errp) 1135 { 1136 ARMCPU *cpu = ARM_CPU(obj); 1137 1138 return cpu->has_pmu; 1139 } 1140 1141 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1142 { 1143 ARMCPU *cpu = ARM_CPU(obj); 1144 1145 if (value) { 1146 if (kvm_enabled() && !kvm_arm_pmu_supported(CPU(cpu))) { 1147 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1148 return; 1149 } 1150 set_feature(&cpu->env, ARM_FEATURE_PMU); 1151 } else { 1152 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1153 } 1154 cpu->has_pmu = value; 1155 } 1156 1157 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1158 { 1159 /* 1160 * The exact approach to calculating guest ticks is: 1161 * 1162 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1163 * NANOSECONDS_PER_SECOND); 1164 * 1165 * We don't do that. Rather we intentionally use integer division 1166 * truncation below and in the caller for the conversion of host monotonic 1167 * time to guest ticks to provide the exact inverse for the semantics of 1168 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1169 * it loses precision when representing frequencies where 1170 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1171 * provide an exact inverse leads to scheduling timers with negative 1172 * periods, which in turn leads to sticky behaviour in the guest. 1173 * 1174 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1175 * cannot become zero. 1176 */ 1177 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1178 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1179 } 1180 1181 void arm_cpu_post_init(Object *obj) 1182 { 1183 ARMCPU *cpu = ARM_CPU(obj); 1184 1185 /* M profile implies PMSA. We have to do this here rather than 1186 * in realize with the other feature-implication checks because 1187 * we look at the PMSA bit to see if we should add some properties. 1188 */ 1189 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1190 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1191 } 1192 1193 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1194 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1195 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1196 } 1197 1198 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1199 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1200 } 1201 1202 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1203 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property); 1204 } 1205 1206 #ifndef CONFIG_USER_ONLY 1207 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1208 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1209 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1210 */ 1211 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1212 1213 object_property_add_link(obj, "secure-memory", 1214 TYPE_MEMORY_REGION, 1215 (Object **)&cpu->secure_memory, 1216 qdev_prop_allow_set_link_before_realize, 1217 OBJ_PROP_LINK_STRONG, 1218 &error_abort); 1219 } 1220 1221 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1222 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1223 } 1224 #endif 1225 1226 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1227 cpu->has_pmu = true; 1228 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu, 1229 &error_abort); 1230 } 1231 1232 /* 1233 * Allow user to turn off VFP and Neon support, but only for TCG -- 1234 * KVM does not currently allow us to lie to the guest about its 1235 * ID/feature registers, so the guest always sees what the host has. 1236 */ 1237 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 1238 ? cpu_isar_feature(aa64_fp_simd, cpu) 1239 : cpu_isar_feature(aa32_vfp, cpu)) { 1240 cpu->has_vfp = true; 1241 if (!kvm_enabled()) { 1242 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1243 } 1244 } 1245 1246 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1247 cpu->has_neon = true; 1248 if (!kvm_enabled()) { 1249 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1250 } 1251 } 1252 1253 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1254 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1255 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1256 } 1257 1258 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1259 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1260 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1261 qdev_property_add_static(DEVICE(obj), 1262 &arm_cpu_pmsav7_dregion_property); 1263 } 1264 } 1265 1266 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1267 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1268 qdev_prop_allow_set_link_before_realize, 1269 OBJ_PROP_LINK_STRONG, 1270 &error_abort); 1271 /* 1272 * M profile: initial value of the Secure VTOR. We can't just use 1273 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1274 * the property to be set after realize. 1275 */ 1276 object_property_add_uint32_ptr(obj, "init-svtor", 1277 &cpu->init_svtor, 1278 OBJ_PROP_FLAG_READWRITE, &error_abort); 1279 } 1280 1281 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1282 1283 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1284 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1285 } 1286 } 1287 1288 static void arm_cpu_finalizefn(Object *obj) 1289 { 1290 ARMCPU *cpu = ARM_CPU(obj); 1291 ARMELChangeHook *hook, *next; 1292 1293 g_hash_table_destroy(cpu->cp_regs); 1294 1295 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1296 QLIST_REMOVE(hook, node); 1297 g_free(hook); 1298 } 1299 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1300 QLIST_REMOVE(hook, node); 1301 g_free(hook); 1302 } 1303 #ifndef CONFIG_USER_ONLY 1304 if (cpu->pmu_timer) { 1305 timer_del(cpu->pmu_timer); 1306 timer_deinit(cpu->pmu_timer); 1307 timer_free(cpu->pmu_timer); 1308 } 1309 #endif 1310 } 1311 1312 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1313 { 1314 Error *local_err = NULL; 1315 1316 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1317 arm_cpu_sve_finalize(cpu, &local_err); 1318 if (local_err != NULL) { 1319 error_propagate(errp, local_err); 1320 return; 1321 } 1322 } 1323 } 1324 1325 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1326 { 1327 CPUState *cs = CPU(dev); 1328 ARMCPU *cpu = ARM_CPU(dev); 1329 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1330 CPUARMState *env = &cpu->env; 1331 int pagebits; 1332 Error *local_err = NULL; 1333 bool no_aa32 = false; 1334 1335 /* If we needed to query the host kernel for the CPU features 1336 * then it's possible that might have failed in the initfn, but 1337 * this is the first point where we can report it. 1338 */ 1339 if (cpu->host_cpu_probe_failed) { 1340 if (!kvm_enabled()) { 1341 error_setg(errp, "The 'host' CPU type can only be used with KVM"); 1342 } else { 1343 error_setg(errp, "Failed to retrieve host CPU features"); 1344 } 1345 return; 1346 } 1347 1348 #ifndef CONFIG_USER_ONLY 1349 /* The NVIC and M-profile CPU are two halves of a single piece of 1350 * hardware; trying to use one without the other is a command line 1351 * error and will result in segfaults if not caught here. 1352 */ 1353 if (arm_feature(env, ARM_FEATURE_M)) { 1354 if (!env->nvic) { 1355 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1356 return; 1357 } 1358 } else { 1359 if (env->nvic) { 1360 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1361 return; 1362 } 1363 } 1364 1365 { 1366 uint64_t scale; 1367 1368 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1369 if (!cpu->gt_cntfrq_hz) { 1370 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1371 cpu->gt_cntfrq_hz); 1372 return; 1373 } 1374 scale = gt_cntfrq_period_ns(cpu); 1375 } else { 1376 scale = GTIMER_SCALE; 1377 } 1378 1379 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1380 arm_gt_ptimer_cb, cpu); 1381 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1382 arm_gt_vtimer_cb, cpu); 1383 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1384 arm_gt_htimer_cb, cpu); 1385 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1386 arm_gt_stimer_cb, cpu); 1387 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1388 arm_gt_hvtimer_cb, cpu); 1389 } 1390 #endif 1391 1392 cpu_exec_realizefn(cs, &local_err); 1393 if (local_err != NULL) { 1394 error_propagate(errp, local_err); 1395 return; 1396 } 1397 1398 arm_cpu_finalize_features(cpu, &local_err); 1399 if (local_err != NULL) { 1400 error_propagate(errp, local_err); 1401 return; 1402 } 1403 1404 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1405 cpu->has_vfp != cpu->has_neon) { 1406 /* 1407 * This is an architectural requirement for AArch64; AArch32 is 1408 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1409 */ 1410 error_setg(errp, 1411 "AArch64 CPUs must have both VFP and Neon or neither"); 1412 return; 1413 } 1414 1415 if (!cpu->has_vfp) { 1416 uint64_t t; 1417 uint32_t u; 1418 1419 t = cpu->isar.id_aa64isar1; 1420 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1421 cpu->isar.id_aa64isar1 = t; 1422 1423 t = cpu->isar.id_aa64pfr0; 1424 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1425 cpu->isar.id_aa64pfr0 = t; 1426 1427 u = cpu->isar.id_isar6; 1428 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1429 cpu->isar.id_isar6 = u; 1430 1431 u = cpu->isar.mvfr0; 1432 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1433 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1434 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1435 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1436 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1437 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1438 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1439 cpu->isar.mvfr0 = u; 1440 1441 u = cpu->isar.mvfr1; 1442 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1443 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1444 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1445 cpu->isar.mvfr1 = u; 1446 1447 u = cpu->isar.mvfr2; 1448 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1449 cpu->isar.mvfr2 = u; 1450 } 1451 1452 if (!cpu->has_neon) { 1453 uint64_t t; 1454 uint32_t u; 1455 1456 unset_feature(env, ARM_FEATURE_NEON); 1457 1458 t = cpu->isar.id_aa64isar0; 1459 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1460 cpu->isar.id_aa64isar0 = t; 1461 1462 t = cpu->isar.id_aa64isar1; 1463 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1464 cpu->isar.id_aa64isar1 = t; 1465 1466 t = cpu->isar.id_aa64pfr0; 1467 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1468 cpu->isar.id_aa64pfr0 = t; 1469 1470 u = cpu->isar.id_isar5; 1471 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1472 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1473 cpu->isar.id_isar5 = u; 1474 1475 u = cpu->isar.id_isar6; 1476 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1477 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1478 cpu->isar.id_isar6 = u; 1479 1480 u = cpu->isar.mvfr1; 1481 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1482 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1483 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1484 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1485 cpu->isar.mvfr1 = u; 1486 1487 u = cpu->isar.mvfr2; 1488 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1489 cpu->isar.mvfr2 = u; 1490 } 1491 1492 if (!cpu->has_neon && !cpu->has_vfp) { 1493 uint64_t t; 1494 uint32_t u; 1495 1496 t = cpu->isar.id_aa64isar0; 1497 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1498 cpu->isar.id_aa64isar0 = t; 1499 1500 t = cpu->isar.id_aa64isar1; 1501 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1502 cpu->isar.id_aa64isar1 = t; 1503 1504 u = cpu->isar.mvfr0; 1505 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1506 cpu->isar.mvfr0 = u; 1507 1508 /* Despite the name, this field covers both VFP and Neon */ 1509 u = cpu->isar.mvfr1; 1510 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1511 cpu->isar.mvfr1 = u; 1512 } 1513 1514 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1515 uint32_t u; 1516 1517 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1518 1519 u = cpu->isar.id_isar1; 1520 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1521 cpu->isar.id_isar1 = u; 1522 1523 u = cpu->isar.id_isar2; 1524 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1525 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1526 cpu->isar.id_isar2 = u; 1527 1528 u = cpu->isar.id_isar3; 1529 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1530 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1531 cpu->isar.id_isar3 = u; 1532 } 1533 1534 /* Some features automatically imply others: */ 1535 if (arm_feature(env, ARM_FEATURE_V8)) { 1536 if (arm_feature(env, ARM_FEATURE_M)) { 1537 set_feature(env, ARM_FEATURE_V7); 1538 } else { 1539 set_feature(env, ARM_FEATURE_V7VE); 1540 } 1541 } 1542 1543 /* 1544 * There exist AArch64 cpus without AArch32 support. When KVM 1545 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1546 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1547 * As a general principle, we also do not make ID register 1548 * consistency checks anywhere unless using TCG, because only 1549 * for TCG would a consistency-check failure be a QEMU bug. 1550 */ 1551 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1552 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1553 } 1554 1555 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1556 /* v7 Virtualization Extensions. In real hardware this implies 1557 * EL2 and also the presence of the Security Extensions. 1558 * For QEMU, for backwards-compatibility we implement some 1559 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1560 * include the various other features that V7VE implies. 1561 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1562 * Security Extensions is ARM_FEATURE_EL3. 1563 */ 1564 assert(!tcg_enabled() || no_aa32 || 1565 cpu_isar_feature(aa32_arm_div, cpu)); 1566 set_feature(env, ARM_FEATURE_LPAE); 1567 set_feature(env, ARM_FEATURE_V7); 1568 } 1569 if (arm_feature(env, ARM_FEATURE_V7)) { 1570 set_feature(env, ARM_FEATURE_VAPA); 1571 set_feature(env, ARM_FEATURE_THUMB2); 1572 set_feature(env, ARM_FEATURE_MPIDR); 1573 if (!arm_feature(env, ARM_FEATURE_M)) { 1574 set_feature(env, ARM_FEATURE_V6K); 1575 } else { 1576 set_feature(env, ARM_FEATURE_V6); 1577 } 1578 1579 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1580 * non-EL3 configs. This is needed by some legacy boards. 1581 */ 1582 set_feature(env, ARM_FEATURE_VBAR); 1583 } 1584 if (arm_feature(env, ARM_FEATURE_V6K)) { 1585 set_feature(env, ARM_FEATURE_V6); 1586 set_feature(env, ARM_FEATURE_MVFR); 1587 } 1588 if (arm_feature(env, ARM_FEATURE_V6)) { 1589 set_feature(env, ARM_FEATURE_V5); 1590 if (!arm_feature(env, ARM_FEATURE_M)) { 1591 assert(!tcg_enabled() || no_aa32 || 1592 cpu_isar_feature(aa32_jazelle, cpu)); 1593 set_feature(env, ARM_FEATURE_AUXCR); 1594 } 1595 } 1596 if (arm_feature(env, ARM_FEATURE_V5)) { 1597 set_feature(env, ARM_FEATURE_V4T); 1598 } 1599 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1600 set_feature(env, ARM_FEATURE_V7MP); 1601 set_feature(env, ARM_FEATURE_PXN); 1602 } 1603 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1604 set_feature(env, ARM_FEATURE_CBAR); 1605 } 1606 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1607 !arm_feature(env, ARM_FEATURE_M)) { 1608 set_feature(env, ARM_FEATURE_THUMB_DSP); 1609 } 1610 1611 /* 1612 * We rely on no XScale CPU having VFP so we can use the same bits in the 1613 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1614 */ 1615 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1616 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1617 !arm_feature(env, ARM_FEATURE_XSCALE)); 1618 1619 if (arm_feature(env, ARM_FEATURE_V7) && 1620 !arm_feature(env, ARM_FEATURE_M) && 1621 !arm_feature(env, ARM_FEATURE_PMSA)) { 1622 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1623 * can use 4K pages. 1624 */ 1625 pagebits = 12; 1626 } else { 1627 /* For CPUs which might have tiny 1K pages, or which have an 1628 * MPU and might have small region sizes, stick with 1K pages. 1629 */ 1630 pagebits = 10; 1631 } 1632 if (!set_preferred_target_page_bits(pagebits)) { 1633 /* This can only ever happen for hotplugging a CPU, or if 1634 * the board code incorrectly creates a CPU which it has 1635 * promised via minimum_page_size that it will not. 1636 */ 1637 error_setg(errp, "This CPU requires a smaller page size than the " 1638 "system is using"); 1639 return; 1640 } 1641 1642 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1643 * We don't support setting cluster ID ([16..23]) (known as Aff2 1644 * in later ARM ARM versions), or any of the higher affinity level fields, 1645 * so these bits always RAZ. 1646 */ 1647 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1648 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1649 ARM_DEFAULT_CPUS_PER_CLUSTER); 1650 } 1651 1652 if (cpu->reset_hivecs) { 1653 cpu->reset_sctlr |= (1 << 13); 1654 } 1655 1656 if (cpu->cfgend) { 1657 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1658 cpu->reset_sctlr |= SCTLR_EE; 1659 } else { 1660 cpu->reset_sctlr |= SCTLR_B; 1661 } 1662 } 1663 1664 if (!cpu->has_el3) { 1665 /* If the has_el3 CPU property is disabled then we need to disable the 1666 * feature. 1667 */ 1668 unset_feature(env, ARM_FEATURE_EL3); 1669 1670 /* Disable the security extension feature bits in the processor feature 1671 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 1672 */ 1673 cpu->id_pfr1 &= ~0xf0; 1674 cpu->isar.id_aa64pfr0 &= ~0xf000; 1675 } 1676 1677 if (!cpu->has_el2) { 1678 unset_feature(env, ARM_FEATURE_EL2); 1679 } 1680 1681 if (!cpu->has_pmu) { 1682 unset_feature(env, ARM_FEATURE_PMU); 1683 } 1684 if (arm_feature(env, ARM_FEATURE_PMU)) { 1685 pmu_init(cpu); 1686 1687 if (!kvm_enabled()) { 1688 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1689 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1690 } 1691 1692 #ifndef CONFIG_USER_ONLY 1693 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1694 cpu); 1695 #endif 1696 } else { 1697 cpu->isar.id_aa64dfr0 = 1698 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 1699 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 1700 cpu->pmceid0 = 0; 1701 cpu->pmceid1 = 0; 1702 } 1703 1704 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1705 /* Disable the hypervisor feature bits in the processor feature 1706 * registers if we don't have EL2. These are id_pfr1[15:12] and 1707 * id_aa64pfr0_el1[11:8]. 1708 */ 1709 cpu->isar.id_aa64pfr0 &= ~0xf00; 1710 cpu->id_pfr1 &= ~0xf000; 1711 } 1712 1713 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1714 * to false or by setting pmsav7-dregion to 0. 1715 */ 1716 if (!cpu->has_mpu) { 1717 cpu->pmsav7_dregion = 0; 1718 } 1719 if (cpu->pmsav7_dregion == 0) { 1720 cpu->has_mpu = false; 1721 } 1722 1723 if (arm_feature(env, ARM_FEATURE_PMSA) && 1724 arm_feature(env, ARM_FEATURE_V7)) { 1725 uint32_t nr = cpu->pmsav7_dregion; 1726 1727 if (nr > 0xff) { 1728 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1729 return; 1730 } 1731 1732 if (nr) { 1733 if (arm_feature(env, ARM_FEATURE_V8)) { 1734 /* PMSAv8 */ 1735 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1736 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1737 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1738 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1739 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1740 } 1741 } else { 1742 env->pmsav7.drbar = g_new0(uint32_t, nr); 1743 env->pmsav7.drsr = g_new0(uint32_t, nr); 1744 env->pmsav7.dracr = g_new0(uint32_t, nr); 1745 } 1746 } 1747 } 1748 1749 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1750 uint32_t nr = cpu->sau_sregion; 1751 1752 if (nr > 0xff) { 1753 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1754 return; 1755 } 1756 1757 if (nr) { 1758 env->sau.rbar = g_new0(uint32_t, nr); 1759 env->sau.rlar = g_new0(uint32_t, nr); 1760 } 1761 } 1762 1763 if (arm_feature(env, ARM_FEATURE_EL3)) { 1764 set_feature(env, ARM_FEATURE_VBAR); 1765 } 1766 1767 register_cp_regs_for_features(cpu); 1768 arm_cpu_register_gdb_regs_for_features(cpu); 1769 1770 init_cpreg_list(cpu); 1771 1772 #ifndef CONFIG_USER_ONLY 1773 MachineState *ms = MACHINE(qdev_get_machine()); 1774 unsigned int smp_cpus = ms->smp.cpus; 1775 1776 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1777 cs->num_ases = 2; 1778 1779 if (!cpu->secure_memory) { 1780 cpu->secure_memory = cs->memory; 1781 } 1782 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1783 cpu->secure_memory); 1784 } else { 1785 cs->num_ases = 1; 1786 } 1787 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1788 1789 /* No core_count specified, default to smp_cpus. */ 1790 if (cpu->core_count == -1) { 1791 cpu->core_count = smp_cpus; 1792 } 1793 #endif 1794 1795 qemu_init_vcpu(cs); 1796 cpu_reset(cs); 1797 1798 acc->parent_realize(dev, errp); 1799 } 1800 1801 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1802 { 1803 ObjectClass *oc; 1804 char *typename; 1805 char **cpuname; 1806 const char *cpunamestr; 1807 1808 cpuname = g_strsplit(cpu_model, ",", 1); 1809 cpunamestr = cpuname[0]; 1810 #ifdef CONFIG_USER_ONLY 1811 /* For backwards compatibility usermode emulation allows "-cpu any", 1812 * which has the same semantics as "-cpu max". 1813 */ 1814 if (!strcmp(cpunamestr, "any")) { 1815 cpunamestr = "max"; 1816 } 1817 #endif 1818 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 1819 oc = object_class_by_name(typename); 1820 g_strfreev(cpuname); 1821 g_free(typename); 1822 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 1823 object_class_is_abstract(oc)) { 1824 return NULL; 1825 } 1826 return oc; 1827 } 1828 1829 /* CPU models. These are not needed for the AArch64 linux-user build. */ 1830 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1831 1832 static void arm926_initfn(Object *obj) 1833 { 1834 ARMCPU *cpu = ARM_CPU(obj); 1835 1836 cpu->dtb_compatible = "arm,arm926"; 1837 set_feature(&cpu->env, ARM_FEATURE_V5); 1838 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1839 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1840 cpu->midr = 0x41069265; 1841 cpu->reset_fpsid = 0x41011090; 1842 cpu->ctr = 0x1dd20d2; 1843 cpu->reset_sctlr = 0x00090078; 1844 1845 /* 1846 * ARMv5 does not have the ID_ISAR registers, but we can still 1847 * set the field to indicate Jazelle support within QEMU. 1848 */ 1849 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 1850 /* 1851 * Similarly, we need to set MVFR0 fields to enable vfp and short vector 1852 * support even though ARMv5 doesn't have this register. 1853 */ 1854 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 1855 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); 1856 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); 1857 } 1858 1859 static void arm946_initfn(Object *obj) 1860 { 1861 ARMCPU *cpu = ARM_CPU(obj); 1862 1863 cpu->dtb_compatible = "arm,arm946"; 1864 set_feature(&cpu->env, ARM_FEATURE_V5); 1865 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1866 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1867 cpu->midr = 0x41059461; 1868 cpu->ctr = 0x0f004006; 1869 cpu->reset_sctlr = 0x00000078; 1870 } 1871 1872 static void arm1026_initfn(Object *obj) 1873 { 1874 ARMCPU *cpu = ARM_CPU(obj); 1875 1876 cpu->dtb_compatible = "arm,arm1026"; 1877 set_feature(&cpu->env, ARM_FEATURE_V5); 1878 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 1879 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1880 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1881 cpu->midr = 0x4106a262; 1882 cpu->reset_fpsid = 0x410110a0; 1883 cpu->ctr = 0x1dd20d2; 1884 cpu->reset_sctlr = 0x00090078; 1885 cpu->reset_auxcr = 1; 1886 1887 /* 1888 * ARMv5 does not have the ID_ISAR registers, but we can still 1889 * set the field to indicate Jazelle support within QEMU. 1890 */ 1891 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 1892 /* 1893 * Similarly, we need to set MVFR0 fields to enable vfp and short vector 1894 * support even though ARMv5 doesn't have this register. 1895 */ 1896 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 1897 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); 1898 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); 1899 1900 { 1901 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 1902 ARMCPRegInfo ifar = { 1903 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 1904 .access = PL1_RW, 1905 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 1906 .resetvalue = 0 1907 }; 1908 define_one_arm_cp_reg(cpu, &ifar); 1909 } 1910 } 1911 1912 static void arm1136_r2_initfn(Object *obj) 1913 { 1914 ARMCPU *cpu = ARM_CPU(obj); 1915 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 1916 * older core than plain "arm1136". In particular this does not 1917 * have the v6K features. 1918 * These ID register values are correct for 1136 but may be wrong 1919 * for 1136_r2 (in particular r0p2 does not actually implement most 1920 * of the ID registers). 1921 */ 1922 1923 cpu->dtb_compatible = "arm,arm1136"; 1924 set_feature(&cpu->env, ARM_FEATURE_V6); 1925 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1926 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1927 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1928 cpu->midr = 0x4107b362; 1929 cpu->reset_fpsid = 0x410120b4; 1930 cpu->isar.mvfr0 = 0x11111111; 1931 cpu->isar.mvfr1 = 0x00000000; 1932 cpu->ctr = 0x1dd20d2; 1933 cpu->reset_sctlr = 0x00050078; 1934 cpu->id_pfr0 = 0x111; 1935 cpu->id_pfr1 = 0x1; 1936 cpu->isar.id_dfr0 = 0x2; 1937 cpu->id_afr0 = 0x3; 1938 cpu->isar.id_mmfr0 = 0x01130003; 1939 cpu->isar.id_mmfr1 = 0x10030302; 1940 cpu->isar.id_mmfr2 = 0x01222110; 1941 cpu->isar.id_isar0 = 0x00140011; 1942 cpu->isar.id_isar1 = 0x12002111; 1943 cpu->isar.id_isar2 = 0x11231111; 1944 cpu->isar.id_isar3 = 0x01102131; 1945 cpu->isar.id_isar4 = 0x141; 1946 cpu->reset_auxcr = 7; 1947 } 1948 1949 static void arm1136_initfn(Object *obj) 1950 { 1951 ARMCPU *cpu = ARM_CPU(obj); 1952 1953 cpu->dtb_compatible = "arm,arm1136"; 1954 set_feature(&cpu->env, ARM_FEATURE_V6K); 1955 set_feature(&cpu->env, ARM_FEATURE_V6); 1956 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1957 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1958 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1959 cpu->midr = 0x4117b363; 1960 cpu->reset_fpsid = 0x410120b4; 1961 cpu->isar.mvfr0 = 0x11111111; 1962 cpu->isar.mvfr1 = 0x00000000; 1963 cpu->ctr = 0x1dd20d2; 1964 cpu->reset_sctlr = 0x00050078; 1965 cpu->id_pfr0 = 0x111; 1966 cpu->id_pfr1 = 0x1; 1967 cpu->isar.id_dfr0 = 0x2; 1968 cpu->id_afr0 = 0x3; 1969 cpu->isar.id_mmfr0 = 0x01130003; 1970 cpu->isar.id_mmfr1 = 0x10030302; 1971 cpu->isar.id_mmfr2 = 0x01222110; 1972 cpu->isar.id_isar0 = 0x00140011; 1973 cpu->isar.id_isar1 = 0x12002111; 1974 cpu->isar.id_isar2 = 0x11231111; 1975 cpu->isar.id_isar3 = 0x01102131; 1976 cpu->isar.id_isar4 = 0x141; 1977 cpu->reset_auxcr = 7; 1978 } 1979 1980 static void arm1176_initfn(Object *obj) 1981 { 1982 ARMCPU *cpu = ARM_CPU(obj); 1983 1984 cpu->dtb_compatible = "arm,arm1176"; 1985 set_feature(&cpu->env, ARM_FEATURE_V6K); 1986 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1987 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1988 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1989 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1990 set_feature(&cpu->env, ARM_FEATURE_EL3); 1991 cpu->midr = 0x410fb767; 1992 cpu->reset_fpsid = 0x410120b5; 1993 cpu->isar.mvfr0 = 0x11111111; 1994 cpu->isar.mvfr1 = 0x00000000; 1995 cpu->ctr = 0x1dd20d2; 1996 cpu->reset_sctlr = 0x00050078; 1997 cpu->id_pfr0 = 0x111; 1998 cpu->id_pfr1 = 0x11; 1999 cpu->isar.id_dfr0 = 0x33; 2000 cpu->id_afr0 = 0; 2001 cpu->isar.id_mmfr0 = 0x01130003; 2002 cpu->isar.id_mmfr1 = 0x10030302; 2003 cpu->isar.id_mmfr2 = 0x01222100; 2004 cpu->isar.id_isar0 = 0x0140011; 2005 cpu->isar.id_isar1 = 0x12002111; 2006 cpu->isar.id_isar2 = 0x11231121; 2007 cpu->isar.id_isar3 = 0x01102131; 2008 cpu->isar.id_isar4 = 0x01141; 2009 cpu->reset_auxcr = 7; 2010 } 2011 2012 static void arm11mpcore_initfn(Object *obj) 2013 { 2014 ARMCPU *cpu = ARM_CPU(obj); 2015 2016 cpu->dtb_compatible = "arm,arm11mpcore"; 2017 set_feature(&cpu->env, ARM_FEATURE_V6K); 2018 set_feature(&cpu->env, ARM_FEATURE_VAPA); 2019 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 2020 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2021 cpu->midr = 0x410fb022; 2022 cpu->reset_fpsid = 0x410120b4; 2023 cpu->isar.mvfr0 = 0x11111111; 2024 cpu->isar.mvfr1 = 0x00000000; 2025 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 2026 cpu->id_pfr0 = 0x111; 2027 cpu->id_pfr1 = 0x1; 2028 cpu->isar.id_dfr0 = 0; 2029 cpu->id_afr0 = 0x2; 2030 cpu->isar.id_mmfr0 = 0x01100103; 2031 cpu->isar.id_mmfr1 = 0x10020302; 2032 cpu->isar.id_mmfr2 = 0x01222000; 2033 cpu->isar.id_isar0 = 0x00100011; 2034 cpu->isar.id_isar1 = 0x12002111; 2035 cpu->isar.id_isar2 = 0x11221011; 2036 cpu->isar.id_isar3 = 0x01102131; 2037 cpu->isar.id_isar4 = 0x141; 2038 cpu->reset_auxcr = 1; 2039 } 2040 2041 static void cortex_m0_initfn(Object *obj) 2042 { 2043 ARMCPU *cpu = ARM_CPU(obj); 2044 set_feature(&cpu->env, ARM_FEATURE_V6); 2045 set_feature(&cpu->env, ARM_FEATURE_M); 2046 2047 cpu->midr = 0x410cc200; 2048 } 2049 2050 static void cortex_m3_initfn(Object *obj) 2051 { 2052 ARMCPU *cpu = ARM_CPU(obj); 2053 set_feature(&cpu->env, ARM_FEATURE_V7); 2054 set_feature(&cpu->env, ARM_FEATURE_M); 2055 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 2056 cpu->midr = 0x410fc231; 2057 cpu->pmsav7_dregion = 8; 2058 cpu->id_pfr0 = 0x00000030; 2059 cpu->id_pfr1 = 0x00000200; 2060 cpu->isar.id_dfr0 = 0x00100000; 2061 cpu->id_afr0 = 0x00000000; 2062 cpu->isar.id_mmfr0 = 0x00000030; 2063 cpu->isar.id_mmfr1 = 0x00000000; 2064 cpu->isar.id_mmfr2 = 0x00000000; 2065 cpu->isar.id_mmfr3 = 0x00000000; 2066 cpu->isar.id_isar0 = 0x01141110; 2067 cpu->isar.id_isar1 = 0x02111000; 2068 cpu->isar.id_isar2 = 0x21112231; 2069 cpu->isar.id_isar3 = 0x01111110; 2070 cpu->isar.id_isar4 = 0x01310102; 2071 cpu->isar.id_isar5 = 0x00000000; 2072 cpu->isar.id_isar6 = 0x00000000; 2073 } 2074 2075 static void cortex_m4_initfn(Object *obj) 2076 { 2077 ARMCPU *cpu = ARM_CPU(obj); 2078 2079 set_feature(&cpu->env, ARM_FEATURE_V7); 2080 set_feature(&cpu->env, ARM_FEATURE_M); 2081 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 2082 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 2083 cpu->midr = 0x410fc240; /* r0p0 */ 2084 cpu->pmsav7_dregion = 8; 2085 cpu->isar.mvfr0 = 0x10110021; 2086 cpu->isar.mvfr1 = 0x11000011; 2087 cpu->isar.mvfr2 = 0x00000000; 2088 cpu->id_pfr0 = 0x00000030; 2089 cpu->id_pfr1 = 0x00000200; 2090 cpu->isar.id_dfr0 = 0x00100000; 2091 cpu->id_afr0 = 0x00000000; 2092 cpu->isar.id_mmfr0 = 0x00000030; 2093 cpu->isar.id_mmfr1 = 0x00000000; 2094 cpu->isar.id_mmfr2 = 0x00000000; 2095 cpu->isar.id_mmfr3 = 0x00000000; 2096 cpu->isar.id_isar0 = 0x01141110; 2097 cpu->isar.id_isar1 = 0x02111000; 2098 cpu->isar.id_isar2 = 0x21112231; 2099 cpu->isar.id_isar3 = 0x01111110; 2100 cpu->isar.id_isar4 = 0x01310102; 2101 cpu->isar.id_isar5 = 0x00000000; 2102 cpu->isar.id_isar6 = 0x00000000; 2103 } 2104 2105 static void cortex_m7_initfn(Object *obj) 2106 { 2107 ARMCPU *cpu = ARM_CPU(obj); 2108 2109 set_feature(&cpu->env, ARM_FEATURE_V7); 2110 set_feature(&cpu->env, ARM_FEATURE_M); 2111 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 2112 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 2113 cpu->midr = 0x411fc272; /* r1p2 */ 2114 cpu->pmsav7_dregion = 8; 2115 cpu->isar.mvfr0 = 0x10110221; 2116 cpu->isar.mvfr1 = 0x12000011; 2117 cpu->isar.mvfr2 = 0x00000040; 2118 cpu->id_pfr0 = 0x00000030; 2119 cpu->id_pfr1 = 0x00000200; 2120 cpu->isar.id_dfr0 = 0x00100000; 2121 cpu->id_afr0 = 0x00000000; 2122 cpu->isar.id_mmfr0 = 0x00100030; 2123 cpu->isar.id_mmfr1 = 0x00000000; 2124 cpu->isar.id_mmfr2 = 0x01000000; 2125 cpu->isar.id_mmfr3 = 0x00000000; 2126 cpu->isar.id_isar0 = 0x01101110; 2127 cpu->isar.id_isar1 = 0x02112000; 2128 cpu->isar.id_isar2 = 0x20232231; 2129 cpu->isar.id_isar3 = 0x01111131; 2130 cpu->isar.id_isar4 = 0x01310132; 2131 cpu->isar.id_isar5 = 0x00000000; 2132 cpu->isar.id_isar6 = 0x00000000; 2133 } 2134 2135 static void cortex_m33_initfn(Object *obj) 2136 { 2137 ARMCPU *cpu = ARM_CPU(obj); 2138 2139 set_feature(&cpu->env, ARM_FEATURE_V8); 2140 set_feature(&cpu->env, ARM_FEATURE_M); 2141 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 2142 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); 2143 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 2144 cpu->midr = 0x410fd213; /* r0p3 */ 2145 cpu->pmsav7_dregion = 16; 2146 cpu->sau_sregion = 8; 2147 cpu->isar.mvfr0 = 0x10110021; 2148 cpu->isar.mvfr1 = 0x11000011; 2149 cpu->isar.mvfr2 = 0x00000040; 2150 cpu->id_pfr0 = 0x00000030; 2151 cpu->id_pfr1 = 0x00000210; 2152 cpu->isar.id_dfr0 = 0x00200000; 2153 cpu->id_afr0 = 0x00000000; 2154 cpu->isar.id_mmfr0 = 0x00101F40; 2155 cpu->isar.id_mmfr1 = 0x00000000; 2156 cpu->isar.id_mmfr2 = 0x01000000; 2157 cpu->isar.id_mmfr3 = 0x00000000; 2158 cpu->isar.id_isar0 = 0x01101110; 2159 cpu->isar.id_isar1 = 0x02212000; 2160 cpu->isar.id_isar2 = 0x20232232; 2161 cpu->isar.id_isar3 = 0x01111131; 2162 cpu->isar.id_isar4 = 0x01310132; 2163 cpu->isar.id_isar5 = 0x00000000; 2164 cpu->isar.id_isar6 = 0x00000000; 2165 cpu->clidr = 0x00000000; 2166 cpu->ctr = 0x8000c000; 2167 } 2168 2169 static void arm_v7m_class_init(ObjectClass *oc, void *data) 2170 { 2171 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2172 CPUClass *cc = CPU_CLASS(oc); 2173 2174 acc->info = data; 2175 #ifndef CONFIG_USER_ONLY 2176 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 2177 #endif 2178 2179 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 2180 } 2181 2182 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 2183 /* Dummy the TCM region regs for the moment */ 2184 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 2185 .access = PL1_RW, .type = ARM_CP_CONST }, 2186 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 2187 .access = PL1_RW, .type = ARM_CP_CONST }, 2188 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 2189 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 2190 REGINFO_SENTINEL 2191 }; 2192 2193 static void cortex_r5_initfn(Object *obj) 2194 { 2195 ARMCPU *cpu = ARM_CPU(obj); 2196 2197 set_feature(&cpu->env, ARM_FEATURE_V7); 2198 set_feature(&cpu->env, ARM_FEATURE_V7MP); 2199 set_feature(&cpu->env, ARM_FEATURE_PMSA); 2200 set_feature(&cpu->env, ARM_FEATURE_PMU); 2201 cpu->midr = 0x411fc153; /* r1p3 */ 2202 cpu->id_pfr0 = 0x0131; 2203 cpu->id_pfr1 = 0x001; 2204 cpu->isar.id_dfr0 = 0x010400; 2205 cpu->id_afr0 = 0x0; 2206 cpu->isar.id_mmfr0 = 0x0210030; 2207 cpu->isar.id_mmfr1 = 0x00000000; 2208 cpu->isar.id_mmfr2 = 0x01200000; 2209 cpu->isar.id_mmfr3 = 0x0211; 2210 cpu->isar.id_isar0 = 0x02101111; 2211 cpu->isar.id_isar1 = 0x13112111; 2212 cpu->isar.id_isar2 = 0x21232141; 2213 cpu->isar.id_isar3 = 0x01112131; 2214 cpu->isar.id_isar4 = 0x0010142; 2215 cpu->isar.id_isar5 = 0x0; 2216 cpu->isar.id_isar6 = 0x0; 2217 cpu->mp_is_up = true; 2218 cpu->pmsav7_dregion = 16; 2219 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 2220 } 2221 2222 static void cortex_r5f_initfn(Object *obj) 2223 { 2224 ARMCPU *cpu = ARM_CPU(obj); 2225 2226 cortex_r5_initfn(obj); 2227 cpu->isar.mvfr0 = 0x10110221; 2228 cpu->isar.mvfr1 = 0x00000011; 2229 } 2230 2231 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 2232 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 2233 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 2234 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 2235 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 2236 REGINFO_SENTINEL 2237 }; 2238 2239 static void cortex_a8_initfn(Object *obj) 2240 { 2241 ARMCPU *cpu = ARM_CPU(obj); 2242 2243 cpu->dtb_compatible = "arm,cortex-a8"; 2244 set_feature(&cpu->env, ARM_FEATURE_V7); 2245 set_feature(&cpu->env, ARM_FEATURE_NEON); 2246 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2247 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2248 set_feature(&cpu->env, ARM_FEATURE_EL3); 2249 cpu->midr = 0x410fc080; 2250 cpu->reset_fpsid = 0x410330c0; 2251 cpu->isar.mvfr0 = 0x11110222; 2252 cpu->isar.mvfr1 = 0x00011111; 2253 cpu->ctr = 0x82048004; 2254 cpu->reset_sctlr = 0x00c50078; 2255 cpu->id_pfr0 = 0x1031; 2256 cpu->id_pfr1 = 0x11; 2257 cpu->isar.id_dfr0 = 0x400; 2258 cpu->id_afr0 = 0; 2259 cpu->isar.id_mmfr0 = 0x31100003; 2260 cpu->isar.id_mmfr1 = 0x20000000; 2261 cpu->isar.id_mmfr2 = 0x01202000; 2262 cpu->isar.id_mmfr3 = 0x11; 2263 cpu->isar.id_isar0 = 0x00101111; 2264 cpu->isar.id_isar1 = 0x12112111; 2265 cpu->isar.id_isar2 = 0x21232031; 2266 cpu->isar.id_isar3 = 0x11112131; 2267 cpu->isar.id_isar4 = 0x00111142; 2268 cpu->isar.dbgdidr = 0x15141000; 2269 cpu->clidr = (1 << 27) | (2 << 24) | 3; 2270 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 2271 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 2272 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 2273 cpu->reset_auxcr = 2; 2274 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 2275 } 2276 2277 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 2278 /* power_control should be set to maximum latency. Again, 2279 * default to 0 and set by private hook 2280 */ 2281 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 2282 .access = PL1_RW, .resetvalue = 0, 2283 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 2284 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 2285 .access = PL1_RW, .resetvalue = 0, 2286 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 2287 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 2288 .access = PL1_RW, .resetvalue = 0, 2289 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 2290 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 2291 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 2292 /* TLB lockdown control */ 2293 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 2294 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 2295 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 2296 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 2297 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 2298 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 2299 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 2300 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 2301 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 2302 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 2303 REGINFO_SENTINEL 2304 }; 2305 2306 static void cortex_a9_initfn(Object *obj) 2307 { 2308 ARMCPU *cpu = ARM_CPU(obj); 2309 2310 cpu->dtb_compatible = "arm,cortex-a9"; 2311 set_feature(&cpu->env, ARM_FEATURE_V7); 2312 set_feature(&cpu->env, ARM_FEATURE_NEON); 2313 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2314 set_feature(&cpu->env, ARM_FEATURE_EL3); 2315 /* Note that A9 supports the MP extensions even for 2316 * A9UP and single-core A9MP (which are both different 2317 * and valid configurations; we don't model A9UP). 2318 */ 2319 set_feature(&cpu->env, ARM_FEATURE_V7MP); 2320 set_feature(&cpu->env, ARM_FEATURE_CBAR); 2321 cpu->midr = 0x410fc090; 2322 cpu->reset_fpsid = 0x41033090; 2323 cpu->isar.mvfr0 = 0x11110222; 2324 cpu->isar.mvfr1 = 0x01111111; 2325 cpu->ctr = 0x80038003; 2326 cpu->reset_sctlr = 0x00c50078; 2327 cpu->id_pfr0 = 0x1031; 2328 cpu->id_pfr1 = 0x11; 2329 cpu->isar.id_dfr0 = 0x000; 2330 cpu->id_afr0 = 0; 2331 cpu->isar.id_mmfr0 = 0x00100103; 2332 cpu->isar.id_mmfr1 = 0x20000000; 2333 cpu->isar.id_mmfr2 = 0x01230000; 2334 cpu->isar.id_mmfr3 = 0x00002111; 2335 cpu->isar.id_isar0 = 0x00101111; 2336 cpu->isar.id_isar1 = 0x13112111; 2337 cpu->isar.id_isar2 = 0x21232041; 2338 cpu->isar.id_isar3 = 0x11112131; 2339 cpu->isar.id_isar4 = 0x00111142; 2340 cpu->isar.dbgdidr = 0x35141000; 2341 cpu->clidr = (1 << 27) | (1 << 24) | 3; 2342 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 2343 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 2344 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 2345 } 2346 2347 #ifndef CONFIG_USER_ONLY 2348 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 2349 { 2350 MachineState *ms = MACHINE(qdev_get_machine()); 2351 2352 /* Linux wants the number of processors from here. 2353 * Might as well set the interrupt-controller bit too. 2354 */ 2355 return ((ms->smp.cpus - 1) << 24) | (1 << 23); 2356 } 2357 #endif 2358 2359 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 2360 #ifndef CONFIG_USER_ONLY 2361 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 2362 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 2363 .writefn = arm_cp_write_ignore, }, 2364 #endif 2365 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 2366 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 2367 REGINFO_SENTINEL 2368 }; 2369 2370 static void cortex_a7_initfn(Object *obj) 2371 { 2372 ARMCPU *cpu = ARM_CPU(obj); 2373 2374 cpu->dtb_compatible = "arm,cortex-a7"; 2375 set_feature(&cpu->env, ARM_FEATURE_V7VE); 2376 set_feature(&cpu->env, ARM_FEATURE_NEON); 2377 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2378 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 2379 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2380 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 2381 set_feature(&cpu->env, ARM_FEATURE_EL2); 2382 set_feature(&cpu->env, ARM_FEATURE_EL3); 2383 set_feature(&cpu->env, ARM_FEATURE_PMU); 2384 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 2385 cpu->midr = 0x410fc075; 2386 cpu->reset_fpsid = 0x41023075; 2387 cpu->isar.mvfr0 = 0x10110222; 2388 cpu->isar.mvfr1 = 0x11111111; 2389 cpu->ctr = 0x84448003; 2390 cpu->reset_sctlr = 0x00c50078; 2391 cpu->id_pfr0 = 0x00001131; 2392 cpu->id_pfr1 = 0x00011011; 2393 cpu->isar.id_dfr0 = 0x02010555; 2394 cpu->id_afr0 = 0x00000000; 2395 cpu->isar.id_mmfr0 = 0x10101105; 2396 cpu->isar.id_mmfr1 = 0x40000000; 2397 cpu->isar.id_mmfr2 = 0x01240000; 2398 cpu->isar.id_mmfr3 = 0x02102211; 2399 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but 2400 * table 4-41 gives 0x02101110, which includes the arm div insns. 2401 */ 2402 cpu->isar.id_isar0 = 0x02101110; 2403 cpu->isar.id_isar1 = 0x13112111; 2404 cpu->isar.id_isar2 = 0x21232041; 2405 cpu->isar.id_isar3 = 0x11112131; 2406 cpu->isar.id_isar4 = 0x10011142; 2407 cpu->isar.dbgdidr = 0x3515f005; 2408 cpu->clidr = 0x0a200023; 2409 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 2410 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 2411 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 2412 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 2413 } 2414 2415 static void cortex_a15_initfn(Object *obj) 2416 { 2417 ARMCPU *cpu = ARM_CPU(obj); 2418 2419 cpu->dtb_compatible = "arm,cortex-a15"; 2420 set_feature(&cpu->env, ARM_FEATURE_V7VE); 2421 set_feature(&cpu->env, ARM_FEATURE_NEON); 2422 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 2423 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 2424 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2425 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 2426 set_feature(&cpu->env, ARM_FEATURE_EL2); 2427 set_feature(&cpu->env, ARM_FEATURE_EL3); 2428 set_feature(&cpu->env, ARM_FEATURE_PMU); 2429 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 2430 cpu->midr = 0x412fc0f1; 2431 cpu->reset_fpsid = 0x410430f0; 2432 cpu->isar.mvfr0 = 0x10110222; 2433 cpu->isar.mvfr1 = 0x11111111; 2434 cpu->ctr = 0x8444c004; 2435 cpu->reset_sctlr = 0x00c50078; 2436 cpu->id_pfr0 = 0x00001131; 2437 cpu->id_pfr1 = 0x00011011; 2438 cpu->isar.id_dfr0 = 0x02010555; 2439 cpu->id_afr0 = 0x00000000; 2440 cpu->isar.id_mmfr0 = 0x10201105; 2441 cpu->isar.id_mmfr1 = 0x20000000; 2442 cpu->isar.id_mmfr2 = 0x01240000; 2443 cpu->isar.id_mmfr3 = 0x02102211; 2444 cpu->isar.id_isar0 = 0x02101110; 2445 cpu->isar.id_isar1 = 0x13112111; 2446 cpu->isar.id_isar2 = 0x21232041; 2447 cpu->isar.id_isar3 = 0x11112131; 2448 cpu->isar.id_isar4 = 0x10011142; 2449 cpu->isar.dbgdidr = 0x3515f021; 2450 cpu->clidr = 0x0a200023; 2451 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 2452 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 2453 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 2454 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 2455 } 2456 2457 static void ti925t_initfn(Object *obj) 2458 { 2459 ARMCPU *cpu = ARM_CPU(obj); 2460 set_feature(&cpu->env, ARM_FEATURE_V4T); 2461 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 2462 cpu->midr = ARM_CPUID_TI925T; 2463 cpu->ctr = 0x5109149; 2464 cpu->reset_sctlr = 0x00000070; 2465 } 2466 2467 static void sa1100_initfn(Object *obj) 2468 { 2469 ARMCPU *cpu = ARM_CPU(obj); 2470 2471 cpu->dtb_compatible = "intel,sa1100"; 2472 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 2473 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2474 cpu->midr = 0x4401A11B; 2475 cpu->reset_sctlr = 0x00000070; 2476 } 2477 2478 static void sa1110_initfn(Object *obj) 2479 { 2480 ARMCPU *cpu = ARM_CPU(obj); 2481 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 2482 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 2483 cpu->midr = 0x6901B119; 2484 cpu->reset_sctlr = 0x00000070; 2485 } 2486 2487 static void pxa250_initfn(Object *obj) 2488 { 2489 ARMCPU *cpu = ARM_CPU(obj); 2490 2491 cpu->dtb_compatible = "marvell,xscale"; 2492 set_feature(&cpu->env, ARM_FEATURE_V5); 2493 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2494 cpu->midr = 0x69052100; 2495 cpu->ctr = 0xd172172; 2496 cpu->reset_sctlr = 0x00000078; 2497 } 2498 2499 static void pxa255_initfn(Object *obj) 2500 { 2501 ARMCPU *cpu = ARM_CPU(obj); 2502 2503 cpu->dtb_compatible = "marvell,xscale"; 2504 set_feature(&cpu->env, ARM_FEATURE_V5); 2505 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2506 cpu->midr = 0x69052d00; 2507 cpu->ctr = 0xd172172; 2508 cpu->reset_sctlr = 0x00000078; 2509 } 2510 2511 static void pxa260_initfn(Object *obj) 2512 { 2513 ARMCPU *cpu = ARM_CPU(obj); 2514 2515 cpu->dtb_compatible = "marvell,xscale"; 2516 set_feature(&cpu->env, ARM_FEATURE_V5); 2517 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2518 cpu->midr = 0x69052903; 2519 cpu->ctr = 0xd172172; 2520 cpu->reset_sctlr = 0x00000078; 2521 } 2522 2523 static void pxa261_initfn(Object *obj) 2524 { 2525 ARMCPU *cpu = ARM_CPU(obj); 2526 2527 cpu->dtb_compatible = "marvell,xscale"; 2528 set_feature(&cpu->env, ARM_FEATURE_V5); 2529 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2530 cpu->midr = 0x69052d05; 2531 cpu->ctr = 0xd172172; 2532 cpu->reset_sctlr = 0x00000078; 2533 } 2534 2535 static void pxa262_initfn(Object *obj) 2536 { 2537 ARMCPU *cpu = ARM_CPU(obj); 2538 2539 cpu->dtb_compatible = "marvell,xscale"; 2540 set_feature(&cpu->env, ARM_FEATURE_V5); 2541 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2542 cpu->midr = 0x69052d06; 2543 cpu->ctr = 0xd172172; 2544 cpu->reset_sctlr = 0x00000078; 2545 } 2546 2547 static void pxa270a0_initfn(Object *obj) 2548 { 2549 ARMCPU *cpu = ARM_CPU(obj); 2550 2551 cpu->dtb_compatible = "marvell,xscale"; 2552 set_feature(&cpu->env, ARM_FEATURE_V5); 2553 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2554 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2555 cpu->midr = 0x69054110; 2556 cpu->ctr = 0xd172172; 2557 cpu->reset_sctlr = 0x00000078; 2558 } 2559 2560 static void pxa270a1_initfn(Object *obj) 2561 { 2562 ARMCPU *cpu = ARM_CPU(obj); 2563 2564 cpu->dtb_compatible = "marvell,xscale"; 2565 set_feature(&cpu->env, ARM_FEATURE_V5); 2566 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2567 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2568 cpu->midr = 0x69054111; 2569 cpu->ctr = 0xd172172; 2570 cpu->reset_sctlr = 0x00000078; 2571 } 2572 2573 static void pxa270b0_initfn(Object *obj) 2574 { 2575 ARMCPU *cpu = ARM_CPU(obj); 2576 2577 cpu->dtb_compatible = "marvell,xscale"; 2578 set_feature(&cpu->env, ARM_FEATURE_V5); 2579 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2580 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2581 cpu->midr = 0x69054112; 2582 cpu->ctr = 0xd172172; 2583 cpu->reset_sctlr = 0x00000078; 2584 } 2585 2586 static void pxa270b1_initfn(Object *obj) 2587 { 2588 ARMCPU *cpu = ARM_CPU(obj); 2589 2590 cpu->dtb_compatible = "marvell,xscale"; 2591 set_feature(&cpu->env, ARM_FEATURE_V5); 2592 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2593 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2594 cpu->midr = 0x69054113; 2595 cpu->ctr = 0xd172172; 2596 cpu->reset_sctlr = 0x00000078; 2597 } 2598 2599 static void pxa270c0_initfn(Object *obj) 2600 { 2601 ARMCPU *cpu = ARM_CPU(obj); 2602 2603 cpu->dtb_compatible = "marvell,xscale"; 2604 set_feature(&cpu->env, ARM_FEATURE_V5); 2605 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2606 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2607 cpu->midr = 0x69054114; 2608 cpu->ctr = 0xd172172; 2609 cpu->reset_sctlr = 0x00000078; 2610 } 2611 2612 static void pxa270c5_initfn(Object *obj) 2613 { 2614 ARMCPU *cpu = ARM_CPU(obj); 2615 2616 cpu->dtb_compatible = "marvell,xscale"; 2617 set_feature(&cpu->env, ARM_FEATURE_V5); 2618 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2619 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2620 cpu->midr = 0x69054117; 2621 cpu->ctr = 0xd172172; 2622 cpu->reset_sctlr = 0x00000078; 2623 } 2624 2625 #ifndef TARGET_AARCH64 2626 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 2627 * otherwise, a CPU with as many features enabled as our emulation supports. 2628 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; 2629 * this only needs to handle 32 bits. 2630 */ 2631 static void arm_max_initfn(Object *obj) 2632 { 2633 ARMCPU *cpu = ARM_CPU(obj); 2634 2635 if (kvm_enabled()) { 2636 kvm_arm_set_cpu_features_from_host(cpu); 2637 kvm_arm_add_vcpu_properties(obj); 2638 } else { 2639 cortex_a15_initfn(obj); 2640 2641 /* old-style VFP short-vector support */ 2642 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 2643 2644 #ifdef CONFIG_USER_ONLY 2645 /* We don't set these in system emulation mode for the moment, 2646 * since we don't correctly set (all of) the ID registers to 2647 * advertise them. 2648 */ 2649 set_feature(&cpu->env, ARM_FEATURE_V8); 2650 { 2651 uint32_t t; 2652 2653 t = cpu->isar.id_isar5; 2654 t = FIELD_DP32(t, ID_ISAR5, AES, 2); 2655 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); 2656 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); 2657 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); 2658 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); 2659 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); 2660 cpu->isar.id_isar5 = t; 2661 2662 t = cpu->isar.id_isar6; 2663 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); 2664 t = FIELD_DP32(t, ID_ISAR6, DP, 1); 2665 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); 2666 t = FIELD_DP32(t, ID_ISAR6, SB, 1); 2667 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); 2668 cpu->isar.id_isar6 = t; 2669 2670 t = cpu->isar.mvfr1; 2671 t = FIELD_DP32(t, MVFR1, FPHP, 2); /* v8.0 FP support */ 2672 cpu->isar.mvfr1 = t; 2673 2674 t = cpu->isar.mvfr2; 2675 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ 2676 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ 2677 cpu->isar.mvfr2 = t; 2678 2679 t = cpu->isar.id_mmfr3; 2680 t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ 2681 cpu->isar.id_mmfr3 = t; 2682 2683 t = cpu->isar.id_mmfr4; 2684 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ 2685 t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ 2686 t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ 2687 cpu->isar.id_mmfr4 = t; 2688 } 2689 #endif 2690 } 2691 } 2692 #endif 2693 2694 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 2695 2696 struct ARMCPUInfo { 2697 const char *name; 2698 void (*initfn)(Object *obj); 2699 void (*class_init)(ObjectClass *oc, void *data); 2700 }; 2701 2702 static const ARMCPUInfo arm_cpus[] = { 2703 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 2704 { .name = "arm926", .initfn = arm926_initfn }, 2705 { .name = "arm946", .initfn = arm946_initfn }, 2706 { .name = "arm1026", .initfn = arm1026_initfn }, 2707 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 2708 * older core than plain "arm1136". In particular this does not 2709 * have the v6K features. 2710 */ 2711 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 2712 { .name = "arm1136", .initfn = arm1136_initfn }, 2713 { .name = "arm1176", .initfn = arm1176_initfn }, 2714 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 2715 { .name = "cortex-m0", .initfn = cortex_m0_initfn, 2716 .class_init = arm_v7m_class_init }, 2717 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 2718 .class_init = arm_v7m_class_init }, 2719 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 2720 .class_init = arm_v7m_class_init }, 2721 { .name = "cortex-m7", .initfn = cortex_m7_initfn, 2722 .class_init = arm_v7m_class_init }, 2723 { .name = "cortex-m33", .initfn = cortex_m33_initfn, 2724 .class_init = arm_v7m_class_init }, 2725 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 2726 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, 2727 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 2728 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 2729 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 2730 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 2731 { .name = "ti925t", .initfn = ti925t_initfn }, 2732 { .name = "sa1100", .initfn = sa1100_initfn }, 2733 { .name = "sa1110", .initfn = sa1110_initfn }, 2734 { .name = "pxa250", .initfn = pxa250_initfn }, 2735 { .name = "pxa255", .initfn = pxa255_initfn }, 2736 { .name = "pxa260", .initfn = pxa260_initfn }, 2737 { .name = "pxa261", .initfn = pxa261_initfn }, 2738 { .name = "pxa262", .initfn = pxa262_initfn }, 2739 /* "pxa270" is an alias for "pxa270-a0" */ 2740 { .name = "pxa270", .initfn = pxa270a0_initfn }, 2741 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 2742 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 2743 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 2744 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 2745 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 2746 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 2747 #ifndef TARGET_AARCH64 2748 { .name = "max", .initfn = arm_max_initfn }, 2749 #endif 2750 #ifdef CONFIG_USER_ONLY 2751 { .name = "any", .initfn = arm_max_initfn }, 2752 #endif 2753 #endif 2754 { .name = NULL } 2755 }; 2756 2757 static Property arm_cpu_properties[] = { 2758 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 2759 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 2760 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 2761 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2762 mp_affinity, ARM64_AFFINITY_INVALID), 2763 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2764 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2765 DEFINE_PROP_END_OF_LIST() 2766 }; 2767 2768 static gchar *arm_gdb_arch_name(CPUState *cs) 2769 { 2770 ARMCPU *cpu = ARM_CPU(cs); 2771 CPUARMState *env = &cpu->env; 2772 2773 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2774 return g_strdup("iwmmxt"); 2775 } 2776 return g_strdup("arm"); 2777 } 2778 2779 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2780 { 2781 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2782 CPUClass *cc = CPU_CLASS(acc); 2783 DeviceClass *dc = DEVICE_CLASS(oc); 2784 2785 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2786 &acc->parent_realize); 2787 2788 device_class_set_props(dc, arm_cpu_properties); 2789 device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); 2790 2791 cc->class_by_name = arm_cpu_class_by_name; 2792 cc->has_work = arm_cpu_has_work; 2793 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 2794 cc->dump_state = arm_cpu_dump_state; 2795 cc->set_pc = arm_cpu_set_pc; 2796 cc->synchronize_from_tb = arm_cpu_synchronize_from_tb; 2797 cc->gdb_read_register = arm_cpu_gdb_read_register; 2798 cc->gdb_write_register = arm_cpu_gdb_write_register; 2799 #ifndef CONFIG_USER_ONLY 2800 cc->do_interrupt = arm_cpu_do_interrupt; 2801 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 2802 cc->asidx_from_attrs = arm_asidx_from_attrs; 2803 cc->vmsd = &vmstate_arm_cpu; 2804 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 2805 cc->write_elf64_note = arm_cpu_write_elf64_note; 2806 cc->write_elf32_note = arm_cpu_write_elf32_note; 2807 #endif 2808 cc->gdb_num_core_regs = 26; 2809 cc->gdb_core_xml_file = "arm-core.xml"; 2810 cc->gdb_arch_name = arm_gdb_arch_name; 2811 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2812 cc->gdb_stop_before_watchpoint = true; 2813 cc->disas_set_info = arm_disas_set_info; 2814 #ifdef CONFIG_TCG 2815 cc->tcg_initialize = arm_translate_init; 2816 cc->tlb_fill = arm_cpu_tlb_fill; 2817 cc->debug_excp_handler = arm_debug_excp_handler; 2818 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 2819 #if !defined(CONFIG_USER_ONLY) 2820 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 2821 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 2822 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 2823 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 2824 #endif 2825 } 2826 2827 #ifdef CONFIG_KVM 2828 static void arm_host_initfn(Object *obj) 2829 { 2830 ARMCPU *cpu = ARM_CPU(obj); 2831 2832 kvm_arm_set_cpu_features_from_host(cpu); 2833 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 2834 aarch64_add_sve_properties(obj); 2835 } 2836 kvm_arm_add_vcpu_properties(obj); 2837 arm_cpu_post_init(obj); 2838 } 2839 2840 static const TypeInfo host_arm_cpu_type_info = { 2841 .name = TYPE_ARM_HOST_CPU, 2842 #ifdef TARGET_AARCH64 2843 .parent = TYPE_AARCH64_CPU, 2844 #else 2845 .parent = TYPE_ARM_CPU, 2846 #endif 2847 .instance_init = arm_host_initfn, 2848 }; 2849 2850 #endif 2851 2852 static void arm_cpu_instance_init(Object *obj) 2853 { 2854 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2855 2856 acc->info->initfn(obj); 2857 arm_cpu_post_init(obj); 2858 } 2859 2860 static void cpu_register_class_init(ObjectClass *oc, void *data) 2861 { 2862 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2863 2864 acc->info = data; 2865 } 2866 2867 static void cpu_register(const ARMCPUInfo *info) 2868 { 2869 TypeInfo type_info = { 2870 .parent = TYPE_ARM_CPU, 2871 .instance_size = sizeof(ARMCPU), 2872 .instance_init = arm_cpu_instance_init, 2873 .class_size = sizeof(ARMCPUClass), 2874 .class_init = info->class_init ?: cpu_register_class_init, 2875 .class_data = (void *)info, 2876 }; 2877 2878 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2879 type_register(&type_info); 2880 g_free((void *)type_info.name); 2881 } 2882 2883 static const TypeInfo arm_cpu_type_info = { 2884 .name = TYPE_ARM_CPU, 2885 .parent = TYPE_CPU, 2886 .instance_size = sizeof(ARMCPU), 2887 .instance_init = arm_cpu_initfn, 2888 .instance_finalize = arm_cpu_finalizefn, 2889 .abstract = true, 2890 .class_size = sizeof(ARMCPUClass), 2891 .class_init = arm_cpu_class_init, 2892 }; 2893 2894 static const TypeInfo idau_interface_type_info = { 2895 .name = TYPE_IDAU_INTERFACE, 2896 .parent = TYPE_INTERFACE, 2897 .class_size = sizeof(IDAUInterfaceClass), 2898 }; 2899 2900 static void arm_cpu_register_types(void) 2901 { 2902 const ARMCPUInfo *info = arm_cpus; 2903 2904 type_register_static(&arm_cpu_type_info); 2905 type_register_static(&idau_interface_type_info); 2906 2907 while (info->name) { 2908 cpu_register(info); 2909 info++; 2910 } 2911 2912 #ifdef CONFIG_KVM 2913 type_register_static(&host_arm_cpu_type_info); 2914 #endif 2915 } 2916 2917 type_init(arm_cpu_register_types) 2918