1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "target/arm/idau.h" 23 #include "qapi/error.h" 24 #include "qapi/visitor.h" 25 #include "cpu.h" 26 #include "internals.h" 27 #include "qemu-common.h" 28 #include "exec/exec-all.h" 29 #include "hw/qdev-properties.h" 30 #if !defined(CONFIG_USER_ONLY) 31 #include "hw/loader.h" 32 #endif 33 #include "sysemu/sysemu.h" 34 #include "sysemu/hw_accel.h" 35 #include "kvm_arm.h" 36 #include "disas/capstone.h" 37 #include "fpu/softfloat.h" 38 39 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 40 { 41 ARMCPU *cpu = ARM_CPU(cs); 42 CPUARMState *env = &cpu->env; 43 44 if (is_a64(env)) { 45 env->pc = value; 46 env->thumb = 0; 47 } else { 48 env->regs[15] = value & ~1; 49 env->thumb = value & 1; 50 } 51 } 52 53 static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 54 { 55 ARMCPU *cpu = ARM_CPU(cs); 56 CPUARMState *env = &cpu->env; 57 58 /* 59 * It's OK to look at env for the current mode here, because it's 60 * never possible for an AArch64 TB to chain to an AArch32 TB. 61 */ 62 if (is_a64(env)) { 63 env->pc = tb->pc; 64 } else { 65 env->regs[15] = tb->pc; 66 } 67 } 68 69 static bool arm_cpu_has_work(CPUState *cs) 70 { 71 ARMCPU *cpu = ARM_CPU(cs); 72 73 return (cpu->power_state != PSCI_OFF) 74 && cs->interrupt_request & 75 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 76 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 77 | CPU_INTERRUPT_EXITTB); 78 } 79 80 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 81 void *opaque) 82 { 83 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 84 85 entry->hook = hook; 86 entry->opaque = opaque; 87 88 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 89 } 90 91 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 92 void *opaque) 93 { 94 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 95 96 entry->hook = hook; 97 entry->opaque = opaque; 98 99 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 100 } 101 102 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 103 { 104 /* Reset a single ARMCPRegInfo register */ 105 ARMCPRegInfo *ri = value; 106 ARMCPU *cpu = opaque; 107 108 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 109 return; 110 } 111 112 if (ri->resetfn) { 113 ri->resetfn(&cpu->env, ri); 114 return; 115 } 116 117 /* A zero offset is never possible as it would be regs[0] 118 * so we use it to indicate that reset is being handled elsewhere. 119 * This is basically only used for fields in non-core coprocessors 120 * (like the pxa2xx ones). 121 */ 122 if (!ri->fieldoffset) { 123 return; 124 } 125 126 if (cpreg_field_is_64bit(ri)) { 127 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 128 } else { 129 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 130 } 131 } 132 133 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 134 { 135 /* Purely an assertion check: we've already done reset once, 136 * so now check that running the reset for the cpreg doesn't 137 * change its value. This traps bugs where two different cpregs 138 * both try to reset the same state field but to different values. 139 */ 140 ARMCPRegInfo *ri = value; 141 ARMCPU *cpu = opaque; 142 uint64_t oldvalue, newvalue; 143 144 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 145 return; 146 } 147 148 oldvalue = read_raw_cp_reg(&cpu->env, ri); 149 cp_reg_reset(key, value, opaque); 150 newvalue = read_raw_cp_reg(&cpu->env, ri); 151 assert(oldvalue == newvalue); 152 } 153 154 /* CPUClass::reset() */ 155 static void arm_cpu_reset(CPUState *s) 156 { 157 ARMCPU *cpu = ARM_CPU(s); 158 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 159 CPUARMState *env = &cpu->env; 160 161 acc->parent_reset(s); 162 163 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 164 165 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 166 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 167 168 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 169 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 170 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 171 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 172 173 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 174 s->halted = cpu->start_powered_off; 175 176 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 177 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 178 } 179 180 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 181 /* 64 bit CPUs always start in 64 bit mode */ 182 env->aarch64 = 1; 183 #if defined(CONFIG_USER_ONLY) 184 env->pstate = PSTATE_MODE_EL0t; 185 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 186 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 187 /* Enable all PAC keys. */ 188 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 189 SCTLR_EnDA | SCTLR_EnDB); 190 /* Enable all PAC instructions */ 191 env->cp15.hcr_el2 |= HCR_API; 192 env->cp15.scr_el3 |= SCR_API; 193 /* and to the FP/Neon instructions */ 194 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 195 /* and to the SVE instructions */ 196 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 197 env->cp15.cptr_el[3] |= CPTR_EZ; 198 /* with maximum vector length */ 199 env->vfp.zcr_el[1] = cpu->sve_max_vq - 1; 200 env->vfp.zcr_el[2] = env->vfp.zcr_el[1]; 201 env->vfp.zcr_el[3] = env->vfp.zcr_el[1]; 202 /* 203 * Enable TBI0 and TBI1. While the real kernel only enables TBI0, 204 * turning on both here will produce smaller code and otherwise 205 * make no difference to the user-level emulation. 206 */ 207 env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); 208 #else 209 /* Reset into the highest available EL */ 210 if (arm_feature(env, ARM_FEATURE_EL3)) { 211 env->pstate = PSTATE_MODE_EL3h; 212 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 213 env->pstate = PSTATE_MODE_EL2h; 214 } else { 215 env->pstate = PSTATE_MODE_EL1h; 216 } 217 env->pc = cpu->rvbar; 218 #endif 219 } else { 220 #if defined(CONFIG_USER_ONLY) 221 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 222 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 223 #endif 224 } 225 226 #if defined(CONFIG_USER_ONLY) 227 env->uncached_cpsr = ARM_CPU_MODE_USR; 228 /* For user mode we must enable access to coprocessors */ 229 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 230 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 231 env->cp15.c15_cpar = 3; 232 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 233 env->cp15.c15_cpar = 1; 234 } 235 #else 236 237 /* 238 * If the highest available EL is EL2, AArch32 will start in Hyp 239 * mode; otherwise it starts in SVC. Note that if we start in 240 * AArch64 then these values in the uncached_cpsr will be ignored. 241 */ 242 if (arm_feature(env, ARM_FEATURE_EL2) && 243 !arm_feature(env, ARM_FEATURE_EL3)) { 244 env->uncached_cpsr = ARM_CPU_MODE_HYP; 245 } else { 246 env->uncached_cpsr = ARM_CPU_MODE_SVC; 247 } 248 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 249 250 if (arm_feature(env, ARM_FEATURE_M)) { 251 uint32_t initial_msp; /* Loaded from 0x0 */ 252 uint32_t initial_pc; /* Loaded from 0x4 */ 253 uint8_t *rom; 254 uint32_t vecbase; 255 256 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 257 env->v7m.secure = true; 258 } else { 259 /* This bit resets to 0 if security is supported, but 1 if 260 * it is not. The bit is not present in v7M, but we set it 261 * here so we can avoid having to make checks on it conditional 262 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 263 */ 264 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 265 } 266 267 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 268 * that it resets to 1, so QEMU always does that rather than making 269 * it dependent on CPU model. In v8M it is RES1. 270 */ 271 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 272 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 273 if (arm_feature(env, ARM_FEATURE_V8)) { 274 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 275 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 276 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 277 } 278 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 279 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 280 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 281 } 282 283 if (arm_feature(env, ARM_FEATURE_VFP)) { 284 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 285 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 286 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 287 } 288 /* Unlike A/R profile, M profile defines the reset LR value */ 289 env->regs[14] = 0xffffffff; 290 291 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 292 293 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 294 vecbase = env->v7m.vecbase[env->v7m.secure]; 295 rom = rom_ptr(vecbase, 8); 296 if (rom) { 297 /* Address zero is covered by ROM which hasn't yet been 298 * copied into physical memory. 299 */ 300 initial_msp = ldl_p(rom); 301 initial_pc = ldl_p(rom + 4); 302 } else { 303 /* Address zero not covered by a ROM blob, or the ROM blob 304 * is in non-modifiable memory and this is a second reset after 305 * it got copied into memory. In the latter case, rom_ptr 306 * will return a NULL pointer and we should use ldl_phys instead. 307 */ 308 initial_msp = ldl_phys(s->as, vecbase); 309 initial_pc = ldl_phys(s->as, vecbase + 4); 310 } 311 312 env->regs[13] = initial_msp & 0xFFFFFFFC; 313 env->regs[15] = initial_pc & ~1; 314 env->thumb = initial_pc & 1; 315 } 316 317 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 318 * executing as AArch32 then check if highvecs are enabled and 319 * adjust the PC accordingly. 320 */ 321 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 322 env->regs[15] = 0xFFFF0000; 323 } 324 325 /* M profile requires that reset clears the exclusive monitor; 326 * A profile does not, but clearing it makes more sense than having it 327 * set with an exclusive access on address zero. 328 */ 329 arm_clear_exclusive(env); 330 331 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 332 #endif 333 334 if (arm_feature(env, ARM_FEATURE_PMSA)) { 335 if (cpu->pmsav7_dregion > 0) { 336 if (arm_feature(env, ARM_FEATURE_V8)) { 337 memset(env->pmsav8.rbar[M_REG_NS], 0, 338 sizeof(*env->pmsav8.rbar[M_REG_NS]) 339 * cpu->pmsav7_dregion); 340 memset(env->pmsav8.rlar[M_REG_NS], 0, 341 sizeof(*env->pmsav8.rlar[M_REG_NS]) 342 * cpu->pmsav7_dregion); 343 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 344 memset(env->pmsav8.rbar[M_REG_S], 0, 345 sizeof(*env->pmsav8.rbar[M_REG_S]) 346 * cpu->pmsav7_dregion); 347 memset(env->pmsav8.rlar[M_REG_S], 0, 348 sizeof(*env->pmsav8.rlar[M_REG_S]) 349 * cpu->pmsav7_dregion); 350 } 351 } else if (arm_feature(env, ARM_FEATURE_V7)) { 352 memset(env->pmsav7.drbar, 0, 353 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 354 memset(env->pmsav7.drsr, 0, 355 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 356 memset(env->pmsav7.dracr, 0, 357 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 358 } 359 } 360 env->pmsav7.rnr[M_REG_NS] = 0; 361 env->pmsav7.rnr[M_REG_S] = 0; 362 env->pmsav8.mair0[M_REG_NS] = 0; 363 env->pmsav8.mair0[M_REG_S] = 0; 364 env->pmsav8.mair1[M_REG_NS] = 0; 365 env->pmsav8.mair1[M_REG_S] = 0; 366 } 367 368 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 369 if (cpu->sau_sregion > 0) { 370 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 371 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 372 } 373 env->sau.rnr = 0; 374 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 375 * the Cortex-M33 does. 376 */ 377 env->sau.ctrl = 0; 378 } 379 380 set_flush_to_zero(1, &env->vfp.standard_fp_status); 381 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 382 set_default_nan_mode(1, &env->vfp.standard_fp_status); 383 set_float_detect_tininess(float_tininess_before_rounding, 384 &env->vfp.fp_status); 385 set_float_detect_tininess(float_tininess_before_rounding, 386 &env->vfp.standard_fp_status); 387 set_float_detect_tininess(float_tininess_before_rounding, 388 &env->vfp.fp_status_f16); 389 #ifndef CONFIG_USER_ONLY 390 if (kvm_enabled()) { 391 kvm_arm_reset_vcpu(cpu); 392 } 393 #endif 394 395 hw_breakpoint_update_all(cpu); 396 hw_watchpoint_update_all(cpu); 397 } 398 399 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 400 { 401 CPUClass *cc = CPU_GET_CLASS(cs); 402 CPUARMState *env = cs->env_ptr; 403 uint32_t cur_el = arm_current_el(env); 404 bool secure = arm_is_secure(env); 405 uint32_t target_el; 406 uint32_t excp_idx; 407 bool ret = false; 408 409 if (interrupt_request & CPU_INTERRUPT_FIQ) { 410 excp_idx = EXCP_FIQ; 411 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 412 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 413 cs->exception_index = excp_idx; 414 env->exception.target_el = target_el; 415 cc->do_interrupt(cs); 416 ret = true; 417 } 418 } 419 if (interrupt_request & CPU_INTERRUPT_HARD) { 420 excp_idx = EXCP_IRQ; 421 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 422 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 423 cs->exception_index = excp_idx; 424 env->exception.target_el = target_el; 425 cc->do_interrupt(cs); 426 ret = true; 427 } 428 } 429 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 430 excp_idx = EXCP_VIRQ; 431 target_el = 1; 432 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 433 cs->exception_index = excp_idx; 434 env->exception.target_el = target_el; 435 cc->do_interrupt(cs); 436 ret = true; 437 } 438 } 439 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 440 excp_idx = EXCP_VFIQ; 441 target_el = 1; 442 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 443 cs->exception_index = excp_idx; 444 env->exception.target_el = target_el; 445 cc->do_interrupt(cs); 446 ret = true; 447 } 448 } 449 450 return ret; 451 } 452 453 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 454 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 455 { 456 CPUClass *cc = CPU_GET_CLASS(cs); 457 ARMCPU *cpu = ARM_CPU(cs); 458 CPUARMState *env = &cpu->env; 459 bool ret = false; 460 461 /* ARMv7-M interrupt masking works differently than -A or -R. 462 * There is no FIQ/IRQ distinction. Instead of I and F bits 463 * masking FIQ and IRQ interrupts, an exception is taken only 464 * if it is higher priority than the current execution priority 465 * (which depends on state like BASEPRI, FAULTMASK and the 466 * currently active exception). 467 */ 468 if (interrupt_request & CPU_INTERRUPT_HARD 469 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 470 cs->exception_index = EXCP_IRQ; 471 cc->do_interrupt(cs); 472 ret = true; 473 } 474 return ret; 475 } 476 #endif 477 478 void arm_cpu_update_virq(ARMCPU *cpu) 479 { 480 /* 481 * Update the interrupt level for VIRQ, which is the logical OR of 482 * the HCR_EL2.VI bit and the input line level from the GIC. 483 */ 484 CPUARMState *env = &cpu->env; 485 CPUState *cs = CPU(cpu); 486 487 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 488 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 489 490 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 491 if (new_state) { 492 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 493 } else { 494 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 495 } 496 } 497 } 498 499 void arm_cpu_update_vfiq(ARMCPU *cpu) 500 { 501 /* 502 * Update the interrupt level for VFIQ, which is the logical OR of 503 * the HCR_EL2.VF bit and the input line level from the GIC. 504 */ 505 CPUARMState *env = &cpu->env; 506 CPUState *cs = CPU(cpu); 507 508 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 509 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 510 511 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 512 if (new_state) { 513 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 514 } else { 515 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 516 } 517 } 518 } 519 520 #ifndef CONFIG_USER_ONLY 521 static void arm_cpu_set_irq(void *opaque, int irq, int level) 522 { 523 ARMCPU *cpu = opaque; 524 CPUARMState *env = &cpu->env; 525 CPUState *cs = CPU(cpu); 526 static const int mask[] = { 527 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 528 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 529 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 530 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 531 }; 532 533 if (level) { 534 env->irq_line_state |= mask[irq]; 535 } else { 536 env->irq_line_state &= ~mask[irq]; 537 } 538 539 switch (irq) { 540 case ARM_CPU_VIRQ: 541 assert(arm_feature(env, ARM_FEATURE_EL2)); 542 arm_cpu_update_virq(cpu); 543 break; 544 case ARM_CPU_VFIQ: 545 assert(arm_feature(env, ARM_FEATURE_EL2)); 546 arm_cpu_update_vfiq(cpu); 547 break; 548 case ARM_CPU_IRQ: 549 case ARM_CPU_FIQ: 550 if (level) { 551 cpu_interrupt(cs, mask[irq]); 552 } else { 553 cpu_reset_interrupt(cs, mask[irq]); 554 } 555 break; 556 default: 557 g_assert_not_reached(); 558 } 559 } 560 561 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 562 { 563 #ifdef CONFIG_KVM 564 ARMCPU *cpu = opaque; 565 CPUARMState *env = &cpu->env; 566 CPUState *cs = CPU(cpu); 567 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 568 uint32_t linestate_bit; 569 570 switch (irq) { 571 case ARM_CPU_IRQ: 572 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 573 linestate_bit = CPU_INTERRUPT_HARD; 574 break; 575 case ARM_CPU_FIQ: 576 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 577 linestate_bit = CPU_INTERRUPT_FIQ; 578 break; 579 default: 580 g_assert_not_reached(); 581 } 582 583 if (level) { 584 env->irq_line_state |= linestate_bit; 585 } else { 586 env->irq_line_state &= ~linestate_bit; 587 } 588 589 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 590 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 591 #endif 592 } 593 594 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 595 { 596 ARMCPU *cpu = ARM_CPU(cs); 597 CPUARMState *env = &cpu->env; 598 599 cpu_synchronize_state(cs); 600 return arm_cpu_data_is_big_endian(env); 601 } 602 603 #endif 604 605 static inline void set_feature(CPUARMState *env, int feature) 606 { 607 env->features |= 1ULL << feature; 608 } 609 610 static inline void unset_feature(CPUARMState *env, int feature) 611 { 612 env->features &= ~(1ULL << feature); 613 } 614 615 static int 616 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 617 { 618 return print_insn_arm(pc | 1, info); 619 } 620 621 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 622 { 623 ARMCPU *ac = ARM_CPU(cpu); 624 CPUARMState *env = &ac->env; 625 bool sctlr_b; 626 627 if (is_a64(env)) { 628 /* We might not be compiled with the A64 disassembler 629 * because it needs a C++ compiler. Leave print_insn 630 * unset in this case to use the caller default behaviour. 631 */ 632 #if defined(CONFIG_ARM_A64_DIS) 633 info->print_insn = print_insn_arm_a64; 634 #endif 635 info->cap_arch = CS_ARCH_ARM64; 636 info->cap_insn_unit = 4; 637 info->cap_insn_split = 4; 638 } else { 639 int cap_mode; 640 if (env->thumb) { 641 info->print_insn = print_insn_thumb1; 642 info->cap_insn_unit = 2; 643 info->cap_insn_split = 4; 644 cap_mode = CS_MODE_THUMB; 645 } else { 646 info->print_insn = print_insn_arm; 647 info->cap_insn_unit = 4; 648 info->cap_insn_split = 4; 649 cap_mode = CS_MODE_ARM; 650 } 651 if (arm_feature(env, ARM_FEATURE_V8)) { 652 cap_mode |= CS_MODE_V8; 653 } 654 if (arm_feature(env, ARM_FEATURE_M)) { 655 cap_mode |= CS_MODE_MCLASS; 656 } 657 info->cap_arch = CS_ARCH_ARM; 658 info->cap_mode = cap_mode; 659 } 660 661 sctlr_b = arm_sctlr_b(env); 662 if (bswap_code(sctlr_b)) { 663 #ifdef TARGET_WORDS_BIGENDIAN 664 info->endian = BFD_ENDIAN_LITTLE; 665 #else 666 info->endian = BFD_ENDIAN_BIG; 667 #endif 668 } 669 info->flags &= ~INSN_ARM_BE32; 670 #ifndef CONFIG_USER_ONLY 671 if (sctlr_b) { 672 info->flags |= INSN_ARM_BE32; 673 } 674 #endif 675 } 676 677 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 678 { 679 uint32_t Aff1 = idx / clustersz; 680 uint32_t Aff0 = idx % clustersz; 681 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 682 } 683 684 static void cpreg_hashtable_data_destroy(gpointer data) 685 { 686 /* 687 * Destroy function for cpu->cp_regs hashtable data entries. 688 * We must free the name string because it was g_strdup()ed in 689 * add_cpreg_to_hashtable(). It's OK to cast away the 'const' 690 * from r->name because we know we definitely allocated it. 691 */ 692 ARMCPRegInfo *r = data; 693 694 g_free((void *)r->name); 695 g_free(r); 696 } 697 698 static void arm_cpu_initfn(Object *obj) 699 { 700 CPUState *cs = CPU(obj); 701 ARMCPU *cpu = ARM_CPU(obj); 702 703 cs->env_ptr = &cpu->env; 704 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 705 g_free, cpreg_hashtable_data_destroy); 706 707 QLIST_INIT(&cpu->pre_el_change_hooks); 708 QLIST_INIT(&cpu->el_change_hooks); 709 710 #ifndef CONFIG_USER_ONLY 711 /* Our inbound IRQ and FIQ lines */ 712 if (kvm_enabled()) { 713 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 714 * the same interface as non-KVM CPUs. 715 */ 716 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 717 } else { 718 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 719 } 720 721 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 722 ARRAY_SIZE(cpu->gt_timer_outputs)); 723 724 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 725 "gicv3-maintenance-interrupt", 1); 726 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 727 "pmu-interrupt", 1); 728 #endif 729 730 /* DTB consumers generally don't in fact care what the 'compatible' 731 * string is, so always provide some string and trust that a hypothetical 732 * picky DTB consumer will also provide a helpful error message. 733 */ 734 cpu->dtb_compatible = "qemu,unknown"; 735 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 736 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 737 738 if (tcg_enabled()) { 739 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 740 } 741 } 742 743 static Property arm_cpu_reset_cbar_property = 744 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 745 746 static Property arm_cpu_reset_hivecs_property = 747 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 748 749 static Property arm_cpu_rvbar_property = 750 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 751 752 static Property arm_cpu_has_el2_property = 753 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 754 755 static Property arm_cpu_has_el3_property = 756 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 757 758 static Property arm_cpu_cfgend_property = 759 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 760 761 /* use property name "pmu" to match other archs and virt tools */ 762 static Property arm_cpu_has_pmu_property = 763 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 764 765 static Property arm_cpu_has_mpu_property = 766 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 767 768 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 769 * because the CPU initfn will have already set cpu->pmsav7_dregion to 770 * the right value for that particular CPU type, and we don't want 771 * to override that with an incorrect constant value. 772 */ 773 static Property arm_cpu_pmsav7_dregion_property = 774 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 775 pmsav7_dregion, 776 qdev_prop_uint32, uint32_t); 777 778 static void arm_get_init_svtor(Object *obj, Visitor *v, const char *name, 779 void *opaque, Error **errp) 780 { 781 ARMCPU *cpu = ARM_CPU(obj); 782 783 visit_type_uint32(v, name, &cpu->init_svtor, errp); 784 } 785 786 static void arm_set_init_svtor(Object *obj, Visitor *v, const char *name, 787 void *opaque, Error **errp) 788 { 789 ARMCPU *cpu = ARM_CPU(obj); 790 791 visit_type_uint32(v, name, &cpu->init_svtor, errp); 792 } 793 794 void arm_cpu_post_init(Object *obj) 795 { 796 ARMCPU *cpu = ARM_CPU(obj); 797 798 /* M profile implies PMSA. We have to do this here rather than 799 * in realize with the other feature-implication checks because 800 * we look at the PMSA bit to see if we should add some properties. 801 */ 802 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 803 set_feature(&cpu->env, ARM_FEATURE_PMSA); 804 } 805 806 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 807 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 808 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 809 &error_abort); 810 } 811 812 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 813 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 814 &error_abort); 815 } 816 817 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 818 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 819 &error_abort); 820 } 821 822 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 823 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 824 * prevent "has_el3" from existing on CPUs which cannot support EL3. 825 */ 826 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 827 &error_abort); 828 829 #ifndef CONFIG_USER_ONLY 830 object_property_add_link(obj, "secure-memory", 831 TYPE_MEMORY_REGION, 832 (Object **)&cpu->secure_memory, 833 qdev_prop_allow_set_link_before_realize, 834 OBJ_PROP_LINK_STRONG, 835 &error_abort); 836 #endif 837 } 838 839 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 840 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 841 &error_abort); 842 } 843 844 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 845 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 846 &error_abort); 847 } 848 849 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 850 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 851 &error_abort); 852 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 853 qdev_property_add_static(DEVICE(obj), 854 &arm_cpu_pmsav7_dregion_property, 855 &error_abort); 856 } 857 } 858 859 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 860 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 861 qdev_prop_allow_set_link_before_realize, 862 OBJ_PROP_LINK_STRONG, 863 &error_abort); 864 /* 865 * M profile: initial value of the Secure VTOR. We can't just use 866 * a simple DEFINE_PROP_UINT32 for this because we want to permit 867 * the property to be set after realize. 868 */ 869 object_property_add(obj, "init-svtor", "uint32", 870 arm_get_init_svtor, arm_set_init_svtor, 871 NULL, NULL, &error_abort); 872 } 873 874 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 875 &error_abort); 876 } 877 878 static void arm_cpu_finalizefn(Object *obj) 879 { 880 ARMCPU *cpu = ARM_CPU(obj); 881 ARMELChangeHook *hook, *next; 882 883 g_hash_table_destroy(cpu->cp_regs); 884 885 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 886 QLIST_REMOVE(hook, node); 887 g_free(hook); 888 } 889 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 890 QLIST_REMOVE(hook, node); 891 g_free(hook); 892 } 893 #ifndef CONFIG_USER_ONLY 894 if (cpu->pmu_timer) { 895 timer_del(cpu->pmu_timer); 896 timer_deinit(cpu->pmu_timer); 897 timer_free(cpu->pmu_timer); 898 } 899 #endif 900 } 901 902 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 903 { 904 CPUState *cs = CPU(dev); 905 ARMCPU *cpu = ARM_CPU(dev); 906 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 907 CPUARMState *env = &cpu->env; 908 int pagebits; 909 Error *local_err = NULL; 910 bool no_aa32 = false; 911 912 /* If we needed to query the host kernel for the CPU features 913 * then it's possible that might have failed in the initfn, but 914 * this is the first point where we can report it. 915 */ 916 if (cpu->host_cpu_probe_failed) { 917 if (!kvm_enabled()) { 918 error_setg(errp, "The 'host' CPU type can only be used with KVM"); 919 } else { 920 error_setg(errp, "Failed to retrieve host CPU features"); 921 } 922 return; 923 } 924 925 #ifndef CONFIG_USER_ONLY 926 /* The NVIC and M-profile CPU are two halves of a single piece of 927 * hardware; trying to use one without the other is a command line 928 * error and will result in segfaults if not caught here. 929 */ 930 if (arm_feature(env, ARM_FEATURE_M)) { 931 if (!env->nvic) { 932 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 933 return; 934 } 935 } else { 936 if (env->nvic) { 937 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 938 return; 939 } 940 } 941 942 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 943 arm_gt_ptimer_cb, cpu); 944 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 945 arm_gt_vtimer_cb, cpu); 946 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 947 arm_gt_htimer_cb, cpu); 948 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 949 arm_gt_stimer_cb, cpu); 950 #endif 951 952 cpu_exec_realizefn(cs, &local_err); 953 if (local_err != NULL) { 954 error_propagate(errp, local_err); 955 return; 956 } 957 958 /* Some features automatically imply others: */ 959 if (arm_feature(env, ARM_FEATURE_V8)) { 960 if (arm_feature(env, ARM_FEATURE_M)) { 961 set_feature(env, ARM_FEATURE_V7); 962 } else { 963 set_feature(env, ARM_FEATURE_V7VE); 964 } 965 } 966 967 /* 968 * There exist AArch64 cpus without AArch32 support. When KVM 969 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 970 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 971 */ 972 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 973 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 974 } 975 976 if (arm_feature(env, ARM_FEATURE_V7VE)) { 977 /* v7 Virtualization Extensions. In real hardware this implies 978 * EL2 and also the presence of the Security Extensions. 979 * For QEMU, for backwards-compatibility we implement some 980 * CPUs or CPU configs which have no actual EL2 or EL3 but do 981 * include the various other features that V7VE implies. 982 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 983 * Security Extensions is ARM_FEATURE_EL3. 984 */ 985 assert(no_aa32 || cpu_isar_feature(arm_div, cpu)); 986 set_feature(env, ARM_FEATURE_LPAE); 987 set_feature(env, ARM_FEATURE_V7); 988 } 989 if (arm_feature(env, ARM_FEATURE_V7)) { 990 set_feature(env, ARM_FEATURE_VAPA); 991 set_feature(env, ARM_FEATURE_THUMB2); 992 set_feature(env, ARM_FEATURE_MPIDR); 993 if (!arm_feature(env, ARM_FEATURE_M)) { 994 set_feature(env, ARM_FEATURE_V6K); 995 } else { 996 set_feature(env, ARM_FEATURE_V6); 997 } 998 999 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1000 * non-EL3 configs. This is needed by some legacy boards. 1001 */ 1002 set_feature(env, ARM_FEATURE_VBAR); 1003 } 1004 if (arm_feature(env, ARM_FEATURE_V6K)) { 1005 set_feature(env, ARM_FEATURE_V6); 1006 set_feature(env, ARM_FEATURE_MVFR); 1007 } 1008 if (arm_feature(env, ARM_FEATURE_V6)) { 1009 set_feature(env, ARM_FEATURE_V5); 1010 if (!arm_feature(env, ARM_FEATURE_M)) { 1011 assert(no_aa32 || cpu_isar_feature(jazelle, cpu)); 1012 set_feature(env, ARM_FEATURE_AUXCR); 1013 } 1014 } 1015 if (arm_feature(env, ARM_FEATURE_V5)) { 1016 set_feature(env, ARM_FEATURE_V4T); 1017 } 1018 if (arm_feature(env, ARM_FEATURE_VFP4)) { 1019 set_feature(env, ARM_FEATURE_VFP3); 1020 } 1021 if (arm_feature(env, ARM_FEATURE_VFP3)) { 1022 set_feature(env, ARM_FEATURE_VFP); 1023 } 1024 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1025 set_feature(env, ARM_FEATURE_V7MP); 1026 set_feature(env, ARM_FEATURE_PXN); 1027 } 1028 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1029 set_feature(env, ARM_FEATURE_CBAR); 1030 } 1031 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1032 !arm_feature(env, ARM_FEATURE_M)) { 1033 set_feature(env, ARM_FEATURE_THUMB_DSP); 1034 } 1035 1036 /* 1037 * We rely on no XScale CPU having VFP so we can use the same bits in the 1038 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1039 */ 1040 assert(!(arm_feature(env, ARM_FEATURE_VFP) && 1041 arm_feature(env, ARM_FEATURE_XSCALE))); 1042 1043 if (arm_feature(env, ARM_FEATURE_V7) && 1044 !arm_feature(env, ARM_FEATURE_M) && 1045 !arm_feature(env, ARM_FEATURE_PMSA)) { 1046 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1047 * can use 4K pages. 1048 */ 1049 pagebits = 12; 1050 } else { 1051 /* For CPUs which might have tiny 1K pages, or which have an 1052 * MPU and might have small region sizes, stick with 1K pages. 1053 */ 1054 pagebits = 10; 1055 } 1056 if (!set_preferred_target_page_bits(pagebits)) { 1057 /* This can only ever happen for hotplugging a CPU, or if 1058 * the board code incorrectly creates a CPU which it has 1059 * promised via minimum_page_size that it will not. 1060 */ 1061 error_setg(errp, "This CPU requires a smaller page size than the " 1062 "system is using"); 1063 return; 1064 } 1065 1066 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1067 * We don't support setting cluster ID ([16..23]) (known as Aff2 1068 * in later ARM ARM versions), or any of the higher affinity level fields, 1069 * so these bits always RAZ. 1070 */ 1071 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1072 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1073 ARM_DEFAULT_CPUS_PER_CLUSTER); 1074 } 1075 1076 if (cpu->reset_hivecs) { 1077 cpu->reset_sctlr |= (1 << 13); 1078 } 1079 1080 if (cpu->cfgend) { 1081 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1082 cpu->reset_sctlr |= SCTLR_EE; 1083 } else { 1084 cpu->reset_sctlr |= SCTLR_B; 1085 } 1086 } 1087 1088 if (!cpu->has_el3) { 1089 /* If the has_el3 CPU property is disabled then we need to disable the 1090 * feature. 1091 */ 1092 unset_feature(env, ARM_FEATURE_EL3); 1093 1094 /* Disable the security extension feature bits in the processor feature 1095 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 1096 */ 1097 cpu->id_pfr1 &= ~0xf0; 1098 cpu->isar.id_aa64pfr0 &= ~0xf000; 1099 } 1100 1101 if (!cpu->has_el2) { 1102 unset_feature(env, ARM_FEATURE_EL2); 1103 } 1104 1105 if (!cpu->has_pmu) { 1106 unset_feature(env, ARM_FEATURE_PMU); 1107 } 1108 if (arm_feature(env, ARM_FEATURE_PMU)) { 1109 pmu_init(cpu); 1110 1111 if (!kvm_enabled()) { 1112 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1113 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1114 } 1115 1116 #ifndef CONFIG_USER_ONLY 1117 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1118 cpu); 1119 #endif 1120 } else { 1121 cpu->id_aa64dfr0 &= ~0xf00; 1122 cpu->id_dfr0 &= ~(0xf << 24); 1123 cpu->pmceid0 = 0; 1124 cpu->pmceid1 = 0; 1125 } 1126 1127 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1128 /* Disable the hypervisor feature bits in the processor feature 1129 * registers if we don't have EL2. These are id_pfr1[15:12] and 1130 * id_aa64pfr0_el1[11:8]. 1131 */ 1132 cpu->isar.id_aa64pfr0 &= ~0xf00; 1133 cpu->id_pfr1 &= ~0xf000; 1134 } 1135 1136 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1137 * to false or by setting pmsav7-dregion to 0. 1138 */ 1139 if (!cpu->has_mpu) { 1140 cpu->pmsav7_dregion = 0; 1141 } 1142 if (cpu->pmsav7_dregion == 0) { 1143 cpu->has_mpu = false; 1144 } 1145 1146 if (arm_feature(env, ARM_FEATURE_PMSA) && 1147 arm_feature(env, ARM_FEATURE_V7)) { 1148 uint32_t nr = cpu->pmsav7_dregion; 1149 1150 if (nr > 0xff) { 1151 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1152 return; 1153 } 1154 1155 if (nr) { 1156 if (arm_feature(env, ARM_FEATURE_V8)) { 1157 /* PMSAv8 */ 1158 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1159 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1160 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1161 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1162 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1163 } 1164 } else { 1165 env->pmsav7.drbar = g_new0(uint32_t, nr); 1166 env->pmsav7.drsr = g_new0(uint32_t, nr); 1167 env->pmsav7.dracr = g_new0(uint32_t, nr); 1168 } 1169 } 1170 } 1171 1172 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1173 uint32_t nr = cpu->sau_sregion; 1174 1175 if (nr > 0xff) { 1176 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1177 return; 1178 } 1179 1180 if (nr) { 1181 env->sau.rbar = g_new0(uint32_t, nr); 1182 env->sau.rlar = g_new0(uint32_t, nr); 1183 } 1184 } 1185 1186 if (arm_feature(env, ARM_FEATURE_EL3)) { 1187 set_feature(env, ARM_FEATURE_VBAR); 1188 } 1189 1190 register_cp_regs_for_features(cpu); 1191 arm_cpu_register_gdb_regs_for_features(cpu); 1192 1193 init_cpreg_list(cpu); 1194 1195 #ifndef CONFIG_USER_ONLY 1196 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1197 cs->num_ases = 2; 1198 1199 if (!cpu->secure_memory) { 1200 cpu->secure_memory = cs->memory; 1201 } 1202 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1203 cpu->secure_memory); 1204 } else { 1205 cs->num_ases = 1; 1206 } 1207 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1208 1209 /* No core_count specified, default to smp_cpus. */ 1210 if (cpu->core_count == -1) { 1211 cpu->core_count = smp_cpus; 1212 } 1213 #endif 1214 1215 qemu_init_vcpu(cs); 1216 cpu_reset(cs); 1217 1218 acc->parent_realize(dev, errp); 1219 } 1220 1221 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1222 { 1223 ObjectClass *oc; 1224 char *typename; 1225 char **cpuname; 1226 const char *cpunamestr; 1227 1228 cpuname = g_strsplit(cpu_model, ",", 1); 1229 cpunamestr = cpuname[0]; 1230 #ifdef CONFIG_USER_ONLY 1231 /* For backwards compatibility usermode emulation allows "-cpu any", 1232 * which has the same semantics as "-cpu max". 1233 */ 1234 if (!strcmp(cpunamestr, "any")) { 1235 cpunamestr = "max"; 1236 } 1237 #endif 1238 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 1239 oc = object_class_by_name(typename); 1240 g_strfreev(cpuname); 1241 g_free(typename); 1242 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 1243 object_class_is_abstract(oc)) { 1244 return NULL; 1245 } 1246 return oc; 1247 } 1248 1249 /* CPU models. These are not needed for the AArch64 linux-user build. */ 1250 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1251 1252 static void arm926_initfn(Object *obj) 1253 { 1254 ARMCPU *cpu = ARM_CPU(obj); 1255 1256 cpu->dtb_compatible = "arm,arm926"; 1257 set_feature(&cpu->env, ARM_FEATURE_V5); 1258 set_feature(&cpu->env, ARM_FEATURE_VFP); 1259 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1260 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1261 cpu->midr = 0x41069265; 1262 cpu->reset_fpsid = 0x41011090; 1263 cpu->ctr = 0x1dd20d2; 1264 cpu->reset_sctlr = 0x00090078; 1265 1266 /* 1267 * ARMv5 does not have the ID_ISAR registers, but we can still 1268 * set the field to indicate Jazelle support within QEMU. 1269 */ 1270 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 1271 } 1272 1273 static void arm946_initfn(Object *obj) 1274 { 1275 ARMCPU *cpu = ARM_CPU(obj); 1276 1277 cpu->dtb_compatible = "arm,arm946"; 1278 set_feature(&cpu->env, ARM_FEATURE_V5); 1279 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1280 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1281 cpu->midr = 0x41059461; 1282 cpu->ctr = 0x0f004006; 1283 cpu->reset_sctlr = 0x00000078; 1284 } 1285 1286 static void arm1026_initfn(Object *obj) 1287 { 1288 ARMCPU *cpu = ARM_CPU(obj); 1289 1290 cpu->dtb_compatible = "arm,arm1026"; 1291 set_feature(&cpu->env, ARM_FEATURE_V5); 1292 set_feature(&cpu->env, ARM_FEATURE_VFP); 1293 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 1294 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1295 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1296 cpu->midr = 0x4106a262; 1297 cpu->reset_fpsid = 0x410110a0; 1298 cpu->ctr = 0x1dd20d2; 1299 cpu->reset_sctlr = 0x00090078; 1300 cpu->reset_auxcr = 1; 1301 1302 /* 1303 * ARMv5 does not have the ID_ISAR registers, but we can still 1304 * set the field to indicate Jazelle support within QEMU. 1305 */ 1306 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 1307 1308 { 1309 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 1310 ARMCPRegInfo ifar = { 1311 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 1312 .access = PL1_RW, 1313 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 1314 .resetvalue = 0 1315 }; 1316 define_one_arm_cp_reg(cpu, &ifar); 1317 } 1318 } 1319 1320 static void arm1136_r2_initfn(Object *obj) 1321 { 1322 ARMCPU *cpu = ARM_CPU(obj); 1323 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 1324 * older core than plain "arm1136". In particular this does not 1325 * have the v6K features. 1326 * These ID register values are correct for 1136 but may be wrong 1327 * for 1136_r2 (in particular r0p2 does not actually implement most 1328 * of the ID registers). 1329 */ 1330 1331 cpu->dtb_compatible = "arm,arm1136"; 1332 set_feature(&cpu->env, ARM_FEATURE_V6); 1333 set_feature(&cpu->env, ARM_FEATURE_VFP); 1334 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1335 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1336 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1337 cpu->midr = 0x4107b362; 1338 cpu->reset_fpsid = 0x410120b4; 1339 cpu->isar.mvfr0 = 0x11111111; 1340 cpu->isar.mvfr1 = 0x00000000; 1341 cpu->ctr = 0x1dd20d2; 1342 cpu->reset_sctlr = 0x00050078; 1343 cpu->id_pfr0 = 0x111; 1344 cpu->id_pfr1 = 0x1; 1345 cpu->id_dfr0 = 0x2; 1346 cpu->id_afr0 = 0x3; 1347 cpu->id_mmfr0 = 0x01130003; 1348 cpu->id_mmfr1 = 0x10030302; 1349 cpu->id_mmfr2 = 0x01222110; 1350 cpu->isar.id_isar0 = 0x00140011; 1351 cpu->isar.id_isar1 = 0x12002111; 1352 cpu->isar.id_isar2 = 0x11231111; 1353 cpu->isar.id_isar3 = 0x01102131; 1354 cpu->isar.id_isar4 = 0x141; 1355 cpu->reset_auxcr = 7; 1356 } 1357 1358 static void arm1136_initfn(Object *obj) 1359 { 1360 ARMCPU *cpu = ARM_CPU(obj); 1361 1362 cpu->dtb_compatible = "arm,arm1136"; 1363 set_feature(&cpu->env, ARM_FEATURE_V6K); 1364 set_feature(&cpu->env, ARM_FEATURE_V6); 1365 set_feature(&cpu->env, ARM_FEATURE_VFP); 1366 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1367 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1368 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1369 cpu->midr = 0x4117b363; 1370 cpu->reset_fpsid = 0x410120b4; 1371 cpu->isar.mvfr0 = 0x11111111; 1372 cpu->isar.mvfr1 = 0x00000000; 1373 cpu->ctr = 0x1dd20d2; 1374 cpu->reset_sctlr = 0x00050078; 1375 cpu->id_pfr0 = 0x111; 1376 cpu->id_pfr1 = 0x1; 1377 cpu->id_dfr0 = 0x2; 1378 cpu->id_afr0 = 0x3; 1379 cpu->id_mmfr0 = 0x01130003; 1380 cpu->id_mmfr1 = 0x10030302; 1381 cpu->id_mmfr2 = 0x01222110; 1382 cpu->isar.id_isar0 = 0x00140011; 1383 cpu->isar.id_isar1 = 0x12002111; 1384 cpu->isar.id_isar2 = 0x11231111; 1385 cpu->isar.id_isar3 = 0x01102131; 1386 cpu->isar.id_isar4 = 0x141; 1387 cpu->reset_auxcr = 7; 1388 } 1389 1390 static void arm1176_initfn(Object *obj) 1391 { 1392 ARMCPU *cpu = ARM_CPU(obj); 1393 1394 cpu->dtb_compatible = "arm,arm1176"; 1395 set_feature(&cpu->env, ARM_FEATURE_V6K); 1396 set_feature(&cpu->env, ARM_FEATURE_VFP); 1397 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1398 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1399 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1400 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1401 set_feature(&cpu->env, ARM_FEATURE_EL3); 1402 cpu->midr = 0x410fb767; 1403 cpu->reset_fpsid = 0x410120b5; 1404 cpu->isar.mvfr0 = 0x11111111; 1405 cpu->isar.mvfr1 = 0x00000000; 1406 cpu->ctr = 0x1dd20d2; 1407 cpu->reset_sctlr = 0x00050078; 1408 cpu->id_pfr0 = 0x111; 1409 cpu->id_pfr1 = 0x11; 1410 cpu->id_dfr0 = 0x33; 1411 cpu->id_afr0 = 0; 1412 cpu->id_mmfr0 = 0x01130003; 1413 cpu->id_mmfr1 = 0x10030302; 1414 cpu->id_mmfr2 = 0x01222100; 1415 cpu->isar.id_isar0 = 0x0140011; 1416 cpu->isar.id_isar1 = 0x12002111; 1417 cpu->isar.id_isar2 = 0x11231121; 1418 cpu->isar.id_isar3 = 0x01102131; 1419 cpu->isar.id_isar4 = 0x01141; 1420 cpu->reset_auxcr = 7; 1421 } 1422 1423 static void arm11mpcore_initfn(Object *obj) 1424 { 1425 ARMCPU *cpu = ARM_CPU(obj); 1426 1427 cpu->dtb_compatible = "arm,arm11mpcore"; 1428 set_feature(&cpu->env, ARM_FEATURE_V6K); 1429 set_feature(&cpu->env, ARM_FEATURE_VFP); 1430 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1431 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1432 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1433 cpu->midr = 0x410fb022; 1434 cpu->reset_fpsid = 0x410120b4; 1435 cpu->isar.mvfr0 = 0x11111111; 1436 cpu->isar.mvfr1 = 0x00000000; 1437 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1438 cpu->id_pfr0 = 0x111; 1439 cpu->id_pfr1 = 0x1; 1440 cpu->id_dfr0 = 0; 1441 cpu->id_afr0 = 0x2; 1442 cpu->id_mmfr0 = 0x01100103; 1443 cpu->id_mmfr1 = 0x10020302; 1444 cpu->id_mmfr2 = 0x01222000; 1445 cpu->isar.id_isar0 = 0x00100011; 1446 cpu->isar.id_isar1 = 0x12002111; 1447 cpu->isar.id_isar2 = 0x11221011; 1448 cpu->isar.id_isar3 = 0x01102131; 1449 cpu->isar.id_isar4 = 0x141; 1450 cpu->reset_auxcr = 1; 1451 } 1452 1453 static void cortex_m0_initfn(Object *obj) 1454 { 1455 ARMCPU *cpu = ARM_CPU(obj); 1456 set_feature(&cpu->env, ARM_FEATURE_V6); 1457 set_feature(&cpu->env, ARM_FEATURE_M); 1458 1459 cpu->midr = 0x410cc200; 1460 } 1461 1462 static void cortex_m3_initfn(Object *obj) 1463 { 1464 ARMCPU *cpu = ARM_CPU(obj); 1465 set_feature(&cpu->env, ARM_FEATURE_V7); 1466 set_feature(&cpu->env, ARM_FEATURE_M); 1467 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1468 cpu->midr = 0x410fc231; 1469 cpu->pmsav7_dregion = 8; 1470 cpu->id_pfr0 = 0x00000030; 1471 cpu->id_pfr1 = 0x00000200; 1472 cpu->id_dfr0 = 0x00100000; 1473 cpu->id_afr0 = 0x00000000; 1474 cpu->id_mmfr0 = 0x00000030; 1475 cpu->id_mmfr1 = 0x00000000; 1476 cpu->id_mmfr2 = 0x00000000; 1477 cpu->id_mmfr3 = 0x00000000; 1478 cpu->isar.id_isar0 = 0x01141110; 1479 cpu->isar.id_isar1 = 0x02111000; 1480 cpu->isar.id_isar2 = 0x21112231; 1481 cpu->isar.id_isar3 = 0x01111110; 1482 cpu->isar.id_isar4 = 0x01310102; 1483 cpu->isar.id_isar5 = 0x00000000; 1484 cpu->isar.id_isar6 = 0x00000000; 1485 } 1486 1487 static void cortex_m4_initfn(Object *obj) 1488 { 1489 ARMCPU *cpu = ARM_CPU(obj); 1490 1491 set_feature(&cpu->env, ARM_FEATURE_V7); 1492 set_feature(&cpu->env, ARM_FEATURE_M); 1493 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1494 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1495 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1496 cpu->midr = 0x410fc240; /* r0p0 */ 1497 cpu->pmsav7_dregion = 8; 1498 cpu->isar.mvfr0 = 0x10110021; 1499 cpu->isar.mvfr1 = 0x11000011; 1500 cpu->isar.mvfr2 = 0x00000000; 1501 cpu->id_pfr0 = 0x00000030; 1502 cpu->id_pfr1 = 0x00000200; 1503 cpu->id_dfr0 = 0x00100000; 1504 cpu->id_afr0 = 0x00000000; 1505 cpu->id_mmfr0 = 0x00000030; 1506 cpu->id_mmfr1 = 0x00000000; 1507 cpu->id_mmfr2 = 0x00000000; 1508 cpu->id_mmfr3 = 0x00000000; 1509 cpu->isar.id_isar0 = 0x01141110; 1510 cpu->isar.id_isar1 = 0x02111000; 1511 cpu->isar.id_isar2 = 0x21112231; 1512 cpu->isar.id_isar3 = 0x01111110; 1513 cpu->isar.id_isar4 = 0x01310102; 1514 cpu->isar.id_isar5 = 0x00000000; 1515 cpu->isar.id_isar6 = 0x00000000; 1516 } 1517 1518 static void cortex_m33_initfn(Object *obj) 1519 { 1520 ARMCPU *cpu = ARM_CPU(obj); 1521 1522 set_feature(&cpu->env, ARM_FEATURE_V8); 1523 set_feature(&cpu->env, ARM_FEATURE_M); 1524 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1525 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); 1526 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1527 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1528 cpu->midr = 0x410fd213; /* r0p3 */ 1529 cpu->pmsav7_dregion = 16; 1530 cpu->sau_sregion = 8; 1531 cpu->isar.mvfr0 = 0x10110021; 1532 cpu->isar.mvfr1 = 0x11000011; 1533 cpu->isar.mvfr2 = 0x00000040; 1534 cpu->id_pfr0 = 0x00000030; 1535 cpu->id_pfr1 = 0x00000210; 1536 cpu->id_dfr0 = 0x00200000; 1537 cpu->id_afr0 = 0x00000000; 1538 cpu->id_mmfr0 = 0x00101F40; 1539 cpu->id_mmfr1 = 0x00000000; 1540 cpu->id_mmfr2 = 0x01000000; 1541 cpu->id_mmfr3 = 0x00000000; 1542 cpu->isar.id_isar0 = 0x01101110; 1543 cpu->isar.id_isar1 = 0x02212000; 1544 cpu->isar.id_isar2 = 0x20232232; 1545 cpu->isar.id_isar3 = 0x01111131; 1546 cpu->isar.id_isar4 = 0x01310132; 1547 cpu->isar.id_isar5 = 0x00000000; 1548 cpu->isar.id_isar6 = 0x00000000; 1549 cpu->clidr = 0x00000000; 1550 cpu->ctr = 0x8000c000; 1551 } 1552 1553 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1554 { 1555 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1556 CPUClass *cc = CPU_CLASS(oc); 1557 1558 acc->info = data; 1559 #ifndef CONFIG_USER_ONLY 1560 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1561 #endif 1562 1563 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1564 } 1565 1566 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1567 /* Dummy the TCM region regs for the moment */ 1568 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1569 .access = PL1_RW, .type = ARM_CP_CONST }, 1570 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1571 .access = PL1_RW, .type = ARM_CP_CONST }, 1572 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 1573 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 1574 REGINFO_SENTINEL 1575 }; 1576 1577 static void cortex_r5_initfn(Object *obj) 1578 { 1579 ARMCPU *cpu = ARM_CPU(obj); 1580 1581 set_feature(&cpu->env, ARM_FEATURE_V7); 1582 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1583 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1584 cpu->midr = 0x411fc153; /* r1p3 */ 1585 cpu->id_pfr0 = 0x0131; 1586 cpu->id_pfr1 = 0x001; 1587 cpu->id_dfr0 = 0x010400; 1588 cpu->id_afr0 = 0x0; 1589 cpu->id_mmfr0 = 0x0210030; 1590 cpu->id_mmfr1 = 0x00000000; 1591 cpu->id_mmfr2 = 0x01200000; 1592 cpu->id_mmfr3 = 0x0211; 1593 cpu->isar.id_isar0 = 0x02101111; 1594 cpu->isar.id_isar1 = 0x13112111; 1595 cpu->isar.id_isar2 = 0x21232141; 1596 cpu->isar.id_isar3 = 0x01112131; 1597 cpu->isar.id_isar4 = 0x0010142; 1598 cpu->isar.id_isar5 = 0x0; 1599 cpu->isar.id_isar6 = 0x0; 1600 cpu->mp_is_up = true; 1601 cpu->pmsav7_dregion = 16; 1602 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1603 } 1604 1605 static void cortex_r5f_initfn(Object *obj) 1606 { 1607 ARMCPU *cpu = ARM_CPU(obj); 1608 1609 cortex_r5_initfn(obj); 1610 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1611 } 1612 1613 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1614 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1615 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1616 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1617 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1618 REGINFO_SENTINEL 1619 }; 1620 1621 static void cortex_a8_initfn(Object *obj) 1622 { 1623 ARMCPU *cpu = ARM_CPU(obj); 1624 1625 cpu->dtb_compatible = "arm,cortex-a8"; 1626 set_feature(&cpu->env, ARM_FEATURE_V7); 1627 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1628 set_feature(&cpu->env, ARM_FEATURE_NEON); 1629 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1630 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1631 set_feature(&cpu->env, ARM_FEATURE_EL3); 1632 cpu->midr = 0x410fc080; 1633 cpu->reset_fpsid = 0x410330c0; 1634 cpu->isar.mvfr0 = 0x11110222; 1635 cpu->isar.mvfr1 = 0x00011111; 1636 cpu->ctr = 0x82048004; 1637 cpu->reset_sctlr = 0x00c50078; 1638 cpu->id_pfr0 = 0x1031; 1639 cpu->id_pfr1 = 0x11; 1640 cpu->id_dfr0 = 0x400; 1641 cpu->id_afr0 = 0; 1642 cpu->id_mmfr0 = 0x31100003; 1643 cpu->id_mmfr1 = 0x20000000; 1644 cpu->id_mmfr2 = 0x01202000; 1645 cpu->id_mmfr3 = 0x11; 1646 cpu->isar.id_isar0 = 0x00101111; 1647 cpu->isar.id_isar1 = 0x12112111; 1648 cpu->isar.id_isar2 = 0x21232031; 1649 cpu->isar.id_isar3 = 0x11112131; 1650 cpu->isar.id_isar4 = 0x00111142; 1651 cpu->dbgdidr = 0x15141000; 1652 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1653 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1654 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1655 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1656 cpu->reset_auxcr = 2; 1657 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1658 } 1659 1660 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1661 /* power_control should be set to maximum latency. Again, 1662 * default to 0 and set by private hook 1663 */ 1664 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1665 .access = PL1_RW, .resetvalue = 0, 1666 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1667 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1668 .access = PL1_RW, .resetvalue = 0, 1669 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1670 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1671 .access = PL1_RW, .resetvalue = 0, 1672 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1673 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1674 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1675 /* TLB lockdown control */ 1676 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1677 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1678 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1679 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1680 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1681 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1682 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1683 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1684 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1685 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1686 REGINFO_SENTINEL 1687 }; 1688 1689 static void cortex_a9_initfn(Object *obj) 1690 { 1691 ARMCPU *cpu = ARM_CPU(obj); 1692 1693 cpu->dtb_compatible = "arm,cortex-a9"; 1694 set_feature(&cpu->env, ARM_FEATURE_V7); 1695 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1696 set_feature(&cpu->env, ARM_FEATURE_NEON); 1697 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1698 set_feature(&cpu->env, ARM_FEATURE_EL3); 1699 /* Note that A9 supports the MP extensions even for 1700 * A9UP and single-core A9MP (which are both different 1701 * and valid configurations; we don't model A9UP). 1702 */ 1703 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1704 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1705 cpu->midr = 0x410fc090; 1706 cpu->reset_fpsid = 0x41033090; 1707 cpu->isar.mvfr0 = 0x11110222; 1708 cpu->isar.mvfr1 = 0x01111111; 1709 cpu->ctr = 0x80038003; 1710 cpu->reset_sctlr = 0x00c50078; 1711 cpu->id_pfr0 = 0x1031; 1712 cpu->id_pfr1 = 0x11; 1713 cpu->id_dfr0 = 0x000; 1714 cpu->id_afr0 = 0; 1715 cpu->id_mmfr0 = 0x00100103; 1716 cpu->id_mmfr1 = 0x20000000; 1717 cpu->id_mmfr2 = 0x01230000; 1718 cpu->id_mmfr3 = 0x00002111; 1719 cpu->isar.id_isar0 = 0x00101111; 1720 cpu->isar.id_isar1 = 0x13112111; 1721 cpu->isar.id_isar2 = 0x21232041; 1722 cpu->isar.id_isar3 = 0x11112131; 1723 cpu->isar.id_isar4 = 0x00111142; 1724 cpu->dbgdidr = 0x35141000; 1725 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1726 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1727 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1728 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1729 } 1730 1731 #ifndef CONFIG_USER_ONLY 1732 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1733 { 1734 /* Linux wants the number of processors from here. 1735 * Might as well set the interrupt-controller bit too. 1736 */ 1737 return ((smp_cpus - 1) << 24) | (1 << 23); 1738 } 1739 #endif 1740 1741 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1742 #ifndef CONFIG_USER_ONLY 1743 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1744 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1745 .writefn = arm_cp_write_ignore, }, 1746 #endif 1747 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1748 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1749 REGINFO_SENTINEL 1750 }; 1751 1752 static void cortex_a7_initfn(Object *obj) 1753 { 1754 ARMCPU *cpu = ARM_CPU(obj); 1755 1756 cpu->dtb_compatible = "arm,cortex-a7"; 1757 set_feature(&cpu->env, ARM_FEATURE_V7VE); 1758 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1759 set_feature(&cpu->env, ARM_FEATURE_NEON); 1760 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1761 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1762 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1763 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1764 set_feature(&cpu->env, ARM_FEATURE_EL2); 1765 set_feature(&cpu->env, ARM_FEATURE_EL3); 1766 set_feature(&cpu->env, ARM_FEATURE_PMU); 1767 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1768 cpu->midr = 0x410fc075; 1769 cpu->reset_fpsid = 0x41023075; 1770 cpu->isar.mvfr0 = 0x10110222; 1771 cpu->isar.mvfr1 = 0x11111111; 1772 cpu->ctr = 0x84448003; 1773 cpu->reset_sctlr = 0x00c50078; 1774 cpu->id_pfr0 = 0x00001131; 1775 cpu->id_pfr1 = 0x00011011; 1776 cpu->id_dfr0 = 0x02010555; 1777 cpu->id_afr0 = 0x00000000; 1778 cpu->id_mmfr0 = 0x10101105; 1779 cpu->id_mmfr1 = 0x40000000; 1780 cpu->id_mmfr2 = 0x01240000; 1781 cpu->id_mmfr3 = 0x02102211; 1782 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but 1783 * table 4-41 gives 0x02101110, which includes the arm div insns. 1784 */ 1785 cpu->isar.id_isar0 = 0x02101110; 1786 cpu->isar.id_isar1 = 0x13112111; 1787 cpu->isar.id_isar2 = 0x21232041; 1788 cpu->isar.id_isar3 = 0x11112131; 1789 cpu->isar.id_isar4 = 0x10011142; 1790 cpu->dbgdidr = 0x3515f005; 1791 cpu->clidr = 0x0a200023; 1792 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1793 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1794 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1795 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1796 } 1797 1798 static void cortex_a15_initfn(Object *obj) 1799 { 1800 ARMCPU *cpu = ARM_CPU(obj); 1801 1802 cpu->dtb_compatible = "arm,cortex-a15"; 1803 set_feature(&cpu->env, ARM_FEATURE_V7VE); 1804 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1805 set_feature(&cpu->env, ARM_FEATURE_NEON); 1806 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1807 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1808 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1809 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1810 set_feature(&cpu->env, ARM_FEATURE_EL2); 1811 set_feature(&cpu->env, ARM_FEATURE_EL3); 1812 set_feature(&cpu->env, ARM_FEATURE_PMU); 1813 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1814 cpu->midr = 0x412fc0f1; 1815 cpu->reset_fpsid = 0x410430f0; 1816 cpu->isar.mvfr0 = 0x10110222; 1817 cpu->isar.mvfr1 = 0x11111111; 1818 cpu->ctr = 0x8444c004; 1819 cpu->reset_sctlr = 0x00c50078; 1820 cpu->id_pfr0 = 0x00001131; 1821 cpu->id_pfr1 = 0x00011011; 1822 cpu->id_dfr0 = 0x02010555; 1823 cpu->id_afr0 = 0x00000000; 1824 cpu->id_mmfr0 = 0x10201105; 1825 cpu->id_mmfr1 = 0x20000000; 1826 cpu->id_mmfr2 = 0x01240000; 1827 cpu->id_mmfr3 = 0x02102211; 1828 cpu->isar.id_isar0 = 0x02101110; 1829 cpu->isar.id_isar1 = 0x13112111; 1830 cpu->isar.id_isar2 = 0x21232041; 1831 cpu->isar.id_isar3 = 0x11112131; 1832 cpu->isar.id_isar4 = 0x10011142; 1833 cpu->dbgdidr = 0x3515f021; 1834 cpu->clidr = 0x0a200023; 1835 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1836 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1837 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1838 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 1839 } 1840 1841 static void ti925t_initfn(Object *obj) 1842 { 1843 ARMCPU *cpu = ARM_CPU(obj); 1844 set_feature(&cpu->env, ARM_FEATURE_V4T); 1845 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 1846 cpu->midr = ARM_CPUID_TI925T; 1847 cpu->ctr = 0x5109149; 1848 cpu->reset_sctlr = 0x00000070; 1849 } 1850 1851 static void sa1100_initfn(Object *obj) 1852 { 1853 ARMCPU *cpu = ARM_CPU(obj); 1854 1855 cpu->dtb_compatible = "intel,sa1100"; 1856 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1857 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1858 cpu->midr = 0x4401A11B; 1859 cpu->reset_sctlr = 0x00000070; 1860 } 1861 1862 static void sa1110_initfn(Object *obj) 1863 { 1864 ARMCPU *cpu = ARM_CPU(obj); 1865 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1866 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1867 cpu->midr = 0x6901B119; 1868 cpu->reset_sctlr = 0x00000070; 1869 } 1870 1871 static void pxa250_initfn(Object *obj) 1872 { 1873 ARMCPU *cpu = ARM_CPU(obj); 1874 1875 cpu->dtb_compatible = "marvell,xscale"; 1876 set_feature(&cpu->env, ARM_FEATURE_V5); 1877 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1878 cpu->midr = 0x69052100; 1879 cpu->ctr = 0xd172172; 1880 cpu->reset_sctlr = 0x00000078; 1881 } 1882 1883 static void pxa255_initfn(Object *obj) 1884 { 1885 ARMCPU *cpu = ARM_CPU(obj); 1886 1887 cpu->dtb_compatible = "marvell,xscale"; 1888 set_feature(&cpu->env, ARM_FEATURE_V5); 1889 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1890 cpu->midr = 0x69052d00; 1891 cpu->ctr = 0xd172172; 1892 cpu->reset_sctlr = 0x00000078; 1893 } 1894 1895 static void pxa260_initfn(Object *obj) 1896 { 1897 ARMCPU *cpu = ARM_CPU(obj); 1898 1899 cpu->dtb_compatible = "marvell,xscale"; 1900 set_feature(&cpu->env, ARM_FEATURE_V5); 1901 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1902 cpu->midr = 0x69052903; 1903 cpu->ctr = 0xd172172; 1904 cpu->reset_sctlr = 0x00000078; 1905 } 1906 1907 static void pxa261_initfn(Object *obj) 1908 { 1909 ARMCPU *cpu = ARM_CPU(obj); 1910 1911 cpu->dtb_compatible = "marvell,xscale"; 1912 set_feature(&cpu->env, ARM_FEATURE_V5); 1913 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1914 cpu->midr = 0x69052d05; 1915 cpu->ctr = 0xd172172; 1916 cpu->reset_sctlr = 0x00000078; 1917 } 1918 1919 static void pxa262_initfn(Object *obj) 1920 { 1921 ARMCPU *cpu = ARM_CPU(obj); 1922 1923 cpu->dtb_compatible = "marvell,xscale"; 1924 set_feature(&cpu->env, ARM_FEATURE_V5); 1925 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1926 cpu->midr = 0x69052d06; 1927 cpu->ctr = 0xd172172; 1928 cpu->reset_sctlr = 0x00000078; 1929 } 1930 1931 static void pxa270a0_initfn(Object *obj) 1932 { 1933 ARMCPU *cpu = ARM_CPU(obj); 1934 1935 cpu->dtb_compatible = "marvell,xscale"; 1936 set_feature(&cpu->env, ARM_FEATURE_V5); 1937 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1938 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1939 cpu->midr = 0x69054110; 1940 cpu->ctr = 0xd172172; 1941 cpu->reset_sctlr = 0x00000078; 1942 } 1943 1944 static void pxa270a1_initfn(Object *obj) 1945 { 1946 ARMCPU *cpu = ARM_CPU(obj); 1947 1948 cpu->dtb_compatible = "marvell,xscale"; 1949 set_feature(&cpu->env, ARM_FEATURE_V5); 1950 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1951 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1952 cpu->midr = 0x69054111; 1953 cpu->ctr = 0xd172172; 1954 cpu->reset_sctlr = 0x00000078; 1955 } 1956 1957 static void pxa270b0_initfn(Object *obj) 1958 { 1959 ARMCPU *cpu = ARM_CPU(obj); 1960 1961 cpu->dtb_compatible = "marvell,xscale"; 1962 set_feature(&cpu->env, ARM_FEATURE_V5); 1963 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1964 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1965 cpu->midr = 0x69054112; 1966 cpu->ctr = 0xd172172; 1967 cpu->reset_sctlr = 0x00000078; 1968 } 1969 1970 static void pxa270b1_initfn(Object *obj) 1971 { 1972 ARMCPU *cpu = ARM_CPU(obj); 1973 1974 cpu->dtb_compatible = "marvell,xscale"; 1975 set_feature(&cpu->env, ARM_FEATURE_V5); 1976 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1977 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1978 cpu->midr = 0x69054113; 1979 cpu->ctr = 0xd172172; 1980 cpu->reset_sctlr = 0x00000078; 1981 } 1982 1983 static void pxa270c0_initfn(Object *obj) 1984 { 1985 ARMCPU *cpu = ARM_CPU(obj); 1986 1987 cpu->dtb_compatible = "marvell,xscale"; 1988 set_feature(&cpu->env, ARM_FEATURE_V5); 1989 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1990 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1991 cpu->midr = 0x69054114; 1992 cpu->ctr = 0xd172172; 1993 cpu->reset_sctlr = 0x00000078; 1994 } 1995 1996 static void pxa270c5_initfn(Object *obj) 1997 { 1998 ARMCPU *cpu = ARM_CPU(obj); 1999 2000 cpu->dtb_compatible = "marvell,xscale"; 2001 set_feature(&cpu->env, ARM_FEATURE_V5); 2002 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 2003 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 2004 cpu->midr = 0x69054117; 2005 cpu->ctr = 0xd172172; 2006 cpu->reset_sctlr = 0x00000078; 2007 } 2008 2009 #ifndef TARGET_AARCH64 2010 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 2011 * otherwise, a CPU with as many features enabled as our emulation supports. 2012 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; 2013 * this only needs to handle 32 bits. 2014 */ 2015 static void arm_max_initfn(Object *obj) 2016 { 2017 ARMCPU *cpu = ARM_CPU(obj); 2018 2019 if (kvm_enabled()) { 2020 kvm_arm_set_cpu_features_from_host(cpu); 2021 } else { 2022 cortex_a15_initfn(obj); 2023 #ifdef CONFIG_USER_ONLY 2024 /* We don't set these in system emulation mode for the moment, 2025 * since we don't correctly set (all of) the ID registers to 2026 * advertise them. 2027 */ 2028 set_feature(&cpu->env, ARM_FEATURE_V8); 2029 { 2030 uint32_t t; 2031 2032 t = cpu->isar.id_isar5; 2033 t = FIELD_DP32(t, ID_ISAR5, AES, 2); 2034 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); 2035 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); 2036 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); 2037 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); 2038 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); 2039 cpu->isar.id_isar5 = t; 2040 2041 t = cpu->isar.id_isar6; 2042 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); 2043 t = FIELD_DP32(t, ID_ISAR6, DP, 1); 2044 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); 2045 t = FIELD_DP32(t, ID_ISAR6, SB, 1); 2046 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); 2047 cpu->isar.id_isar6 = t; 2048 2049 t = cpu->isar.mvfr2; 2050 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ 2051 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ 2052 cpu->isar.mvfr2 = t; 2053 2054 t = cpu->id_mmfr4; 2055 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ 2056 cpu->id_mmfr4 = t; 2057 } 2058 #endif 2059 } 2060 } 2061 #endif 2062 2063 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 2064 2065 struct ARMCPUInfo { 2066 const char *name; 2067 void (*initfn)(Object *obj); 2068 void (*class_init)(ObjectClass *oc, void *data); 2069 }; 2070 2071 static const ARMCPUInfo arm_cpus[] = { 2072 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 2073 { .name = "arm926", .initfn = arm926_initfn }, 2074 { .name = "arm946", .initfn = arm946_initfn }, 2075 { .name = "arm1026", .initfn = arm1026_initfn }, 2076 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 2077 * older core than plain "arm1136". In particular this does not 2078 * have the v6K features. 2079 */ 2080 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 2081 { .name = "arm1136", .initfn = arm1136_initfn }, 2082 { .name = "arm1176", .initfn = arm1176_initfn }, 2083 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 2084 { .name = "cortex-m0", .initfn = cortex_m0_initfn, 2085 .class_init = arm_v7m_class_init }, 2086 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 2087 .class_init = arm_v7m_class_init }, 2088 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 2089 .class_init = arm_v7m_class_init }, 2090 { .name = "cortex-m33", .initfn = cortex_m33_initfn, 2091 .class_init = arm_v7m_class_init }, 2092 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 2093 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, 2094 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 2095 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 2096 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 2097 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 2098 { .name = "ti925t", .initfn = ti925t_initfn }, 2099 { .name = "sa1100", .initfn = sa1100_initfn }, 2100 { .name = "sa1110", .initfn = sa1110_initfn }, 2101 { .name = "pxa250", .initfn = pxa250_initfn }, 2102 { .name = "pxa255", .initfn = pxa255_initfn }, 2103 { .name = "pxa260", .initfn = pxa260_initfn }, 2104 { .name = "pxa261", .initfn = pxa261_initfn }, 2105 { .name = "pxa262", .initfn = pxa262_initfn }, 2106 /* "pxa270" is an alias for "pxa270-a0" */ 2107 { .name = "pxa270", .initfn = pxa270a0_initfn }, 2108 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 2109 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 2110 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 2111 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 2112 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 2113 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 2114 #ifndef TARGET_AARCH64 2115 { .name = "max", .initfn = arm_max_initfn }, 2116 #endif 2117 #ifdef CONFIG_USER_ONLY 2118 { .name = "any", .initfn = arm_max_initfn }, 2119 #endif 2120 #endif 2121 { .name = NULL } 2122 }; 2123 2124 static Property arm_cpu_properties[] = { 2125 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 2126 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 2127 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 2128 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2129 mp_affinity, ARM64_AFFINITY_INVALID), 2130 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2131 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2132 DEFINE_PROP_END_OF_LIST() 2133 }; 2134 2135 static gchar *arm_gdb_arch_name(CPUState *cs) 2136 { 2137 ARMCPU *cpu = ARM_CPU(cs); 2138 CPUARMState *env = &cpu->env; 2139 2140 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2141 return g_strdup("iwmmxt"); 2142 } 2143 return g_strdup("arm"); 2144 } 2145 2146 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2147 { 2148 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2149 CPUClass *cc = CPU_CLASS(acc); 2150 DeviceClass *dc = DEVICE_CLASS(oc); 2151 2152 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2153 &acc->parent_realize); 2154 dc->props = arm_cpu_properties; 2155 2156 acc->parent_reset = cc->reset; 2157 cc->reset = arm_cpu_reset; 2158 2159 cc->class_by_name = arm_cpu_class_by_name; 2160 cc->has_work = arm_cpu_has_work; 2161 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 2162 cc->dump_state = arm_cpu_dump_state; 2163 cc->set_pc = arm_cpu_set_pc; 2164 cc->synchronize_from_tb = arm_cpu_synchronize_from_tb; 2165 cc->gdb_read_register = arm_cpu_gdb_read_register; 2166 cc->gdb_write_register = arm_cpu_gdb_write_register; 2167 #ifndef CONFIG_USER_ONLY 2168 cc->do_interrupt = arm_cpu_do_interrupt; 2169 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 2170 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 2171 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 2172 cc->asidx_from_attrs = arm_asidx_from_attrs; 2173 cc->vmsd = &vmstate_arm_cpu; 2174 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 2175 cc->write_elf64_note = arm_cpu_write_elf64_note; 2176 cc->write_elf32_note = arm_cpu_write_elf32_note; 2177 #endif 2178 cc->gdb_num_core_regs = 26; 2179 cc->gdb_core_xml_file = "arm-core.xml"; 2180 cc->gdb_arch_name = arm_gdb_arch_name; 2181 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2182 cc->gdb_stop_before_watchpoint = true; 2183 cc->debug_excp_handler = arm_debug_excp_handler; 2184 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 2185 #if !defined(CONFIG_USER_ONLY) 2186 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 2187 #endif 2188 2189 cc->disas_set_info = arm_disas_set_info; 2190 #ifdef CONFIG_TCG 2191 cc->tcg_initialize = arm_translate_init; 2192 cc->tlb_fill = arm_cpu_tlb_fill; 2193 #endif 2194 } 2195 2196 #ifdef CONFIG_KVM 2197 static void arm_host_initfn(Object *obj) 2198 { 2199 ARMCPU *cpu = ARM_CPU(obj); 2200 2201 kvm_arm_set_cpu_features_from_host(cpu); 2202 arm_cpu_post_init(obj); 2203 } 2204 2205 static const TypeInfo host_arm_cpu_type_info = { 2206 .name = TYPE_ARM_HOST_CPU, 2207 #ifdef TARGET_AARCH64 2208 .parent = TYPE_AARCH64_CPU, 2209 #else 2210 .parent = TYPE_ARM_CPU, 2211 #endif 2212 .instance_init = arm_host_initfn, 2213 }; 2214 2215 #endif 2216 2217 static void arm_cpu_instance_init(Object *obj) 2218 { 2219 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2220 2221 acc->info->initfn(obj); 2222 arm_cpu_post_init(obj); 2223 } 2224 2225 static void cpu_register_class_init(ObjectClass *oc, void *data) 2226 { 2227 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2228 2229 acc->info = data; 2230 } 2231 2232 static void cpu_register(const ARMCPUInfo *info) 2233 { 2234 TypeInfo type_info = { 2235 .parent = TYPE_ARM_CPU, 2236 .instance_size = sizeof(ARMCPU), 2237 .instance_init = arm_cpu_instance_init, 2238 .class_size = sizeof(ARMCPUClass), 2239 .class_init = info->class_init ?: cpu_register_class_init, 2240 .class_data = (void *)info, 2241 }; 2242 2243 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2244 type_register(&type_info); 2245 g_free((void *)type_info.name); 2246 } 2247 2248 static const TypeInfo arm_cpu_type_info = { 2249 .name = TYPE_ARM_CPU, 2250 .parent = TYPE_CPU, 2251 .instance_size = sizeof(ARMCPU), 2252 .instance_init = arm_cpu_initfn, 2253 .instance_finalize = arm_cpu_finalizefn, 2254 .abstract = true, 2255 .class_size = sizeof(ARMCPUClass), 2256 .class_init = arm_cpu_class_init, 2257 }; 2258 2259 static const TypeInfo idau_interface_type_info = { 2260 .name = TYPE_IDAU_INTERFACE, 2261 .parent = TYPE_INTERFACE, 2262 .class_size = sizeof(IDAUInterfaceClass), 2263 }; 2264 2265 static void arm_cpu_register_types(void) 2266 { 2267 const ARMCPUInfo *info = arm_cpus; 2268 2269 type_register_static(&arm_cpu_type_info); 2270 type_register_static(&idau_interface_type_info); 2271 2272 while (info->name) { 2273 cpu_register(info); 2274 info++; 2275 } 2276 2277 #ifdef CONFIG_KVM 2278 type_register_static(&host_arm_cpu_type_info); 2279 #endif 2280 } 2281 2282 type_init(arm_cpu_register_types) 2283