1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "target/arm/idau.h" 23 #include "qemu/error-report.h" 24 #include "qapi/error.h" 25 #include "cpu.h" 26 #include "internals.h" 27 #include "qemu-common.h" 28 #include "exec/exec-all.h" 29 #include "hw/qdev-properties.h" 30 #if !defined(CONFIG_USER_ONLY) 31 #include "hw/loader.h" 32 #endif 33 #include "hw/arm/arm.h" 34 #include "sysemu/sysemu.h" 35 #include "sysemu/hw_accel.h" 36 #include "kvm_arm.h" 37 #include "disas/capstone.h" 38 #include "fpu/softfloat.h" 39 40 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 41 { 42 ARMCPU *cpu = ARM_CPU(cs); 43 44 cpu->env.regs[15] = value; 45 } 46 47 static bool arm_cpu_has_work(CPUState *cs) 48 { 49 ARMCPU *cpu = ARM_CPU(cs); 50 51 return (cpu->power_state != PSCI_OFF) 52 && cs->interrupt_request & 53 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 54 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 55 | CPU_INTERRUPT_EXITTB); 56 } 57 58 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 59 void *opaque) 60 { 61 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 62 63 entry->hook = hook; 64 entry->opaque = opaque; 65 66 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 67 } 68 69 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 70 void *opaque) 71 { 72 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 73 74 entry->hook = hook; 75 entry->opaque = opaque; 76 77 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 78 } 79 80 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 81 { 82 /* Reset a single ARMCPRegInfo register */ 83 ARMCPRegInfo *ri = value; 84 ARMCPU *cpu = opaque; 85 86 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 87 return; 88 } 89 90 if (ri->resetfn) { 91 ri->resetfn(&cpu->env, ri); 92 return; 93 } 94 95 /* A zero offset is never possible as it would be regs[0] 96 * so we use it to indicate that reset is being handled elsewhere. 97 * This is basically only used for fields in non-core coprocessors 98 * (like the pxa2xx ones). 99 */ 100 if (!ri->fieldoffset) { 101 return; 102 } 103 104 if (cpreg_field_is_64bit(ri)) { 105 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 106 } else { 107 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 108 } 109 } 110 111 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 112 { 113 /* Purely an assertion check: we've already done reset once, 114 * so now check that running the reset for the cpreg doesn't 115 * change its value. This traps bugs where two different cpregs 116 * both try to reset the same state field but to different values. 117 */ 118 ARMCPRegInfo *ri = value; 119 ARMCPU *cpu = opaque; 120 uint64_t oldvalue, newvalue; 121 122 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 123 return; 124 } 125 126 oldvalue = read_raw_cp_reg(&cpu->env, ri); 127 cp_reg_reset(key, value, opaque); 128 newvalue = read_raw_cp_reg(&cpu->env, ri); 129 assert(oldvalue == newvalue); 130 } 131 132 /* CPUClass::reset() */ 133 static void arm_cpu_reset(CPUState *s) 134 { 135 ARMCPU *cpu = ARM_CPU(s); 136 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 137 CPUARMState *env = &cpu->env; 138 139 acc->parent_reset(s); 140 141 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 142 143 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 144 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 145 146 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 147 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 148 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 149 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 150 151 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 152 s->halted = cpu->start_powered_off; 153 154 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 155 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 156 } 157 158 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 159 /* 64 bit CPUs always start in 64 bit mode */ 160 env->aarch64 = 1; 161 #if defined(CONFIG_USER_ONLY) 162 env->pstate = PSTATE_MODE_EL0t; 163 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 164 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 165 /* and to the FP/Neon instructions */ 166 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 167 /* and to the SVE instructions */ 168 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 169 env->cp15.cptr_el[3] |= CPTR_EZ; 170 /* with maximum vector length */ 171 env->vfp.zcr_el[1] = cpu->sve_max_vq - 1; 172 env->vfp.zcr_el[2] = env->vfp.zcr_el[1]; 173 env->vfp.zcr_el[3] = env->vfp.zcr_el[1]; 174 #else 175 /* Reset into the highest available EL */ 176 if (arm_feature(env, ARM_FEATURE_EL3)) { 177 env->pstate = PSTATE_MODE_EL3h; 178 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 179 env->pstate = PSTATE_MODE_EL2h; 180 } else { 181 env->pstate = PSTATE_MODE_EL1h; 182 } 183 env->pc = cpu->rvbar; 184 #endif 185 } else { 186 #if defined(CONFIG_USER_ONLY) 187 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 188 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 189 #endif 190 } 191 192 #if defined(CONFIG_USER_ONLY) 193 env->uncached_cpsr = ARM_CPU_MODE_USR; 194 /* For user mode we must enable access to coprocessors */ 195 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 196 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 197 env->cp15.c15_cpar = 3; 198 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 199 env->cp15.c15_cpar = 1; 200 } 201 #else 202 203 /* 204 * If the highest available EL is EL2, AArch32 will start in Hyp 205 * mode; otherwise it starts in SVC. Note that if we start in 206 * AArch64 then these values in the uncached_cpsr will be ignored. 207 */ 208 if (arm_feature(env, ARM_FEATURE_EL2) && 209 !arm_feature(env, ARM_FEATURE_EL3)) { 210 env->uncached_cpsr = ARM_CPU_MODE_HYP; 211 } else { 212 env->uncached_cpsr = ARM_CPU_MODE_SVC; 213 } 214 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 215 216 if (arm_feature(env, ARM_FEATURE_M)) { 217 uint32_t initial_msp; /* Loaded from 0x0 */ 218 uint32_t initial_pc; /* Loaded from 0x4 */ 219 uint8_t *rom; 220 uint32_t vecbase; 221 222 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 223 env->v7m.secure = true; 224 } else { 225 /* This bit resets to 0 if security is supported, but 1 if 226 * it is not. The bit is not present in v7M, but we set it 227 * here so we can avoid having to make checks on it conditional 228 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 229 */ 230 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 231 } 232 233 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 234 * that it resets to 1, so QEMU always does that rather than making 235 * it dependent on CPU model. In v8M it is RES1. 236 */ 237 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 238 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 239 if (arm_feature(env, ARM_FEATURE_V8)) { 240 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 241 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 242 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 243 } 244 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 245 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 246 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 247 } 248 249 /* Unlike A/R profile, M profile defines the reset LR value */ 250 env->regs[14] = 0xffffffff; 251 252 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 253 254 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 255 vecbase = env->v7m.vecbase[env->v7m.secure]; 256 rom = rom_ptr(vecbase, 8); 257 if (rom) { 258 /* Address zero is covered by ROM which hasn't yet been 259 * copied into physical memory. 260 */ 261 initial_msp = ldl_p(rom); 262 initial_pc = ldl_p(rom + 4); 263 } else { 264 /* Address zero not covered by a ROM blob, or the ROM blob 265 * is in non-modifiable memory and this is a second reset after 266 * it got copied into memory. In the latter case, rom_ptr 267 * will return a NULL pointer and we should use ldl_phys instead. 268 */ 269 initial_msp = ldl_phys(s->as, vecbase); 270 initial_pc = ldl_phys(s->as, vecbase + 4); 271 } 272 273 env->regs[13] = initial_msp & 0xFFFFFFFC; 274 env->regs[15] = initial_pc & ~1; 275 env->thumb = initial_pc & 1; 276 } 277 278 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 279 * executing as AArch32 then check if highvecs are enabled and 280 * adjust the PC accordingly. 281 */ 282 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 283 env->regs[15] = 0xFFFF0000; 284 } 285 286 /* M profile requires that reset clears the exclusive monitor; 287 * A profile does not, but clearing it makes more sense than having it 288 * set with an exclusive access on address zero. 289 */ 290 arm_clear_exclusive(env); 291 292 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 293 #endif 294 295 if (arm_feature(env, ARM_FEATURE_PMSA)) { 296 if (cpu->pmsav7_dregion > 0) { 297 if (arm_feature(env, ARM_FEATURE_V8)) { 298 memset(env->pmsav8.rbar[M_REG_NS], 0, 299 sizeof(*env->pmsav8.rbar[M_REG_NS]) 300 * cpu->pmsav7_dregion); 301 memset(env->pmsav8.rlar[M_REG_NS], 0, 302 sizeof(*env->pmsav8.rlar[M_REG_NS]) 303 * cpu->pmsav7_dregion); 304 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 305 memset(env->pmsav8.rbar[M_REG_S], 0, 306 sizeof(*env->pmsav8.rbar[M_REG_S]) 307 * cpu->pmsav7_dregion); 308 memset(env->pmsav8.rlar[M_REG_S], 0, 309 sizeof(*env->pmsav8.rlar[M_REG_S]) 310 * cpu->pmsav7_dregion); 311 } 312 } else if (arm_feature(env, ARM_FEATURE_V7)) { 313 memset(env->pmsav7.drbar, 0, 314 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 315 memset(env->pmsav7.drsr, 0, 316 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 317 memset(env->pmsav7.dracr, 0, 318 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 319 } 320 } 321 env->pmsav7.rnr[M_REG_NS] = 0; 322 env->pmsav7.rnr[M_REG_S] = 0; 323 env->pmsav8.mair0[M_REG_NS] = 0; 324 env->pmsav8.mair0[M_REG_S] = 0; 325 env->pmsav8.mair1[M_REG_NS] = 0; 326 env->pmsav8.mair1[M_REG_S] = 0; 327 } 328 329 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 330 if (cpu->sau_sregion > 0) { 331 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 332 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 333 } 334 env->sau.rnr = 0; 335 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 336 * the Cortex-M33 does. 337 */ 338 env->sau.ctrl = 0; 339 } 340 341 set_flush_to_zero(1, &env->vfp.standard_fp_status); 342 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 343 set_default_nan_mode(1, &env->vfp.standard_fp_status); 344 set_float_detect_tininess(float_tininess_before_rounding, 345 &env->vfp.fp_status); 346 set_float_detect_tininess(float_tininess_before_rounding, 347 &env->vfp.standard_fp_status); 348 set_float_detect_tininess(float_tininess_before_rounding, 349 &env->vfp.fp_status_f16); 350 #ifndef CONFIG_USER_ONLY 351 if (kvm_enabled()) { 352 kvm_arm_reset_vcpu(cpu); 353 } 354 #endif 355 356 hw_breakpoint_update_all(cpu); 357 hw_watchpoint_update_all(cpu); 358 } 359 360 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 361 { 362 CPUClass *cc = CPU_GET_CLASS(cs); 363 CPUARMState *env = cs->env_ptr; 364 uint32_t cur_el = arm_current_el(env); 365 bool secure = arm_is_secure(env); 366 uint32_t target_el; 367 uint32_t excp_idx; 368 bool ret = false; 369 370 if (interrupt_request & CPU_INTERRUPT_FIQ) { 371 excp_idx = EXCP_FIQ; 372 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 373 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 374 cs->exception_index = excp_idx; 375 env->exception.target_el = target_el; 376 cc->do_interrupt(cs); 377 ret = true; 378 } 379 } 380 if (interrupt_request & CPU_INTERRUPT_HARD) { 381 excp_idx = EXCP_IRQ; 382 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 383 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 384 cs->exception_index = excp_idx; 385 env->exception.target_el = target_el; 386 cc->do_interrupt(cs); 387 ret = true; 388 } 389 } 390 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 391 excp_idx = EXCP_VIRQ; 392 target_el = 1; 393 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 394 cs->exception_index = excp_idx; 395 env->exception.target_el = target_el; 396 cc->do_interrupt(cs); 397 ret = true; 398 } 399 } 400 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 401 excp_idx = EXCP_VFIQ; 402 target_el = 1; 403 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 404 cs->exception_index = excp_idx; 405 env->exception.target_el = target_el; 406 cc->do_interrupt(cs); 407 ret = true; 408 } 409 } 410 411 return ret; 412 } 413 414 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 415 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 416 { 417 CPUClass *cc = CPU_GET_CLASS(cs); 418 ARMCPU *cpu = ARM_CPU(cs); 419 CPUARMState *env = &cpu->env; 420 bool ret = false; 421 422 /* ARMv7-M interrupt masking works differently than -A or -R. 423 * There is no FIQ/IRQ distinction. Instead of I and F bits 424 * masking FIQ and IRQ interrupts, an exception is taken only 425 * if it is higher priority than the current execution priority 426 * (which depends on state like BASEPRI, FAULTMASK and the 427 * currently active exception). 428 */ 429 if (interrupt_request & CPU_INTERRUPT_HARD 430 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 431 cs->exception_index = EXCP_IRQ; 432 cc->do_interrupt(cs); 433 ret = true; 434 } 435 return ret; 436 } 437 #endif 438 439 #ifndef CONFIG_USER_ONLY 440 static void arm_cpu_set_irq(void *opaque, int irq, int level) 441 { 442 ARMCPU *cpu = opaque; 443 CPUARMState *env = &cpu->env; 444 CPUState *cs = CPU(cpu); 445 static const int mask[] = { 446 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 447 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 448 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 449 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 450 }; 451 452 switch (irq) { 453 case ARM_CPU_VIRQ: 454 case ARM_CPU_VFIQ: 455 assert(arm_feature(env, ARM_FEATURE_EL2)); 456 /* fall through */ 457 case ARM_CPU_IRQ: 458 case ARM_CPU_FIQ: 459 if (level) { 460 cpu_interrupt(cs, mask[irq]); 461 } else { 462 cpu_reset_interrupt(cs, mask[irq]); 463 } 464 break; 465 default: 466 g_assert_not_reached(); 467 } 468 } 469 470 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 471 { 472 #ifdef CONFIG_KVM 473 ARMCPU *cpu = opaque; 474 CPUState *cs = CPU(cpu); 475 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 476 477 switch (irq) { 478 case ARM_CPU_IRQ: 479 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 480 break; 481 case ARM_CPU_FIQ: 482 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 483 break; 484 default: 485 g_assert_not_reached(); 486 } 487 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 488 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 489 #endif 490 } 491 492 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 493 { 494 ARMCPU *cpu = ARM_CPU(cs); 495 CPUARMState *env = &cpu->env; 496 497 cpu_synchronize_state(cs); 498 return arm_cpu_data_is_big_endian(env); 499 } 500 501 #endif 502 503 static inline void set_feature(CPUARMState *env, int feature) 504 { 505 env->features |= 1ULL << feature; 506 } 507 508 static inline void unset_feature(CPUARMState *env, int feature) 509 { 510 env->features &= ~(1ULL << feature); 511 } 512 513 static int 514 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 515 { 516 return print_insn_arm(pc | 1, info); 517 } 518 519 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 520 { 521 ARMCPU *ac = ARM_CPU(cpu); 522 CPUARMState *env = &ac->env; 523 bool sctlr_b; 524 525 if (is_a64(env)) { 526 /* We might not be compiled with the A64 disassembler 527 * because it needs a C++ compiler. Leave print_insn 528 * unset in this case to use the caller default behaviour. 529 */ 530 #if defined(CONFIG_ARM_A64_DIS) 531 info->print_insn = print_insn_arm_a64; 532 #endif 533 info->cap_arch = CS_ARCH_ARM64; 534 info->cap_insn_unit = 4; 535 info->cap_insn_split = 4; 536 } else { 537 int cap_mode; 538 if (env->thumb) { 539 info->print_insn = print_insn_thumb1; 540 info->cap_insn_unit = 2; 541 info->cap_insn_split = 4; 542 cap_mode = CS_MODE_THUMB; 543 } else { 544 info->print_insn = print_insn_arm; 545 info->cap_insn_unit = 4; 546 info->cap_insn_split = 4; 547 cap_mode = CS_MODE_ARM; 548 } 549 if (arm_feature(env, ARM_FEATURE_V8)) { 550 cap_mode |= CS_MODE_V8; 551 } 552 if (arm_feature(env, ARM_FEATURE_M)) { 553 cap_mode |= CS_MODE_MCLASS; 554 } 555 info->cap_arch = CS_ARCH_ARM; 556 info->cap_mode = cap_mode; 557 } 558 559 sctlr_b = arm_sctlr_b(env); 560 if (bswap_code(sctlr_b)) { 561 #ifdef TARGET_WORDS_BIGENDIAN 562 info->endian = BFD_ENDIAN_LITTLE; 563 #else 564 info->endian = BFD_ENDIAN_BIG; 565 #endif 566 } 567 info->flags &= ~INSN_ARM_BE32; 568 #ifndef CONFIG_USER_ONLY 569 if (sctlr_b) { 570 info->flags |= INSN_ARM_BE32; 571 } 572 #endif 573 } 574 575 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 576 { 577 uint32_t Aff1 = idx / clustersz; 578 uint32_t Aff0 = idx % clustersz; 579 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 580 } 581 582 static void arm_cpu_initfn(Object *obj) 583 { 584 CPUState *cs = CPU(obj); 585 ARMCPU *cpu = ARM_CPU(obj); 586 587 cs->env_ptr = &cpu->env; 588 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 589 g_free, g_free); 590 591 QLIST_INIT(&cpu->pre_el_change_hooks); 592 QLIST_INIT(&cpu->el_change_hooks); 593 594 #ifndef CONFIG_USER_ONLY 595 /* Our inbound IRQ and FIQ lines */ 596 if (kvm_enabled()) { 597 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 598 * the same interface as non-KVM CPUs. 599 */ 600 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 601 } else { 602 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 603 } 604 605 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 606 arm_gt_ptimer_cb, cpu); 607 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 608 arm_gt_vtimer_cb, cpu); 609 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 610 arm_gt_htimer_cb, cpu); 611 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 612 arm_gt_stimer_cb, cpu); 613 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 614 ARRAY_SIZE(cpu->gt_timer_outputs)); 615 616 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 617 "gicv3-maintenance-interrupt", 1); 618 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 619 "pmu-interrupt", 1); 620 #endif 621 622 /* DTB consumers generally don't in fact care what the 'compatible' 623 * string is, so always provide some string and trust that a hypothetical 624 * picky DTB consumer will also provide a helpful error message. 625 */ 626 cpu->dtb_compatible = "qemu,unknown"; 627 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 628 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 629 630 if (tcg_enabled()) { 631 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 632 } 633 } 634 635 static Property arm_cpu_reset_cbar_property = 636 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 637 638 static Property arm_cpu_reset_hivecs_property = 639 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 640 641 static Property arm_cpu_rvbar_property = 642 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 643 644 static Property arm_cpu_has_el2_property = 645 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 646 647 static Property arm_cpu_has_el3_property = 648 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 649 650 static Property arm_cpu_cfgend_property = 651 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 652 653 /* use property name "pmu" to match other archs and virt tools */ 654 static Property arm_cpu_has_pmu_property = 655 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 656 657 static Property arm_cpu_has_mpu_property = 658 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 659 660 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 661 * because the CPU initfn will have already set cpu->pmsav7_dregion to 662 * the right value for that particular CPU type, and we don't want 663 * to override that with an incorrect constant value. 664 */ 665 static Property arm_cpu_pmsav7_dregion_property = 666 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 667 pmsav7_dregion, 668 qdev_prop_uint32, uint32_t); 669 670 /* M profile: initial value of the Secure VTOR */ 671 static Property arm_cpu_initsvtor_property = 672 DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0); 673 674 static void arm_cpu_post_init(Object *obj) 675 { 676 ARMCPU *cpu = ARM_CPU(obj); 677 678 /* M profile implies PMSA. We have to do this here rather than 679 * in realize with the other feature-implication checks because 680 * we look at the PMSA bit to see if we should add some properties. 681 */ 682 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 683 set_feature(&cpu->env, ARM_FEATURE_PMSA); 684 } 685 686 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 687 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 688 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 689 &error_abort); 690 } 691 692 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 693 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 694 &error_abort); 695 } 696 697 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 698 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 699 &error_abort); 700 } 701 702 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 703 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 704 * prevent "has_el3" from existing on CPUs which cannot support EL3. 705 */ 706 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 707 &error_abort); 708 709 #ifndef CONFIG_USER_ONLY 710 object_property_add_link(obj, "secure-memory", 711 TYPE_MEMORY_REGION, 712 (Object **)&cpu->secure_memory, 713 qdev_prop_allow_set_link_before_realize, 714 OBJ_PROP_LINK_STRONG, 715 &error_abort); 716 #endif 717 } 718 719 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 720 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 721 &error_abort); 722 } 723 724 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 725 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 726 &error_abort); 727 } 728 729 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 730 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 731 &error_abort); 732 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 733 qdev_property_add_static(DEVICE(obj), 734 &arm_cpu_pmsav7_dregion_property, 735 &error_abort); 736 } 737 } 738 739 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 740 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 741 qdev_prop_allow_set_link_before_realize, 742 OBJ_PROP_LINK_STRONG, 743 &error_abort); 744 qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property, 745 &error_abort); 746 } 747 748 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 749 &error_abort); 750 } 751 752 static void arm_cpu_finalizefn(Object *obj) 753 { 754 ARMCPU *cpu = ARM_CPU(obj); 755 ARMELChangeHook *hook, *next; 756 757 g_hash_table_destroy(cpu->cp_regs); 758 759 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 760 QLIST_REMOVE(hook, node); 761 g_free(hook); 762 } 763 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 764 QLIST_REMOVE(hook, node); 765 g_free(hook); 766 } 767 } 768 769 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 770 { 771 CPUState *cs = CPU(dev); 772 ARMCPU *cpu = ARM_CPU(dev); 773 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 774 CPUARMState *env = &cpu->env; 775 int pagebits; 776 Error *local_err = NULL; 777 bool no_aa32 = false; 778 779 /* If we needed to query the host kernel for the CPU features 780 * then it's possible that might have failed in the initfn, but 781 * this is the first point where we can report it. 782 */ 783 if (cpu->host_cpu_probe_failed) { 784 if (!kvm_enabled()) { 785 error_setg(errp, "The 'host' CPU type can only be used with KVM"); 786 } else { 787 error_setg(errp, "Failed to retrieve host CPU features"); 788 } 789 return; 790 } 791 792 #ifndef CONFIG_USER_ONLY 793 /* The NVIC and M-profile CPU are two halves of a single piece of 794 * hardware; trying to use one without the other is a command line 795 * error and will result in segfaults if not caught here. 796 */ 797 if (arm_feature(env, ARM_FEATURE_M)) { 798 if (!env->nvic) { 799 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 800 return; 801 } 802 } else { 803 if (env->nvic) { 804 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 805 return; 806 } 807 } 808 #endif 809 810 cpu_exec_realizefn(cs, &local_err); 811 if (local_err != NULL) { 812 error_propagate(errp, local_err); 813 return; 814 } 815 816 /* Some features automatically imply others: */ 817 if (arm_feature(env, ARM_FEATURE_V8)) { 818 if (arm_feature(env, ARM_FEATURE_M)) { 819 set_feature(env, ARM_FEATURE_V7); 820 } else { 821 set_feature(env, ARM_FEATURE_V7VE); 822 } 823 } 824 825 /* 826 * There exist AArch64 cpus without AArch32 support. When KVM 827 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 828 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 829 */ 830 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 831 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 832 } 833 834 if (arm_feature(env, ARM_FEATURE_V7VE)) { 835 /* v7 Virtualization Extensions. In real hardware this implies 836 * EL2 and also the presence of the Security Extensions. 837 * For QEMU, for backwards-compatibility we implement some 838 * CPUs or CPU configs which have no actual EL2 or EL3 but do 839 * include the various other features that V7VE implies. 840 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 841 * Security Extensions is ARM_FEATURE_EL3. 842 */ 843 assert(no_aa32 || cpu_isar_feature(arm_div, cpu)); 844 set_feature(env, ARM_FEATURE_LPAE); 845 set_feature(env, ARM_FEATURE_V7); 846 } 847 if (arm_feature(env, ARM_FEATURE_V7)) { 848 set_feature(env, ARM_FEATURE_VAPA); 849 set_feature(env, ARM_FEATURE_THUMB2); 850 set_feature(env, ARM_FEATURE_MPIDR); 851 if (!arm_feature(env, ARM_FEATURE_M)) { 852 set_feature(env, ARM_FEATURE_V6K); 853 } else { 854 set_feature(env, ARM_FEATURE_V6); 855 } 856 857 /* Always define VBAR for V7 CPUs even if it doesn't exist in 858 * non-EL3 configs. This is needed by some legacy boards. 859 */ 860 set_feature(env, ARM_FEATURE_VBAR); 861 } 862 if (arm_feature(env, ARM_FEATURE_V6K)) { 863 set_feature(env, ARM_FEATURE_V6); 864 set_feature(env, ARM_FEATURE_MVFR); 865 } 866 if (arm_feature(env, ARM_FEATURE_V6)) { 867 set_feature(env, ARM_FEATURE_V5); 868 if (!arm_feature(env, ARM_FEATURE_M)) { 869 assert(no_aa32 || cpu_isar_feature(jazelle, cpu)); 870 set_feature(env, ARM_FEATURE_AUXCR); 871 } 872 } 873 if (arm_feature(env, ARM_FEATURE_V5)) { 874 set_feature(env, ARM_FEATURE_V4T); 875 } 876 if (arm_feature(env, ARM_FEATURE_VFP4)) { 877 set_feature(env, ARM_FEATURE_VFP3); 878 set_feature(env, ARM_FEATURE_VFP_FP16); 879 } 880 if (arm_feature(env, ARM_FEATURE_VFP3)) { 881 set_feature(env, ARM_FEATURE_VFP); 882 } 883 if (arm_feature(env, ARM_FEATURE_LPAE)) { 884 set_feature(env, ARM_FEATURE_V7MP); 885 set_feature(env, ARM_FEATURE_PXN); 886 } 887 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 888 set_feature(env, ARM_FEATURE_CBAR); 889 } 890 if (arm_feature(env, ARM_FEATURE_THUMB2) && 891 !arm_feature(env, ARM_FEATURE_M)) { 892 set_feature(env, ARM_FEATURE_THUMB_DSP); 893 } 894 895 if (arm_feature(env, ARM_FEATURE_V7) && 896 !arm_feature(env, ARM_FEATURE_M) && 897 !arm_feature(env, ARM_FEATURE_PMSA)) { 898 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 899 * can use 4K pages. 900 */ 901 pagebits = 12; 902 } else { 903 /* For CPUs which might have tiny 1K pages, or which have an 904 * MPU and might have small region sizes, stick with 1K pages. 905 */ 906 pagebits = 10; 907 } 908 if (!set_preferred_target_page_bits(pagebits)) { 909 /* This can only ever happen for hotplugging a CPU, or if 910 * the board code incorrectly creates a CPU which it has 911 * promised via minimum_page_size that it will not. 912 */ 913 error_setg(errp, "This CPU requires a smaller page size than the " 914 "system is using"); 915 return; 916 } 917 918 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 919 * We don't support setting cluster ID ([16..23]) (known as Aff2 920 * in later ARM ARM versions), or any of the higher affinity level fields, 921 * so these bits always RAZ. 922 */ 923 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 924 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 925 ARM_DEFAULT_CPUS_PER_CLUSTER); 926 } 927 928 if (cpu->reset_hivecs) { 929 cpu->reset_sctlr |= (1 << 13); 930 } 931 932 if (cpu->cfgend) { 933 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 934 cpu->reset_sctlr |= SCTLR_EE; 935 } else { 936 cpu->reset_sctlr |= SCTLR_B; 937 } 938 } 939 940 if (!cpu->has_el3) { 941 /* If the has_el3 CPU property is disabled then we need to disable the 942 * feature. 943 */ 944 unset_feature(env, ARM_FEATURE_EL3); 945 946 /* Disable the security extension feature bits in the processor feature 947 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 948 */ 949 cpu->id_pfr1 &= ~0xf0; 950 cpu->isar.id_aa64pfr0 &= ~0xf000; 951 } 952 953 if (!cpu->has_el2) { 954 unset_feature(env, ARM_FEATURE_EL2); 955 } 956 957 if (!cpu->has_pmu) { 958 unset_feature(env, ARM_FEATURE_PMU); 959 cpu->id_aa64dfr0 &= ~0xf00; 960 } 961 962 if (!arm_feature(env, ARM_FEATURE_EL2)) { 963 /* Disable the hypervisor feature bits in the processor feature 964 * registers if we don't have EL2. These are id_pfr1[15:12] and 965 * id_aa64pfr0_el1[11:8]. 966 */ 967 cpu->isar.id_aa64pfr0 &= ~0xf00; 968 cpu->id_pfr1 &= ~0xf000; 969 } 970 971 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 972 * to false or by setting pmsav7-dregion to 0. 973 */ 974 if (!cpu->has_mpu) { 975 cpu->pmsav7_dregion = 0; 976 } 977 if (cpu->pmsav7_dregion == 0) { 978 cpu->has_mpu = false; 979 } 980 981 if (arm_feature(env, ARM_FEATURE_PMSA) && 982 arm_feature(env, ARM_FEATURE_V7)) { 983 uint32_t nr = cpu->pmsav7_dregion; 984 985 if (nr > 0xff) { 986 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 987 return; 988 } 989 990 if (nr) { 991 if (arm_feature(env, ARM_FEATURE_V8)) { 992 /* PMSAv8 */ 993 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 994 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 995 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 996 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 997 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 998 } 999 } else { 1000 env->pmsav7.drbar = g_new0(uint32_t, nr); 1001 env->pmsav7.drsr = g_new0(uint32_t, nr); 1002 env->pmsav7.dracr = g_new0(uint32_t, nr); 1003 } 1004 } 1005 } 1006 1007 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1008 uint32_t nr = cpu->sau_sregion; 1009 1010 if (nr > 0xff) { 1011 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1012 return; 1013 } 1014 1015 if (nr) { 1016 env->sau.rbar = g_new0(uint32_t, nr); 1017 env->sau.rlar = g_new0(uint32_t, nr); 1018 } 1019 } 1020 1021 if (arm_feature(env, ARM_FEATURE_EL3)) { 1022 set_feature(env, ARM_FEATURE_VBAR); 1023 } 1024 1025 register_cp_regs_for_features(cpu); 1026 arm_cpu_register_gdb_regs_for_features(cpu); 1027 1028 init_cpreg_list(cpu); 1029 1030 #ifndef CONFIG_USER_ONLY 1031 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1032 cs->num_ases = 2; 1033 1034 if (!cpu->secure_memory) { 1035 cpu->secure_memory = cs->memory; 1036 } 1037 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1038 cpu->secure_memory); 1039 } else { 1040 cs->num_ases = 1; 1041 } 1042 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1043 1044 /* No core_count specified, default to smp_cpus. */ 1045 if (cpu->core_count == -1) { 1046 cpu->core_count = smp_cpus; 1047 } 1048 #endif 1049 1050 qemu_init_vcpu(cs); 1051 cpu_reset(cs); 1052 1053 acc->parent_realize(dev, errp); 1054 } 1055 1056 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1057 { 1058 ObjectClass *oc; 1059 char *typename; 1060 char **cpuname; 1061 const char *cpunamestr; 1062 1063 cpuname = g_strsplit(cpu_model, ",", 1); 1064 cpunamestr = cpuname[0]; 1065 #ifdef CONFIG_USER_ONLY 1066 /* For backwards compatibility usermode emulation allows "-cpu any", 1067 * which has the same semantics as "-cpu max". 1068 */ 1069 if (!strcmp(cpunamestr, "any")) { 1070 cpunamestr = "max"; 1071 } 1072 #endif 1073 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 1074 oc = object_class_by_name(typename); 1075 g_strfreev(cpuname); 1076 g_free(typename); 1077 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 1078 object_class_is_abstract(oc)) { 1079 return NULL; 1080 } 1081 return oc; 1082 } 1083 1084 /* CPU models. These are not needed for the AArch64 linux-user build. */ 1085 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1086 1087 static void arm926_initfn(Object *obj) 1088 { 1089 ARMCPU *cpu = ARM_CPU(obj); 1090 1091 cpu->dtb_compatible = "arm,arm926"; 1092 set_feature(&cpu->env, ARM_FEATURE_V5); 1093 set_feature(&cpu->env, ARM_FEATURE_VFP); 1094 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1095 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1096 cpu->midr = 0x41069265; 1097 cpu->reset_fpsid = 0x41011090; 1098 cpu->ctr = 0x1dd20d2; 1099 cpu->reset_sctlr = 0x00090078; 1100 1101 /* 1102 * ARMv5 does not have the ID_ISAR registers, but we can still 1103 * set the field to indicate Jazelle support within QEMU. 1104 */ 1105 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 1106 } 1107 1108 static void arm946_initfn(Object *obj) 1109 { 1110 ARMCPU *cpu = ARM_CPU(obj); 1111 1112 cpu->dtb_compatible = "arm,arm946"; 1113 set_feature(&cpu->env, ARM_FEATURE_V5); 1114 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1115 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1116 cpu->midr = 0x41059461; 1117 cpu->ctr = 0x0f004006; 1118 cpu->reset_sctlr = 0x00000078; 1119 } 1120 1121 static void arm1026_initfn(Object *obj) 1122 { 1123 ARMCPU *cpu = ARM_CPU(obj); 1124 1125 cpu->dtb_compatible = "arm,arm1026"; 1126 set_feature(&cpu->env, ARM_FEATURE_V5); 1127 set_feature(&cpu->env, ARM_FEATURE_VFP); 1128 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 1129 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1130 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1131 cpu->midr = 0x4106a262; 1132 cpu->reset_fpsid = 0x410110a0; 1133 cpu->ctr = 0x1dd20d2; 1134 cpu->reset_sctlr = 0x00090078; 1135 cpu->reset_auxcr = 1; 1136 1137 /* 1138 * ARMv5 does not have the ID_ISAR registers, but we can still 1139 * set the field to indicate Jazelle support within QEMU. 1140 */ 1141 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 1142 1143 { 1144 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 1145 ARMCPRegInfo ifar = { 1146 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 1147 .access = PL1_RW, 1148 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 1149 .resetvalue = 0 1150 }; 1151 define_one_arm_cp_reg(cpu, &ifar); 1152 } 1153 } 1154 1155 static void arm1136_r2_initfn(Object *obj) 1156 { 1157 ARMCPU *cpu = ARM_CPU(obj); 1158 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 1159 * older core than plain "arm1136". In particular this does not 1160 * have the v6K features. 1161 * These ID register values are correct for 1136 but may be wrong 1162 * for 1136_r2 (in particular r0p2 does not actually implement most 1163 * of the ID registers). 1164 */ 1165 1166 cpu->dtb_compatible = "arm,arm1136"; 1167 set_feature(&cpu->env, ARM_FEATURE_V6); 1168 set_feature(&cpu->env, ARM_FEATURE_VFP); 1169 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1170 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1171 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1172 cpu->midr = 0x4107b362; 1173 cpu->reset_fpsid = 0x410120b4; 1174 cpu->isar.mvfr0 = 0x11111111; 1175 cpu->isar.mvfr1 = 0x00000000; 1176 cpu->ctr = 0x1dd20d2; 1177 cpu->reset_sctlr = 0x00050078; 1178 cpu->id_pfr0 = 0x111; 1179 cpu->id_pfr1 = 0x1; 1180 cpu->id_dfr0 = 0x2; 1181 cpu->id_afr0 = 0x3; 1182 cpu->id_mmfr0 = 0x01130003; 1183 cpu->id_mmfr1 = 0x10030302; 1184 cpu->id_mmfr2 = 0x01222110; 1185 cpu->isar.id_isar0 = 0x00140011; 1186 cpu->isar.id_isar1 = 0x12002111; 1187 cpu->isar.id_isar2 = 0x11231111; 1188 cpu->isar.id_isar3 = 0x01102131; 1189 cpu->isar.id_isar4 = 0x141; 1190 cpu->reset_auxcr = 7; 1191 } 1192 1193 static void arm1136_initfn(Object *obj) 1194 { 1195 ARMCPU *cpu = ARM_CPU(obj); 1196 1197 cpu->dtb_compatible = "arm,arm1136"; 1198 set_feature(&cpu->env, ARM_FEATURE_V6K); 1199 set_feature(&cpu->env, ARM_FEATURE_V6); 1200 set_feature(&cpu->env, ARM_FEATURE_VFP); 1201 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1202 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1203 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1204 cpu->midr = 0x4117b363; 1205 cpu->reset_fpsid = 0x410120b4; 1206 cpu->isar.mvfr0 = 0x11111111; 1207 cpu->isar.mvfr1 = 0x00000000; 1208 cpu->ctr = 0x1dd20d2; 1209 cpu->reset_sctlr = 0x00050078; 1210 cpu->id_pfr0 = 0x111; 1211 cpu->id_pfr1 = 0x1; 1212 cpu->id_dfr0 = 0x2; 1213 cpu->id_afr0 = 0x3; 1214 cpu->id_mmfr0 = 0x01130003; 1215 cpu->id_mmfr1 = 0x10030302; 1216 cpu->id_mmfr2 = 0x01222110; 1217 cpu->isar.id_isar0 = 0x00140011; 1218 cpu->isar.id_isar1 = 0x12002111; 1219 cpu->isar.id_isar2 = 0x11231111; 1220 cpu->isar.id_isar3 = 0x01102131; 1221 cpu->isar.id_isar4 = 0x141; 1222 cpu->reset_auxcr = 7; 1223 } 1224 1225 static void arm1176_initfn(Object *obj) 1226 { 1227 ARMCPU *cpu = ARM_CPU(obj); 1228 1229 cpu->dtb_compatible = "arm,arm1176"; 1230 set_feature(&cpu->env, ARM_FEATURE_V6K); 1231 set_feature(&cpu->env, ARM_FEATURE_VFP); 1232 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1233 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1234 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1235 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1236 set_feature(&cpu->env, ARM_FEATURE_EL3); 1237 cpu->midr = 0x410fb767; 1238 cpu->reset_fpsid = 0x410120b5; 1239 cpu->isar.mvfr0 = 0x11111111; 1240 cpu->isar.mvfr1 = 0x00000000; 1241 cpu->ctr = 0x1dd20d2; 1242 cpu->reset_sctlr = 0x00050078; 1243 cpu->id_pfr0 = 0x111; 1244 cpu->id_pfr1 = 0x11; 1245 cpu->id_dfr0 = 0x33; 1246 cpu->id_afr0 = 0; 1247 cpu->id_mmfr0 = 0x01130003; 1248 cpu->id_mmfr1 = 0x10030302; 1249 cpu->id_mmfr2 = 0x01222100; 1250 cpu->isar.id_isar0 = 0x0140011; 1251 cpu->isar.id_isar1 = 0x12002111; 1252 cpu->isar.id_isar2 = 0x11231121; 1253 cpu->isar.id_isar3 = 0x01102131; 1254 cpu->isar.id_isar4 = 0x01141; 1255 cpu->reset_auxcr = 7; 1256 } 1257 1258 static void arm11mpcore_initfn(Object *obj) 1259 { 1260 ARMCPU *cpu = ARM_CPU(obj); 1261 1262 cpu->dtb_compatible = "arm,arm11mpcore"; 1263 set_feature(&cpu->env, ARM_FEATURE_V6K); 1264 set_feature(&cpu->env, ARM_FEATURE_VFP); 1265 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1266 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1267 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1268 cpu->midr = 0x410fb022; 1269 cpu->reset_fpsid = 0x410120b4; 1270 cpu->isar.mvfr0 = 0x11111111; 1271 cpu->isar.mvfr1 = 0x00000000; 1272 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1273 cpu->id_pfr0 = 0x111; 1274 cpu->id_pfr1 = 0x1; 1275 cpu->id_dfr0 = 0; 1276 cpu->id_afr0 = 0x2; 1277 cpu->id_mmfr0 = 0x01100103; 1278 cpu->id_mmfr1 = 0x10020302; 1279 cpu->id_mmfr2 = 0x01222000; 1280 cpu->isar.id_isar0 = 0x00100011; 1281 cpu->isar.id_isar1 = 0x12002111; 1282 cpu->isar.id_isar2 = 0x11221011; 1283 cpu->isar.id_isar3 = 0x01102131; 1284 cpu->isar.id_isar4 = 0x141; 1285 cpu->reset_auxcr = 1; 1286 } 1287 1288 static void cortex_m0_initfn(Object *obj) 1289 { 1290 ARMCPU *cpu = ARM_CPU(obj); 1291 set_feature(&cpu->env, ARM_FEATURE_V6); 1292 set_feature(&cpu->env, ARM_FEATURE_M); 1293 1294 cpu->midr = 0x410cc200; 1295 } 1296 1297 static void cortex_m3_initfn(Object *obj) 1298 { 1299 ARMCPU *cpu = ARM_CPU(obj); 1300 set_feature(&cpu->env, ARM_FEATURE_V7); 1301 set_feature(&cpu->env, ARM_FEATURE_M); 1302 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1303 cpu->midr = 0x410fc231; 1304 cpu->pmsav7_dregion = 8; 1305 cpu->id_pfr0 = 0x00000030; 1306 cpu->id_pfr1 = 0x00000200; 1307 cpu->id_dfr0 = 0x00100000; 1308 cpu->id_afr0 = 0x00000000; 1309 cpu->id_mmfr0 = 0x00000030; 1310 cpu->id_mmfr1 = 0x00000000; 1311 cpu->id_mmfr2 = 0x00000000; 1312 cpu->id_mmfr3 = 0x00000000; 1313 cpu->isar.id_isar0 = 0x01141110; 1314 cpu->isar.id_isar1 = 0x02111000; 1315 cpu->isar.id_isar2 = 0x21112231; 1316 cpu->isar.id_isar3 = 0x01111110; 1317 cpu->isar.id_isar4 = 0x01310102; 1318 cpu->isar.id_isar5 = 0x00000000; 1319 cpu->isar.id_isar6 = 0x00000000; 1320 } 1321 1322 static void cortex_m4_initfn(Object *obj) 1323 { 1324 ARMCPU *cpu = ARM_CPU(obj); 1325 1326 set_feature(&cpu->env, ARM_FEATURE_V7); 1327 set_feature(&cpu->env, ARM_FEATURE_M); 1328 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1329 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1330 cpu->midr = 0x410fc240; /* r0p0 */ 1331 cpu->pmsav7_dregion = 8; 1332 cpu->id_pfr0 = 0x00000030; 1333 cpu->id_pfr1 = 0x00000200; 1334 cpu->id_dfr0 = 0x00100000; 1335 cpu->id_afr0 = 0x00000000; 1336 cpu->id_mmfr0 = 0x00000030; 1337 cpu->id_mmfr1 = 0x00000000; 1338 cpu->id_mmfr2 = 0x00000000; 1339 cpu->id_mmfr3 = 0x00000000; 1340 cpu->isar.id_isar0 = 0x01141110; 1341 cpu->isar.id_isar1 = 0x02111000; 1342 cpu->isar.id_isar2 = 0x21112231; 1343 cpu->isar.id_isar3 = 0x01111110; 1344 cpu->isar.id_isar4 = 0x01310102; 1345 cpu->isar.id_isar5 = 0x00000000; 1346 cpu->isar.id_isar6 = 0x00000000; 1347 } 1348 1349 static void cortex_m33_initfn(Object *obj) 1350 { 1351 ARMCPU *cpu = ARM_CPU(obj); 1352 1353 set_feature(&cpu->env, ARM_FEATURE_V8); 1354 set_feature(&cpu->env, ARM_FEATURE_M); 1355 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1356 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); 1357 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1358 cpu->midr = 0x410fd213; /* r0p3 */ 1359 cpu->pmsav7_dregion = 16; 1360 cpu->sau_sregion = 8; 1361 cpu->id_pfr0 = 0x00000030; 1362 cpu->id_pfr1 = 0x00000210; 1363 cpu->id_dfr0 = 0x00200000; 1364 cpu->id_afr0 = 0x00000000; 1365 cpu->id_mmfr0 = 0x00101F40; 1366 cpu->id_mmfr1 = 0x00000000; 1367 cpu->id_mmfr2 = 0x01000000; 1368 cpu->id_mmfr3 = 0x00000000; 1369 cpu->isar.id_isar0 = 0x01101110; 1370 cpu->isar.id_isar1 = 0x02212000; 1371 cpu->isar.id_isar2 = 0x20232232; 1372 cpu->isar.id_isar3 = 0x01111131; 1373 cpu->isar.id_isar4 = 0x01310132; 1374 cpu->isar.id_isar5 = 0x00000000; 1375 cpu->isar.id_isar6 = 0x00000000; 1376 cpu->clidr = 0x00000000; 1377 cpu->ctr = 0x8000c000; 1378 } 1379 1380 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1381 { 1382 CPUClass *cc = CPU_CLASS(oc); 1383 1384 #ifndef CONFIG_USER_ONLY 1385 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1386 #endif 1387 1388 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1389 } 1390 1391 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1392 /* Dummy the TCM region regs for the moment */ 1393 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1394 .access = PL1_RW, .type = ARM_CP_CONST }, 1395 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1396 .access = PL1_RW, .type = ARM_CP_CONST }, 1397 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 1398 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 1399 REGINFO_SENTINEL 1400 }; 1401 1402 static void cortex_r5_initfn(Object *obj) 1403 { 1404 ARMCPU *cpu = ARM_CPU(obj); 1405 1406 set_feature(&cpu->env, ARM_FEATURE_V7); 1407 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1408 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1409 cpu->midr = 0x411fc153; /* r1p3 */ 1410 cpu->id_pfr0 = 0x0131; 1411 cpu->id_pfr1 = 0x001; 1412 cpu->id_dfr0 = 0x010400; 1413 cpu->id_afr0 = 0x0; 1414 cpu->id_mmfr0 = 0x0210030; 1415 cpu->id_mmfr1 = 0x00000000; 1416 cpu->id_mmfr2 = 0x01200000; 1417 cpu->id_mmfr3 = 0x0211; 1418 cpu->isar.id_isar0 = 0x02101111; 1419 cpu->isar.id_isar1 = 0x13112111; 1420 cpu->isar.id_isar2 = 0x21232141; 1421 cpu->isar.id_isar3 = 0x01112131; 1422 cpu->isar.id_isar4 = 0x0010142; 1423 cpu->isar.id_isar5 = 0x0; 1424 cpu->isar.id_isar6 = 0x0; 1425 cpu->mp_is_up = true; 1426 cpu->pmsav7_dregion = 16; 1427 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1428 } 1429 1430 static void cortex_r5f_initfn(Object *obj) 1431 { 1432 ARMCPU *cpu = ARM_CPU(obj); 1433 1434 cortex_r5_initfn(obj); 1435 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1436 } 1437 1438 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1439 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1440 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1441 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1442 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1443 REGINFO_SENTINEL 1444 }; 1445 1446 static void cortex_a8_initfn(Object *obj) 1447 { 1448 ARMCPU *cpu = ARM_CPU(obj); 1449 1450 cpu->dtb_compatible = "arm,cortex-a8"; 1451 set_feature(&cpu->env, ARM_FEATURE_V7); 1452 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1453 set_feature(&cpu->env, ARM_FEATURE_NEON); 1454 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1455 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1456 set_feature(&cpu->env, ARM_FEATURE_EL3); 1457 cpu->midr = 0x410fc080; 1458 cpu->reset_fpsid = 0x410330c0; 1459 cpu->isar.mvfr0 = 0x11110222; 1460 cpu->isar.mvfr1 = 0x00011111; 1461 cpu->ctr = 0x82048004; 1462 cpu->reset_sctlr = 0x00c50078; 1463 cpu->id_pfr0 = 0x1031; 1464 cpu->id_pfr1 = 0x11; 1465 cpu->id_dfr0 = 0x400; 1466 cpu->id_afr0 = 0; 1467 cpu->id_mmfr0 = 0x31100003; 1468 cpu->id_mmfr1 = 0x20000000; 1469 cpu->id_mmfr2 = 0x01202000; 1470 cpu->id_mmfr3 = 0x11; 1471 cpu->isar.id_isar0 = 0x00101111; 1472 cpu->isar.id_isar1 = 0x12112111; 1473 cpu->isar.id_isar2 = 0x21232031; 1474 cpu->isar.id_isar3 = 0x11112131; 1475 cpu->isar.id_isar4 = 0x00111142; 1476 cpu->dbgdidr = 0x15141000; 1477 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1478 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1479 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1480 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1481 cpu->reset_auxcr = 2; 1482 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1483 } 1484 1485 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1486 /* power_control should be set to maximum latency. Again, 1487 * default to 0 and set by private hook 1488 */ 1489 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1490 .access = PL1_RW, .resetvalue = 0, 1491 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1492 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1493 .access = PL1_RW, .resetvalue = 0, 1494 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1495 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1496 .access = PL1_RW, .resetvalue = 0, 1497 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1498 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1499 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1500 /* TLB lockdown control */ 1501 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1502 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1503 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1504 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1505 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1506 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1507 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1508 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1509 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1510 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1511 REGINFO_SENTINEL 1512 }; 1513 1514 static void cortex_a9_initfn(Object *obj) 1515 { 1516 ARMCPU *cpu = ARM_CPU(obj); 1517 1518 cpu->dtb_compatible = "arm,cortex-a9"; 1519 set_feature(&cpu->env, ARM_FEATURE_V7); 1520 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1521 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); 1522 set_feature(&cpu->env, ARM_FEATURE_NEON); 1523 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1524 set_feature(&cpu->env, ARM_FEATURE_EL3); 1525 /* Note that A9 supports the MP extensions even for 1526 * A9UP and single-core A9MP (which are both different 1527 * and valid configurations; we don't model A9UP). 1528 */ 1529 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1530 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1531 cpu->midr = 0x410fc090; 1532 cpu->reset_fpsid = 0x41033090; 1533 cpu->isar.mvfr0 = 0x11110222; 1534 cpu->isar.mvfr1 = 0x01111111; 1535 cpu->ctr = 0x80038003; 1536 cpu->reset_sctlr = 0x00c50078; 1537 cpu->id_pfr0 = 0x1031; 1538 cpu->id_pfr1 = 0x11; 1539 cpu->id_dfr0 = 0x000; 1540 cpu->id_afr0 = 0; 1541 cpu->id_mmfr0 = 0x00100103; 1542 cpu->id_mmfr1 = 0x20000000; 1543 cpu->id_mmfr2 = 0x01230000; 1544 cpu->id_mmfr3 = 0x00002111; 1545 cpu->isar.id_isar0 = 0x00101111; 1546 cpu->isar.id_isar1 = 0x13112111; 1547 cpu->isar.id_isar2 = 0x21232041; 1548 cpu->isar.id_isar3 = 0x11112131; 1549 cpu->isar.id_isar4 = 0x00111142; 1550 cpu->dbgdidr = 0x35141000; 1551 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1552 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1553 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1554 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1555 } 1556 1557 #ifndef CONFIG_USER_ONLY 1558 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1559 { 1560 /* Linux wants the number of processors from here. 1561 * Might as well set the interrupt-controller bit too. 1562 */ 1563 return ((smp_cpus - 1) << 24) | (1 << 23); 1564 } 1565 #endif 1566 1567 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1568 #ifndef CONFIG_USER_ONLY 1569 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1570 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1571 .writefn = arm_cp_write_ignore, }, 1572 #endif 1573 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1574 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1575 REGINFO_SENTINEL 1576 }; 1577 1578 static void cortex_a7_initfn(Object *obj) 1579 { 1580 ARMCPU *cpu = ARM_CPU(obj); 1581 1582 cpu->dtb_compatible = "arm,cortex-a7"; 1583 set_feature(&cpu->env, ARM_FEATURE_V7VE); 1584 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1585 set_feature(&cpu->env, ARM_FEATURE_NEON); 1586 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1587 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1588 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1589 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1590 set_feature(&cpu->env, ARM_FEATURE_EL3); 1591 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1592 cpu->midr = 0x410fc075; 1593 cpu->reset_fpsid = 0x41023075; 1594 cpu->isar.mvfr0 = 0x10110222; 1595 cpu->isar.mvfr1 = 0x11111111; 1596 cpu->ctr = 0x84448003; 1597 cpu->reset_sctlr = 0x00c50078; 1598 cpu->id_pfr0 = 0x00001131; 1599 cpu->id_pfr1 = 0x00011011; 1600 cpu->id_dfr0 = 0x02010555; 1601 cpu->pmceid0 = 0x00000000; 1602 cpu->pmceid1 = 0x00000000; 1603 cpu->id_afr0 = 0x00000000; 1604 cpu->id_mmfr0 = 0x10101105; 1605 cpu->id_mmfr1 = 0x40000000; 1606 cpu->id_mmfr2 = 0x01240000; 1607 cpu->id_mmfr3 = 0x02102211; 1608 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but 1609 * table 4-41 gives 0x02101110, which includes the arm div insns. 1610 */ 1611 cpu->isar.id_isar0 = 0x02101110; 1612 cpu->isar.id_isar1 = 0x13112111; 1613 cpu->isar.id_isar2 = 0x21232041; 1614 cpu->isar.id_isar3 = 0x11112131; 1615 cpu->isar.id_isar4 = 0x10011142; 1616 cpu->dbgdidr = 0x3515f005; 1617 cpu->clidr = 0x0a200023; 1618 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1619 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1620 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1621 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1622 } 1623 1624 static void cortex_a15_initfn(Object *obj) 1625 { 1626 ARMCPU *cpu = ARM_CPU(obj); 1627 1628 cpu->dtb_compatible = "arm,cortex-a15"; 1629 set_feature(&cpu->env, ARM_FEATURE_V7VE); 1630 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1631 set_feature(&cpu->env, ARM_FEATURE_NEON); 1632 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1633 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1634 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1635 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1636 set_feature(&cpu->env, ARM_FEATURE_EL3); 1637 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1638 cpu->midr = 0x412fc0f1; 1639 cpu->reset_fpsid = 0x410430f0; 1640 cpu->isar.mvfr0 = 0x10110222; 1641 cpu->isar.mvfr1 = 0x11111111; 1642 cpu->ctr = 0x8444c004; 1643 cpu->reset_sctlr = 0x00c50078; 1644 cpu->id_pfr0 = 0x00001131; 1645 cpu->id_pfr1 = 0x00011011; 1646 cpu->id_dfr0 = 0x02010555; 1647 cpu->pmceid0 = 0x0000000; 1648 cpu->pmceid1 = 0x00000000; 1649 cpu->id_afr0 = 0x00000000; 1650 cpu->id_mmfr0 = 0x10201105; 1651 cpu->id_mmfr1 = 0x20000000; 1652 cpu->id_mmfr2 = 0x01240000; 1653 cpu->id_mmfr3 = 0x02102211; 1654 cpu->isar.id_isar0 = 0x02101110; 1655 cpu->isar.id_isar1 = 0x13112111; 1656 cpu->isar.id_isar2 = 0x21232041; 1657 cpu->isar.id_isar3 = 0x11112131; 1658 cpu->isar.id_isar4 = 0x10011142; 1659 cpu->dbgdidr = 0x3515f021; 1660 cpu->clidr = 0x0a200023; 1661 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1662 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1663 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1664 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 1665 } 1666 1667 static void ti925t_initfn(Object *obj) 1668 { 1669 ARMCPU *cpu = ARM_CPU(obj); 1670 set_feature(&cpu->env, ARM_FEATURE_V4T); 1671 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 1672 cpu->midr = ARM_CPUID_TI925T; 1673 cpu->ctr = 0x5109149; 1674 cpu->reset_sctlr = 0x00000070; 1675 } 1676 1677 static void sa1100_initfn(Object *obj) 1678 { 1679 ARMCPU *cpu = ARM_CPU(obj); 1680 1681 cpu->dtb_compatible = "intel,sa1100"; 1682 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1683 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1684 cpu->midr = 0x4401A11B; 1685 cpu->reset_sctlr = 0x00000070; 1686 } 1687 1688 static void sa1110_initfn(Object *obj) 1689 { 1690 ARMCPU *cpu = ARM_CPU(obj); 1691 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1692 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1693 cpu->midr = 0x6901B119; 1694 cpu->reset_sctlr = 0x00000070; 1695 } 1696 1697 static void pxa250_initfn(Object *obj) 1698 { 1699 ARMCPU *cpu = ARM_CPU(obj); 1700 1701 cpu->dtb_compatible = "marvell,xscale"; 1702 set_feature(&cpu->env, ARM_FEATURE_V5); 1703 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1704 cpu->midr = 0x69052100; 1705 cpu->ctr = 0xd172172; 1706 cpu->reset_sctlr = 0x00000078; 1707 } 1708 1709 static void pxa255_initfn(Object *obj) 1710 { 1711 ARMCPU *cpu = ARM_CPU(obj); 1712 1713 cpu->dtb_compatible = "marvell,xscale"; 1714 set_feature(&cpu->env, ARM_FEATURE_V5); 1715 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1716 cpu->midr = 0x69052d00; 1717 cpu->ctr = 0xd172172; 1718 cpu->reset_sctlr = 0x00000078; 1719 } 1720 1721 static void pxa260_initfn(Object *obj) 1722 { 1723 ARMCPU *cpu = ARM_CPU(obj); 1724 1725 cpu->dtb_compatible = "marvell,xscale"; 1726 set_feature(&cpu->env, ARM_FEATURE_V5); 1727 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1728 cpu->midr = 0x69052903; 1729 cpu->ctr = 0xd172172; 1730 cpu->reset_sctlr = 0x00000078; 1731 } 1732 1733 static void pxa261_initfn(Object *obj) 1734 { 1735 ARMCPU *cpu = ARM_CPU(obj); 1736 1737 cpu->dtb_compatible = "marvell,xscale"; 1738 set_feature(&cpu->env, ARM_FEATURE_V5); 1739 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1740 cpu->midr = 0x69052d05; 1741 cpu->ctr = 0xd172172; 1742 cpu->reset_sctlr = 0x00000078; 1743 } 1744 1745 static void pxa262_initfn(Object *obj) 1746 { 1747 ARMCPU *cpu = ARM_CPU(obj); 1748 1749 cpu->dtb_compatible = "marvell,xscale"; 1750 set_feature(&cpu->env, ARM_FEATURE_V5); 1751 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1752 cpu->midr = 0x69052d06; 1753 cpu->ctr = 0xd172172; 1754 cpu->reset_sctlr = 0x00000078; 1755 } 1756 1757 static void pxa270a0_initfn(Object *obj) 1758 { 1759 ARMCPU *cpu = ARM_CPU(obj); 1760 1761 cpu->dtb_compatible = "marvell,xscale"; 1762 set_feature(&cpu->env, ARM_FEATURE_V5); 1763 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1764 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1765 cpu->midr = 0x69054110; 1766 cpu->ctr = 0xd172172; 1767 cpu->reset_sctlr = 0x00000078; 1768 } 1769 1770 static void pxa270a1_initfn(Object *obj) 1771 { 1772 ARMCPU *cpu = ARM_CPU(obj); 1773 1774 cpu->dtb_compatible = "marvell,xscale"; 1775 set_feature(&cpu->env, ARM_FEATURE_V5); 1776 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1777 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1778 cpu->midr = 0x69054111; 1779 cpu->ctr = 0xd172172; 1780 cpu->reset_sctlr = 0x00000078; 1781 } 1782 1783 static void pxa270b0_initfn(Object *obj) 1784 { 1785 ARMCPU *cpu = ARM_CPU(obj); 1786 1787 cpu->dtb_compatible = "marvell,xscale"; 1788 set_feature(&cpu->env, ARM_FEATURE_V5); 1789 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1790 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1791 cpu->midr = 0x69054112; 1792 cpu->ctr = 0xd172172; 1793 cpu->reset_sctlr = 0x00000078; 1794 } 1795 1796 static void pxa270b1_initfn(Object *obj) 1797 { 1798 ARMCPU *cpu = ARM_CPU(obj); 1799 1800 cpu->dtb_compatible = "marvell,xscale"; 1801 set_feature(&cpu->env, ARM_FEATURE_V5); 1802 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1803 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1804 cpu->midr = 0x69054113; 1805 cpu->ctr = 0xd172172; 1806 cpu->reset_sctlr = 0x00000078; 1807 } 1808 1809 static void pxa270c0_initfn(Object *obj) 1810 { 1811 ARMCPU *cpu = ARM_CPU(obj); 1812 1813 cpu->dtb_compatible = "marvell,xscale"; 1814 set_feature(&cpu->env, ARM_FEATURE_V5); 1815 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1816 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1817 cpu->midr = 0x69054114; 1818 cpu->ctr = 0xd172172; 1819 cpu->reset_sctlr = 0x00000078; 1820 } 1821 1822 static void pxa270c5_initfn(Object *obj) 1823 { 1824 ARMCPU *cpu = ARM_CPU(obj); 1825 1826 cpu->dtb_compatible = "marvell,xscale"; 1827 set_feature(&cpu->env, ARM_FEATURE_V5); 1828 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1829 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1830 cpu->midr = 0x69054117; 1831 cpu->ctr = 0xd172172; 1832 cpu->reset_sctlr = 0x00000078; 1833 } 1834 1835 #ifndef TARGET_AARCH64 1836 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 1837 * otherwise, a CPU with as many features enabled as our emulation supports. 1838 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; 1839 * this only needs to handle 32 bits. 1840 */ 1841 static void arm_max_initfn(Object *obj) 1842 { 1843 ARMCPU *cpu = ARM_CPU(obj); 1844 1845 if (kvm_enabled()) { 1846 kvm_arm_set_cpu_features_from_host(cpu); 1847 } else { 1848 cortex_a15_initfn(obj); 1849 #ifdef CONFIG_USER_ONLY 1850 /* We don't set these in system emulation mode for the moment, 1851 * since we don't correctly set (all of) the ID registers to 1852 * advertise them. 1853 */ 1854 set_feature(&cpu->env, ARM_FEATURE_V8); 1855 { 1856 uint32_t t; 1857 1858 t = cpu->isar.id_isar5; 1859 t = FIELD_DP32(t, ID_ISAR5, AES, 2); 1860 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); 1861 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); 1862 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); 1863 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); 1864 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); 1865 cpu->isar.id_isar5 = t; 1866 1867 t = cpu->isar.id_isar6; 1868 t = FIELD_DP32(t, ID_ISAR6, DP, 1); 1869 cpu->isar.id_isar6 = t; 1870 } 1871 #endif 1872 } 1873 } 1874 #endif 1875 1876 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 1877 1878 typedef struct ARMCPUInfo { 1879 const char *name; 1880 void (*initfn)(Object *obj); 1881 void (*class_init)(ObjectClass *oc, void *data); 1882 } ARMCPUInfo; 1883 1884 static const ARMCPUInfo arm_cpus[] = { 1885 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1886 { .name = "arm926", .initfn = arm926_initfn }, 1887 { .name = "arm946", .initfn = arm946_initfn }, 1888 { .name = "arm1026", .initfn = arm1026_initfn }, 1889 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1890 * older core than plain "arm1136". In particular this does not 1891 * have the v6K features. 1892 */ 1893 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1894 { .name = "arm1136", .initfn = arm1136_initfn }, 1895 { .name = "arm1176", .initfn = arm1176_initfn }, 1896 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1897 { .name = "cortex-m0", .initfn = cortex_m0_initfn, 1898 .class_init = arm_v7m_class_init }, 1899 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 1900 .class_init = arm_v7m_class_init }, 1901 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 1902 .class_init = arm_v7m_class_init }, 1903 { .name = "cortex-m33", .initfn = cortex_m33_initfn, 1904 .class_init = arm_v7m_class_init }, 1905 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1906 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, 1907 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1908 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1909 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1910 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1911 { .name = "ti925t", .initfn = ti925t_initfn }, 1912 { .name = "sa1100", .initfn = sa1100_initfn }, 1913 { .name = "sa1110", .initfn = sa1110_initfn }, 1914 { .name = "pxa250", .initfn = pxa250_initfn }, 1915 { .name = "pxa255", .initfn = pxa255_initfn }, 1916 { .name = "pxa260", .initfn = pxa260_initfn }, 1917 { .name = "pxa261", .initfn = pxa261_initfn }, 1918 { .name = "pxa262", .initfn = pxa262_initfn }, 1919 /* "pxa270" is an alias for "pxa270-a0" */ 1920 { .name = "pxa270", .initfn = pxa270a0_initfn }, 1921 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 1922 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 1923 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 1924 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 1925 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 1926 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 1927 #ifndef TARGET_AARCH64 1928 { .name = "max", .initfn = arm_max_initfn }, 1929 #endif 1930 #ifdef CONFIG_USER_ONLY 1931 { .name = "any", .initfn = arm_max_initfn }, 1932 #endif 1933 #endif 1934 { .name = NULL } 1935 }; 1936 1937 static Property arm_cpu_properties[] = { 1938 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 1939 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 1940 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 1941 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 1942 mp_affinity, ARM64_AFFINITY_INVALID), 1943 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 1944 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 1945 DEFINE_PROP_END_OF_LIST() 1946 }; 1947 1948 #ifdef CONFIG_USER_ONLY 1949 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, 1950 int rw, int mmu_idx) 1951 { 1952 ARMCPU *cpu = ARM_CPU(cs); 1953 CPUARMState *env = &cpu->env; 1954 1955 env->exception.vaddress = address; 1956 if (rw == 2) { 1957 cs->exception_index = EXCP_PREFETCH_ABORT; 1958 } else { 1959 cs->exception_index = EXCP_DATA_ABORT; 1960 } 1961 return 1; 1962 } 1963 #endif 1964 1965 static gchar *arm_gdb_arch_name(CPUState *cs) 1966 { 1967 ARMCPU *cpu = ARM_CPU(cs); 1968 CPUARMState *env = &cpu->env; 1969 1970 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 1971 return g_strdup("iwmmxt"); 1972 } 1973 return g_strdup("arm"); 1974 } 1975 1976 static void arm_cpu_class_init(ObjectClass *oc, void *data) 1977 { 1978 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1979 CPUClass *cc = CPU_CLASS(acc); 1980 DeviceClass *dc = DEVICE_CLASS(oc); 1981 1982 device_class_set_parent_realize(dc, arm_cpu_realizefn, 1983 &acc->parent_realize); 1984 dc->props = arm_cpu_properties; 1985 1986 acc->parent_reset = cc->reset; 1987 cc->reset = arm_cpu_reset; 1988 1989 cc->class_by_name = arm_cpu_class_by_name; 1990 cc->has_work = arm_cpu_has_work; 1991 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 1992 cc->dump_state = arm_cpu_dump_state; 1993 cc->set_pc = arm_cpu_set_pc; 1994 cc->gdb_read_register = arm_cpu_gdb_read_register; 1995 cc->gdb_write_register = arm_cpu_gdb_write_register; 1996 #ifdef CONFIG_USER_ONLY 1997 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; 1998 #else 1999 cc->do_interrupt = arm_cpu_do_interrupt; 2000 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 2001 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 2002 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 2003 cc->asidx_from_attrs = arm_asidx_from_attrs; 2004 cc->vmsd = &vmstate_arm_cpu; 2005 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 2006 cc->write_elf64_note = arm_cpu_write_elf64_note; 2007 cc->write_elf32_note = arm_cpu_write_elf32_note; 2008 #endif 2009 cc->gdb_num_core_regs = 26; 2010 cc->gdb_core_xml_file = "arm-core.xml"; 2011 cc->gdb_arch_name = arm_gdb_arch_name; 2012 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2013 cc->gdb_stop_before_watchpoint = true; 2014 cc->debug_excp_handler = arm_debug_excp_handler; 2015 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 2016 #if !defined(CONFIG_USER_ONLY) 2017 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 2018 #endif 2019 2020 cc->disas_set_info = arm_disas_set_info; 2021 #ifdef CONFIG_TCG 2022 cc->tcg_initialize = arm_translate_init; 2023 #endif 2024 } 2025 2026 #ifdef CONFIG_KVM 2027 static void arm_host_initfn(Object *obj) 2028 { 2029 ARMCPU *cpu = ARM_CPU(obj); 2030 2031 kvm_arm_set_cpu_features_from_host(cpu); 2032 } 2033 2034 static const TypeInfo host_arm_cpu_type_info = { 2035 .name = TYPE_ARM_HOST_CPU, 2036 #ifdef TARGET_AARCH64 2037 .parent = TYPE_AARCH64_CPU, 2038 #else 2039 .parent = TYPE_ARM_CPU, 2040 #endif 2041 .instance_init = arm_host_initfn, 2042 }; 2043 2044 #endif 2045 2046 static void cpu_register(const ARMCPUInfo *info) 2047 { 2048 TypeInfo type_info = { 2049 .parent = TYPE_ARM_CPU, 2050 .instance_size = sizeof(ARMCPU), 2051 .instance_init = info->initfn, 2052 .class_size = sizeof(ARMCPUClass), 2053 .class_init = info->class_init, 2054 }; 2055 2056 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2057 type_register(&type_info); 2058 g_free((void *)type_info.name); 2059 } 2060 2061 static const TypeInfo arm_cpu_type_info = { 2062 .name = TYPE_ARM_CPU, 2063 .parent = TYPE_CPU, 2064 .instance_size = sizeof(ARMCPU), 2065 .instance_init = arm_cpu_initfn, 2066 .instance_post_init = arm_cpu_post_init, 2067 .instance_finalize = arm_cpu_finalizefn, 2068 .abstract = true, 2069 .class_size = sizeof(ARMCPUClass), 2070 .class_init = arm_cpu_class_init, 2071 }; 2072 2073 static const TypeInfo idau_interface_type_info = { 2074 .name = TYPE_IDAU_INTERFACE, 2075 .parent = TYPE_INTERFACE, 2076 .class_size = sizeof(IDAUInterfaceClass), 2077 }; 2078 2079 static void arm_cpu_register_types(void) 2080 { 2081 const ARMCPUInfo *info = arm_cpus; 2082 2083 type_register_static(&arm_cpu_type_info); 2084 type_register_static(&idau_interface_type_info); 2085 2086 while (info->name) { 2087 cpu_register(info); 2088 info++; 2089 } 2090 2091 #ifdef CONFIG_KVM 2092 type_register_static(&host_arm_cpu_type_info); 2093 #endif 2094 } 2095 2096 type_init(arm_cpu_register_types) 2097