1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "target/arm/idau.h" 23 #include "qemu/error-report.h" 24 #include "qapi/error.h" 25 #include "cpu.h" 26 #include "internals.h" 27 #include "qemu-common.h" 28 #include "exec/exec-all.h" 29 #include "hw/qdev-properties.h" 30 #if !defined(CONFIG_USER_ONLY) 31 #include "hw/loader.h" 32 #endif 33 #include "hw/arm/arm.h" 34 #include "sysemu/sysemu.h" 35 #include "sysemu/hw_accel.h" 36 #include "kvm_arm.h" 37 #include "disas/capstone.h" 38 #include "fpu/softfloat.h" 39 40 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 41 { 42 ARMCPU *cpu = ARM_CPU(cs); 43 44 cpu->env.regs[15] = value; 45 } 46 47 static bool arm_cpu_has_work(CPUState *cs) 48 { 49 ARMCPU *cpu = ARM_CPU(cs); 50 51 return (cpu->power_state != PSCI_OFF) 52 && cs->interrupt_request & 53 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 54 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 55 | CPU_INTERRUPT_EXITTB); 56 } 57 58 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 59 void *opaque) 60 { 61 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 62 63 entry->hook = hook; 64 entry->opaque = opaque; 65 66 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 67 } 68 69 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 70 void *opaque) 71 { 72 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 73 74 entry->hook = hook; 75 entry->opaque = opaque; 76 77 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 78 } 79 80 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 81 { 82 /* Reset a single ARMCPRegInfo register */ 83 ARMCPRegInfo *ri = value; 84 ARMCPU *cpu = opaque; 85 86 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 87 return; 88 } 89 90 if (ri->resetfn) { 91 ri->resetfn(&cpu->env, ri); 92 return; 93 } 94 95 /* A zero offset is never possible as it would be regs[0] 96 * so we use it to indicate that reset is being handled elsewhere. 97 * This is basically only used for fields in non-core coprocessors 98 * (like the pxa2xx ones). 99 */ 100 if (!ri->fieldoffset) { 101 return; 102 } 103 104 if (cpreg_field_is_64bit(ri)) { 105 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 106 } else { 107 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 108 } 109 } 110 111 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 112 { 113 /* Purely an assertion check: we've already done reset once, 114 * so now check that running the reset for the cpreg doesn't 115 * change its value. This traps bugs where two different cpregs 116 * both try to reset the same state field but to different values. 117 */ 118 ARMCPRegInfo *ri = value; 119 ARMCPU *cpu = opaque; 120 uint64_t oldvalue, newvalue; 121 122 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 123 return; 124 } 125 126 oldvalue = read_raw_cp_reg(&cpu->env, ri); 127 cp_reg_reset(key, value, opaque); 128 newvalue = read_raw_cp_reg(&cpu->env, ri); 129 assert(oldvalue == newvalue); 130 } 131 132 /* CPUClass::reset() */ 133 static void arm_cpu_reset(CPUState *s) 134 { 135 ARMCPU *cpu = ARM_CPU(s); 136 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 137 CPUARMState *env = &cpu->env; 138 139 acc->parent_reset(s); 140 141 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 142 143 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 144 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 145 146 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 147 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; 148 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; 149 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; 150 151 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 152 s->halted = cpu->start_powered_off; 153 154 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 155 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 156 } 157 158 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 159 /* 64 bit CPUs always start in 64 bit mode */ 160 env->aarch64 = 1; 161 #if defined(CONFIG_USER_ONLY) 162 env->pstate = PSTATE_MODE_EL0t; 163 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 164 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 165 /* and to the FP/Neon instructions */ 166 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 167 /* and to the SVE instructions */ 168 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 169 env->cp15.cptr_el[3] |= CPTR_EZ; 170 /* with maximum vector length */ 171 env->vfp.zcr_el[1] = ARM_MAX_VQ - 1; 172 env->vfp.zcr_el[2] = ARM_MAX_VQ - 1; 173 env->vfp.zcr_el[3] = ARM_MAX_VQ - 1; 174 #else 175 /* Reset into the highest available EL */ 176 if (arm_feature(env, ARM_FEATURE_EL3)) { 177 env->pstate = PSTATE_MODE_EL3h; 178 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 179 env->pstate = PSTATE_MODE_EL2h; 180 } else { 181 env->pstate = PSTATE_MODE_EL1h; 182 } 183 env->pc = cpu->rvbar; 184 #endif 185 } else { 186 #if defined(CONFIG_USER_ONLY) 187 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 188 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 189 #endif 190 } 191 192 #if defined(CONFIG_USER_ONLY) 193 env->uncached_cpsr = ARM_CPU_MODE_USR; 194 /* For user mode we must enable access to coprocessors */ 195 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 196 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 197 env->cp15.c15_cpar = 3; 198 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 199 env->cp15.c15_cpar = 1; 200 } 201 #else 202 /* SVC mode with interrupts disabled. */ 203 env->uncached_cpsr = ARM_CPU_MODE_SVC; 204 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 205 206 if (arm_feature(env, ARM_FEATURE_M)) { 207 uint32_t initial_msp; /* Loaded from 0x0 */ 208 uint32_t initial_pc; /* Loaded from 0x4 */ 209 uint8_t *rom; 210 uint32_t vecbase; 211 212 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 213 env->v7m.secure = true; 214 } else { 215 /* This bit resets to 0 if security is supported, but 1 if 216 * it is not. The bit is not present in v7M, but we set it 217 * here so we can avoid having to make checks on it conditional 218 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 219 */ 220 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 221 } 222 223 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 224 * that it resets to 1, so QEMU always does that rather than making 225 * it dependent on CPU model. In v8M it is RES1. 226 */ 227 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 228 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 229 if (arm_feature(env, ARM_FEATURE_V8)) { 230 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 231 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 232 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 233 } 234 235 /* Unlike A/R profile, M profile defines the reset LR value */ 236 env->regs[14] = 0xffffffff; 237 238 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 239 240 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 241 vecbase = env->v7m.vecbase[env->v7m.secure]; 242 rom = rom_ptr(vecbase); 243 if (rom) { 244 /* Address zero is covered by ROM which hasn't yet been 245 * copied into physical memory. 246 */ 247 initial_msp = ldl_p(rom); 248 initial_pc = ldl_p(rom + 4); 249 } else { 250 /* Address zero not covered by a ROM blob, or the ROM blob 251 * is in non-modifiable memory and this is a second reset after 252 * it got copied into memory. In the latter case, rom_ptr 253 * will return a NULL pointer and we should use ldl_phys instead. 254 */ 255 initial_msp = ldl_phys(s->as, vecbase); 256 initial_pc = ldl_phys(s->as, vecbase + 4); 257 } 258 259 env->regs[13] = initial_msp & 0xFFFFFFFC; 260 env->regs[15] = initial_pc & ~1; 261 env->thumb = initial_pc & 1; 262 } 263 264 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 265 * executing as AArch32 then check if highvecs are enabled and 266 * adjust the PC accordingly. 267 */ 268 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 269 env->regs[15] = 0xFFFF0000; 270 } 271 272 /* M profile requires that reset clears the exclusive monitor; 273 * A profile does not, but clearing it makes more sense than having it 274 * set with an exclusive access on address zero. 275 */ 276 arm_clear_exclusive(env); 277 278 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 279 #endif 280 281 if (arm_feature(env, ARM_FEATURE_PMSA)) { 282 if (cpu->pmsav7_dregion > 0) { 283 if (arm_feature(env, ARM_FEATURE_V8)) { 284 memset(env->pmsav8.rbar[M_REG_NS], 0, 285 sizeof(*env->pmsav8.rbar[M_REG_NS]) 286 * cpu->pmsav7_dregion); 287 memset(env->pmsav8.rlar[M_REG_NS], 0, 288 sizeof(*env->pmsav8.rlar[M_REG_NS]) 289 * cpu->pmsav7_dregion); 290 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 291 memset(env->pmsav8.rbar[M_REG_S], 0, 292 sizeof(*env->pmsav8.rbar[M_REG_S]) 293 * cpu->pmsav7_dregion); 294 memset(env->pmsav8.rlar[M_REG_S], 0, 295 sizeof(*env->pmsav8.rlar[M_REG_S]) 296 * cpu->pmsav7_dregion); 297 } 298 } else if (arm_feature(env, ARM_FEATURE_V7)) { 299 memset(env->pmsav7.drbar, 0, 300 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 301 memset(env->pmsav7.drsr, 0, 302 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 303 memset(env->pmsav7.dracr, 0, 304 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 305 } 306 } 307 env->pmsav7.rnr[M_REG_NS] = 0; 308 env->pmsav7.rnr[M_REG_S] = 0; 309 env->pmsav8.mair0[M_REG_NS] = 0; 310 env->pmsav8.mair0[M_REG_S] = 0; 311 env->pmsav8.mair1[M_REG_NS] = 0; 312 env->pmsav8.mair1[M_REG_S] = 0; 313 } 314 315 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 316 if (cpu->sau_sregion > 0) { 317 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 318 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 319 } 320 env->sau.rnr = 0; 321 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 322 * the Cortex-M33 does. 323 */ 324 env->sau.ctrl = 0; 325 } 326 327 set_flush_to_zero(1, &env->vfp.standard_fp_status); 328 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 329 set_default_nan_mode(1, &env->vfp.standard_fp_status); 330 set_float_detect_tininess(float_tininess_before_rounding, 331 &env->vfp.fp_status); 332 set_float_detect_tininess(float_tininess_before_rounding, 333 &env->vfp.standard_fp_status); 334 set_float_detect_tininess(float_tininess_before_rounding, 335 &env->vfp.fp_status_f16); 336 #ifndef CONFIG_USER_ONLY 337 if (kvm_enabled()) { 338 kvm_arm_reset_vcpu(cpu); 339 } 340 #endif 341 342 hw_breakpoint_update_all(cpu); 343 hw_watchpoint_update_all(cpu); 344 } 345 346 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 347 { 348 CPUClass *cc = CPU_GET_CLASS(cs); 349 CPUARMState *env = cs->env_ptr; 350 uint32_t cur_el = arm_current_el(env); 351 bool secure = arm_is_secure(env); 352 uint32_t target_el; 353 uint32_t excp_idx; 354 bool ret = false; 355 356 if (interrupt_request & CPU_INTERRUPT_FIQ) { 357 excp_idx = EXCP_FIQ; 358 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 359 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 360 cs->exception_index = excp_idx; 361 env->exception.target_el = target_el; 362 cc->do_interrupt(cs); 363 ret = true; 364 } 365 } 366 if (interrupt_request & CPU_INTERRUPT_HARD) { 367 excp_idx = EXCP_IRQ; 368 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 369 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 370 cs->exception_index = excp_idx; 371 env->exception.target_el = target_el; 372 cc->do_interrupt(cs); 373 ret = true; 374 } 375 } 376 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 377 excp_idx = EXCP_VIRQ; 378 target_el = 1; 379 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 380 cs->exception_index = excp_idx; 381 env->exception.target_el = target_el; 382 cc->do_interrupt(cs); 383 ret = true; 384 } 385 } 386 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 387 excp_idx = EXCP_VFIQ; 388 target_el = 1; 389 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 390 cs->exception_index = excp_idx; 391 env->exception.target_el = target_el; 392 cc->do_interrupt(cs); 393 ret = true; 394 } 395 } 396 397 return ret; 398 } 399 400 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 401 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 402 { 403 CPUClass *cc = CPU_GET_CLASS(cs); 404 ARMCPU *cpu = ARM_CPU(cs); 405 CPUARMState *env = &cpu->env; 406 bool ret = false; 407 408 /* ARMv7-M interrupt masking works differently than -A or -R. 409 * There is no FIQ/IRQ distinction. Instead of I and F bits 410 * masking FIQ and IRQ interrupts, an exception is taken only 411 * if it is higher priority than the current execution priority 412 * (which depends on state like BASEPRI, FAULTMASK and the 413 * currently active exception). 414 */ 415 if (interrupt_request & CPU_INTERRUPT_HARD 416 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 417 cs->exception_index = EXCP_IRQ; 418 cc->do_interrupt(cs); 419 ret = true; 420 } 421 return ret; 422 } 423 #endif 424 425 #ifndef CONFIG_USER_ONLY 426 static void arm_cpu_set_irq(void *opaque, int irq, int level) 427 { 428 ARMCPU *cpu = opaque; 429 CPUARMState *env = &cpu->env; 430 CPUState *cs = CPU(cpu); 431 static const int mask[] = { 432 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 433 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 434 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 435 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 436 }; 437 438 switch (irq) { 439 case ARM_CPU_VIRQ: 440 case ARM_CPU_VFIQ: 441 assert(arm_feature(env, ARM_FEATURE_EL2)); 442 /* fall through */ 443 case ARM_CPU_IRQ: 444 case ARM_CPU_FIQ: 445 if (level) { 446 cpu_interrupt(cs, mask[irq]); 447 } else { 448 cpu_reset_interrupt(cs, mask[irq]); 449 } 450 break; 451 default: 452 g_assert_not_reached(); 453 } 454 } 455 456 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 457 { 458 #ifdef CONFIG_KVM 459 ARMCPU *cpu = opaque; 460 CPUState *cs = CPU(cpu); 461 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 462 463 switch (irq) { 464 case ARM_CPU_IRQ: 465 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 466 break; 467 case ARM_CPU_FIQ: 468 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 469 break; 470 default: 471 g_assert_not_reached(); 472 } 473 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 474 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 475 #endif 476 } 477 478 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 479 { 480 ARMCPU *cpu = ARM_CPU(cs); 481 CPUARMState *env = &cpu->env; 482 483 cpu_synchronize_state(cs); 484 return arm_cpu_data_is_big_endian(env); 485 } 486 487 #endif 488 489 static inline void set_feature(CPUARMState *env, int feature) 490 { 491 env->features |= 1ULL << feature; 492 } 493 494 static inline void unset_feature(CPUARMState *env, int feature) 495 { 496 env->features &= ~(1ULL << feature); 497 } 498 499 static int 500 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 501 { 502 return print_insn_arm(pc | 1, info); 503 } 504 505 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 506 { 507 ARMCPU *ac = ARM_CPU(cpu); 508 CPUARMState *env = &ac->env; 509 bool sctlr_b; 510 511 if (is_a64(env)) { 512 /* We might not be compiled with the A64 disassembler 513 * because it needs a C++ compiler. Leave print_insn 514 * unset in this case to use the caller default behaviour. 515 */ 516 #if defined(CONFIG_ARM_A64_DIS) 517 info->print_insn = print_insn_arm_a64; 518 #endif 519 info->cap_arch = CS_ARCH_ARM64; 520 info->cap_insn_unit = 4; 521 info->cap_insn_split = 4; 522 } else { 523 int cap_mode; 524 if (env->thumb) { 525 info->print_insn = print_insn_thumb1; 526 info->cap_insn_unit = 2; 527 info->cap_insn_split = 4; 528 cap_mode = CS_MODE_THUMB; 529 } else { 530 info->print_insn = print_insn_arm; 531 info->cap_insn_unit = 4; 532 info->cap_insn_split = 4; 533 cap_mode = CS_MODE_ARM; 534 } 535 if (arm_feature(env, ARM_FEATURE_V8)) { 536 cap_mode |= CS_MODE_V8; 537 } 538 if (arm_feature(env, ARM_FEATURE_M)) { 539 cap_mode |= CS_MODE_MCLASS; 540 } 541 info->cap_arch = CS_ARCH_ARM; 542 info->cap_mode = cap_mode; 543 } 544 545 sctlr_b = arm_sctlr_b(env); 546 if (bswap_code(sctlr_b)) { 547 #ifdef TARGET_WORDS_BIGENDIAN 548 info->endian = BFD_ENDIAN_LITTLE; 549 #else 550 info->endian = BFD_ENDIAN_BIG; 551 #endif 552 } 553 info->flags &= ~INSN_ARM_BE32; 554 #ifndef CONFIG_USER_ONLY 555 if (sctlr_b) { 556 info->flags |= INSN_ARM_BE32; 557 } 558 #endif 559 } 560 561 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 562 { 563 uint32_t Aff1 = idx / clustersz; 564 uint32_t Aff0 = idx % clustersz; 565 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 566 } 567 568 static void arm_cpu_initfn(Object *obj) 569 { 570 CPUState *cs = CPU(obj); 571 ARMCPU *cpu = ARM_CPU(obj); 572 573 cs->env_ptr = &cpu->env; 574 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 575 g_free, g_free); 576 577 QLIST_INIT(&cpu->pre_el_change_hooks); 578 QLIST_INIT(&cpu->el_change_hooks); 579 580 #ifndef CONFIG_USER_ONLY 581 /* Our inbound IRQ and FIQ lines */ 582 if (kvm_enabled()) { 583 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 584 * the same interface as non-KVM CPUs. 585 */ 586 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 587 } else { 588 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 589 } 590 591 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 592 arm_gt_ptimer_cb, cpu); 593 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 594 arm_gt_vtimer_cb, cpu); 595 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 596 arm_gt_htimer_cb, cpu); 597 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 598 arm_gt_stimer_cb, cpu); 599 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 600 ARRAY_SIZE(cpu->gt_timer_outputs)); 601 602 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 603 "gicv3-maintenance-interrupt", 1); 604 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 605 "pmu-interrupt", 1); 606 #endif 607 608 /* DTB consumers generally don't in fact care what the 'compatible' 609 * string is, so always provide some string and trust that a hypothetical 610 * picky DTB consumer will also provide a helpful error message. 611 */ 612 cpu->dtb_compatible = "qemu,unknown"; 613 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 614 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 615 616 if (tcg_enabled()) { 617 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 618 } 619 } 620 621 static Property arm_cpu_reset_cbar_property = 622 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 623 624 static Property arm_cpu_reset_hivecs_property = 625 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 626 627 static Property arm_cpu_rvbar_property = 628 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 629 630 static Property arm_cpu_has_el2_property = 631 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 632 633 static Property arm_cpu_has_el3_property = 634 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 635 636 static Property arm_cpu_cfgend_property = 637 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 638 639 /* use property name "pmu" to match other archs and virt tools */ 640 static Property arm_cpu_has_pmu_property = 641 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 642 643 static Property arm_cpu_has_mpu_property = 644 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 645 646 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 647 * because the CPU initfn will have already set cpu->pmsav7_dregion to 648 * the right value for that particular CPU type, and we don't want 649 * to override that with an incorrect constant value. 650 */ 651 static Property arm_cpu_pmsav7_dregion_property = 652 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 653 pmsav7_dregion, 654 qdev_prop_uint32, uint32_t); 655 656 /* M profile: initial value of the Secure VTOR */ 657 static Property arm_cpu_initsvtor_property = 658 DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0); 659 660 static void arm_cpu_post_init(Object *obj) 661 { 662 ARMCPU *cpu = ARM_CPU(obj); 663 664 /* M profile implies PMSA. We have to do this here rather than 665 * in realize with the other feature-implication checks because 666 * we look at the PMSA bit to see if we should add some properties. 667 */ 668 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 669 set_feature(&cpu->env, ARM_FEATURE_PMSA); 670 } 671 672 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 673 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 674 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 675 &error_abort); 676 } 677 678 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 679 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 680 &error_abort); 681 } 682 683 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 684 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 685 &error_abort); 686 } 687 688 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 689 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 690 * prevent "has_el3" from existing on CPUs which cannot support EL3. 691 */ 692 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 693 &error_abort); 694 695 #ifndef CONFIG_USER_ONLY 696 object_property_add_link(obj, "secure-memory", 697 TYPE_MEMORY_REGION, 698 (Object **)&cpu->secure_memory, 699 qdev_prop_allow_set_link_before_realize, 700 OBJ_PROP_LINK_STRONG, 701 &error_abort); 702 #endif 703 } 704 705 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 706 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 707 &error_abort); 708 } 709 710 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 711 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 712 &error_abort); 713 } 714 715 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 716 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 717 &error_abort); 718 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 719 qdev_property_add_static(DEVICE(obj), 720 &arm_cpu_pmsav7_dregion_property, 721 &error_abort); 722 } 723 } 724 725 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 726 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 727 qdev_prop_allow_set_link_before_realize, 728 OBJ_PROP_LINK_STRONG, 729 &error_abort); 730 qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property, 731 &error_abort); 732 } 733 734 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 735 &error_abort); 736 } 737 738 static void arm_cpu_finalizefn(Object *obj) 739 { 740 ARMCPU *cpu = ARM_CPU(obj); 741 ARMELChangeHook *hook, *next; 742 743 g_hash_table_destroy(cpu->cp_regs); 744 745 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 746 QLIST_REMOVE(hook, node); 747 g_free(hook); 748 } 749 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 750 QLIST_REMOVE(hook, node); 751 g_free(hook); 752 } 753 } 754 755 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 756 { 757 CPUState *cs = CPU(dev); 758 ARMCPU *cpu = ARM_CPU(dev); 759 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 760 CPUARMState *env = &cpu->env; 761 int pagebits; 762 Error *local_err = NULL; 763 764 /* If we needed to query the host kernel for the CPU features 765 * then it's possible that might have failed in the initfn, but 766 * this is the first point where we can report it. 767 */ 768 if (cpu->host_cpu_probe_failed) { 769 if (!kvm_enabled()) { 770 error_setg(errp, "The 'host' CPU type can only be used with KVM"); 771 } else { 772 error_setg(errp, "Failed to retrieve host CPU features"); 773 } 774 return; 775 } 776 777 #ifndef CONFIG_USER_ONLY 778 /* The NVIC and M-profile CPU are two halves of a single piece of 779 * hardware; trying to use one without the other is a command line 780 * error and will result in segfaults if not caught here. 781 */ 782 if (arm_feature(env, ARM_FEATURE_M)) { 783 if (!env->nvic) { 784 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 785 return; 786 } 787 } else { 788 if (env->nvic) { 789 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 790 return; 791 } 792 } 793 #endif 794 795 cpu_exec_realizefn(cs, &local_err); 796 if (local_err != NULL) { 797 error_propagate(errp, local_err); 798 return; 799 } 800 801 /* Some features automatically imply others: */ 802 if (arm_feature(env, ARM_FEATURE_V8)) { 803 set_feature(env, ARM_FEATURE_V7VE); 804 } 805 if (arm_feature(env, ARM_FEATURE_V7VE)) { 806 /* v7 Virtualization Extensions. In real hardware this implies 807 * EL2 and also the presence of the Security Extensions. 808 * For QEMU, for backwards-compatibility we implement some 809 * CPUs or CPU configs which have no actual EL2 or EL3 but do 810 * include the various other features that V7VE implies. 811 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 812 * Security Extensions is ARM_FEATURE_EL3. 813 */ 814 set_feature(env, ARM_FEATURE_ARM_DIV); 815 set_feature(env, ARM_FEATURE_LPAE); 816 set_feature(env, ARM_FEATURE_V7); 817 } 818 if (arm_feature(env, ARM_FEATURE_V7)) { 819 set_feature(env, ARM_FEATURE_VAPA); 820 set_feature(env, ARM_FEATURE_THUMB2); 821 set_feature(env, ARM_FEATURE_MPIDR); 822 if (!arm_feature(env, ARM_FEATURE_M)) { 823 set_feature(env, ARM_FEATURE_V6K); 824 } else { 825 set_feature(env, ARM_FEATURE_V6); 826 } 827 828 /* Always define VBAR for V7 CPUs even if it doesn't exist in 829 * non-EL3 configs. This is needed by some legacy boards. 830 */ 831 set_feature(env, ARM_FEATURE_VBAR); 832 } 833 if (arm_feature(env, ARM_FEATURE_V6K)) { 834 set_feature(env, ARM_FEATURE_V6); 835 set_feature(env, ARM_FEATURE_MVFR); 836 } 837 if (arm_feature(env, ARM_FEATURE_V6)) { 838 set_feature(env, ARM_FEATURE_V5); 839 set_feature(env, ARM_FEATURE_JAZELLE); 840 if (!arm_feature(env, ARM_FEATURE_M)) { 841 set_feature(env, ARM_FEATURE_AUXCR); 842 } 843 } 844 if (arm_feature(env, ARM_FEATURE_V5)) { 845 set_feature(env, ARM_FEATURE_V4T); 846 } 847 if (arm_feature(env, ARM_FEATURE_M)) { 848 set_feature(env, ARM_FEATURE_THUMB_DIV); 849 } 850 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { 851 set_feature(env, ARM_FEATURE_THUMB_DIV); 852 } 853 if (arm_feature(env, ARM_FEATURE_VFP4)) { 854 set_feature(env, ARM_FEATURE_VFP3); 855 set_feature(env, ARM_FEATURE_VFP_FP16); 856 } 857 if (arm_feature(env, ARM_FEATURE_VFP3)) { 858 set_feature(env, ARM_FEATURE_VFP); 859 } 860 if (arm_feature(env, ARM_FEATURE_LPAE)) { 861 set_feature(env, ARM_FEATURE_V7MP); 862 set_feature(env, ARM_FEATURE_PXN); 863 } 864 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 865 set_feature(env, ARM_FEATURE_CBAR); 866 } 867 if (arm_feature(env, ARM_FEATURE_THUMB2) && 868 !arm_feature(env, ARM_FEATURE_M)) { 869 set_feature(env, ARM_FEATURE_THUMB_DSP); 870 } 871 872 if (arm_feature(env, ARM_FEATURE_V7) && 873 !arm_feature(env, ARM_FEATURE_M) && 874 !arm_feature(env, ARM_FEATURE_PMSA)) { 875 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 876 * can use 4K pages. 877 */ 878 pagebits = 12; 879 } else { 880 /* For CPUs which might have tiny 1K pages, or which have an 881 * MPU and might have small region sizes, stick with 1K pages. 882 */ 883 pagebits = 10; 884 } 885 if (!set_preferred_target_page_bits(pagebits)) { 886 /* This can only ever happen for hotplugging a CPU, or if 887 * the board code incorrectly creates a CPU which it has 888 * promised via minimum_page_size that it will not. 889 */ 890 error_setg(errp, "This CPU requires a smaller page size than the " 891 "system is using"); 892 return; 893 } 894 895 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 896 * We don't support setting cluster ID ([16..23]) (known as Aff2 897 * in later ARM ARM versions), or any of the higher affinity level fields, 898 * so these bits always RAZ. 899 */ 900 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 901 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 902 ARM_DEFAULT_CPUS_PER_CLUSTER); 903 } 904 905 if (cpu->reset_hivecs) { 906 cpu->reset_sctlr |= (1 << 13); 907 } 908 909 if (cpu->cfgend) { 910 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 911 cpu->reset_sctlr |= SCTLR_EE; 912 } else { 913 cpu->reset_sctlr |= SCTLR_B; 914 } 915 } 916 917 if (!cpu->has_el3) { 918 /* If the has_el3 CPU property is disabled then we need to disable the 919 * feature. 920 */ 921 unset_feature(env, ARM_FEATURE_EL3); 922 923 /* Disable the security extension feature bits in the processor feature 924 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 925 */ 926 cpu->id_pfr1 &= ~0xf0; 927 cpu->id_aa64pfr0 &= ~0xf000; 928 } 929 930 if (!cpu->has_el2) { 931 unset_feature(env, ARM_FEATURE_EL2); 932 } 933 934 if (!cpu->has_pmu) { 935 unset_feature(env, ARM_FEATURE_PMU); 936 cpu->id_aa64dfr0 &= ~0xf00; 937 } 938 939 if (!arm_feature(env, ARM_FEATURE_EL2)) { 940 /* Disable the hypervisor feature bits in the processor feature 941 * registers if we don't have EL2. These are id_pfr1[15:12] and 942 * id_aa64pfr0_el1[11:8]. 943 */ 944 cpu->id_aa64pfr0 &= ~0xf00; 945 cpu->id_pfr1 &= ~0xf000; 946 } 947 948 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 949 * to false or by setting pmsav7-dregion to 0. 950 */ 951 if (!cpu->has_mpu) { 952 cpu->pmsav7_dregion = 0; 953 } 954 if (cpu->pmsav7_dregion == 0) { 955 cpu->has_mpu = false; 956 } 957 958 if (arm_feature(env, ARM_FEATURE_PMSA) && 959 arm_feature(env, ARM_FEATURE_V7)) { 960 uint32_t nr = cpu->pmsav7_dregion; 961 962 if (nr > 0xff) { 963 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 964 return; 965 } 966 967 if (nr) { 968 if (arm_feature(env, ARM_FEATURE_V8)) { 969 /* PMSAv8 */ 970 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 971 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 972 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 973 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 974 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 975 } 976 } else { 977 env->pmsav7.drbar = g_new0(uint32_t, nr); 978 env->pmsav7.drsr = g_new0(uint32_t, nr); 979 env->pmsav7.dracr = g_new0(uint32_t, nr); 980 } 981 } 982 } 983 984 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 985 uint32_t nr = cpu->sau_sregion; 986 987 if (nr > 0xff) { 988 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 989 return; 990 } 991 992 if (nr) { 993 env->sau.rbar = g_new0(uint32_t, nr); 994 env->sau.rlar = g_new0(uint32_t, nr); 995 } 996 } 997 998 if (arm_feature(env, ARM_FEATURE_EL3)) { 999 set_feature(env, ARM_FEATURE_VBAR); 1000 } 1001 1002 register_cp_regs_for_features(cpu); 1003 arm_cpu_register_gdb_regs_for_features(cpu); 1004 1005 init_cpreg_list(cpu); 1006 1007 #ifndef CONFIG_USER_ONLY 1008 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1009 cs->num_ases = 2; 1010 1011 if (!cpu->secure_memory) { 1012 cpu->secure_memory = cs->memory; 1013 } 1014 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1015 cpu->secure_memory); 1016 } else { 1017 cs->num_ases = 1; 1018 } 1019 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1020 1021 /* No core_count specified, default to smp_cpus. */ 1022 if (cpu->core_count == -1) { 1023 cpu->core_count = smp_cpus; 1024 } 1025 #endif 1026 1027 qemu_init_vcpu(cs); 1028 cpu_reset(cs); 1029 1030 acc->parent_realize(dev, errp); 1031 } 1032 1033 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1034 { 1035 ObjectClass *oc; 1036 char *typename; 1037 char **cpuname; 1038 const char *cpunamestr; 1039 1040 cpuname = g_strsplit(cpu_model, ",", 1); 1041 cpunamestr = cpuname[0]; 1042 #ifdef CONFIG_USER_ONLY 1043 /* For backwards compatibility usermode emulation allows "-cpu any", 1044 * which has the same semantics as "-cpu max". 1045 */ 1046 if (!strcmp(cpunamestr, "any")) { 1047 cpunamestr = "max"; 1048 } 1049 #endif 1050 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 1051 oc = object_class_by_name(typename); 1052 g_strfreev(cpuname); 1053 g_free(typename); 1054 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 1055 object_class_is_abstract(oc)) { 1056 return NULL; 1057 } 1058 return oc; 1059 } 1060 1061 /* CPU models. These are not needed for the AArch64 linux-user build. */ 1062 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1063 1064 static void arm926_initfn(Object *obj) 1065 { 1066 ARMCPU *cpu = ARM_CPU(obj); 1067 1068 cpu->dtb_compatible = "arm,arm926"; 1069 set_feature(&cpu->env, ARM_FEATURE_V5); 1070 set_feature(&cpu->env, ARM_FEATURE_VFP); 1071 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1072 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1073 set_feature(&cpu->env, ARM_FEATURE_JAZELLE); 1074 cpu->midr = 0x41069265; 1075 cpu->reset_fpsid = 0x41011090; 1076 cpu->ctr = 0x1dd20d2; 1077 cpu->reset_sctlr = 0x00090078; 1078 } 1079 1080 static void arm946_initfn(Object *obj) 1081 { 1082 ARMCPU *cpu = ARM_CPU(obj); 1083 1084 cpu->dtb_compatible = "arm,arm946"; 1085 set_feature(&cpu->env, ARM_FEATURE_V5); 1086 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1087 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1088 cpu->midr = 0x41059461; 1089 cpu->ctr = 0x0f004006; 1090 cpu->reset_sctlr = 0x00000078; 1091 } 1092 1093 static void arm1026_initfn(Object *obj) 1094 { 1095 ARMCPU *cpu = ARM_CPU(obj); 1096 1097 cpu->dtb_compatible = "arm,arm1026"; 1098 set_feature(&cpu->env, ARM_FEATURE_V5); 1099 set_feature(&cpu->env, ARM_FEATURE_VFP); 1100 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 1101 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1102 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1103 set_feature(&cpu->env, ARM_FEATURE_JAZELLE); 1104 cpu->midr = 0x4106a262; 1105 cpu->reset_fpsid = 0x410110a0; 1106 cpu->ctr = 0x1dd20d2; 1107 cpu->reset_sctlr = 0x00090078; 1108 cpu->reset_auxcr = 1; 1109 { 1110 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 1111 ARMCPRegInfo ifar = { 1112 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 1113 .access = PL1_RW, 1114 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 1115 .resetvalue = 0 1116 }; 1117 define_one_arm_cp_reg(cpu, &ifar); 1118 } 1119 } 1120 1121 static void arm1136_r2_initfn(Object *obj) 1122 { 1123 ARMCPU *cpu = ARM_CPU(obj); 1124 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 1125 * older core than plain "arm1136". In particular this does not 1126 * have the v6K features. 1127 * These ID register values are correct for 1136 but may be wrong 1128 * for 1136_r2 (in particular r0p2 does not actually implement most 1129 * of the ID registers). 1130 */ 1131 1132 cpu->dtb_compatible = "arm,arm1136"; 1133 set_feature(&cpu->env, ARM_FEATURE_V6); 1134 set_feature(&cpu->env, ARM_FEATURE_VFP); 1135 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1136 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1137 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1138 cpu->midr = 0x4107b362; 1139 cpu->reset_fpsid = 0x410120b4; 1140 cpu->mvfr0 = 0x11111111; 1141 cpu->mvfr1 = 0x00000000; 1142 cpu->ctr = 0x1dd20d2; 1143 cpu->reset_sctlr = 0x00050078; 1144 cpu->id_pfr0 = 0x111; 1145 cpu->id_pfr1 = 0x1; 1146 cpu->id_dfr0 = 0x2; 1147 cpu->id_afr0 = 0x3; 1148 cpu->id_mmfr0 = 0x01130003; 1149 cpu->id_mmfr1 = 0x10030302; 1150 cpu->id_mmfr2 = 0x01222110; 1151 cpu->id_isar0 = 0x00140011; 1152 cpu->id_isar1 = 0x12002111; 1153 cpu->id_isar2 = 0x11231111; 1154 cpu->id_isar3 = 0x01102131; 1155 cpu->id_isar4 = 0x141; 1156 cpu->reset_auxcr = 7; 1157 } 1158 1159 static void arm1136_initfn(Object *obj) 1160 { 1161 ARMCPU *cpu = ARM_CPU(obj); 1162 1163 cpu->dtb_compatible = "arm,arm1136"; 1164 set_feature(&cpu->env, ARM_FEATURE_V6K); 1165 set_feature(&cpu->env, ARM_FEATURE_V6); 1166 set_feature(&cpu->env, ARM_FEATURE_VFP); 1167 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1168 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1169 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1170 cpu->midr = 0x4117b363; 1171 cpu->reset_fpsid = 0x410120b4; 1172 cpu->mvfr0 = 0x11111111; 1173 cpu->mvfr1 = 0x00000000; 1174 cpu->ctr = 0x1dd20d2; 1175 cpu->reset_sctlr = 0x00050078; 1176 cpu->id_pfr0 = 0x111; 1177 cpu->id_pfr1 = 0x1; 1178 cpu->id_dfr0 = 0x2; 1179 cpu->id_afr0 = 0x3; 1180 cpu->id_mmfr0 = 0x01130003; 1181 cpu->id_mmfr1 = 0x10030302; 1182 cpu->id_mmfr2 = 0x01222110; 1183 cpu->id_isar0 = 0x00140011; 1184 cpu->id_isar1 = 0x12002111; 1185 cpu->id_isar2 = 0x11231111; 1186 cpu->id_isar3 = 0x01102131; 1187 cpu->id_isar4 = 0x141; 1188 cpu->reset_auxcr = 7; 1189 } 1190 1191 static void arm1176_initfn(Object *obj) 1192 { 1193 ARMCPU *cpu = ARM_CPU(obj); 1194 1195 cpu->dtb_compatible = "arm,arm1176"; 1196 set_feature(&cpu->env, ARM_FEATURE_V6K); 1197 set_feature(&cpu->env, ARM_FEATURE_VFP); 1198 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1199 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1200 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1201 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1202 set_feature(&cpu->env, ARM_FEATURE_EL3); 1203 cpu->midr = 0x410fb767; 1204 cpu->reset_fpsid = 0x410120b5; 1205 cpu->mvfr0 = 0x11111111; 1206 cpu->mvfr1 = 0x00000000; 1207 cpu->ctr = 0x1dd20d2; 1208 cpu->reset_sctlr = 0x00050078; 1209 cpu->id_pfr0 = 0x111; 1210 cpu->id_pfr1 = 0x11; 1211 cpu->id_dfr0 = 0x33; 1212 cpu->id_afr0 = 0; 1213 cpu->id_mmfr0 = 0x01130003; 1214 cpu->id_mmfr1 = 0x10030302; 1215 cpu->id_mmfr2 = 0x01222100; 1216 cpu->id_isar0 = 0x0140011; 1217 cpu->id_isar1 = 0x12002111; 1218 cpu->id_isar2 = 0x11231121; 1219 cpu->id_isar3 = 0x01102131; 1220 cpu->id_isar4 = 0x01141; 1221 cpu->reset_auxcr = 7; 1222 } 1223 1224 static void arm11mpcore_initfn(Object *obj) 1225 { 1226 ARMCPU *cpu = ARM_CPU(obj); 1227 1228 cpu->dtb_compatible = "arm,arm11mpcore"; 1229 set_feature(&cpu->env, ARM_FEATURE_V6K); 1230 set_feature(&cpu->env, ARM_FEATURE_VFP); 1231 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1232 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1233 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1234 cpu->midr = 0x410fb022; 1235 cpu->reset_fpsid = 0x410120b4; 1236 cpu->mvfr0 = 0x11111111; 1237 cpu->mvfr1 = 0x00000000; 1238 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1239 cpu->id_pfr0 = 0x111; 1240 cpu->id_pfr1 = 0x1; 1241 cpu->id_dfr0 = 0; 1242 cpu->id_afr0 = 0x2; 1243 cpu->id_mmfr0 = 0x01100103; 1244 cpu->id_mmfr1 = 0x10020302; 1245 cpu->id_mmfr2 = 0x01222000; 1246 cpu->id_isar0 = 0x00100011; 1247 cpu->id_isar1 = 0x12002111; 1248 cpu->id_isar2 = 0x11221011; 1249 cpu->id_isar3 = 0x01102131; 1250 cpu->id_isar4 = 0x141; 1251 cpu->reset_auxcr = 1; 1252 } 1253 1254 static void cortex_m3_initfn(Object *obj) 1255 { 1256 ARMCPU *cpu = ARM_CPU(obj); 1257 set_feature(&cpu->env, ARM_FEATURE_V7); 1258 set_feature(&cpu->env, ARM_FEATURE_M); 1259 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1260 cpu->midr = 0x410fc231; 1261 cpu->pmsav7_dregion = 8; 1262 cpu->id_pfr0 = 0x00000030; 1263 cpu->id_pfr1 = 0x00000200; 1264 cpu->id_dfr0 = 0x00100000; 1265 cpu->id_afr0 = 0x00000000; 1266 cpu->id_mmfr0 = 0x00000030; 1267 cpu->id_mmfr1 = 0x00000000; 1268 cpu->id_mmfr2 = 0x00000000; 1269 cpu->id_mmfr3 = 0x00000000; 1270 cpu->id_isar0 = 0x01141110; 1271 cpu->id_isar1 = 0x02111000; 1272 cpu->id_isar2 = 0x21112231; 1273 cpu->id_isar3 = 0x01111110; 1274 cpu->id_isar4 = 0x01310102; 1275 cpu->id_isar5 = 0x00000000; 1276 cpu->id_isar6 = 0x00000000; 1277 } 1278 1279 static void cortex_m4_initfn(Object *obj) 1280 { 1281 ARMCPU *cpu = ARM_CPU(obj); 1282 1283 set_feature(&cpu->env, ARM_FEATURE_V7); 1284 set_feature(&cpu->env, ARM_FEATURE_M); 1285 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1286 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1287 cpu->midr = 0x410fc240; /* r0p0 */ 1288 cpu->pmsav7_dregion = 8; 1289 cpu->id_pfr0 = 0x00000030; 1290 cpu->id_pfr1 = 0x00000200; 1291 cpu->id_dfr0 = 0x00100000; 1292 cpu->id_afr0 = 0x00000000; 1293 cpu->id_mmfr0 = 0x00000030; 1294 cpu->id_mmfr1 = 0x00000000; 1295 cpu->id_mmfr2 = 0x00000000; 1296 cpu->id_mmfr3 = 0x00000000; 1297 cpu->id_isar0 = 0x01141110; 1298 cpu->id_isar1 = 0x02111000; 1299 cpu->id_isar2 = 0x21112231; 1300 cpu->id_isar3 = 0x01111110; 1301 cpu->id_isar4 = 0x01310102; 1302 cpu->id_isar5 = 0x00000000; 1303 cpu->id_isar6 = 0x00000000; 1304 } 1305 1306 static void cortex_m33_initfn(Object *obj) 1307 { 1308 ARMCPU *cpu = ARM_CPU(obj); 1309 1310 set_feature(&cpu->env, ARM_FEATURE_V8); 1311 set_feature(&cpu->env, ARM_FEATURE_M); 1312 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1313 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); 1314 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1315 cpu->midr = 0x410fd213; /* r0p3 */ 1316 cpu->pmsav7_dregion = 16; 1317 cpu->sau_sregion = 8; 1318 cpu->id_pfr0 = 0x00000030; 1319 cpu->id_pfr1 = 0x00000210; 1320 cpu->id_dfr0 = 0x00200000; 1321 cpu->id_afr0 = 0x00000000; 1322 cpu->id_mmfr0 = 0x00101F40; 1323 cpu->id_mmfr1 = 0x00000000; 1324 cpu->id_mmfr2 = 0x01000000; 1325 cpu->id_mmfr3 = 0x00000000; 1326 cpu->id_isar0 = 0x01101110; 1327 cpu->id_isar1 = 0x02212000; 1328 cpu->id_isar2 = 0x20232232; 1329 cpu->id_isar3 = 0x01111131; 1330 cpu->id_isar4 = 0x01310132; 1331 cpu->id_isar5 = 0x00000000; 1332 cpu->id_isar6 = 0x00000000; 1333 cpu->clidr = 0x00000000; 1334 cpu->ctr = 0x8000c000; 1335 } 1336 1337 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1338 { 1339 CPUClass *cc = CPU_CLASS(oc); 1340 1341 #ifndef CONFIG_USER_ONLY 1342 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1343 #endif 1344 1345 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1346 } 1347 1348 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1349 /* Dummy the TCM region regs for the moment */ 1350 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1351 .access = PL1_RW, .type = ARM_CP_CONST }, 1352 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1353 .access = PL1_RW, .type = ARM_CP_CONST }, 1354 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 1355 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 1356 REGINFO_SENTINEL 1357 }; 1358 1359 static void cortex_r5_initfn(Object *obj) 1360 { 1361 ARMCPU *cpu = ARM_CPU(obj); 1362 1363 set_feature(&cpu->env, ARM_FEATURE_V7); 1364 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); 1365 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1366 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1367 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1368 cpu->midr = 0x411fc153; /* r1p3 */ 1369 cpu->id_pfr0 = 0x0131; 1370 cpu->id_pfr1 = 0x001; 1371 cpu->id_dfr0 = 0x010400; 1372 cpu->id_afr0 = 0x0; 1373 cpu->id_mmfr0 = 0x0210030; 1374 cpu->id_mmfr1 = 0x00000000; 1375 cpu->id_mmfr2 = 0x01200000; 1376 cpu->id_mmfr3 = 0x0211; 1377 cpu->id_isar0 = 0x2101111; 1378 cpu->id_isar1 = 0x13112111; 1379 cpu->id_isar2 = 0x21232141; 1380 cpu->id_isar3 = 0x01112131; 1381 cpu->id_isar4 = 0x0010142; 1382 cpu->id_isar5 = 0x0; 1383 cpu->id_isar6 = 0x0; 1384 cpu->mp_is_up = true; 1385 cpu->pmsav7_dregion = 16; 1386 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1387 } 1388 1389 static void cortex_r5f_initfn(Object *obj) 1390 { 1391 ARMCPU *cpu = ARM_CPU(obj); 1392 1393 cortex_r5_initfn(obj); 1394 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1395 } 1396 1397 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1398 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1399 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1400 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1401 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1402 REGINFO_SENTINEL 1403 }; 1404 1405 static void cortex_a8_initfn(Object *obj) 1406 { 1407 ARMCPU *cpu = ARM_CPU(obj); 1408 1409 cpu->dtb_compatible = "arm,cortex-a8"; 1410 set_feature(&cpu->env, ARM_FEATURE_V7); 1411 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1412 set_feature(&cpu->env, ARM_FEATURE_NEON); 1413 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1414 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1415 set_feature(&cpu->env, ARM_FEATURE_EL3); 1416 cpu->midr = 0x410fc080; 1417 cpu->reset_fpsid = 0x410330c0; 1418 cpu->mvfr0 = 0x11110222; 1419 cpu->mvfr1 = 0x00011111; 1420 cpu->ctr = 0x82048004; 1421 cpu->reset_sctlr = 0x00c50078; 1422 cpu->id_pfr0 = 0x1031; 1423 cpu->id_pfr1 = 0x11; 1424 cpu->id_dfr0 = 0x400; 1425 cpu->id_afr0 = 0; 1426 cpu->id_mmfr0 = 0x31100003; 1427 cpu->id_mmfr1 = 0x20000000; 1428 cpu->id_mmfr2 = 0x01202000; 1429 cpu->id_mmfr3 = 0x11; 1430 cpu->id_isar0 = 0x00101111; 1431 cpu->id_isar1 = 0x12112111; 1432 cpu->id_isar2 = 0x21232031; 1433 cpu->id_isar3 = 0x11112131; 1434 cpu->id_isar4 = 0x00111142; 1435 cpu->dbgdidr = 0x15141000; 1436 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1437 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1438 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1439 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1440 cpu->reset_auxcr = 2; 1441 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1442 } 1443 1444 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1445 /* power_control should be set to maximum latency. Again, 1446 * default to 0 and set by private hook 1447 */ 1448 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1449 .access = PL1_RW, .resetvalue = 0, 1450 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1451 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1452 .access = PL1_RW, .resetvalue = 0, 1453 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1454 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1455 .access = PL1_RW, .resetvalue = 0, 1456 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1457 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1458 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1459 /* TLB lockdown control */ 1460 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1461 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1462 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1463 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1464 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1465 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1466 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1467 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1468 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1469 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1470 REGINFO_SENTINEL 1471 }; 1472 1473 static void cortex_a9_initfn(Object *obj) 1474 { 1475 ARMCPU *cpu = ARM_CPU(obj); 1476 1477 cpu->dtb_compatible = "arm,cortex-a9"; 1478 set_feature(&cpu->env, ARM_FEATURE_V7); 1479 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1480 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); 1481 set_feature(&cpu->env, ARM_FEATURE_NEON); 1482 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1483 set_feature(&cpu->env, ARM_FEATURE_EL3); 1484 /* Note that A9 supports the MP extensions even for 1485 * A9UP and single-core A9MP (which are both different 1486 * and valid configurations; we don't model A9UP). 1487 */ 1488 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1489 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1490 cpu->midr = 0x410fc090; 1491 cpu->reset_fpsid = 0x41033090; 1492 cpu->mvfr0 = 0x11110222; 1493 cpu->mvfr1 = 0x01111111; 1494 cpu->ctr = 0x80038003; 1495 cpu->reset_sctlr = 0x00c50078; 1496 cpu->id_pfr0 = 0x1031; 1497 cpu->id_pfr1 = 0x11; 1498 cpu->id_dfr0 = 0x000; 1499 cpu->id_afr0 = 0; 1500 cpu->id_mmfr0 = 0x00100103; 1501 cpu->id_mmfr1 = 0x20000000; 1502 cpu->id_mmfr2 = 0x01230000; 1503 cpu->id_mmfr3 = 0x00002111; 1504 cpu->id_isar0 = 0x00101111; 1505 cpu->id_isar1 = 0x13112111; 1506 cpu->id_isar2 = 0x21232041; 1507 cpu->id_isar3 = 0x11112131; 1508 cpu->id_isar4 = 0x00111142; 1509 cpu->dbgdidr = 0x35141000; 1510 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1511 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1512 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1513 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1514 } 1515 1516 #ifndef CONFIG_USER_ONLY 1517 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1518 { 1519 /* Linux wants the number of processors from here. 1520 * Might as well set the interrupt-controller bit too. 1521 */ 1522 return ((smp_cpus - 1) << 24) | (1 << 23); 1523 } 1524 #endif 1525 1526 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1527 #ifndef CONFIG_USER_ONLY 1528 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1529 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1530 .writefn = arm_cp_write_ignore, }, 1531 #endif 1532 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1533 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1534 REGINFO_SENTINEL 1535 }; 1536 1537 static void cortex_a7_initfn(Object *obj) 1538 { 1539 ARMCPU *cpu = ARM_CPU(obj); 1540 1541 cpu->dtb_compatible = "arm,cortex-a7"; 1542 set_feature(&cpu->env, ARM_FEATURE_V7VE); 1543 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1544 set_feature(&cpu->env, ARM_FEATURE_NEON); 1545 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1546 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1547 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1548 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1549 set_feature(&cpu->env, ARM_FEATURE_EL3); 1550 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1551 cpu->midr = 0x410fc075; 1552 cpu->reset_fpsid = 0x41023075; 1553 cpu->mvfr0 = 0x10110222; 1554 cpu->mvfr1 = 0x11111111; 1555 cpu->ctr = 0x84448003; 1556 cpu->reset_sctlr = 0x00c50078; 1557 cpu->id_pfr0 = 0x00001131; 1558 cpu->id_pfr1 = 0x00011011; 1559 cpu->id_dfr0 = 0x02010555; 1560 cpu->pmceid0 = 0x00000000; 1561 cpu->pmceid1 = 0x00000000; 1562 cpu->id_afr0 = 0x00000000; 1563 cpu->id_mmfr0 = 0x10101105; 1564 cpu->id_mmfr1 = 0x40000000; 1565 cpu->id_mmfr2 = 0x01240000; 1566 cpu->id_mmfr3 = 0x02102211; 1567 cpu->id_isar0 = 0x01101110; 1568 cpu->id_isar1 = 0x13112111; 1569 cpu->id_isar2 = 0x21232041; 1570 cpu->id_isar3 = 0x11112131; 1571 cpu->id_isar4 = 0x10011142; 1572 cpu->dbgdidr = 0x3515f005; 1573 cpu->clidr = 0x0a200023; 1574 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1575 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1576 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1577 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1578 } 1579 1580 static void cortex_a15_initfn(Object *obj) 1581 { 1582 ARMCPU *cpu = ARM_CPU(obj); 1583 1584 cpu->dtb_compatible = "arm,cortex-a15"; 1585 set_feature(&cpu->env, ARM_FEATURE_V7VE); 1586 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1587 set_feature(&cpu->env, ARM_FEATURE_NEON); 1588 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1589 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1590 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1591 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1592 set_feature(&cpu->env, ARM_FEATURE_EL3); 1593 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1594 cpu->midr = 0x412fc0f1; 1595 cpu->reset_fpsid = 0x410430f0; 1596 cpu->mvfr0 = 0x10110222; 1597 cpu->mvfr1 = 0x11111111; 1598 cpu->ctr = 0x8444c004; 1599 cpu->reset_sctlr = 0x00c50078; 1600 cpu->id_pfr0 = 0x00001131; 1601 cpu->id_pfr1 = 0x00011011; 1602 cpu->id_dfr0 = 0x02010555; 1603 cpu->pmceid0 = 0x0000000; 1604 cpu->pmceid1 = 0x00000000; 1605 cpu->id_afr0 = 0x00000000; 1606 cpu->id_mmfr0 = 0x10201105; 1607 cpu->id_mmfr1 = 0x20000000; 1608 cpu->id_mmfr2 = 0x01240000; 1609 cpu->id_mmfr3 = 0x02102211; 1610 cpu->id_isar0 = 0x02101110; 1611 cpu->id_isar1 = 0x13112111; 1612 cpu->id_isar2 = 0x21232041; 1613 cpu->id_isar3 = 0x11112131; 1614 cpu->id_isar4 = 0x10011142; 1615 cpu->dbgdidr = 0x3515f021; 1616 cpu->clidr = 0x0a200023; 1617 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1618 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1619 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1620 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 1621 } 1622 1623 static void ti925t_initfn(Object *obj) 1624 { 1625 ARMCPU *cpu = ARM_CPU(obj); 1626 set_feature(&cpu->env, ARM_FEATURE_V4T); 1627 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 1628 cpu->midr = ARM_CPUID_TI925T; 1629 cpu->ctr = 0x5109149; 1630 cpu->reset_sctlr = 0x00000070; 1631 } 1632 1633 static void sa1100_initfn(Object *obj) 1634 { 1635 ARMCPU *cpu = ARM_CPU(obj); 1636 1637 cpu->dtb_compatible = "intel,sa1100"; 1638 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1639 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1640 cpu->midr = 0x4401A11B; 1641 cpu->reset_sctlr = 0x00000070; 1642 } 1643 1644 static void sa1110_initfn(Object *obj) 1645 { 1646 ARMCPU *cpu = ARM_CPU(obj); 1647 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1648 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1649 cpu->midr = 0x6901B119; 1650 cpu->reset_sctlr = 0x00000070; 1651 } 1652 1653 static void pxa250_initfn(Object *obj) 1654 { 1655 ARMCPU *cpu = ARM_CPU(obj); 1656 1657 cpu->dtb_compatible = "marvell,xscale"; 1658 set_feature(&cpu->env, ARM_FEATURE_V5); 1659 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1660 cpu->midr = 0x69052100; 1661 cpu->ctr = 0xd172172; 1662 cpu->reset_sctlr = 0x00000078; 1663 } 1664 1665 static void pxa255_initfn(Object *obj) 1666 { 1667 ARMCPU *cpu = ARM_CPU(obj); 1668 1669 cpu->dtb_compatible = "marvell,xscale"; 1670 set_feature(&cpu->env, ARM_FEATURE_V5); 1671 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1672 cpu->midr = 0x69052d00; 1673 cpu->ctr = 0xd172172; 1674 cpu->reset_sctlr = 0x00000078; 1675 } 1676 1677 static void pxa260_initfn(Object *obj) 1678 { 1679 ARMCPU *cpu = ARM_CPU(obj); 1680 1681 cpu->dtb_compatible = "marvell,xscale"; 1682 set_feature(&cpu->env, ARM_FEATURE_V5); 1683 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1684 cpu->midr = 0x69052903; 1685 cpu->ctr = 0xd172172; 1686 cpu->reset_sctlr = 0x00000078; 1687 } 1688 1689 static void pxa261_initfn(Object *obj) 1690 { 1691 ARMCPU *cpu = ARM_CPU(obj); 1692 1693 cpu->dtb_compatible = "marvell,xscale"; 1694 set_feature(&cpu->env, ARM_FEATURE_V5); 1695 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1696 cpu->midr = 0x69052d05; 1697 cpu->ctr = 0xd172172; 1698 cpu->reset_sctlr = 0x00000078; 1699 } 1700 1701 static void pxa262_initfn(Object *obj) 1702 { 1703 ARMCPU *cpu = ARM_CPU(obj); 1704 1705 cpu->dtb_compatible = "marvell,xscale"; 1706 set_feature(&cpu->env, ARM_FEATURE_V5); 1707 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1708 cpu->midr = 0x69052d06; 1709 cpu->ctr = 0xd172172; 1710 cpu->reset_sctlr = 0x00000078; 1711 } 1712 1713 static void pxa270a0_initfn(Object *obj) 1714 { 1715 ARMCPU *cpu = ARM_CPU(obj); 1716 1717 cpu->dtb_compatible = "marvell,xscale"; 1718 set_feature(&cpu->env, ARM_FEATURE_V5); 1719 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1720 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1721 cpu->midr = 0x69054110; 1722 cpu->ctr = 0xd172172; 1723 cpu->reset_sctlr = 0x00000078; 1724 } 1725 1726 static void pxa270a1_initfn(Object *obj) 1727 { 1728 ARMCPU *cpu = ARM_CPU(obj); 1729 1730 cpu->dtb_compatible = "marvell,xscale"; 1731 set_feature(&cpu->env, ARM_FEATURE_V5); 1732 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1733 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1734 cpu->midr = 0x69054111; 1735 cpu->ctr = 0xd172172; 1736 cpu->reset_sctlr = 0x00000078; 1737 } 1738 1739 static void pxa270b0_initfn(Object *obj) 1740 { 1741 ARMCPU *cpu = ARM_CPU(obj); 1742 1743 cpu->dtb_compatible = "marvell,xscale"; 1744 set_feature(&cpu->env, ARM_FEATURE_V5); 1745 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1746 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1747 cpu->midr = 0x69054112; 1748 cpu->ctr = 0xd172172; 1749 cpu->reset_sctlr = 0x00000078; 1750 } 1751 1752 static void pxa270b1_initfn(Object *obj) 1753 { 1754 ARMCPU *cpu = ARM_CPU(obj); 1755 1756 cpu->dtb_compatible = "marvell,xscale"; 1757 set_feature(&cpu->env, ARM_FEATURE_V5); 1758 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1759 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1760 cpu->midr = 0x69054113; 1761 cpu->ctr = 0xd172172; 1762 cpu->reset_sctlr = 0x00000078; 1763 } 1764 1765 static void pxa270c0_initfn(Object *obj) 1766 { 1767 ARMCPU *cpu = ARM_CPU(obj); 1768 1769 cpu->dtb_compatible = "marvell,xscale"; 1770 set_feature(&cpu->env, ARM_FEATURE_V5); 1771 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1772 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1773 cpu->midr = 0x69054114; 1774 cpu->ctr = 0xd172172; 1775 cpu->reset_sctlr = 0x00000078; 1776 } 1777 1778 static void pxa270c5_initfn(Object *obj) 1779 { 1780 ARMCPU *cpu = ARM_CPU(obj); 1781 1782 cpu->dtb_compatible = "marvell,xscale"; 1783 set_feature(&cpu->env, ARM_FEATURE_V5); 1784 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1785 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1786 cpu->midr = 0x69054117; 1787 cpu->ctr = 0xd172172; 1788 cpu->reset_sctlr = 0x00000078; 1789 } 1790 1791 #ifndef TARGET_AARCH64 1792 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 1793 * otherwise, a CPU with as many features enabled as our emulation supports. 1794 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; 1795 * this only needs to handle 32 bits. 1796 */ 1797 static void arm_max_initfn(Object *obj) 1798 { 1799 ARMCPU *cpu = ARM_CPU(obj); 1800 1801 if (kvm_enabled()) { 1802 kvm_arm_set_cpu_features_from_host(cpu); 1803 } else { 1804 cortex_a15_initfn(obj); 1805 #ifdef CONFIG_USER_ONLY 1806 /* We don't set these in system emulation mode for the moment, 1807 * since we don't correctly set the ID registers to advertise them, 1808 */ 1809 set_feature(&cpu->env, ARM_FEATURE_V8); 1810 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 1811 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 1812 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 1813 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 1814 set_feature(&cpu->env, ARM_FEATURE_CRC); 1815 set_feature(&cpu->env, ARM_FEATURE_V8_RDM); 1816 set_feature(&cpu->env, ARM_FEATURE_V8_DOTPROD); 1817 set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); 1818 #endif 1819 } 1820 } 1821 #endif 1822 1823 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 1824 1825 typedef struct ARMCPUInfo { 1826 const char *name; 1827 void (*initfn)(Object *obj); 1828 void (*class_init)(ObjectClass *oc, void *data); 1829 } ARMCPUInfo; 1830 1831 static const ARMCPUInfo arm_cpus[] = { 1832 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1833 { .name = "arm926", .initfn = arm926_initfn }, 1834 { .name = "arm946", .initfn = arm946_initfn }, 1835 { .name = "arm1026", .initfn = arm1026_initfn }, 1836 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1837 * older core than plain "arm1136". In particular this does not 1838 * have the v6K features. 1839 */ 1840 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1841 { .name = "arm1136", .initfn = arm1136_initfn }, 1842 { .name = "arm1176", .initfn = arm1176_initfn }, 1843 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1844 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 1845 .class_init = arm_v7m_class_init }, 1846 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 1847 .class_init = arm_v7m_class_init }, 1848 { .name = "cortex-m33", .initfn = cortex_m33_initfn, 1849 .class_init = arm_v7m_class_init }, 1850 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1851 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, 1852 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1853 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1854 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1855 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1856 { .name = "ti925t", .initfn = ti925t_initfn }, 1857 { .name = "sa1100", .initfn = sa1100_initfn }, 1858 { .name = "sa1110", .initfn = sa1110_initfn }, 1859 { .name = "pxa250", .initfn = pxa250_initfn }, 1860 { .name = "pxa255", .initfn = pxa255_initfn }, 1861 { .name = "pxa260", .initfn = pxa260_initfn }, 1862 { .name = "pxa261", .initfn = pxa261_initfn }, 1863 { .name = "pxa262", .initfn = pxa262_initfn }, 1864 /* "pxa270" is an alias for "pxa270-a0" */ 1865 { .name = "pxa270", .initfn = pxa270a0_initfn }, 1866 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 1867 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 1868 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 1869 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 1870 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 1871 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 1872 #ifndef TARGET_AARCH64 1873 { .name = "max", .initfn = arm_max_initfn }, 1874 #endif 1875 #ifdef CONFIG_USER_ONLY 1876 { .name = "any", .initfn = arm_max_initfn }, 1877 #endif 1878 #endif 1879 { .name = NULL } 1880 }; 1881 1882 static Property arm_cpu_properties[] = { 1883 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 1884 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 1885 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 1886 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 1887 mp_affinity, ARM64_AFFINITY_INVALID), 1888 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 1889 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 1890 DEFINE_PROP_END_OF_LIST() 1891 }; 1892 1893 #ifdef CONFIG_USER_ONLY 1894 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, 1895 int rw, int mmu_idx) 1896 { 1897 ARMCPU *cpu = ARM_CPU(cs); 1898 CPUARMState *env = &cpu->env; 1899 1900 env->exception.vaddress = address; 1901 if (rw == 2) { 1902 cs->exception_index = EXCP_PREFETCH_ABORT; 1903 } else { 1904 cs->exception_index = EXCP_DATA_ABORT; 1905 } 1906 return 1; 1907 } 1908 #endif 1909 1910 static gchar *arm_gdb_arch_name(CPUState *cs) 1911 { 1912 ARMCPU *cpu = ARM_CPU(cs); 1913 CPUARMState *env = &cpu->env; 1914 1915 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 1916 return g_strdup("iwmmxt"); 1917 } 1918 return g_strdup("arm"); 1919 } 1920 1921 static void arm_cpu_class_init(ObjectClass *oc, void *data) 1922 { 1923 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1924 CPUClass *cc = CPU_CLASS(acc); 1925 DeviceClass *dc = DEVICE_CLASS(oc); 1926 1927 device_class_set_parent_realize(dc, arm_cpu_realizefn, 1928 &acc->parent_realize); 1929 dc->props = arm_cpu_properties; 1930 1931 acc->parent_reset = cc->reset; 1932 cc->reset = arm_cpu_reset; 1933 1934 cc->class_by_name = arm_cpu_class_by_name; 1935 cc->has_work = arm_cpu_has_work; 1936 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 1937 cc->dump_state = arm_cpu_dump_state; 1938 cc->set_pc = arm_cpu_set_pc; 1939 cc->gdb_read_register = arm_cpu_gdb_read_register; 1940 cc->gdb_write_register = arm_cpu_gdb_write_register; 1941 #ifdef CONFIG_USER_ONLY 1942 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; 1943 #else 1944 cc->do_interrupt = arm_cpu_do_interrupt; 1945 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 1946 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 1947 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 1948 cc->asidx_from_attrs = arm_asidx_from_attrs; 1949 cc->vmsd = &vmstate_arm_cpu; 1950 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 1951 cc->write_elf64_note = arm_cpu_write_elf64_note; 1952 cc->write_elf32_note = arm_cpu_write_elf32_note; 1953 #endif 1954 cc->gdb_num_core_regs = 26; 1955 cc->gdb_core_xml_file = "arm-core.xml"; 1956 cc->gdb_arch_name = arm_gdb_arch_name; 1957 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 1958 cc->gdb_stop_before_watchpoint = true; 1959 cc->debug_excp_handler = arm_debug_excp_handler; 1960 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 1961 #if !defined(CONFIG_USER_ONLY) 1962 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 1963 #endif 1964 1965 cc->disas_set_info = arm_disas_set_info; 1966 #ifdef CONFIG_TCG 1967 cc->tcg_initialize = arm_translate_init; 1968 #endif 1969 } 1970 1971 #ifdef CONFIG_KVM 1972 static void arm_host_initfn(Object *obj) 1973 { 1974 ARMCPU *cpu = ARM_CPU(obj); 1975 1976 kvm_arm_set_cpu_features_from_host(cpu); 1977 } 1978 1979 static const TypeInfo host_arm_cpu_type_info = { 1980 .name = TYPE_ARM_HOST_CPU, 1981 #ifdef TARGET_AARCH64 1982 .parent = TYPE_AARCH64_CPU, 1983 #else 1984 .parent = TYPE_ARM_CPU, 1985 #endif 1986 .instance_init = arm_host_initfn, 1987 }; 1988 1989 #endif 1990 1991 static void cpu_register(const ARMCPUInfo *info) 1992 { 1993 TypeInfo type_info = { 1994 .parent = TYPE_ARM_CPU, 1995 .instance_size = sizeof(ARMCPU), 1996 .instance_init = info->initfn, 1997 .class_size = sizeof(ARMCPUClass), 1998 .class_init = info->class_init, 1999 }; 2000 2001 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2002 type_register(&type_info); 2003 g_free((void *)type_info.name); 2004 } 2005 2006 static const TypeInfo arm_cpu_type_info = { 2007 .name = TYPE_ARM_CPU, 2008 .parent = TYPE_CPU, 2009 .instance_size = sizeof(ARMCPU), 2010 .instance_init = arm_cpu_initfn, 2011 .instance_post_init = arm_cpu_post_init, 2012 .instance_finalize = arm_cpu_finalizefn, 2013 .abstract = true, 2014 .class_size = sizeof(ARMCPUClass), 2015 .class_init = arm_cpu_class_init, 2016 }; 2017 2018 static const TypeInfo idau_interface_type_info = { 2019 .name = TYPE_IDAU_INTERFACE, 2020 .parent = TYPE_INTERFACE, 2021 .class_size = sizeof(IDAUInterfaceClass), 2022 }; 2023 2024 static void arm_cpu_register_types(void) 2025 { 2026 const ARMCPUInfo *info = arm_cpus; 2027 2028 type_register_static(&arm_cpu_type_info); 2029 type_register_static(&idau_interface_type_info); 2030 2031 while (info->name) { 2032 cpu_register(info); 2033 info++; 2034 } 2035 2036 #ifdef CONFIG_KVM 2037 type_register_static(&host_arm_cpu_type_info); 2038 #endif 2039 } 2040 2041 type_init(arm_cpu_register_types) 2042