1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/error-report.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "qemu-common.h" 27 #include "exec/exec-all.h" 28 #include "hw/qdev-properties.h" 29 #if !defined(CONFIG_USER_ONLY) 30 #include "hw/loader.h" 31 #endif 32 #include "hw/arm/arm.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/hw_accel.h" 35 #include "kvm_arm.h" 36 37 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 38 { 39 ARMCPU *cpu = ARM_CPU(cs); 40 41 cpu->env.regs[15] = value; 42 } 43 44 static bool arm_cpu_has_work(CPUState *cs) 45 { 46 ARMCPU *cpu = ARM_CPU(cs); 47 48 return (cpu->power_state != PSCI_OFF) 49 && cs->interrupt_request & 50 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 51 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 52 | CPU_INTERRUPT_EXITTB); 53 } 54 55 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 56 void *opaque) 57 { 58 /* We currently only support registering a single hook function */ 59 assert(!cpu->el_change_hook); 60 cpu->el_change_hook = hook; 61 cpu->el_change_hook_opaque = opaque; 62 } 63 64 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 65 { 66 /* Reset a single ARMCPRegInfo register */ 67 ARMCPRegInfo *ri = value; 68 ARMCPU *cpu = opaque; 69 70 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 71 return; 72 } 73 74 if (ri->resetfn) { 75 ri->resetfn(&cpu->env, ri); 76 return; 77 } 78 79 /* A zero offset is never possible as it would be regs[0] 80 * so we use it to indicate that reset is being handled elsewhere. 81 * This is basically only used for fields in non-core coprocessors 82 * (like the pxa2xx ones). 83 */ 84 if (!ri->fieldoffset) { 85 return; 86 } 87 88 if (cpreg_field_is_64bit(ri)) { 89 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 90 } else { 91 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 92 } 93 } 94 95 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 96 { 97 /* Purely an assertion check: we've already done reset once, 98 * so now check that running the reset for the cpreg doesn't 99 * change its value. This traps bugs where two different cpregs 100 * both try to reset the same state field but to different values. 101 */ 102 ARMCPRegInfo *ri = value; 103 ARMCPU *cpu = opaque; 104 uint64_t oldvalue, newvalue; 105 106 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 107 return; 108 } 109 110 oldvalue = read_raw_cp_reg(&cpu->env, ri); 111 cp_reg_reset(key, value, opaque); 112 newvalue = read_raw_cp_reg(&cpu->env, ri); 113 assert(oldvalue == newvalue); 114 } 115 116 /* CPUClass::reset() */ 117 static void arm_cpu_reset(CPUState *s) 118 { 119 ARMCPU *cpu = ARM_CPU(s); 120 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 121 CPUARMState *env = &cpu->env; 122 123 acc->parent_reset(s); 124 125 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 126 127 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 128 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 129 130 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 131 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; 132 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; 133 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; 134 135 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 136 s->halted = cpu->start_powered_off; 137 138 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 139 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 140 } 141 142 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 143 /* 64 bit CPUs always start in 64 bit mode */ 144 env->aarch64 = 1; 145 #if defined(CONFIG_USER_ONLY) 146 env->pstate = PSTATE_MODE_EL0t; 147 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 148 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 149 /* and to the FP/Neon instructions */ 150 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 151 #else 152 /* Reset into the highest available EL */ 153 if (arm_feature(env, ARM_FEATURE_EL3)) { 154 env->pstate = PSTATE_MODE_EL3h; 155 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 156 env->pstate = PSTATE_MODE_EL2h; 157 } else { 158 env->pstate = PSTATE_MODE_EL1h; 159 } 160 env->pc = cpu->rvbar; 161 #endif 162 } else { 163 #if defined(CONFIG_USER_ONLY) 164 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 165 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 166 #endif 167 } 168 169 #if defined(CONFIG_USER_ONLY) 170 env->uncached_cpsr = ARM_CPU_MODE_USR; 171 /* For user mode we must enable access to coprocessors */ 172 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 173 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 174 env->cp15.c15_cpar = 3; 175 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 176 env->cp15.c15_cpar = 1; 177 } 178 #else 179 /* SVC mode with interrupts disabled. */ 180 env->uncached_cpsr = ARM_CPU_MODE_SVC; 181 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 182 183 if (arm_feature(env, ARM_FEATURE_M)) { 184 uint32_t initial_msp; /* Loaded from 0x0 */ 185 uint32_t initial_pc; /* Loaded from 0x4 */ 186 uint8_t *rom; 187 188 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 189 env->v7m.secure = true; 190 } 191 192 /* The reset value of this bit is IMPDEF, but ARM recommends 193 * that it resets to 1, so QEMU always does that rather than making 194 * it dependent on CPU model. 195 */ 196 env->v7m.ccr = R_V7M_CCR_STKALIGN_MASK; 197 198 /* Unlike A/R profile, M profile defines the reset LR value */ 199 env->regs[14] = 0xffffffff; 200 201 /* Load the initial SP and PC from the vector table at address 0 */ 202 rom = rom_ptr(0); 203 if (rom) { 204 /* Address zero is covered by ROM which hasn't yet been 205 * copied into physical memory. 206 */ 207 initial_msp = ldl_p(rom); 208 initial_pc = ldl_p(rom + 4); 209 } else { 210 /* Address zero not covered by a ROM blob, or the ROM blob 211 * is in non-modifiable memory and this is a second reset after 212 * it got copied into memory. In the latter case, rom_ptr 213 * will return a NULL pointer and we should use ldl_phys instead. 214 */ 215 initial_msp = ldl_phys(s->as, 0); 216 initial_pc = ldl_phys(s->as, 4); 217 } 218 219 env->regs[13] = initial_msp & 0xFFFFFFFC; 220 env->regs[15] = initial_pc & ~1; 221 env->thumb = initial_pc & 1; 222 } 223 224 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 225 * executing as AArch32 then check if highvecs are enabled and 226 * adjust the PC accordingly. 227 */ 228 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 229 env->regs[15] = 0xFFFF0000; 230 } 231 232 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 233 #endif 234 235 if (arm_feature(env, ARM_FEATURE_PMSA)) { 236 if (cpu->pmsav7_dregion > 0) { 237 if (arm_feature(env, ARM_FEATURE_V8)) { 238 memset(env->pmsav8.rbar, 0, 239 sizeof(*env->pmsav8.rbar) * cpu->pmsav7_dregion); 240 memset(env->pmsav8.rlar, 0, 241 sizeof(*env->pmsav8.rlar) * cpu->pmsav7_dregion); 242 } else if (arm_feature(env, ARM_FEATURE_V7)) { 243 memset(env->pmsav7.drbar, 0, 244 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 245 memset(env->pmsav7.drsr, 0, 246 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 247 memset(env->pmsav7.dracr, 0, 248 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 249 } 250 } 251 env->pmsav7.rnr = 0; 252 env->pmsav8.mair0[M_REG_NS] = 0; 253 env->pmsav8.mair0[M_REG_S] = 0; 254 env->pmsav8.mair1[M_REG_NS] = 0; 255 env->pmsav8.mair1[M_REG_S] = 0; 256 } 257 258 set_flush_to_zero(1, &env->vfp.standard_fp_status); 259 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 260 set_default_nan_mode(1, &env->vfp.standard_fp_status); 261 set_float_detect_tininess(float_tininess_before_rounding, 262 &env->vfp.fp_status); 263 set_float_detect_tininess(float_tininess_before_rounding, 264 &env->vfp.standard_fp_status); 265 #ifndef CONFIG_USER_ONLY 266 if (kvm_enabled()) { 267 kvm_arm_reset_vcpu(cpu); 268 } 269 #endif 270 271 hw_breakpoint_update_all(cpu); 272 hw_watchpoint_update_all(cpu); 273 } 274 275 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 276 { 277 CPUClass *cc = CPU_GET_CLASS(cs); 278 CPUARMState *env = cs->env_ptr; 279 uint32_t cur_el = arm_current_el(env); 280 bool secure = arm_is_secure(env); 281 uint32_t target_el; 282 uint32_t excp_idx; 283 bool ret = false; 284 285 if (interrupt_request & CPU_INTERRUPT_FIQ) { 286 excp_idx = EXCP_FIQ; 287 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 288 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 289 cs->exception_index = excp_idx; 290 env->exception.target_el = target_el; 291 cc->do_interrupt(cs); 292 ret = true; 293 } 294 } 295 if (interrupt_request & CPU_INTERRUPT_HARD) { 296 excp_idx = EXCP_IRQ; 297 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 298 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 299 cs->exception_index = excp_idx; 300 env->exception.target_el = target_el; 301 cc->do_interrupt(cs); 302 ret = true; 303 } 304 } 305 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 306 excp_idx = EXCP_VIRQ; 307 target_el = 1; 308 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 309 cs->exception_index = excp_idx; 310 env->exception.target_el = target_el; 311 cc->do_interrupt(cs); 312 ret = true; 313 } 314 } 315 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 316 excp_idx = EXCP_VFIQ; 317 target_el = 1; 318 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 319 cs->exception_index = excp_idx; 320 env->exception.target_el = target_el; 321 cc->do_interrupt(cs); 322 ret = true; 323 } 324 } 325 326 return ret; 327 } 328 329 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 330 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 331 { 332 CPUClass *cc = CPU_GET_CLASS(cs); 333 ARMCPU *cpu = ARM_CPU(cs); 334 CPUARMState *env = &cpu->env; 335 bool ret = false; 336 337 /* ARMv7-M interrupt masking works differently than -A or -R. 338 * There is no FIQ/IRQ distinction. Instead of I and F bits 339 * masking FIQ and IRQ interrupts, an exception is taken only 340 * if it is higher priority than the current execution priority 341 * (which depends on state like BASEPRI, FAULTMASK and the 342 * currently active exception). 343 */ 344 if (interrupt_request & CPU_INTERRUPT_HARD 345 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 346 cs->exception_index = EXCP_IRQ; 347 cc->do_interrupt(cs); 348 ret = true; 349 } 350 return ret; 351 } 352 #endif 353 354 #ifndef CONFIG_USER_ONLY 355 static void arm_cpu_set_irq(void *opaque, int irq, int level) 356 { 357 ARMCPU *cpu = opaque; 358 CPUARMState *env = &cpu->env; 359 CPUState *cs = CPU(cpu); 360 static const int mask[] = { 361 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 362 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 363 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 364 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 365 }; 366 367 switch (irq) { 368 case ARM_CPU_VIRQ: 369 case ARM_CPU_VFIQ: 370 assert(arm_feature(env, ARM_FEATURE_EL2)); 371 /* fall through */ 372 case ARM_CPU_IRQ: 373 case ARM_CPU_FIQ: 374 if (level) { 375 cpu_interrupt(cs, mask[irq]); 376 } else { 377 cpu_reset_interrupt(cs, mask[irq]); 378 } 379 break; 380 default: 381 g_assert_not_reached(); 382 } 383 } 384 385 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 386 { 387 #ifdef CONFIG_KVM 388 ARMCPU *cpu = opaque; 389 CPUState *cs = CPU(cpu); 390 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 391 392 switch (irq) { 393 case ARM_CPU_IRQ: 394 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 395 break; 396 case ARM_CPU_FIQ: 397 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 398 break; 399 default: 400 g_assert_not_reached(); 401 } 402 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 403 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 404 #endif 405 } 406 407 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 408 { 409 ARMCPU *cpu = ARM_CPU(cs); 410 CPUARMState *env = &cpu->env; 411 412 cpu_synchronize_state(cs); 413 return arm_cpu_data_is_big_endian(env); 414 } 415 416 #endif 417 418 static inline void set_feature(CPUARMState *env, int feature) 419 { 420 env->features |= 1ULL << feature; 421 } 422 423 static inline void unset_feature(CPUARMState *env, int feature) 424 { 425 env->features &= ~(1ULL << feature); 426 } 427 428 static int 429 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 430 { 431 return print_insn_arm(pc | 1, info); 432 } 433 434 static int arm_read_memory_func(bfd_vma memaddr, bfd_byte *b, 435 int length, struct disassemble_info *info) 436 { 437 assert(info->read_memory_inner_func); 438 assert((info->flags & INSN_ARM_BE32) == 0 || length == 2 || length == 4); 439 440 if ((info->flags & INSN_ARM_BE32) != 0 && length == 2) { 441 assert(info->endian == BFD_ENDIAN_LITTLE); 442 return info->read_memory_inner_func(memaddr ^ 2, (bfd_byte *)b, 2, 443 info); 444 } else { 445 return info->read_memory_inner_func(memaddr, b, length, info); 446 } 447 } 448 449 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 450 { 451 ARMCPU *ac = ARM_CPU(cpu); 452 CPUARMState *env = &ac->env; 453 454 if (is_a64(env)) { 455 /* We might not be compiled with the A64 disassembler 456 * because it needs a C++ compiler. Leave print_insn 457 * unset in this case to use the caller default behaviour. 458 */ 459 #if defined(CONFIG_ARM_A64_DIS) 460 info->print_insn = print_insn_arm_a64; 461 #endif 462 } else if (env->thumb) { 463 info->print_insn = print_insn_thumb1; 464 } else { 465 info->print_insn = print_insn_arm; 466 } 467 if (bswap_code(arm_sctlr_b(env))) { 468 #ifdef TARGET_WORDS_BIGENDIAN 469 info->endian = BFD_ENDIAN_LITTLE; 470 #else 471 info->endian = BFD_ENDIAN_BIG; 472 #endif 473 } 474 if (info->read_memory_inner_func == NULL) { 475 info->read_memory_inner_func = info->read_memory_func; 476 info->read_memory_func = arm_read_memory_func; 477 } 478 info->flags &= ~INSN_ARM_BE32; 479 if (arm_sctlr_b(env)) { 480 info->flags |= INSN_ARM_BE32; 481 } 482 } 483 484 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 485 { 486 uint32_t Aff1 = idx / clustersz; 487 uint32_t Aff0 = idx % clustersz; 488 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 489 } 490 491 static void arm_cpu_initfn(Object *obj) 492 { 493 CPUState *cs = CPU(obj); 494 ARMCPU *cpu = ARM_CPU(obj); 495 static bool inited; 496 497 cs->env_ptr = &cpu->env; 498 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 499 g_free, g_free); 500 501 #ifndef CONFIG_USER_ONLY 502 /* Our inbound IRQ and FIQ lines */ 503 if (kvm_enabled()) { 504 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 505 * the same interface as non-KVM CPUs. 506 */ 507 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 508 } else { 509 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 510 } 511 512 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 513 arm_gt_ptimer_cb, cpu); 514 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 515 arm_gt_vtimer_cb, cpu); 516 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 517 arm_gt_htimer_cb, cpu); 518 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 519 arm_gt_stimer_cb, cpu); 520 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 521 ARRAY_SIZE(cpu->gt_timer_outputs)); 522 523 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 524 "gicv3-maintenance-interrupt", 1); 525 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 526 "pmu-interrupt", 1); 527 #endif 528 529 /* DTB consumers generally don't in fact care what the 'compatible' 530 * string is, so always provide some string and trust that a hypothetical 531 * picky DTB consumer will also provide a helpful error message. 532 */ 533 cpu->dtb_compatible = "qemu,unknown"; 534 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 535 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 536 537 if (tcg_enabled()) { 538 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 539 if (!inited) { 540 inited = true; 541 arm_translate_init(); 542 } 543 } 544 } 545 546 static Property arm_cpu_reset_cbar_property = 547 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 548 549 static Property arm_cpu_reset_hivecs_property = 550 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 551 552 static Property arm_cpu_rvbar_property = 553 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 554 555 static Property arm_cpu_has_el2_property = 556 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 557 558 static Property arm_cpu_has_el3_property = 559 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 560 561 static Property arm_cpu_cfgend_property = 562 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 563 564 /* use property name "pmu" to match other archs and virt tools */ 565 static Property arm_cpu_has_pmu_property = 566 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 567 568 static Property arm_cpu_has_mpu_property = 569 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 570 571 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 572 * because the CPU initfn will have already set cpu->pmsav7_dregion to 573 * the right value for that particular CPU type, and we don't want 574 * to override that with an incorrect constant value. 575 */ 576 static Property arm_cpu_pmsav7_dregion_property = 577 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 578 pmsav7_dregion, 579 qdev_prop_uint32, uint32_t); 580 581 static void arm_cpu_post_init(Object *obj) 582 { 583 ARMCPU *cpu = ARM_CPU(obj); 584 585 /* M profile implies PMSA. We have to do this here rather than 586 * in realize with the other feature-implication checks because 587 * we look at the PMSA bit to see if we should add some properties. 588 */ 589 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 590 set_feature(&cpu->env, ARM_FEATURE_PMSA); 591 } 592 593 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 594 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 595 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 596 &error_abort); 597 } 598 599 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 600 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 601 &error_abort); 602 } 603 604 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 605 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 606 &error_abort); 607 } 608 609 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 610 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 611 * prevent "has_el3" from existing on CPUs which cannot support EL3. 612 */ 613 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 614 &error_abort); 615 616 #ifndef CONFIG_USER_ONLY 617 object_property_add_link(obj, "secure-memory", 618 TYPE_MEMORY_REGION, 619 (Object **)&cpu->secure_memory, 620 qdev_prop_allow_set_link_before_realize, 621 OBJ_PROP_LINK_UNREF_ON_RELEASE, 622 &error_abort); 623 #endif 624 } 625 626 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 627 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 628 &error_abort); 629 } 630 631 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 632 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 633 &error_abort); 634 } 635 636 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 637 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 638 &error_abort); 639 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 640 qdev_property_add_static(DEVICE(obj), 641 &arm_cpu_pmsav7_dregion_property, 642 &error_abort); 643 } 644 } 645 646 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 647 &error_abort); 648 } 649 650 static void arm_cpu_finalizefn(Object *obj) 651 { 652 ARMCPU *cpu = ARM_CPU(obj); 653 g_hash_table_destroy(cpu->cp_regs); 654 } 655 656 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 657 { 658 CPUState *cs = CPU(dev); 659 ARMCPU *cpu = ARM_CPU(dev); 660 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 661 CPUARMState *env = &cpu->env; 662 int pagebits; 663 Error *local_err = NULL; 664 665 cpu_exec_realizefn(cs, &local_err); 666 if (local_err != NULL) { 667 error_propagate(errp, local_err); 668 return; 669 } 670 671 /* Some features automatically imply others: */ 672 if (arm_feature(env, ARM_FEATURE_V8)) { 673 set_feature(env, ARM_FEATURE_V7); 674 set_feature(env, ARM_FEATURE_ARM_DIV); 675 set_feature(env, ARM_FEATURE_LPAE); 676 } 677 if (arm_feature(env, ARM_FEATURE_V7)) { 678 set_feature(env, ARM_FEATURE_VAPA); 679 set_feature(env, ARM_FEATURE_THUMB2); 680 set_feature(env, ARM_FEATURE_MPIDR); 681 if (!arm_feature(env, ARM_FEATURE_M)) { 682 set_feature(env, ARM_FEATURE_V6K); 683 } else { 684 set_feature(env, ARM_FEATURE_V6); 685 } 686 687 /* Always define VBAR for V7 CPUs even if it doesn't exist in 688 * non-EL3 configs. This is needed by some legacy boards. 689 */ 690 set_feature(env, ARM_FEATURE_VBAR); 691 } 692 if (arm_feature(env, ARM_FEATURE_V6K)) { 693 set_feature(env, ARM_FEATURE_V6); 694 set_feature(env, ARM_FEATURE_MVFR); 695 } 696 if (arm_feature(env, ARM_FEATURE_V6)) { 697 set_feature(env, ARM_FEATURE_V5); 698 if (!arm_feature(env, ARM_FEATURE_M)) { 699 set_feature(env, ARM_FEATURE_AUXCR); 700 } 701 } 702 if (arm_feature(env, ARM_FEATURE_V5)) { 703 set_feature(env, ARM_FEATURE_V4T); 704 } 705 if (arm_feature(env, ARM_FEATURE_M)) { 706 set_feature(env, ARM_FEATURE_THUMB_DIV); 707 } 708 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { 709 set_feature(env, ARM_FEATURE_THUMB_DIV); 710 } 711 if (arm_feature(env, ARM_FEATURE_VFP4)) { 712 set_feature(env, ARM_FEATURE_VFP3); 713 set_feature(env, ARM_FEATURE_VFP_FP16); 714 } 715 if (arm_feature(env, ARM_FEATURE_VFP3)) { 716 set_feature(env, ARM_FEATURE_VFP); 717 } 718 if (arm_feature(env, ARM_FEATURE_LPAE)) { 719 set_feature(env, ARM_FEATURE_V7MP); 720 set_feature(env, ARM_FEATURE_PXN); 721 } 722 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 723 set_feature(env, ARM_FEATURE_CBAR); 724 } 725 if (arm_feature(env, ARM_FEATURE_THUMB2) && 726 !arm_feature(env, ARM_FEATURE_M)) { 727 set_feature(env, ARM_FEATURE_THUMB_DSP); 728 } 729 730 if (arm_feature(env, ARM_FEATURE_V7) && 731 !arm_feature(env, ARM_FEATURE_M) && 732 !arm_feature(env, ARM_FEATURE_PMSA)) { 733 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 734 * can use 4K pages. 735 */ 736 pagebits = 12; 737 } else { 738 /* For CPUs which might have tiny 1K pages, or which have an 739 * MPU and might have small region sizes, stick with 1K pages. 740 */ 741 pagebits = 10; 742 } 743 if (!set_preferred_target_page_bits(pagebits)) { 744 /* This can only ever happen for hotplugging a CPU, or if 745 * the board code incorrectly creates a CPU which it has 746 * promised via minimum_page_size that it will not. 747 */ 748 error_setg(errp, "This CPU requires a smaller page size than the " 749 "system is using"); 750 return; 751 } 752 753 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 754 * We don't support setting cluster ID ([16..23]) (known as Aff2 755 * in later ARM ARM versions), or any of the higher affinity level fields, 756 * so these bits always RAZ. 757 */ 758 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 759 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 760 ARM_DEFAULT_CPUS_PER_CLUSTER); 761 } 762 763 if (cpu->reset_hivecs) { 764 cpu->reset_sctlr |= (1 << 13); 765 } 766 767 if (cpu->cfgend) { 768 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 769 cpu->reset_sctlr |= SCTLR_EE; 770 } else { 771 cpu->reset_sctlr |= SCTLR_B; 772 } 773 } 774 775 if (!cpu->has_el3) { 776 /* If the has_el3 CPU property is disabled then we need to disable the 777 * feature. 778 */ 779 unset_feature(env, ARM_FEATURE_EL3); 780 781 /* Disable the security extension feature bits in the processor feature 782 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 783 */ 784 cpu->id_pfr1 &= ~0xf0; 785 cpu->id_aa64pfr0 &= ~0xf000; 786 } 787 788 if (!cpu->has_el2) { 789 unset_feature(env, ARM_FEATURE_EL2); 790 } 791 792 if (!cpu->has_pmu) { 793 unset_feature(env, ARM_FEATURE_PMU); 794 cpu->id_aa64dfr0 &= ~0xf00; 795 } 796 797 if (!arm_feature(env, ARM_FEATURE_EL2)) { 798 /* Disable the hypervisor feature bits in the processor feature 799 * registers if we don't have EL2. These are id_pfr1[15:12] and 800 * id_aa64pfr0_el1[11:8]. 801 */ 802 cpu->id_aa64pfr0 &= ~0xf00; 803 cpu->id_pfr1 &= ~0xf000; 804 } 805 806 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 807 * to false or by setting pmsav7-dregion to 0. 808 */ 809 if (!cpu->has_mpu) { 810 cpu->pmsav7_dregion = 0; 811 } 812 if (cpu->pmsav7_dregion == 0) { 813 cpu->has_mpu = false; 814 } 815 816 if (arm_feature(env, ARM_FEATURE_PMSA) && 817 arm_feature(env, ARM_FEATURE_V7)) { 818 uint32_t nr = cpu->pmsav7_dregion; 819 820 if (nr > 0xff) { 821 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 822 return; 823 } 824 825 if (nr) { 826 if (arm_feature(env, ARM_FEATURE_V8)) { 827 /* PMSAv8 */ 828 env->pmsav8.rbar = g_new0(uint32_t, nr); 829 env->pmsav8.rlar = g_new0(uint32_t, nr); 830 } else { 831 env->pmsav7.drbar = g_new0(uint32_t, nr); 832 env->pmsav7.drsr = g_new0(uint32_t, nr); 833 env->pmsav7.dracr = g_new0(uint32_t, nr); 834 } 835 } 836 } 837 838 if (arm_feature(env, ARM_FEATURE_EL3)) { 839 set_feature(env, ARM_FEATURE_VBAR); 840 } 841 842 register_cp_regs_for_features(cpu); 843 arm_cpu_register_gdb_regs_for_features(cpu); 844 845 init_cpreg_list(cpu); 846 847 #ifndef CONFIG_USER_ONLY 848 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 849 AddressSpace *as; 850 851 cs->num_ases = 2; 852 853 if (!cpu->secure_memory) { 854 cpu->secure_memory = cs->memory; 855 } 856 as = address_space_init_shareable(cpu->secure_memory, 857 "cpu-secure-memory"); 858 cpu_address_space_init(cs, as, ARMASIdx_S); 859 } else { 860 cs->num_ases = 1; 861 } 862 863 cpu_address_space_init(cs, 864 address_space_init_shareable(cs->memory, 865 "cpu-memory"), 866 ARMASIdx_NS); 867 #endif 868 869 qemu_init_vcpu(cs); 870 cpu_reset(cs); 871 872 acc->parent_realize(dev, errp); 873 } 874 875 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 876 { 877 ObjectClass *oc; 878 char *typename; 879 char **cpuname; 880 881 if (!cpu_model) { 882 return NULL; 883 } 884 885 cpuname = g_strsplit(cpu_model, ",", 1); 886 typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]); 887 oc = object_class_by_name(typename); 888 g_strfreev(cpuname); 889 g_free(typename); 890 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 891 object_class_is_abstract(oc)) { 892 return NULL; 893 } 894 return oc; 895 } 896 897 /* CPU models. These are not needed for the AArch64 linux-user build. */ 898 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 899 900 static void arm926_initfn(Object *obj) 901 { 902 ARMCPU *cpu = ARM_CPU(obj); 903 904 cpu->dtb_compatible = "arm,arm926"; 905 set_feature(&cpu->env, ARM_FEATURE_V5); 906 set_feature(&cpu->env, ARM_FEATURE_VFP); 907 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 908 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 909 cpu->midr = 0x41069265; 910 cpu->reset_fpsid = 0x41011090; 911 cpu->ctr = 0x1dd20d2; 912 cpu->reset_sctlr = 0x00090078; 913 } 914 915 static void arm946_initfn(Object *obj) 916 { 917 ARMCPU *cpu = ARM_CPU(obj); 918 919 cpu->dtb_compatible = "arm,arm946"; 920 set_feature(&cpu->env, ARM_FEATURE_V5); 921 set_feature(&cpu->env, ARM_FEATURE_PMSA); 922 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 923 cpu->midr = 0x41059461; 924 cpu->ctr = 0x0f004006; 925 cpu->reset_sctlr = 0x00000078; 926 } 927 928 static void arm1026_initfn(Object *obj) 929 { 930 ARMCPU *cpu = ARM_CPU(obj); 931 932 cpu->dtb_compatible = "arm,arm1026"; 933 set_feature(&cpu->env, ARM_FEATURE_V5); 934 set_feature(&cpu->env, ARM_FEATURE_VFP); 935 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 936 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 937 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 938 cpu->midr = 0x4106a262; 939 cpu->reset_fpsid = 0x410110a0; 940 cpu->ctr = 0x1dd20d2; 941 cpu->reset_sctlr = 0x00090078; 942 cpu->reset_auxcr = 1; 943 { 944 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 945 ARMCPRegInfo ifar = { 946 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 947 .access = PL1_RW, 948 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 949 .resetvalue = 0 950 }; 951 define_one_arm_cp_reg(cpu, &ifar); 952 } 953 } 954 955 static void arm1136_r2_initfn(Object *obj) 956 { 957 ARMCPU *cpu = ARM_CPU(obj); 958 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 959 * older core than plain "arm1136". In particular this does not 960 * have the v6K features. 961 * These ID register values are correct for 1136 but may be wrong 962 * for 1136_r2 (in particular r0p2 does not actually implement most 963 * of the ID registers). 964 */ 965 966 cpu->dtb_compatible = "arm,arm1136"; 967 set_feature(&cpu->env, ARM_FEATURE_V6); 968 set_feature(&cpu->env, ARM_FEATURE_VFP); 969 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 970 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 971 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 972 cpu->midr = 0x4107b362; 973 cpu->reset_fpsid = 0x410120b4; 974 cpu->mvfr0 = 0x11111111; 975 cpu->mvfr1 = 0x00000000; 976 cpu->ctr = 0x1dd20d2; 977 cpu->reset_sctlr = 0x00050078; 978 cpu->id_pfr0 = 0x111; 979 cpu->id_pfr1 = 0x1; 980 cpu->id_dfr0 = 0x2; 981 cpu->id_afr0 = 0x3; 982 cpu->id_mmfr0 = 0x01130003; 983 cpu->id_mmfr1 = 0x10030302; 984 cpu->id_mmfr2 = 0x01222110; 985 cpu->id_isar0 = 0x00140011; 986 cpu->id_isar1 = 0x12002111; 987 cpu->id_isar2 = 0x11231111; 988 cpu->id_isar3 = 0x01102131; 989 cpu->id_isar4 = 0x141; 990 cpu->reset_auxcr = 7; 991 } 992 993 static void arm1136_initfn(Object *obj) 994 { 995 ARMCPU *cpu = ARM_CPU(obj); 996 997 cpu->dtb_compatible = "arm,arm1136"; 998 set_feature(&cpu->env, ARM_FEATURE_V6K); 999 set_feature(&cpu->env, ARM_FEATURE_V6); 1000 set_feature(&cpu->env, ARM_FEATURE_VFP); 1001 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1002 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1003 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1004 cpu->midr = 0x4117b363; 1005 cpu->reset_fpsid = 0x410120b4; 1006 cpu->mvfr0 = 0x11111111; 1007 cpu->mvfr1 = 0x00000000; 1008 cpu->ctr = 0x1dd20d2; 1009 cpu->reset_sctlr = 0x00050078; 1010 cpu->id_pfr0 = 0x111; 1011 cpu->id_pfr1 = 0x1; 1012 cpu->id_dfr0 = 0x2; 1013 cpu->id_afr0 = 0x3; 1014 cpu->id_mmfr0 = 0x01130003; 1015 cpu->id_mmfr1 = 0x10030302; 1016 cpu->id_mmfr2 = 0x01222110; 1017 cpu->id_isar0 = 0x00140011; 1018 cpu->id_isar1 = 0x12002111; 1019 cpu->id_isar2 = 0x11231111; 1020 cpu->id_isar3 = 0x01102131; 1021 cpu->id_isar4 = 0x141; 1022 cpu->reset_auxcr = 7; 1023 } 1024 1025 static void arm1176_initfn(Object *obj) 1026 { 1027 ARMCPU *cpu = ARM_CPU(obj); 1028 1029 cpu->dtb_compatible = "arm,arm1176"; 1030 set_feature(&cpu->env, ARM_FEATURE_V6K); 1031 set_feature(&cpu->env, ARM_FEATURE_VFP); 1032 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1033 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1034 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1035 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1036 set_feature(&cpu->env, ARM_FEATURE_EL3); 1037 cpu->midr = 0x410fb767; 1038 cpu->reset_fpsid = 0x410120b5; 1039 cpu->mvfr0 = 0x11111111; 1040 cpu->mvfr1 = 0x00000000; 1041 cpu->ctr = 0x1dd20d2; 1042 cpu->reset_sctlr = 0x00050078; 1043 cpu->id_pfr0 = 0x111; 1044 cpu->id_pfr1 = 0x11; 1045 cpu->id_dfr0 = 0x33; 1046 cpu->id_afr0 = 0; 1047 cpu->id_mmfr0 = 0x01130003; 1048 cpu->id_mmfr1 = 0x10030302; 1049 cpu->id_mmfr2 = 0x01222100; 1050 cpu->id_isar0 = 0x0140011; 1051 cpu->id_isar1 = 0x12002111; 1052 cpu->id_isar2 = 0x11231121; 1053 cpu->id_isar3 = 0x01102131; 1054 cpu->id_isar4 = 0x01141; 1055 cpu->reset_auxcr = 7; 1056 } 1057 1058 static void arm11mpcore_initfn(Object *obj) 1059 { 1060 ARMCPU *cpu = ARM_CPU(obj); 1061 1062 cpu->dtb_compatible = "arm,arm11mpcore"; 1063 set_feature(&cpu->env, ARM_FEATURE_V6K); 1064 set_feature(&cpu->env, ARM_FEATURE_VFP); 1065 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1066 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1067 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1068 cpu->midr = 0x410fb022; 1069 cpu->reset_fpsid = 0x410120b4; 1070 cpu->mvfr0 = 0x11111111; 1071 cpu->mvfr1 = 0x00000000; 1072 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1073 cpu->id_pfr0 = 0x111; 1074 cpu->id_pfr1 = 0x1; 1075 cpu->id_dfr0 = 0; 1076 cpu->id_afr0 = 0x2; 1077 cpu->id_mmfr0 = 0x01100103; 1078 cpu->id_mmfr1 = 0x10020302; 1079 cpu->id_mmfr2 = 0x01222000; 1080 cpu->id_isar0 = 0x00100011; 1081 cpu->id_isar1 = 0x12002111; 1082 cpu->id_isar2 = 0x11221011; 1083 cpu->id_isar3 = 0x01102131; 1084 cpu->id_isar4 = 0x141; 1085 cpu->reset_auxcr = 1; 1086 } 1087 1088 static void cortex_m3_initfn(Object *obj) 1089 { 1090 ARMCPU *cpu = ARM_CPU(obj); 1091 set_feature(&cpu->env, ARM_FEATURE_V7); 1092 set_feature(&cpu->env, ARM_FEATURE_M); 1093 cpu->midr = 0x410fc231; 1094 cpu->pmsav7_dregion = 8; 1095 } 1096 1097 static void cortex_m4_initfn(Object *obj) 1098 { 1099 ARMCPU *cpu = ARM_CPU(obj); 1100 1101 set_feature(&cpu->env, ARM_FEATURE_V7); 1102 set_feature(&cpu->env, ARM_FEATURE_M); 1103 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1104 cpu->midr = 0x410fc240; /* r0p0 */ 1105 cpu->pmsav7_dregion = 8; 1106 } 1107 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1108 { 1109 CPUClass *cc = CPU_CLASS(oc); 1110 1111 #ifndef CONFIG_USER_ONLY 1112 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1113 #endif 1114 1115 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1116 } 1117 1118 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1119 /* Dummy the TCM region regs for the moment */ 1120 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1121 .access = PL1_RW, .type = ARM_CP_CONST }, 1122 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1123 .access = PL1_RW, .type = ARM_CP_CONST }, 1124 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 1125 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 1126 REGINFO_SENTINEL 1127 }; 1128 1129 static void cortex_r5_initfn(Object *obj) 1130 { 1131 ARMCPU *cpu = ARM_CPU(obj); 1132 1133 set_feature(&cpu->env, ARM_FEATURE_V7); 1134 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); 1135 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1136 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1137 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1138 cpu->midr = 0x411fc153; /* r1p3 */ 1139 cpu->id_pfr0 = 0x0131; 1140 cpu->id_pfr1 = 0x001; 1141 cpu->id_dfr0 = 0x010400; 1142 cpu->id_afr0 = 0x0; 1143 cpu->id_mmfr0 = 0x0210030; 1144 cpu->id_mmfr1 = 0x00000000; 1145 cpu->id_mmfr2 = 0x01200000; 1146 cpu->id_mmfr3 = 0x0211; 1147 cpu->id_isar0 = 0x2101111; 1148 cpu->id_isar1 = 0x13112111; 1149 cpu->id_isar2 = 0x21232141; 1150 cpu->id_isar3 = 0x01112131; 1151 cpu->id_isar4 = 0x0010142; 1152 cpu->id_isar5 = 0x0; 1153 cpu->mp_is_up = true; 1154 cpu->pmsav7_dregion = 16; 1155 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1156 } 1157 1158 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1159 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1160 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1161 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1162 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1163 REGINFO_SENTINEL 1164 }; 1165 1166 static void cortex_a8_initfn(Object *obj) 1167 { 1168 ARMCPU *cpu = ARM_CPU(obj); 1169 1170 cpu->dtb_compatible = "arm,cortex-a8"; 1171 set_feature(&cpu->env, ARM_FEATURE_V7); 1172 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1173 set_feature(&cpu->env, ARM_FEATURE_NEON); 1174 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1175 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1176 set_feature(&cpu->env, ARM_FEATURE_EL3); 1177 cpu->midr = 0x410fc080; 1178 cpu->reset_fpsid = 0x410330c0; 1179 cpu->mvfr0 = 0x11110222; 1180 cpu->mvfr1 = 0x00011111; 1181 cpu->ctr = 0x82048004; 1182 cpu->reset_sctlr = 0x00c50078; 1183 cpu->id_pfr0 = 0x1031; 1184 cpu->id_pfr1 = 0x11; 1185 cpu->id_dfr0 = 0x400; 1186 cpu->id_afr0 = 0; 1187 cpu->id_mmfr0 = 0x31100003; 1188 cpu->id_mmfr1 = 0x20000000; 1189 cpu->id_mmfr2 = 0x01202000; 1190 cpu->id_mmfr3 = 0x11; 1191 cpu->id_isar0 = 0x00101111; 1192 cpu->id_isar1 = 0x12112111; 1193 cpu->id_isar2 = 0x21232031; 1194 cpu->id_isar3 = 0x11112131; 1195 cpu->id_isar4 = 0x00111142; 1196 cpu->dbgdidr = 0x15141000; 1197 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1198 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1199 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1200 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1201 cpu->reset_auxcr = 2; 1202 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1203 } 1204 1205 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1206 /* power_control should be set to maximum latency. Again, 1207 * default to 0 and set by private hook 1208 */ 1209 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1210 .access = PL1_RW, .resetvalue = 0, 1211 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1212 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1213 .access = PL1_RW, .resetvalue = 0, 1214 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1215 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1216 .access = PL1_RW, .resetvalue = 0, 1217 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1218 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1219 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1220 /* TLB lockdown control */ 1221 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1222 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1223 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1224 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1225 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1226 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1227 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1228 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1229 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1230 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1231 REGINFO_SENTINEL 1232 }; 1233 1234 static void cortex_a9_initfn(Object *obj) 1235 { 1236 ARMCPU *cpu = ARM_CPU(obj); 1237 1238 cpu->dtb_compatible = "arm,cortex-a9"; 1239 set_feature(&cpu->env, ARM_FEATURE_V7); 1240 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1241 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); 1242 set_feature(&cpu->env, ARM_FEATURE_NEON); 1243 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1244 set_feature(&cpu->env, ARM_FEATURE_EL3); 1245 /* Note that A9 supports the MP extensions even for 1246 * A9UP and single-core A9MP (which are both different 1247 * and valid configurations; we don't model A9UP). 1248 */ 1249 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1250 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1251 cpu->midr = 0x410fc090; 1252 cpu->reset_fpsid = 0x41033090; 1253 cpu->mvfr0 = 0x11110222; 1254 cpu->mvfr1 = 0x01111111; 1255 cpu->ctr = 0x80038003; 1256 cpu->reset_sctlr = 0x00c50078; 1257 cpu->id_pfr0 = 0x1031; 1258 cpu->id_pfr1 = 0x11; 1259 cpu->id_dfr0 = 0x000; 1260 cpu->id_afr0 = 0; 1261 cpu->id_mmfr0 = 0x00100103; 1262 cpu->id_mmfr1 = 0x20000000; 1263 cpu->id_mmfr2 = 0x01230000; 1264 cpu->id_mmfr3 = 0x00002111; 1265 cpu->id_isar0 = 0x00101111; 1266 cpu->id_isar1 = 0x13112111; 1267 cpu->id_isar2 = 0x21232041; 1268 cpu->id_isar3 = 0x11112131; 1269 cpu->id_isar4 = 0x00111142; 1270 cpu->dbgdidr = 0x35141000; 1271 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1272 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1273 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1274 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1275 } 1276 1277 #ifndef CONFIG_USER_ONLY 1278 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1279 { 1280 /* Linux wants the number of processors from here. 1281 * Might as well set the interrupt-controller bit too. 1282 */ 1283 return ((smp_cpus - 1) << 24) | (1 << 23); 1284 } 1285 #endif 1286 1287 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1288 #ifndef CONFIG_USER_ONLY 1289 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1290 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1291 .writefn = arm_cp_write_ignore, }, 1292 #endif 1293 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1294 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1295 REGINFO_SENTINEL 1296 }; 1297 1298 static void cortex_a7_initfn(Object *obj) 1299 { 1300 ARMCPU *cpu = ARM_CPU(obj); 1301 1302 cpu->dtb_compatible = "arm,cortex-a7"; 1303 set_feature(&cpu->env, ARM_FEATURE_V7); 1304 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1305 set_feature(&cpu->env, ARM_FEATURE_NEON); 1306 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1307 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1308 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1309 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1310 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1311 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1312 set_feature(&cpu->env, ARM_FEATURE_EL3); 1313 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1314 cpu->midr = 0x410fc075; 1315 cpu->reset_fpsid = 0x41023075; 1316 cpu->mvfr0 = 0x10110222; 1317 cpu->mvfr1 = 0x11111111; 1318 cpu->ctr = 0x84448003; 1319 cpu->reset_sctlr = 0x00c50078; 1320 cpu->id_pfr0 = 0x00001131; 1321 cpu->id_pfr1 = 0x00011011; 1322 cpu->id_dfr0 = 0x02010555; 1323 cpu->pmceid0 = 0x00000000; 1324 cpu->pmceid1 = 0x00000000; 1325 cpu->id_afr0 = 0x00000000; 1326 cpu->id_mmfr0 = 0x10101105; 1327 cpu->id_mmfr1 = 0x40000000; 1328 cpu->id_mmfr2 = 0x01240000; 1329 cpu->id_mmfr3 = 0x02102211; 1330 cpu->id_isar0 = 0x01101110; 1331 cpu->id_isar1 = 0x13112111; 1332 cpu->id_isar2 = 0x21232041; 1333 cpu->id_isar3 = 0x11112131; 1334 cpu->id_isar4 = 0x10011142; 1335 cpu->dbgdidr = 0x3515f005; 1336 cpu->clidr = 0x0a200023; 1337 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1338 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1339 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1340 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1341 } 1342 1343 static void cortex_a15_initfn(Object *obj) 1344 { 1345 ARMCPU *cpu = ARM_CPU(obj); 1346 1347 cpu->dtb_compatible = "arm,cortex-a15"; 1348 set_feature(&cpu->env, ARM_FEATURE_V7); 1349 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1350 set_feature(&cpu->env, ARM_FEATURE_NEON); 1351 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1352 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1353 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1354 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1355 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1356 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1357 set_feature(&cpu->env, ARM_FEATURE_EL3); 1358 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1359 cpu->midr = 0x412fc0f1; 1360 cpu->reset_fpsid = 0x410430f0; 1361 cpu->mvfr0 = 0x10110222; 1362 cpu->mvfr1 = 0x11111111; 1363 cpu->ctr = 0x8444c004; 1364 cpu->reset_sctlr = 0x00c50078; 1365 cpu->id_pfr0 = 0x00001131; 1366 cpu->id_pfr1 = 0x00011011; 1367 cpu->id_dfr0 = 0x02010555; 1368 cpu->pmceid0 = 0x0000000; 1369 cpu->pmceid1 = 0x00000000; 1370 cpu->id_afr0 = 0x00000000; 1371 cpu->id_mmfr0 = 0x10201105; 1372 cpu->id_mmfr1 = 0x20000000; 1373 cpu->id_mmfr2 = 0x01240000; 1374 cpu->id_mmfr3 = 0x02102211; 1375 cpu->id_isar0 = 0x02101110; 1376 cpu->id_isar1 = 0x13112111; 1377 cpu->id_isar2 = 0x21232041; 1378 cpu->id_isar3 = 0x11112131; 1379 cpu->id_isar4 = 0x10011142; 1380 cpu->dbgdidr = 0x3515f021; 1381 cpu->clidr = 0x0a200023; 1382 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1383 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1384 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1385 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 1386 } 1387 1388 static void ti925t_initfn(Object *obj) 1389 { 1390 ARMCPU *cpu = ARM_CPU(obj); 1391 set_feature(&cpu->env, ARM_FEATURE_V4T); 1392 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 1393 cpu->midr = ARM_CPUID_TI925T; 1394 cpu->ctr = 0x5109149; 1395 cpu->reset_sctlr = 0x00000070; 1396 } 1397 1398 static void sa1100_initfn(Object *obj) 1399 { 1400 ARMCPU *cpu = ARM_CPU(obj); 1401 1402 cpu->dtb_compatible = "intel,sa1100"; 1403 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1404 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1405 cpu->midr = 0x4401A11B; 1406 cpu->reset_sctlr = 0x00000070; 1407 } 1408 1409 static void sa1110_initfn(Object *obj) 1410 { 1411 ARMCPU *cpu = ARM_CPU(obj); 1412 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1413 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1414 cpu->midr = 0x6901B119; 1415 cpu->reset_sctlr = 0x00000070; 1416 } 1417 1418 static void pxa250_initfn(Object *obj) 1419 { 1420 ARMCPU *cpu = ARM_CPU(obj); 1421 1422 cpu->dtb_compatible = "marvell,xscale"; 1423 set_feature(&cpu->env, ARM_FEATURE_V5); 1424 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1425 cpu->midr = 0x69052100; 1426 cpu->ctr = 0xd172172; 1427 cpu->reset_sctlr = 0x00000078; 1428 } 1429 1430 static void pxa255_initfn(Object *obj) 1431 { 1432 ARMCPU *cpu = ARM_CPU(obj); 1433 1434 cpu->dtb_compatible = "marvell,xscale"; 1435 set_feature(&cpu->env, ARM_FEATURE_V5); 1436 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1437 cpu->midr = 0x69052d00; 1438 cpu->ctr = 0xd172172; 1439 cpu->reset_sctlr = 0x00000078; 1440 } 1441 1442 static void pxa260_initfn(Object *obj) 1443 { 1444 ARMCPU *cpu = ARM_CPU(obj); 1445 1446 cpu->dtb_compatible = "marvell,xscale"; 1447 set_feature(&cpu->env, ARM_FEATURE_V5); 1448 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1449 cpu->midr = 0x69052903; 1450 cpu->ctr = 0xd172172; 1451 cpu->reset_sctlr = 0x00000078; 1452 } 1453 1454 static void pxa261_initfn(Object *obj) 1455 { 1456 ARMCPU *cpu = ARM_CPU(obj); 1457 1458 cpu->dtb_compatible = "marvell,xscale"; 1459 set_feature(&cpu->env, ARM_FEATURE_V5); 1460 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1461 cpu->midr = 0x69052d05; 1462 cpu->ctr = 0xd172172; 1463 cpu->reset_sctlr = 0x00000078; 1464 } 1465 1466 static void pxa262_initfn(Object *obj) 1467 { 1468 ARMCPU *cpu = ARM_CPU(obj); 1469 1470 cpu->dtb_compatible = "marvell,xscale"; 1471 set_feature(&cpu->env, ARM_FEATURE_V5); 1472 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1473 cpu->midr = 0x69052d06; 1474 cpu->ctr = 0xd172172; 1475 cpu->reset_sctlr = 0x00000078; 1476 } 1477 1478 static void pxa270a0_initfn(Object *obj) 1479 { 1480 ARMCPU *cpu = ARM_CPU(obj); 1481 1482 cpu->dtb_compatible = "marvell,xscale"; 1483 set_feature(&cpu->env, ARM_FEATURE_V5); 1484 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1485 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1486 cpu->midr = 0x69054110; 1487 cpu->ctr = 0xd172172; 1488 cpu->reset_sctlr = 0x00000078; 1489 } 1490 1491 static void pxa270a1_initfn(Object *obj) 1492 { 1493 ARMCPU *cpu = ARM_CPU(obj); 1494 1495 cpu->dtb_compatible = "marvell,xscale"; 1496 set_feature(&cpu->env, ARM_FEATURE_V5); 1497 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1498 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1499 cpu->midr = 0x69054111; 1500 cpu->ctr = 0xd172172; 1501 cpu->reset_sctlr = 0x00000078; 1502 } 1503 1504 static void pxa270b0_initfn(Object *obj) 1505 { 1506 ARMCPU *cpu = ARM_CPU(obj); 1507 1508 cpu->dtb_compatible = "marvell,xscale"; 1509 set_feature(&cpu->env, ARM_FEATURE_V5); 1510 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1511 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1512 cpu->midr = 0x69054112; 1513 cpu->ctr = 0xd172172; 1514 cpu->reset_sctlr = 0x00000078; 1515 } 1516 1517 static void pxa270b1_initfn(Object *obj) 1518 { 1519 ARMCPU *cpu = ARM_CPU(obj); 1520 1521 cpu->dtb_compatible = "marvell,xscale"; 1522 set_feature(&cpu->env, ARM_FEATURE_V5); 1523 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1524 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1525 cpu->midr = 0x69054113; 1526 cpu->ctr = 0xd172172; 1527 cpu->reset_sctlr = 0x00000078; 1528 } 1529 1530 static void pxa270c0_initfn(Object *obj) 1531 { 1532 ARMCPU *cpu = ARM_CPU(obj); 1533 1534 cpu->dtb_compatible = "marvell,xscale"; 1535 set_feature(&cpu->env, ARM_FEATURE_V5); 1536 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1537 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1538 cpu->midr = 0x69054114; 1539 cpu->ctr = 0xd172172; 1540 cpu->reset_sctlr = 0x00000078; 1541 } 1542 1543 static void pxa270c5_initfn(Object *obj) 1544 { 1545 ARMCPU *cpu = ARM_CPU(obj); 1546 1547 cpu->dtb_compatible = "marvell,xscale"; 1548 set_feature(&cpu->env, ARM_FEATURE_V5); 1549 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1550 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1551 cpu->midr = 0x69054117; 1552 cpu->ctr = 0xd172172; 1553 cpu->reset_sctlr = 0x00000078; 1554 } 1555 1556 #ifdef CONFIG_USER_ONLY 1557 static void arm_any_initfn(Object *obj) 1558 { 1559 ARMCPU *cpu = ARM_CPU(obj); 1560 set_feature(&cpu->env, ARM_FEATURE_V8); 1561 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1562 set_feature(&cpu->env, ARM_FEATURE_NEON); 1563 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1564 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 1565 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 1566 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 1567 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 1568 set_feature(&cpu->env, ARM_FEATURE_CRC); 1569 cpu->midr = 0xffffffff; 1570 } 1571 #endif 1572 1573 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 1574 1575 typedef struct ARMCPUInfo { 1576 const char *name; 1577 void (*initfn)(Object *obj); 1578 void (*class_init)(ObjectClass *oc, void *data); 1579 } ARMCPUInfo; 1580 1581 static const ARMCPUInfo arm_cpus[] = { 1582 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1583 { .name = "arm926", .initfn = arm926_initfn }, 1584 { .name = "arm946", .initfn = arm946_initfn }, 1585 { .name = "arm1026", .initfn = arm1026_initfn }, 1586 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1587 * older core than plain "arm1136". In particular this does not 1588 * have the v6K features. 1589 */ 1590 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1591 { .name = "arm1136", .initfn = arm1136_initfn }, 1592 { .name = "arm1176", .initfn = arm1176_initfn }, 1593 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1594 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 1595 .class_init = arm_v7m_class_init }, 1596 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 1597 .class_init = arm_v7m_class_init }, 1598 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1599 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1600 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1601 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1602 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1603 { .name = "ti925t", .initfn = ti925t_initfn }, 1604 { .name = "sa1100", .initfn = sa1100_initfn }, 1605 { .name = "sa1110", .initfn = sa1110_initfn }, 1606 { .name = "pxa250", .initfn = pxa250_initfn }, 1607 { .name = "pxa255", .initfn = pxa255_initfn }, 1608 { .name = "pxa260", .initfn = pxa260_initfn }, 1609 { .name = "pxa261", .initfn = pxa261_initfn }, 1610 { .name = "pxa262", .initfn = pxa262_initfn }, 1611 /* "pxa270" is an alias for "pxa270-a0" */ 1612 { .name = "pxa270", .initfn = pxa270a0_initfn }, 1613 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 1614 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 1615 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 1616 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 1617 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 1618 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 1619 #ifdef CONFIG_USER_ONLY 1620 { .name = "any", .initfn = arm_any_initfn }, 1621 #endif 1622 #endif 1623 { .name = NULL } 1624 }; 1625 1626 static Property arm_cpu_properties[] = { 1627 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 1628 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 1629 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 1630 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 1631 mp_affinity, ARM64_AFFINITY_INVALID), 1632 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 1633 DEFINE_PROP_END_OF_LIST() 1634 }; 1635 1636 #ifdef CONFIG_USER_ONLY 1637 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, 1638 int mmu_idx) 1639 { 1640 ARMCPU *cpu = ARM_CPU(cs); 1641 CPUARMState *env = &cpu->env; 1642 1643 env->exception.vaddress = address; 1644 if (rw == 2) { 1645 cs->exception_index = EXCP_PREFETCH_ABORT; 1646 } else { 1647 cs->exception_index = EXCP_DATA_ABORT; 1648 } 1649 return 1; 1650 } 1651 #endif 1652 1653 static gchar *arm_gdb_arch_name(CPUState *cs) 1654 { 1655 ARMCPU *cpu = ARM_CPU(cs); 1656 CPUARMState *env = &cpu->env; 1657 1658 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 1659 return g_strdup("iwmmxt"); 1660 } 1661 return g_strdup("arm"); 1662 } 1663 1664 static void arm_cpu_class_init(ObjectClass *oc, void *data) 1665 { 1666 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1667 CPUClass *cc = CPU_CLASS(acc); 1668 DeviceClass *dc = DEVICE_CLASS(oc); 1669 1670 acc->parent_realize = dc->realize; 1671 dc->realize = arm_cpu_realizefn; 1672 dc->props = arm_cpu_properties; 1673 1674 acc->parent_reset = cc->reset; 1675 cc->reset = arm_cpu_reset; 1676 1677 cc->class_by_name = arm_cpu_class_by_name; 1678 cc->has_work = arm_cpu_has_work; 1679 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 1680 cc->dump_state = arm_cpu_dump_state; 1681 cc->set_pc = arm_cpu_set_pc; 1682 cc->gdb_read_register = arm_cpu_gdb_read_register; 1683 cc->gdb_write_register = arm_cpu_gdb_write_register; 1684 #ifdef CONFIG_USER_ONLY 1685 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; 1686 #else 1687 cc->do_interrupt = arm_cpu_do_interrupt; 1688 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 1689 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 1690 cc->asidx_from_attrs = arm_asidx_from_attrs; 1691 cc->vmsd = &vmstate_arm_cpu; 1692 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 1693 cc->write_elf64_note = arm_cpu_write_elf64_note; 1694 cc->write_elf32_note = arm_cpu_write_elf32_note; 1695 #endif 1696 cc->gdb_num_core_regs = 26; 1697 cc->gdb_core_xml_file = "arm-core.xml"; 1698 cc->gdb_arch_name = arm_gdb_arch_name; 1699 cc->gdb_stop_before_watchpoint = true; 1700 cc->debug_excp_handler = arm_debug_excp_handler; 1701 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 1702 #if !defined(CONFIG_USER_ONLY) 1703 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 1704 #endif 1705 1706 cc->disas_set_info = arm_disas_set_info; 1707 } 1708 1709 static void cpu_register(const ARMCPUInfo *info) 1710 { 1711 TypeInfo type_info = { 1712 .parent = TYPE_ARM_CPU, 1713 .instance_size = sizeof(ARMCPU), 1714 .instance_init = info->initfn, 1715 .class_size = sizeof(ARMCPUClass), 1716 .class_init = info->class_init, 1717 }; 1718 1719 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 1720 type_register(&type_info); 1721 g_free((void *)type_info.name); 1722 } 1723 1724 static const TypeInfo arm_cpu_type_info = { 1725 .name = TYPE_ARM_CPU, 1726 .parent = TYPE_CPU, 1727 .instance_size = sizeof(ARMCPU), 1728 .instance_init = arm_cpu_initfn, 1729 .instance_post_init = arm_cpu_post_init, 1730 .instance_finalize = arm_cpu_finalizefn, 1731 .abstract = true, 1732 .class_size = sizeof(ARMCPUClass), 1733 .class_init = arm_cpu_class_init, 1734 }; 1735 1736 static void arm_cpu_register_types(void) 1737 { 1738 const ARMCPUInfo *info = arm_cpus; 1739 1740 type_register_static(&arm_cpu_type_info); 1741 1742 while (info->name) { 1743 cpu_register(info); 1744 info++; 1745 } 1746 } 1747 1748 type_init(arm_cpu_register_types) 1749