1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu/timer.h" 24 #include "qemu/log.h" 25 #include "exec/page-vary.h" 26 #include "target/arm/idau.h" 27 #include "qemu/module.h" 28 #include "qapi/error.h" 29 #include "cpu.h" 30 #ifdef CONFIG_TCG 31 #include "hw/core/tcg-cpu-ops.h" 32 #endif /* CONFIG_TCG */ 33 #include "internals.h" 34 #include "exec/exec-all.h" 35 #include "hw/qdev-properties.h" 36 #if !defined(CONFIG_USER_ONLY) 37 #include "hw/loader.h" 38 #include "hw/boards.h" 39 #ifdef CONFIG_TCG 40 #include "hw/intc/armv7m_nvic.h" 41 #endif /* CONFIG_TCG */ 42 #endif /* !CONFIG_USER_ONLY */ 43 #include "sysemu/tcg.h" 44 #include "sysemu/qtest.h" 45 #include "sysemu/hw_accel.h" 46 #include "kvm_arm.h" 47 #include "disas/capstone.h" 48 #include "fpu/softfloat.h" 49 #include "cpregs.h" 50 51 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 52 { 53 ARMCPU *cpu = ARM_CPU(cs); 54 CPUARMState *env = &cpu->env; 55 56 if (is_a64(env)) { 57 env->pc = value; 58 env->thumb = false; 59 } else { 60 env->regs[15] = value & ~1; 61 env->thumb = value & 1; 62 } 63 } 64 65 static vaddr arm_cpu_get_pc(CPUState *cs) 66 { 67 ARMCPU *cpu = ARM_CPU(cs); 68 CPUARMState *env = &cpu->env; 69 70 if (is_a64(env)) { 71 return env->pc; 72 } else { 73 return env->regs[15]; 74 } 75 } 76 77 #ifdef CONFIG_TCG 78 void arm_cpu_synchronize_from_tb(CPUState *cs, 79 const TranslationBlock *tb) 80 { 81 /* The program counter is always up to date with TARGET_TB_PCREL. */ 82 if (!TARGET_TB_PCREL) { 83 CPUARMState *env = cs->env_ptr; 84 /* 85 * It's OK to look at env for the current mode here, because it's 86 * never possible for an AArch64 TB to chain to an AArch32 TB. 87 */ 88 if (is_a64(env)) { 89 env->pc = tb_pc(tb); 90 } else { 91 env->regs[15] = tb_pc(tb); 92 } 93 } 94 } 95 96 void arm_restore_state_to_opc(CPUState *cs, 97 const TranslationBlock *tb, 98 const uint64_t *data) 99 { 100 CPUARMState *env = cs->env_ptr; 101 102 if (is_a64(env)) { 103 if (TARGET_TB_PCREL) { 104 env->pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 105 } else { 106 env->pc = data[0]; 107 } 108 env->condexec_bits = 0; 109 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 110 } else { 111 if (TARGET_TB_PCREL) { 112 env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0]; 113 } else { 114 env->regs[15] = data[0]; 115 } 116 env->condexec_bits = data[1]; 117 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 118 } 119 } 120 #endif /* CONFIG_TCG */ 121 122 static bool arm_cpu_has_work(CPUState *cs) 123 { 124 ARMCPU *cpu = ARM_CPU(cs); 125 126 return (cpu->power_state != PSCI_OFF) 127 && cs->interrupt_request & 128 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 129 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR 130 | CPU_INTERRUPT_EXITTB); 131 } 132 133 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 134 void *opaque) 135 { 136 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 137 138 entry->hook = hook; 139 entry->opaque = opaque; 140 141 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 142 } 143 144 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 145 void *opaque) 146 { 147 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 148 149 entry->hook = hook; 150 entry->opaque = opaque; 151 152 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 153 } 154 155 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 156 { 157 /* Reset a single ARMCPRegInfo register */ 158 ARMCPRegInfo *ri = value; 159 ARMCPU *cpu = opaque; 160 161 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { 162 return; 163 } 164 165 if (ri->resetfn) { 166 ri->resetfn(&cpu->env, ri); 167 return; 168 } 169 170 /* A zero offset is never possible as it would be regs[0] 171 * so we use it to indicate that reset is being handled elsewhere. 172 * This is basically only used for fields in non-core coprocessors 173 * (like the pxa2xx ones). 174 */ 175 if (!ri->fieldoffset) { 176 return; 177 } 178 179 if (cpreg_field_is_64bit(ri)) { 180 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 181 } else { 182 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 183 } 184 } 185 186 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 187 { 188 /* Purely an assertion check: we've already done reset once, 189 * so now check that running the reset for the cpreg doesn't 190 * change its value. This traps bugs where two different cpregs 191 * both try to reset the same state field but to different values. 192 */ 193 ARMCPRegInfo *ri = value; 194 ARMCPU *cpu = opaque; 195 uint64_t oldvalue, newvalue; 196 197 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 198 return; 199 } 200 201 oldvalue = read_raw_cp_reg(&cpu->env, ri); 202 cp_reg_reset(key, value, opaque); 203 newvalue = read_raw_cp_reg(&cpu->env, ri); 204 assert(oldvalue == newvalue); 205 } 206 207 static void arm_cpu_reset_hold(Object *obj) 208 { 209 CPUState *s = CPU(obj); 210 ARMCPU *cpu = ARM_CPU(s); 211 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 212 CPUARMState *env = &cpu->env; 213 214 if (acc->parent_phases.hold) { 215 acc->parent_phases.hold(obj); 216 } 217 218 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 219 220 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 221 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 222 223 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 224 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 225 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 226 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 227 228 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; 229 230 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 231 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 232 } 233 234 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 235 /* 64 bit CPUs always start in 64 bit mode */ 236 env->aarch64 = true; 237 #if defined(CONFIG_USER_ONLY) 238 env->pstate = PSTATE_MODE_EL0t; 239 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 240 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 241 /* Enable all PAC keys. */ 242 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 243 SCTLR_EnDA | SCTLR_EnDB); 244 /* Trap on btype=3 for PACIxSP. */ 245 env->cp15.sctlr_el[1] |= SCTLR_BT0; 246 /* and to the FP/Neon instructions */ 247 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 248 CPACR_EL1, FPEN, 3); 249 /* and to the SVE instructions, with default vector length */ 250 if (cpu_isar_feature(aa64_sve, cpu)) { 251 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 252 CPACR_EL1, ZEN, 3); 253 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; 254 } 255 /* and for SME instructions, with default vector length, and TPIDR2 */ 256 if (cpu_isar_feature(aa64_sme, cpu)) { 257 env->cp15.sctlr_el[1] |= SCTLR_EnTP2; 258 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 259 CPACR_EL1, SMEN, 3); 260 env->vfp.smcr_el[1] = cpu->sme_default_vq - 1; 261 if (cpu_isar_feature(aa64_sme_fa64, cpu)) { 262 env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1], 263 SMCR, FA64, 1); 264 } 265 } 266 /* 267 * Enable 48-bit address space (TODO: take reserved_va into account). 268 * Enable TBI0 but not TBI1. 269 * Note that this must match useronly_clean_ptr. 270 */ 271 env->cp15.tcr_el[1] = 5 | (1ULL << 37); 272 273 /* Enable MTE */ 274 if (cpu_isar_feature(aa64_mte, cpu)) { 275 /* Enable tag access, but leave TCF0 as No Effect (0). */ 276 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 277 /* 278 * Exclude all tags, so that tag 0 is always used. 279 * This corresponds to Linux current->thread.gcr_incl = 0. 280 * 281 * Set RRND, so that helper_irg() will generate a seed later. 282 * Here in cpu_reset(), the crypto subsystem has not yet been 283 * initialized. 284 */ 285 env->cp15.gcr_el1 = 0x1ffff; 286 } 287 /* 288 * Disable access to SCXTNUM_EL0 from CSV2_1p2. 289 * This is not yet exposed from the Linux kernel in any way. 290 */ 291 env->cp15.sctlr_el[1] |= SCTLR_TSCXT; 292 #else 293 /* Reset into the highest available EL */ 294 if (arm_feature(env, ARM_FEATURE_EL3)) { 295 env->pstate = PSTATE_MODE_EL3h; 296 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 297 env->pstate = PSTATE_MODE_EL2h; 298 } else { 299 env->pstate = PSTATE_MODE_EL1h; 300 } 301 302 /* Sample rvbar at reset. */ 303 env->cp15.rvbar = cpu->rvbar_prop; 304 env->pc = env->cp15.rvbar; 305 #endif 306 } else { 307 #if defined(CONFIG_USER_ONLY) 308 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 309 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 310 CPACR, CP10, 3); 311 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 312 CPACR, CP11, 3); 313 #endif 314 if (arm_feature(env, ARM_FEATURE_V8)) { 315 env->cp15.rvbar = cpu->rvbar_prop; 316 env->regs[15] = cpu->rvbar_prop; 317 } 318 } 319 320 #if defined(CONFIG_USER_ONLY) 321 env->uncached_cpsr = ARM_CPU_MODE_USR; 322 /* For user mode we must enable access to coprocessors */ 323 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 324 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 325 env->cp15.c15_cpar = 3; 326 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 327 env->cp15.c15_cpar = 1; 328 } 329 #else 330 331 /* 332 * If the highest available EL is EL2, AArch32 will start in Hyp 333 * mode; otherwise it starts in SVC. Note that if we start in 334 * AArch64 then these values in the uncached_cpsr will be ignored. 335 */ 336 if (arm_feature(env, ARM_FEATURE_EL2) && 337 !arm_feature(env, ARM_FEATURE_EL3)) { 338 env->uncached_cpsr = ARM_CPU_MODE_HYP; 339 } else { 340 env->uncached_cpsr = ARM_CPU_MODE_SVC; 341 } 342 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 343 344 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 345 * executing as AArch32 then check if highvecs are enabled and 346 * adjust the PC accordingly. 347 */ 348 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 349 env->regs[15] = 0xFFFF0000; 350 } 351 352 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 353 #endif 354 355 if (arm_feature(env, ARM_FEATURE_M)) { 356 #ifndef CONFIG_USER_ONLY 357 uint32_t initial_msp; /* Loaded from 0x0 */ 358 uint32_t initial_pc; /* Loaded from 0x4 */ 359 uint8_t *rom; 360 uint32_t vecbase; 361 #endif 362 363 if (cpu_isar_feature(aa32_lob, cpu)) { 364 /* 365 * LTPSIZE is constant 4 if MVE not implemented, and resets 366 * to an UNKNOWN value if MVE is implemented. We choose to 367 * always reset to 4. 368 */ 369 env->v7m.ltpsize = 4; 370 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 371 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 372 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 373 } 374 375 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 376 env->v7m.secure = true; 377 } else { 378 /* This bit resets to 0 if security is supported, but 1 if 379 * it is not. The bit is not present in v7M, but we set it 380 * here so we can avoid having to make checks on it conditional 381 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 382 */ 383 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 384 /* 385 * Set NSACR to indicate "NS access permitted to everything"; 386 * this avoids having to have all the tests of it being 387 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 388 * v8.1M the guest-visible value of NSACR in a CPU without the 389 * Security Extension is 0xcff. 390 */ 391 env->v7m.nsacr = 0xcff; 392 } 393 394 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 395 * that it resets to 1, so QEMU always does that rather than making 396 * it dependent on CPU model. In v8M it is RES1. 397 */ 398 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 399 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 400 if (arm_feature(env, ARM_FEATURE_V8)) { 401 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 402 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 403 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 404 } 405 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 406 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 407 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 408 } 409 410 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 411 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 412 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 413 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 414 } 415 416 #ifndef CONFIG_USER_ONLY 417 /* Unlike A/R profile, M profile defines the reset LR value */ 418 env->regs[14] = 0xffffffff; 419 420 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 421 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 422 423 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 424 vecbase = env->v7m.vecbase[env->v7m.secure]; 425 rom = rom_ptr_for_as(s->as, vecbase, 8); 426 if (rom) { 427 /* Address zero is covered by ROM which hasn't yet been 428 * copied into physical memory. 429 */ 430 initial_msp = ldl_p(rom); 431 initial_pc = ldl_p(rom + 4); 432 } else { 433 /* Address zero not covered by a ROM blob, or the ROM blob 434 * is in non-modifiable memory and this is a second reset after 435 * it got copied into memory. In the latter case, rom_ptr 436 * will return a NULL pointer and we should use ldl_phys instead. 437 */ 438 initial_msp = ldl_phys(s->as, vecbase); 439 initial_pc = ldl_phys(s->as, vecbase + 4); 440 } 441 442 qemu_log_mask(CPU_LOG_INT, 443 "Loaded reset SP 0x%x PC 0x%x from vector table\n", 444 initial_msp, initial_pc); 445 446 env->regs[13] = initial_msp & 0xFFFFFFFC; 447 env->regs[15] = initial_pc & ~1; 448 env->thumb = initial_pc & 1; 449 #else 450 /* 451 * For user mode we run non-secure and with access to the FPU. 452 * The FPU context is active (ie does not need further setup) 453 * and is owned by non-secure. 454 */ 455 env->v7m.secure = false; 456 env->v7m.nsacr = 0xcff; 457 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 458 env->v7m.fpccr[M_REG_S] &= 459 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 460 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 461 #endif 462 } 463 464 /* M profile requires that reset clears the exclusive monitor; 465 * A profile does not, but clearing it makes more sense than having it 466 * set with an exclusive access on address zero. 467 */ 468 arm_clear_exclusive(env); 469 470 if (arm_feature(env, ARM_FEATURE_PMSA)) { 471 if (cpu->pmsav7_dregion > 0) { 472 if (arm_feature(env, ARM_FEATURE_V8)) { 473 memset(env->pmsav8.rbar[M_REG_NS], 0, 474 sizeof(*env->pmsav8.rbar[M_REG_NS]) 475 * cpu->pmsav7_dregion); 476 memset(env->pmsav8.rlar[M_REG_NS], 0, 477 sizeof(*env->pmsav8.rlar[M_REG_NS]) 478 * cpu->pmsav7_dregion); 479 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 480 memset(env->pmsav8.rbar[M_REG_S], 0, 481 sizeof(*env->pmsav8.rbar[M_REG_S]) 482 * cpu->pmsav7_dregion); 483 memset(env->pmsav8.rlar[M_REG_S], 0, 484 sizeof(*env->pmsav8.rlar[M_REG_S]) 485 * cpu->pmsav7_dregion); 486 } 487 } else if (arm_feature(env, ARM_FEATURE_V7)) { 488 memset(env->pmsav7.drbar, 0, 489 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 490 memset(env->pmsav7.drsr, 0, 491 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 492 memset(env->pmsav7.dracr, 0, 493 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 494 } 495 } 496 497 if (cpu->pmsav8r_hdregion > 0) { 498 memset(env->pmsav8.hprbar, 0, 499 sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion); 500 memset(env->pmsav8.hprlar, 0, 501 sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion); 502 } 503 504 env->pmsav7.rnr[M_REG_NS] = 0; 505 env->pmsav7.rnr[M_REG_S] = 0; 506 env->pmsav8.mair0[M_REG_NS] = 0; 507 env->pmsav8.mair0[M_REG_S] = 0; 508 env->pmsav8.mair1[M_REG_NS] = 0; 509 env->pmsav8.mair1[M_REG_S] = 0; 510 } 511 512 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 513 if (cpu->sau_sregion > 0) { 514 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 515 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 516 } 517 env->sau.rnr = 0; 518 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 519 * the Cortex-M33 does. 520 */ 521 env->sau.ctrl = 0; 522 } 523 524 set_flush_to_zero(1, &env->vfp.standard_fp_status); 525 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 526 set_default_nan_mode(1, &env->vfp.standard_fp_status); 527 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); 528 set_float_detect_tininess(float_tininess_before_rounding, 529 &env->vfp.fp_status); 530 set_float_detect_tininess(float_tininess_before_rounding, 531 &env->vfp.standard_fp_status); 532 set_float_detect_tininess(float_tininess_before_rounding, 533 &env->vfp.fp_status_f16); 534 set_float_detect_tininess(float_tininess_before_rounding, 535 &env->vfp.standard_fp_status_f16); 536 #ifndef CONFIG_USER_ONLY 537 if (kvm_enabled()) { 538 kvm_arm_reset_vcpu(cpu); 539 } 540 #endif 541 542 hw_breakpoint_update_all(cpu); 543 hw_watchpoint_update_all(cpu); 544 arm_rebuild_hflags(env); 545 } 546 547 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 548 549 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 550 unsigned int target_el, 551 unsigned int cur_el, bool secure, 552 uint64_t hcr_el2) 553 { 554 CPUARMState *env = cs->env_ptr; 555 bool pstate_unmasked; 556 bool unmasked = false; 557 558 /* 559 * Don't take exceptions if they target a lower EL. 560 * This check should catch any exceptions that would not be taken 561 * but left pending. 562 */ 563 if (cur_el > target_el) { 564 return false; 565 } 566 567 switch (excp_idx) { 568 case EXCP_FIQ: 569 pstate_unmasked = !(env->daif & PSTATE_F); 570 break; 571 572 case EXCP_IRQ: 573 pstate_unmasked = !(env->daif & PSTATE_I); 574 break; 575 576 case EXCP_VFIQ: 577 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 578 /* VFIQs are only taken when hypervized. */ 579 return false; 580 } 581 return !(env->daif & PSTATE_F); 582 case EXCP_VIRQ: 583 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 584 /* VIRQs are only taken when hypervized. */ 585 return false; 586 } 587 return !(env->daif & PSTATE_I); 588 case EXCP_VSERR: 589 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { 590 /* VIRQs are only taken when hypervized. */ 591 return false; 592 } 593 return !(env->daif & PSTATE_A); 594 default: 595 g_assert_not_reached(); 596 } 597 598 /* 599 * Use the target EL, current execution state and SCR/HCR settings to 600 * determine whether the corresponding CPSR bit is used to mask the 601 * interrupt. 602 */ 603 if ((target_el > cur_el) && (target_el != 1)) { 604 /* Exceptions targeting a higher EL may not be maskable */ 605 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 606 switch (target_el) { 607 case 2: 608 /* 609 * According to ARM DDI 0487H.a, an interrupt can be masked 610 * when HCR_E2H and HCR_TGE are both set regardless of the 611 * current Security state. Note that we need to revisit this 612 * part again once we need to support NMI. 613 */ 614 if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { 615 unmasked = true; 616 } 617 break; 618 case 3: 619 /* Interrupt cannot be masked when the target EL is 3 */ 620 unmasked = true; 621 break; 622 default: 623 g_assert_not_reached(); 624 } 625 } else { 626 /* 627 * The old 32-bit-only environment has a more complicated 628 * masking setup. HCR and SCR bits not only affect interrupt 629 * routing but also change the behaviour of masking. 630 */ 631 bool hcr, scr; 632 633 switch (excp_idx) { 634 case EXCP_FIQ: 635 /* 636 * If FIQs are routed to EL3 or EL2 then there are cases where 637 * we override the CPSR.F in determining if the exception is 638 * masked or not. If neither of these are set then we fall back 639 * to the CPSR.F setting otherwise we further assess the state 640 * below. 641 */ 642 hcr = hcr_el2 & HCR_FMO; 643 scr = (env->cp15.scr_el3 & SCR_FIQ); 644 645 /* 646 * When EL3 is 32-bit, the SCR.FW bit controls whether the 647 * CPSR.F bit masks FIQ interrupts when taken in non-secure 648 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 649 * when non-secure but only when FIQs are only routed to EL3. 650 */ 651 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 652 break; 653 case EXCP_IRQ: 654 /* 655 * When EL3 execution state is 32-bit, if HCR.IMO is set then 656 * we may override the CPSR.I masking when in non-secure state. 657 * The SCR.IRQ setting has already been taken into consideration 658 * when setting the target EL, so it does not have a further 659 * affect here. 660 */ 661 hcr = hcr_el2 & HCR_IMO; 662 scr = false; 663 break; 664 default: 665 g_assert_not_reached(); 666 } 667 668 if ((scr || hcr) && !secure) { 669 unmasked = true; 670 } 671 } 672 } 673 674 /* 675 * The PSTATE bits only mask the interrupt if we have not overriden the 676 * ability above. 677 */ 678 return unmasked || pstate_unmasked; 679 } 680 681 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 682 { 683 CPUClass *cc = CPU_GET_CLASS(cs); 684 CPUARMState *env = cs->env_ptr; 685 uint32_t cur_el = arm_current_el(env); 686 bool secure = arm_is_secure(env); 687 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 688 uint32_t target_el; 689 uint32_t excp_idx; 690 691 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 692 693 if (interrupt_request & CPU_INTERRUPT_FIQ) { 694 excp_idx = EXCP_FIQ; 695 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 696 if (arm_excp_unmasked(cs, excp_idx, target_el, 697 cur_el, secure, hcr_el2)) { 698 goto found; 699 } 700 } 701 if (interrupt_request & CPU_INTERRUPT_HARD) { 702 excp_idx = EXCP_IRQ; 703 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 704 if (arm_excp_unmasked(cs, excp_idx, target_el, 705 cur_el, secure, hcr_el2)) { 706 goto found; 707 } 708 } 709 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 710 excp_idx = EXCP_VIRQ; 711 target_el = 1; 712 if (arm_excp_unmasked(cs, excp_idx, target_el, 713 cur_el, secure, hcr_el2)) { 714 goto found; 715 } 716 } 717 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 718 excp_idx = EXCP_VFIQ; 719 target_el = 1; 720 if (arm_excp_unmasked(cs, excp_idx, target_el, 721 cur_el, secure, hcr_el2)) { 722 goto found; 723 } 724 } 725 if (interrupt_request & CPU_INTERRUPT_VSERR) { 726 excp_idx = EXCP_VSERR; 727 target_el = 1; 728 if (arm_excp_unmasked(cs, excp_idx, target_el, 729 cur_el, secure, hcr_el2)) { 730 /* Taking a virtual abort clears HCR_EL2.VSE */ 731 env->cp15.hcr_el2 &= ~HCR_VSE; 732 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 733 goto found; 734 } 735 } 736 return false; 737 738 found: 739 cs->exception_index = excp_idx; 740 env->exception.target_el = target_el; 741 cc->tcg_ops->do_interrupt(cs); 742 return true; 743 } 744 745 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 746 747 void arm_cpu_update_virq(ARMCPU *cpu) 748 { 749 /* 750 * Update the interrupt level for VIRQ, which is the logical OR of 751 * the HCR_EL2.VI bit and the input line level from the GIC. 752 */ 753 CPUARMState *env = &cpu->env; 754 CPUState *cs = CPU(cpu); 755 756 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 757 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 758 759 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 760 if (new_state) { 761 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 762 } else { 763 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 764 } 765 } 766 } 767 768 void arm_cpu_update_vfiq(ARMCPU *cpu) 769 { 770 /* 771 * Update the interrupt level for VFIQ, which is the logical OR of 772 * the HCR_EL2.VF bit and the input line level from the GIC. 773 */ 774 CPUARMState *env = &cpu->env; 775 CPUState *cs = CPU(cpu); 776 777 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 778 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 779 780 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 781 if (new_state) { 782 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 783 } else { 784 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 785 } 786 } 787 } 788 789 void arm_cpu_update_vserr(ARMCPU *cpu) 790 { 791 /* 792 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. 793 */ 794 CPUARMState *env = &cpu->env; 795 CPUState *cs = CPU(cpu); 796 797 bool new_state = env->cp15.hcr_el2 & HCR_VSE; 798 799 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { 800 if (new_state) { 801 cpu_interrupt(cs, CPU_INTERRUPT_VSERR); 802 } else { 803 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 804 } 805 } 806 } 807 808 #ifndef CONFIG_USER_ONLY 809 static void arm_cpu_set_irq(void *opaque, int irq, int level) 810 { 811 ARMCPU *cpu = opaque; 812 CPUARMState *env = &cpu->env; 813 CPUState *cs = CPU(cpu); 814 static const int mask[] = { 815 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 816 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 817 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 818 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 819 }; 820 821 if (!arm_feature(env, ARM_FEATURE_EL2) && 822 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { 823 /* 824 * The GIC might tell us about VIRQ and VFIQ state, but if we don't 825 * have EL2 support we don't care. (Unless the guest is doing something 826 * silly this will only be calls saying "level is still 0".) 827 */ 828 return; 829 } 830 831 if (level) { 832 env->irq_line_state |= mask[irq]; 833 } else { 834 env->irq_line_state &= ~mask[irq]; 835 } 836 837 switch (irq) { 838 case ARM_CPU_VIRQ: 839 arm_cpu_update_virq(cpu); 840 break; 841 case ARM_CPU_VFIQ: 842 arm_cpu_update_vfiq(cpu); 843 break; 844 case ARM_CPU_IRQ: 845 case ARM_CPU_FIQ: 846 if (level) { 847 cpu_interrupt(cs, mask[irq]); 848 } else { 849 cpu_reset_interrupt(cs, mask[irq]); 850 } 851 break; 852 default: 853 g_assert_not_reached(); 854 } 855 } 856 857 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 858 { 859 #ifdef CONFIG_KVM 860 ARMCPU *cpu = opaque; 861 CPUARMState *env = &cpu->env; 862 CPUState *cs = CPU(cpu); 863 uint32_t linestate_bit; 864 int irq_id; 865 866 switch (irq) { 867 case ARM_CPU_IRQ: 868 irq_id = KVM_ARM_IRQ_CPU_IRQ; 869 linestate_bit = CPU_INTERRUPT_HARD; 870 break; 871 case ARM_CPU_FIQ: 872 irq_id = KVM_ARM_IRQ_CPU_FIQ; 873 linestate_bit = CPU_INTERRUPT_FIQ; 874 break; 875 default: 876 g_assert_not_reached(); 877 } 878 879 if (level) { 880 env->irq_line_state |= linestate_bit; 881 } else { 882 env->irq_line_state &= ~linestate_bit; 883 } 884 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 885 #endif 886 } 887 888 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 889 { 890 ARMCPU *cpu = ARM_CPU(cs); 891 CPUARMState *env = &cpu->env; 892 893 cpu_synchronize_state(cs); 894 return arm_cpu_data_is_big_endian(env); 895 } 896 897 #endif 898 899 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 900 { 901 ARMCPU *ac = ARM_CPU(cpu); 902 CPUARMState *env = &ac->env; 903 bool sctlr_b; 904 905 if (is_a64(env)) { 906 info->cap_arch = CS_ARCH_ARM64; 907 info->cap_insn_unit = 4; 908 info->cap_insn_split = 4; 909 } else { 910 int cap_mode; 911 if (env->thumb) { 912 info->cap_insn_unit = 2; 913 info->cap_insn_split = 4; 914 cap_mode = CS_MODE_THUMB; 915 } else { 916 info->cap_insn_unit = 4; 917 info->cap_insn_split = 4; 918 cap_mode = CS_MODE_ARM; 919 } 920 if (arm_feature(env, ARM_FEATURE_V8)) { 921 cap_mode |= CS_MODE_V8; 922 } 923 if (arm_feature(env, ARM_FEATURE_M)) { 924 cap_mode |= CS_MODE_MCLASS; 925 } 926 info->cap_arch = CS_ARCH_ARM; 927 info->cap_mode = cap_mode; 928 } 929 930 sctlr_b = arm_sctlr_b(env); 931 if (bswap_code(sctlr_b)) { 932 #if TARGET_BIG_ENDIAN 933 info->endian = BFD_ENDIAN_LITTLE; 934 #else 935 info->endian = BFD_ENDIAN_BIG; 936 #endif 937 } 938 info->flags &= ~INSN_ARM_BE32; 939 #ifndef CONFIG_USER_ONLY 940 if (sctlr_b) { 941 info->flags |= INSN_ARM_BE32; 942 } 943 #endif 944 } 945 946 #ifdef TARGET_AARCH64 947 948 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 949 { 950 ARMCPU *cpu = ARM_CPU(cs); 951 CPUARMState *env = &cpu->env; 952 uint32_t psr = pstate_read(env); 953 int i; 954 int el = arm_current_el(env); 955 const char *ns_status; 956 bool sve; 957 958 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 959 for (i = 0; i < 32; i++) { 960 if (i == 31) { 961 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 962 } else { 963 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 964 (i + 2) % 3 ? " " : "\n"); 965 } 966 } 967 968 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 969 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 970 } else { 971 ns_status = ""; 972 } 973 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 974 psr, 975 psr & PSTATE_N ? 'N' : '-', 976 psr & PSTATE_Z ? 'Z' : '-', 977 psr & PSTATE_C ? 'C' : '-', 978 psr & PSTATE_V ? 'V' : '-', 979 ns_status, 980 el, 981 psr & PSTATE_SP ? 'h' : 't'); 982 983 if (cpu_isar_feature(aa64_sme, cpu)) { 984 qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c", 985 env->svcr, 986 (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), 987 (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); 988 } 989 if (cpu_isar_feature(aa64_bti, cpu)) { 990 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 991 } 992 if (!(flags & CPU_DUMP_FPU)) { 993 qemu_fprintf(f, "\n"); 994 return; 995 } 996 if (fp_exception_el(env, el) != 0) { 997 qemu_fprintf(f, " FPU disabled\n"); 998 return; 999 } 1000 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 1001 vfp_get_fpcr(env), vfp_get_fpsr(env)); 1002 1003 if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) { 1004 sve = sme_exception_el(env, el) == 0; 1005 } else if (cpu_isar_feature(aa64_sve, cpu)) { 1006 sve = sve_exception_el(env, el) == 0; 1007 } else { 1008 sve = false; 1009 } 1010 1011 if (sve) { 1012 int j, zcr_len = sve_vqm1_for_el(env, el); 1013 1014 for (i = 0; i <= FFR_PRED_NUM; i++) { 1015 bool eol; 1016 if (i == FFR_PRED_NUM) { 1017 qemu_fprintf(f, "FFR="); 1018 /* It's last, so end the line. */ 1019 eol = true; 1020 } else { 1021 qemu_fprintf(f, "P%02d=", i); 1022 switch (zcr_len) { 1023 case 0: 1024 eol = i % 8 == 7; 1025 break; 1026 case 1: 1027 eol = i % 6 == 5; 1028 break; 1029 case 2: 1030 case 3: 1031 eol = i % 3 == 2; 1032 break; 1033 default: 1034 /* More than one quadword per predicate. */ 1035 eol = true; 1036 break; 1037 } 1038 } 1039 for (j = zcr_len / 4; j >= 0; j--) { 1040 int digits; 1041 if (j * 4 + 4 <= zcr_len + 1) { 1042 digits = 16; 1043 } else { 1044 digits = (zcr_len % 4 + 1) * 4; 1045 } 1046 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 1047 env->vfp.pregs[i].p[j], 1048 j ? ":" : eol ? "\n" : " "); 1049 } 1050 } 1051 1052 for (i = 0; i < 32; i++) { 1053 if (zcr_len == 0) { 1054 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1055 i, env->vfp.zregs[i].d[1], 1056 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 1057 } else if (zcr_len == 1) { 1058 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 1059 ":%016" PRIx64 ":%016" PRIx64 "\n", 1060 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 1061 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 1062 } else { 1063 for (j = zcr_len; j >= 0; j--) { 1064 bool odd = (zcr_len - j) % 2 != 0; 1065 if (j == zcr_len) { 1066 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 1067 } else if (!odd) { 1068 if (j > 0) { 1069 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 1070 } else { 1071 qemu_fprintf(f, " [%x]=", j); 1072 } 1073 } 1074 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 1075 env->vfp.zregs[i].d[j * 2 + 1], 1076 env->vfp.zregs[i].d[j * 2], 1077 odd || j == 0 ? "\n" : ":"); 1078 } 1079 } 1080 } 1081 } else { 1082 for (i = 0; i < 32; i++) { 1083 uint64_t *q = aa64_vfp_qreg(env, i); 1084 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1085 i, q[1], q[0], (i & 1 ? "\n" : " ")); 1086 } 1087 } 1088 } 1089 1090 #else 1091 1092 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1093 { 1094 g_assert_not_reached(); 1095 } 1096 1097 #endif 1098 1099 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1100 { 1101 ARMCPU *cpu = ARM_CPU(cs); 1102 CPUARMState *env = &cpu->env; 1103 int i; 1104 1105 if (is_a64(env)) { 1106 aarch64_cpu_dump_state(cs, f, flags); 1107 return; 1108 } 1109 1110 for (i = 0; i < 16; i++) { 1111 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 1112 if ((i % 4) == 3) { 1113 qemu_fprintf(f, "\n"); 1114 } else { 1115 qemu_fprintf(f, " "); 1116 } 1117 } 1118 1119 if (arm_feature(env, ARM_FEATURE_M)) { 1120 uint32_t xpsr = xpsr_read(env); 1121 const char *mode; 1122 const char *ns_status = ""; 1123 1124 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1125 ns_status = env->v7m.secure ? "S " : "NS "; 1126 } 1127 1128 if (xpsr & XPSR_EXCP) { 1129 mode = "handler"; 1130 } else { 1131 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 1132 mode = "unpriv-thread"; 1133 } else { 1134 mode = "priv-thread"; 1135 } 1136 } 1137 1138 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 1139 xpsr, 1140 xpsr & XPSR_N ? 'N' : '-', 1141 xpsr & XPSR_Z ? 'Z' : '-', 1142 xpsr & XPSR_C ? 'C' : '-', 1143 xpsr & XPSR_V ? 'V' : '-', 1144 xpsr & XPSR_T ? 'T' : 'A', 1145 ns_status, 1146 mode); 1147 } else { 1148 uint32_t psr = cpsr_read(env); 1149 const char *ns_status = ""; 1150 1151 if (arm_feature(env, ARM_FEATURE_EL3) && 1152 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1153 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1154 } 1155 1156 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1157 psr, 1158 psr & CPSR_N ? 'N' : '-', 1159 psr & CPSR_Z ? 'Z' : '-', 1160 psr & CPSR_C ? 'C' : '-', 1161 psr & CPSR_V ? 'V' : '-', 1162 psr & CPSR_T ? 'T' : 'A', 1163 ns_status, 1164 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1165 } 1166 1167 if (flags & CPU_DUMP_FPU) { 1168 int numvfpregs = 0; 1169 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1170 numvfpregs = 32; 1171 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1172 numvfpregs = 16; 1173 } 1174 for (i = 0; i < numvfpregs; i++) { 1175 uint64_t v = *aa32_vfp_dreg(env, i); 1176 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1177 i * 2, (uint32_t)v, 1178 i * 2 + 1, (uint32_t)(v >> 32), 1179 i, v); 1180 } 1181 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1182 if (cpu_isar_feature(aa32_mve, cpu)) { 1183 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1184 } 1185 } 1186 } 1187 1188 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 1189 { 1190 uint32_t Aff1 = idx / clustersz; 1191 uint32_t Aff0 = idx % clustersz; 1192 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1193 } 1194 1195 static void arm_cpu_initfn(Object *obj) 1196 { 1197 ARMCPU *cpu = ARM_CPU(obj); 1198 1199 cpu_set_cpustate_pointers(cpu); 1200 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, 1201 NULL, g_free); 1202 1203 QLIST_INIT(&cpu->pre_el_change_hooks); 1204 QLIST_INIT(&cpu->el_change_hooks); 1205 1206 #ifdef CONFIG_USER_ONLY 1207 # ifdef TARGET_AARCH64 1208 /* 1209 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME. 1210 * These values were chosen to fit within the default signal frame. 1211 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length, 1212 * and our corresponding cpu property. 1213 */ 1214 cpu->sve_default_vq = 4; 1215 cpu->sme_default_vq = 2; 1216 # endif 1217 #else 1218 /* Our inbound IRQ and FIQ lines */ 1219 if (kvm_enabled()) { 1220 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1221 * the same interface as non-KVM CPUs. 1222 */ 1223 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1224 } else { 1225 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1226 } 1227 1228 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1229 ARRAY_SIZE(cpu->gt_timer_outputs)); 1230 1231 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1232 "gicv3-maintenance-interrupt", 1); 1233 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1234 "pmu-interrupt", 1); 1235 #endif 1236 1237 /* DTB consumers generally don't in fact care what the 'compatible' 1238 * string is, so always provide some string and trust that a hypothetical 1239 * picky DTB consumer will also provide a helpful error message. 1240 */ 1241 cpu->dtb_compatible = "qemu,unknown"; 1242 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ 1243 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1244 1245 if (tcg_enabled() || hvf_enabled()) { 1246 /* TCG and HVF implement PSCI 1.1 */ 1247 cpu->psci_version = QEMU_PSCI_VERSION_1_1; 1248 } 1249 } 1250 1251 static Property arm_cpu_gt_cntfrq_property = 1252 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1253 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1254 1255 static Property arm_cpu_reset_cbar_property = 1256 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1257 1258 static Property arm_cpu_reset_hivecs_property = 1259 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1260 1261 #ifndef CONFIG_USER_ONLY 1262 static Property arm_cpu_has_el2_property = 1263 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1264 1265 static Property arm_cpu_has_el3_property = 1266 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1267 #endif 1268 1269 static Property arm_cpu_cfgend_property = 1270 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1271 1272 static Property arm_cpu_has_vfp_property = 1273 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1274 1275 static Property arm_cpu_has_neon_property = 1276 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1277 1278 static Property arm_cpu_has_dsp_property = 1279 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1280 1281 static Property arm_cpu_has_mpu_property = 1282 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1283 1284 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1285 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1286 * the right value for that particular CPU type, and we don't want 1287 * to override that with an incorrect constant value. 1288 */ 1289 static Property arm_cpu_pmsav7_dregion_property = 1290 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1291 pmsav7_dregion, 1292 qdev_prop_uint32, uint32_t); 1293 1294 static bool arm_get_pmu(Object *obj, Error **errp) 1295 { 1296 ARMCPU *cpu = ARM_CPU(obj); 1297 1298 return cpu->has_pmu; 1299 } 1300 1301 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1302 { 1303 ARMCPU *cpu = ARM_CPU(obj); 1304 1305 if (value) { 1306 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1307 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1308 return; 1309 } 1310 set_feature(&cpu->env, ARM_FEATURE_PMU); 1311 } else { 1312 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1313 } 1314 cpu->has_pmu = value; 1315 } 1316 1317 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1318 { 1319 /* 1320 * The exact approach to calculating guest ticks is: 1321 * 1322 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1323 * NANOSECONDS_PER_SECOND); 1324 * 1325 * We don't do that. Rather we intentionally use integer division 1326 * truncation below and in the caller for the conversion of host monotonic 1327 * time to guest ticks to provide the exact inverse for the semantics of 1328 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1329 * it loses precision when representing frequencies where 1330 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1331 * provide an exact inverse leads to scheduling timers with negative 1332 * periods, which in turn leads to sticky behaviour in the guest. 1333 * 1334 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1335 * cannot become zero. 1336 */ 1337 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1338 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1339 } 1340 1341 void arm_cpu_post_init(Object *obj) 1342 { 1343 ARMCPU *cpu = ARM_CPU(obj); 1344 1345 /* M profile implies PMSA. We have to do this here rather than 1346 * in realize with the other feature-implication checks because 1347 * we look at the PMSA bit to see if we should add some properties. 1348 */ 1349 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1350 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1351 } 1352 1353 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1354 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1355 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1356 } 1357 1358 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1359 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1360 } 1361 1362 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1363 object_property_add_uint64_ptr(obj, "rvbar", 1364 &cpu->rvbar_prop, 1365 OBJ_PROP_FLAG_READWRITE); 1366 } 1367 1368 #ifndef CONFIG_USER_ONLY 1369 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1370 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1371 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1372 */ 1373 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1374 1375 object_property_add_link(obj, "secure-memory", 1376 TYPE_MEMORY_REGION, 1377 (Object **)&cpu->secure_memory, 1378 qdev_prop_allow_set_link_before_realize, 1379 OBJ_PROP_LINK_STRONG); 1380 } 1381 1382 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1383 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1384 } 1385 #endif 1386 1387 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1388 cpu->has_pmu = true; 1389 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1390 } 1391 1392 /* 1393 * Allow user to turn off VFP and Neon support, but only for TCG -- 1394 * KVM does not currently allow us to lie to the guest about its 1395 * ID/feature registers, so the guest always sees what the host has. 1396 */ 1397 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 1398 ? cpu_isar_feature(aa64_fp_simd, cpu) 1399 : cpu_isar_feature(aa32_vfp, cpu)) { 1400 cpu->has_vfp = true; 1401 if (!kvm_enabled()) { 1402 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1403 } 1404 } 1405 1406 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1407 cpu->has_neon = true; 1408 if (!kvm_enabled()) { 1409 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1410 } 1411 } 1412 1413 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1414 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1415 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1416 } 1417 1418 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1419 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1420 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1421 qdev_property_add_static(DEVICE(obj), 1422 &arm_cpu_pmsav7_dregion_property); 1423 } 1424 } 1425 1426 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1427 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1428 qdev_prop_allow_set_link_before_realize, 1429 OBJ_PROP_LINK_STRONG); 1430 /* 1431 * M profile: initial value of the Secure VTOR. We can't just use 1432 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1433 * the property to be set after realize. 1434 */ 1435 object_property_add_uint32_ptr(obj, "init-svtor", 1436 &cpu->init_svtor, 1437 OBJ_PROP_FLAG_READWRITE); 1438 } 1439 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1440 /* 1441 * Initial value of the NS VTOR (for cores without the Security 1442 * extension, this is the only VTOR) 1443 */ 1444 object_property_add_uint32_ptr(obj, "init-nsvtor", 1445 &cpu->init_nsvtor, 1446 OBJ_PROP_FLAG_READWRITE); 1447 } 1448 1449 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ 1450 object_property_add_uint32_ptr(obj, "psci-conduit", 1451 &cpu->psci_conduit, 1452 OBJ_PROP_FLAG_READWRITE); 1453 1454 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1455 1456 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1457 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1458 } 1459 1460 if (kvm_enabled()) { 1461 kvm_arm_add_vcpu_properties(obj); 1462 } 1463 1464 #ifndef CONFIG_USER_ONLY 1465 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1466 cpu_isar_feature(aa64_mte, cpu)) { 1467 object_property_add_link(obj, "tag-memory", 1468 TYPE_MEMORY_REGION, 1469 (Object **)&cpu->tag_memory, 1470 qdev_prop_allow_set_link_before_realize, 1471 OBJ_PROP_LINK_STRONG); 1472 1473 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1474 object_property_add_link(obj, "secure-tag-memory", 1475 TYPE_MEMORY_REGION, 1476 (Object **)&cpu->secure_tag_memory, 1477 qdev_prop_allow_set_link_before_realize, 1478 OBJ_PROP_LINK_STRONG); 1479 } 1480 } 1481 #endif 1482 } 1483 1484 static void arm_cpu_finalizefn(Object *obj) 1485 { 1486 ARMCPU *cpu = ARM_CPU(obj); 1487 ARMELChangeHook *hook, *next; 1488 1489 g_hash_table_destroy(cpu->cp_regs); 1490 1491 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1492 QLIST_REMOVE(hook, node); 1493 g_free(hook); 1494 } 1495 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1496 QLIST_REMOVE(hook, node); 1497 g_free(hook); 1498 } 1499 #ifndef CONFIG_USER_ONLY 1500 if (cpu->pmu_timer) { 1501 timer_free(cpu->pmu_timer); 1502 } 1503 #endif 1504 } 1505 1506 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1507 { 1508 Error *local_err = NULL; 1509 1510 #ifdef TARGET_AARCH64 1511 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1512 arm_cpu_sve_finalize(cpu, &local_err); 1513 if (local_err != NULL) { 1514 error_propagate(errp, local_err); 1515 return; 1516 } 1517 1518 arm_cpu_sme_finalize(cpu, &local_err); 1519 if (local_err != NULL) { 1520 error_propagate(errp, local_err); 1521 return; 1522 } 1523 1524 arm_cpu_pauth_finalize(cpu, &local_err); 1525 if (local_err != NULL) { 1526 error_propagate(errp, local_err); 1527 return; 1528 } 1529 1530 arm_cpu_lpa2_finalize(cpu, &local_err); 1531 if (local_err != NULL) { 1532 error_propagate(errp, local_err); 1533 return; 1534 } 1535 } 1536 #endif 1537 1538 if (kvm_enabled()) { 1539 kvm_arm_steal_time_finalize(cpu, &local_err); 1540 if (local_err != NULL) { 1541 error_propagate(errp, local_err); 1542 return; 1543 } 1544 } 1545 } 1546 1547 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1548 { 1549 CPUState *cs = CPU(dev); 1550 ARMCPU *cpu = ARM_CPU(dev); 1551 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1552 CPUARMState *env = &cpu->env; 1553 int pagebits; 1554 Error *local_err = NULL; 1555 bool no_aa32 = false; 1556 1557 /* If we needed to query the host kernel for the CPU features 1558 * then it's possible that might have failed in the initfn, but 1559 * this is the first point where we can report it. 1560 */ 1561 if (cpu->host_cpu_probe_failed) { 1562 if (!kvm_enabled() && !hvf_enabled()) { 1563 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1564 } else { 1565 error_setg(errp, "Failed to retrieve host CPU features"); 1566 } 1567 return; 1568 } 1569 1570 #ifndef CONFIG_USER_ONLY 1571 /* The NVIC and M-profile CPU are two halves of a single piece of 1572 * hardware; trying to use one without the other is a command line 1573 * error and will result in segfaults if not caught here. 1574 */ 1575 if (arm_feature(env, ARM_FEATURE_M)) { 1576 if (!env->nvic) { 1577 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1578 return; 1579 } 1580 } else { 1581 if (env->nvic) { 1582 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1583 return; 1584 } 1585 } 1586 1587 if (!tcg_enabled() && !qtest_enabled()) { 1588 /* 1589 * We assume that no accelerator except TCG (and the "not really an 1590 * accelerator" qtest) can handle these features, because Arm hardware 1591 * virtualization can't virtualize them. 1592 * 1593 * Catch all the cases which might cause us to create more than one 1594 * address space for the CPU (otherwise we will assert() later in 1595 * cpu_address_space_init()). 1596 */ 1597 if (arm_feature(env, ARM_FEATURE_M)) { 1598 error_setg(errp, 1599 "Cannot enable %s when using an M-profile guest CPU", 1600 current_accel_name()); 1601 return; 1602 } 1603 if (cpu->has_el3) { 1604 error_setg(errp, 1605 "Cannot enable %s when guest CPU has EL3 enabled", 1606 current_accel_name()); 1607 return; 1608 } 1609 if (cpu->tag_memory) { 1610 error_setg(errp, 1611 "Cannot enable %s when guest CPUs has MTE enabled", 1612 current_accel_name()); 1613 return; 1614 } 1615 } 1616 1617 { 1618 uint64_t scale; 1619 1620 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1621 if (!cpu->gt_cntfrq_hz) { 1622 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1623 cpu->gt_cntfrq_hz); 1624 return; 1625 } 1626 scale = gt_cntfrq_period_ns(cpu); 1627 } else { 1628 scale = GTIMER_SCALE; 1629 } 1630 1631 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1632 arm_gt_ptimer_cb, cpu); 1633 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1634 arm_gt_vtimer_cb, cpu); 1635 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1636 arm_gt_htimer_cb, cpu); 1637 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1638 arm_gt_stimer_cb, cpu); 1639 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1640 arm_gt_hvtimer_cb, cpu); 1641 } 1642 #endif 1643 1644 cpu_exec_realizefn(cs, &local_err); 1645 if (local_err != NULL) { 1646 error_propagate(errp, local_err); 1647 return; 1648 } 1649 1650 arm_cpu_finalize_features(cpu, &local_err); 1651 if (local_err != NULL) { 1652 error_propagate(errp, local_err); 1653 return; 1654 } 1655 1656 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1657 cpu->has_vfp != cpu->has_neon) { 1658 /* 1659 * This is an architectural requirement for AArch64; AArch32 is 1660 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1661 */ 1662 error_setg(errp, 1663 "AArch64 CPUs must have both VFP and Neon or neither"); 1664 return; 1665 } 1666 1667 if (!cpu->has_vfp) { 1668 uint64_t t; 1669 uint32_t u; 1670 1671 t = cpu->isar.id_aa64isar1; 1672 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1673 cpu->isar.id_aa64isar1 = t; 1674 1675 t = cpu->isar.id_aa64pfr0; 1676 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1677 cpu->isar.id_aa64pfr0 = t; 1678 1679 u = cpu->isar.id_isar6; 1680 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1681 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1682 cpu->isar.id_isar6 = u; 1683 1684 u = cpu->isar.mvfr0; 1685 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1686 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1687 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1688 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1689 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1690 if (!arm_feature(env, ARM_FEATURE_M)) { 1691 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1692 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1693 } 1694 cpu->isar.mvfr0 = u; 1695 1696 u = cpu->isar.mvfr1; 1697 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1698 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1699 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1700 if (arm_feature(env, ARM_FEATURE_M)) { 1701 u = FIELD_DP32(u, MVFR1, FP16, 0); 1702 } 1703 cpu->isar.mvfr1 = u; 1704 1705 u = cpu->isar.mvfr2; 1706 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1707 cpu->isar.mvfr2 = u; 1708 } 1709 1710 if (!cpu->has_neon) { 1711 uint64_t t; 1712 uint32_t u; 1713 1714 unset_feature(env, ARM_FEATURE_NEON); 1715 1716 t = cpu->isar.id_aa64isar0; 1717 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); 1718 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); 1719 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); 1720 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); 1721 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); 1722 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); 1723 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1724 cpu->isar.id_aa64isar0 = t; 1725 1726 t = cpu->isar.id_aa64isar1; 1727 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1728 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 1729 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 1730 cpu->isar.id_aa64isar1 = t; 1731 1732 t = cpu->isar.id_aa64pfr0; 1733 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1734 cpu->isar.id_aa64pfr0 = t; 1735 1736 u = cpu->isar.id_isar5; 1737 u = FIELD_DP32(u, ID_ISAR5, AES, 0); 1738 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); 1739 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); 1740 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1741 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1742 cpu->isar.id_isar5 = u; 1743 1744 u = cpu->isar.id_isar6; 1745 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1746 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1747 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1748 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 1749 cpu->isar.id_isar6 = u; 1750 1751 if (!arm_feature(env, ARM_FEATURE_M)) { 1752 u = cpu->isar.mvfr1; 1753 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1754 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1755 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1756 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1757 cpu->isar.mvfr1 = u; 1758 1759 u = cpu->isar.mvfr2; 1760 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1761 cpu->isar.mvfr2 = u; 1762 } 1763 } 1764 1765 if (!cpu->has_neon && !cpu->has_vfp) { 1766 uint64_t t; 1767 uint32_t u; 1768 1769 t = cpu->isar.id_aa64isar0; 1770 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1771 cpu->isar.id_aa64isar0 = t; 1772 1773 t = cpu->isar.id_aa64isar1; 1774 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1775 cpu->isar.id_aa64isar1 = t; 1776 1777 u = cpu->isar.mvfr0; 1778 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1779 cpu->isar.mvfr0 = u; 1780 1781 /* Despite the name, this field covers both VFP and Neon */ 1782 u = cpu->isar.mvfr1; 1783 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1784 cpu->isar.mvfr1 = u; 1785 } 1786 1787 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1788 uint32_t u; 1789 1790 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1791 1792 u = cpu->isar.id_isar1; 1793 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1794 cpu->isar.id_isar1 = u; 1795 1796 u = cpu->isar.id_isar2; 1797 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1798 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1799 cpu->isar.id_isar2 = u; 1800 1801 u = cpu->isar.id_isar3; 1802 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1803 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1804 cpu->isar.id_isar3 = u; 1805 } 1806 1807 /* Some features automatically imply others: */ 1808 if (arm_feature(env, ARM_FEATURE_V8)) { 1809 if (arm_feature(env, ARM_FEATURE_M)) { 1810 set_feature(env, ARM_FEATURE_V7); 1811 } else { 1812 set_feature(env, ARM_FEATURE_V7VE); 1813 } 1814 } 1815 1816 /* 1817 * There exist AArch64 cpus without AArch32 support. When KVM 1818 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1819 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1820 * As a general principle, we also do not make ID register 1821 * consistency checks anywhere unless using TCG, because only 1822 * for TCG would a consistency-check failure be a QEMU bug. 1823 */ 1824 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1825 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1826 } 1827 1828 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1829 /* v7 Virtualization Extensions. In real hardware this implies 1830 * EL2 and also the presence of the Security Extensions. 1831 * For QEMU, for backwards-compatibility we implement some 1832 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1833 * include the various other features that V7VE implies. 1834 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1835 * Security Extensions is ARM_FEATURE_EL3. 1836 */ 1837 assert(!tcg_enabled() || no_aa32 || 1838 cpu_isar_feature(aa32_arm_div, cpu)); 1839 set_feature(env, ARM_FEATURE_LPAE); 1840 set_feature(env, ARM_FEATURE_V7); 1841 } 1842 if (arm_feature(env, ARM_FEATURE_V7)) { 1843 set_feature(env, ARM_FEATURE_VAPA); 1844 set_feature(env, ARM_FEATURE_THUMB2); 1845 set_feature(env, ARM_FEATURE_MPIDR); 1846 if (!arm_feature(env, ARM_FEATURE_M)) { 1847 set_feature(env, ARM_FEATURE_V6K); 1848 } else { 1849 set_feature(env, ARM_FEATURE_V6); 1850 } 1851 1852 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1853 * non-EL3 configs. This is needed by some legacy boards. 1854 */ 1855 set_feature(env, ARM_FEATURE_VBAR); 1856 } 1857 if (arm_feature(env, ARM_FEATURE_V6K)) { 1858 set_feature(env, ARM_FEATURE_V6); 1859 set_feature(env, ARM_FEATURE_MVFR); 1860 } 1861 if (arm_feature(env, ARM_FEATURE_V6)) { 1862 set_feature(env, ARM_FEATURE_V5); 1863 if (!arm_feature(env, ARM_FEATURE_M)) { 1864 assert(!tcg_enabled() || no_aa32 || 1865 cpu_isar_feature(aa32_jazelle, cpu)); 1866 set_feature(env, ARM_FEATURE_AUXCR); 1867 } 1868 } 1869 if (arm_feature(env, ARM_FEATURE_V5)) { 1870 set_feature(env, ARM_FEATURE_V4T); 1871 } 1872 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1873 set_feature(env, ARM_FEATURE_V7MP); 1874 } 1875 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1876 set_feature(env, ARM_FEATURE_CBAR); 1877 } 1878 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1879 !arm_feature(env, ARM_FEATURE_M)) { 1880 set_feature(env, ARM_FEATURE_THUMB_DSP); 1881 } 1882 1883 /* 1884 * We rely on no XScale CPU having VFP so we can use the same bits in the 1885 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1886 */ 1887 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1888 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1889 !arm_feature(env, ARM_FEATURE_XSCALE)); 1890 1891 if (arm_feature(env, ARM_FEATURE_V7) && 1892 !arm_feature(env, ARM_FEATURE_M) && 1893 !arm_feature(env, ARM_FEATURE_PMSA)) { 1894 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1895 * can use 4K pages. 1896 */ 1897 pagebits = 12; 1898 } else { 1899 /* For CPUs which might have tiny 1K pages, or which have an 1900 * MPU and might have small region sizes, stick with 1K pages. 1901 */ 1902 pagebits = 10; 1903 } 1904 if (!set_preferred_target_page_bits(pagebits)) { 1905 /* This can only ever happen for hotplugging a CPU, or if 1906 * the board code incorrectly creates a CPU which it has 1907 * promised via minimum_page_size that it will not. 1908 */ 1909 error_setg(errp, "This CPU requires a smaller page size than the " 1910 "system is using"); 1911 return; 1912 } 1913 1914 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1915 * We don't support setting cluster ID ([16..23]) (known as Aff2 1916 * in later ARM ARM versions), or any of the higher affinity level fields, 1917 * so these bits always RAZ. 1918 */ 1919 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1920 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1921 ARM_DEFAULT_CPUS_PER_CLUSTER); 1922 } 1923 1924 if (cpu->reset_hivecs) { 1925 cpu->reset_sctlr |= (1 << 13); 1926 } 1927 1928 if (cpu->cfgend) { 1929 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1930 cpu->reset_sctlr |= SCTLR_EE; 1931 } else { 1932 cpu->reset_sctlr |= SCTLR_B; 1933 } 1934 } 1935 1936 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 1937 /* If the has_el3 CPU property is disabled then we need to disable the 1938 * feature. 1939 */ 1940 unset_feature(env, ARM_FEATURE_EL3); 1941 1942 /* 1943 * Disable the security extension feature bits in the processor 1944 * feature registers as well. 1945 */ 1946 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); 1947 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); 1948 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 1949 ID_AA64PFR0, EL3, 0); 1950 } 1951 1952 if (!cpu->has_el2) { 1953 unset_feature(env, ARM_FEATURE_EL2); 1954 } 1955 1956 if (!cpu->has_pmu) { 1957 unset_feature(env, ARM_FEATURE_PMU); 1958 } 1959 if (arm_feature(env, ARM_FEATURE_PMU)) { 1960 pmu_init(cpu); 1961 1962 if (!kvm_enabled()) { 1963 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1964 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1965 } 1966 1967 #ifndef CONFIG_USER_ONLY 1968 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1969 cpu); 1970 #endif 1971 } else { 1972 cpu->isar.id_aa64dfr0 = 1973 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 1974 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 1975 cpu->pmceid0 = 0; 1976 cpu->pmceid1 = 0; 1977 } 1978 1979 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1980 /* 1981 * Disable the hypervisor feature bits in the processor feature 1982 * registers if we don't have EL2. 1983 */ 1984 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 1985 ID_AA64PFR0, EL2, 0); 1986 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, 1987 ID_PFR1, VIRTUALIZATION, 0); 1988 } 1989 1990 #ifndef CONFIG_USER_ONLY 1991 if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { 1992 /* 1993 * Disable the MTE feature bits if we do not have tag-memory 1994 * provided by the machine. 1995 */ 1996 cpu->isar.id_aa64pfr1 = 1997 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 1998 } 1999 #endif 2000 2001 if (tcg_enabled()) { 2002 /* 2003 * Don't report the Statistical Profiling Extension in the ID 2004 * registers, because TCG doesn't implement it yet (not even a 2005 * minimal stub version) and guests will fall over when they 2006 * try to access the non-existent system registers for it. 2007 */ 2008 cpu->isar.id_aa64dfr0 = 2009 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); 2010 } 2011 2012 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 2013 * to false or by setting pmsav7-dregion to 0. 2014 */ 2015 if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) { 2016 cpu->has_mpu = false; 2017 cpu->pmsav7_dregion = 0; 2018 cpu->pmsav8r_hdregion = 0; 2019 } 2020 2021 if (arm_feature(env, ARM_FEATURE_PMSA) && 2022 arm_feature(env, ARM_FEATURE_V7)) { 2023 uint32_t nr = cpu->pmsav7_dregion; 2024 2025 if (nr > 0xff) { 2026 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 2027 return; 2028 } 2029 2030 if (nr) { 2031 if (arm_feature(env, ARM_FEATURE_V8)) { 2032 /* PMSAv8 */ 2033 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 2034 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 2035 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2036 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 2037 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 2038 } 2039 } else { 2040 env->pmsav7.drbar = g_new0(uint32_t, nr); 2041 env->pmsav7.drsr = g_new0(uint32_t, nr); 2042 env->pmsav7.dracr = g_new0(uint32_t, nr); 2043 } 2044 } 2045 2046 if (cpu->pmsav8r_hdregion > 0xff) { 2047 error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32, 2048 cpu->pmsav8r_hdregion); 2049 return; 2050 } 2051 2052 if (cpu->pmsav8r_hdregion) { 2053 env->pmsav8.hprbar = g_new0(uint32_t, 2054 cpu->pmsav8r_hdregion); 2055 env->pmsav8.hprlar = g_new0(uint32_t, 2056 cpu->pmsav8r_hdregion); 2057 } 2058 } 2059 2060 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2061 uint32_t nr = cpu->sau_sregion; 2062 2063 if (nr > 0xff) { 2064 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 2065 return; 2066 } 2067 2068 if (nr) { 2069 env->sau.rbar = g_new0(uint32_t, nr); 2070 env->sau.rlar = g_new0(uint32_t, nr); 2071 } 2072 } 2073 2074 if (arm_feature(env, ARM_FEATURE_EL3)) { 2075 set_feature(env, ARM_FEATURE_VBAR); 2076 } 2077 2078 register_cp_regs_for_features(cpu); 2079 arm_cpu_register_gdb_regs_for_features(cpu); 2080 2081 init_cpreg_list(cpu); 2082 2083 #ifndef CONFIG_USER_ONLY 2084 MachineState *ms = MACHINE(qdev_get_machine()); 2085 unsigned int smp_cpus = ms->smp.cpus; 2086 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 2087 2088 /* 2089 * We must set cs->num_ases to the final value before 2090 * the first call to cpu_address_space_init. 2091 */ 2092 if (cpu->tag_memory != NULL) { 2093 cs->num_ases = 3 + has_secure; 2094 } else { 2095 cs->num_ases = 1 + has_secure; 2096 } 2097 2098 if (has_secure) { 2099 if (!cpu->secure_memory) { 2100 cpu->secure_memory = cs->memory; 2101 } 2102 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 2103 cpu->secure_memory); 2104 } 2105 2106 if (cpu->tag_memory != NULL) { 2107 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 2108 cpu->tag_memory); 2109 if (has_secure) { 2110 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 2111 cpu->secure_tag_memory); 2112 } 2113 } 2114 2115 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 2116 2117 /* No core_count specified, default to smp_cpus. */ 2118 if (cpu->core_count == -1) { 2119 cpu->core_count = smp_cpus; 2120 } 2121 #endif 2122 2123 if (tcg_enabled()) { 2124 int dcz_blocklen = 4 << cpu->dcz_blocksize; 2125 2126 /* 2127 * We only support DCZ blocklen that fits on one page. 2128 * 2129 * Architectually this is always true. However TARGET_PAGE_SIZE 2130 * is variable and, for compatibility with -machine virt-2.7, 2131 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 2132 * But even then, while the largest architectural DCZ blocklen 2133 * is 2KiB, no cpu actually uses such a large blocklen. 2134 */ 2135 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 2136 2137 /* 2138 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 2139 * both nibbles of each byte storing tag data may be written at once. 2140 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 2141 */ 2142 if (cpu_isar_feature(aa64_mte, cpu)) { 2143 assert(dcz_blocklen >= 2 * TAG_GRANULE); 2144 } 2145 } 2146 2147 qemu_init_vcpu(cs); 2148 cpu_reset(cs); 2149 2150 acc->parent_realize(dev, errp); 2151 } 2152 2153 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 2154 { 2155 ObjectClass *oc; 2156 char *typename; 2157 char **cpuname; 2158 const char *cpunamestr; 2159 2160 cpuname = g_strsplit(cpu_model, ",", 1); 2161 cpunamestr = cpuname[0]; 2162 #ifdef CONFIG_USER_ONLY 2163 /* For backwards compatibility usermode emulation allows "-cpu any", 2164 * which has the same semantics as "-cpu max". 2165 */ 2166 if (!strcmp(cpunamestr, "any")) { 2167 cpunamestr = "max"; 2168 } 2169 #endif 2170 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 2171 oc = object_class_by_name(typename); 2172 g_strfreev(cpuname); 2173 g_free(typename); 2174 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 2175 object_class_is_abstract(oc)) { 2176 return NULL; 2177 } 2178 return oc; 2179 } 2180 2181 static Property arm_cpu_properties[] = { 2182 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2183 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2184 mp_affinity, ARM64_AFFINITY_INVALID), 2185 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2186 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2187 DEFINE_PROP_END_OF_LIST() 2188 }; 2189 2190 static gchar *arm_gdb_arch_name(CPUState *cs) 2191 { 2192 ARMCPU *cpu = ARM_CPU(cs); 2193 CPUARMState *env = &cpu->env; 2194 2195 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2196 return g_strdup("iwmmxt"); 2197 } 2198 return g_strdup("arm"); 2199 } 2200 2201 #ifndef CONFIG_USER_ONLY 2202 #include "hw/core/sysemu-cpu-ops.h" 2203 2204 static const struct SysemuCPUOps arm_sysemu_ops = { 2205 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2206 .asidx_from_attrs = arm_asidx_from_attrs, 2207 .write_elf32_note = arm_cpu_write_elf32_note, 2208 .write_elf64_note = arm_cpu_write_elf64_note, 2209 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2210 .legacy_vmsd = &vmstate_arm_cpu, 2211 }; 2212 #endif 2213 2214 #ifdef CONFIG_TCG 2215 static const struct TCGCPUOps arm_tcg_ops = { 2216 .initialize = arm_translate_init, 2217 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2218 .debug_excp_handler = arm_debug_excp_handler, 2219 .restore_state_to_opc = arm_restore_state_to_opc, 2220 2221 #ifdef CONFIG_USER_ONLY 2222 .record_sigsegv = arm_cpu_record_sigsegv, 2223 .record_sigbus = arm_cpu_record_sigbus, 2224 #else 2225 .tlb_fill = arm_cpu_tlb_fill, 2226 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2227 .do_interrupt = arm_cpu_do_interrupt, 2228 .do_transaction_failed = arm_cpu_do_transaction_failed, 2229 .do_unaligned_access = arm_cpu_do_unaligned_access, 2230 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2231 .debug_check_watchpoint = arm_debug_check_watchpoint, 2232 .debug_check_breakpoint = arm_debug_check_breakpoint, 2233 #endif /* !CONFIG_USER_ONLY */ 2234 }; 2235 #endif /* CONFIG_TCG */ 2236 2237 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2238 { 2239 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2240 CPUClass *cc = CPU_CLASS(acc); 2241 DeviceClass *dc = DEVICE_CLASS(oc); 2242 ResettableClass *rc = RESETTABLE_CLASS(oc); 2243 2244 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2245 &acc->parent_realize); 2246 2247 device_class_set_props(dc, arm_cpu_properties); 2248 2249 resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL, 2250 &acc->parent_phases); 2251 2252 cc->class_by_name = arm_cpu_class_by_name; 2253 cc->has_work = arm_cpu_has_work; 2254 cc->dump_state = arm_cpu_dump_state; 2255 cc->set_pc = arm_cpu_set_pc; 2256 cc->get_pc = arm_cpu_get_pc; 2257 cc->gdb_read_register = arm_cpu_gdb_read_register; 2258 cc->gdb_write_register = arm_cpu_gdb_write_register; 2259 #ifndef CONFIG_USER_ONLY 2260 cc->sysemu_ops = &arm_sysemu_ops; 2261 #endif 2262 cc->gdb_num_core_regs = 26; 2263 cc->gdb_core_xml_file = "arm-core.xml"; 2264 cc->gdb_arch_name = arm_gdb_arch_name; 2265 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2266 cc->gdb_stop_before_watchpoint = true; 2267 cc->disas_set_info = arm_disas_set_info; 2268 2269 #ifdef CONFIG_TCG 2270 cc->tcg_ops = &arm_tcg_ops; 2271 #endif /* CONFIG_TCG */ 2272 } 2273 2274 static void arm_cpu_instance_init(Object *obj) 2275 { 2276 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2277 2278 acc->info->initfn(obj); 2279 arm_cpu_post_init(obj); 2280 } 2281 2282 static void cpu_register_class_init(ObjectClass *oc, void *data) 2283 { 2284 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2285 2286 acc->info = data; 2287 } 2288 2289 void arm_cpu_register(const ARMCPUInfo *info) 2290 { 2291 TypeInfo type_info = { 2292 .parent = TYPE_ARM_CPU, 2293 .instance_size = sizeof(ARMCPU), 2294 .instance_align = __alignof__(ARMCPU), 2295 .instance_init = arm_cpu_instance_init, 2296 .class_size = sizeof(ARMCPUClass), 2297 .class_init = info->class_init ?: cpu_register_class_init, 2298 .class_data = (void *)info, 2299 }; 2300 2301 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2302 type_register(&type_info); 2303 g_free((void *)type_info.name); 2304 } 2305 2306 static const TypeInfo arm_cpu_type_info = { 2307 .name = TYPE_ARM_CPU, 2308 .parent = TYPE_CPU, 2309 .instance_size = sizeof(ARMCPU), 2310 .instance_align = __alignof__(ARMCPU), 2311 .instance_init = arm_cpu_initfn, 2312 .instance_finalize = arm_cpu_finalizefn, 2313 .abstract = true, 2314 .class_size = sizeof(ARMCPUClass), 2315 .class_init = arm_cpu_class_init, 2316 }; 2317 2318 static void arm_cpu_register_types(void) 2319 { 2320 type_register_static(&arm_cpu_type_info); 2321 } 2322 2323 type_init(arm_cpu_register_types) 2324