1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu/timer.h" 24 #include "qemu/log.h" 25 #include "exec/page-vary.h" 26 #include "target/arm/idau.h" 27 #include "qemu/module.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "cpu.h" 31 #ifdef CONFIG_TCG 32 #include "hw/core/tcg-cpu-ops.h" 33 #endif /* CONFIG_TCG */ 34 #include "internals.h" 35 #include "exec/exec-all.h" 36 #include "hw/qdev-properties.h" 37 #if !defined(CONFIG_USER_ONLY) 38 #include "hw/loader.h" 39 #include "hw/boards.h" 40 #endif 41 #include "sysemu/tcg.h" 42 #include "sysemu/qtest.h" 43 #include "sysemu/hw_accel.h" 44 #include "kvm_arm.h" 45 #include "disas/capstone.h" 46 #include "fpu/softfloat.h" 47 #include "cpregs.h" 48 49 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 50 { 51 ARMCPU *cpu = ARM_CPU(cs); 52 CPUARMState *env = &cpu->env; 53 54 if (is_a64(env)) { 55 env->pc = value; 56 env->thumb = false; 57 } else { 58 env->regs[15] = value & ~1; 59 env->thumb = value & 1; 60 } 61 } 62 63 static vaddr arm_cpu_get_pc(CPUState *cs) 64 { 65 ARMCPU *cpu = ARM_CPU(cs); 66 CPUARMState *env = &cpu->env; 67 68 if (is_a64(env)) { 69 return env->pc; 70 } else { 71 return env->regs[15]; 72 } 73 } 74 75 #ifdef CONFIG_TCG 76 void arm_cpu_synchronize_from_tb(CPUState *cs, 77 const TranslationBlock *tb) 78 { 79 /* The program counter is always up to date with TARGET_TB_PCREL. */ 80 if (!TARGET_TB_PCREL) { 81 CPUARMState *env = cs->env_ptr; 82 /* 83 * It's OK to look at env for the current mode here, because it's 84 * never possible for an AArch64 TB to chain to an AArch32 TB. 85 */ 86 if (is_a64(env)) { 87 env->pc = tb_pc(tb); 88 } else { 89 env->regs[15] = tb_pc(tb); 90 } 91 } 92 } 93 94 static void arm_restore_state_to_opc(CPUState *cs, 95 const TranslationBlock *tb, 96 const uint64_t *data) 97 { 98 CPUARMState *env = cs->env_ptr; 99 100 if (is_a64(env)) { 101 if (TARGET_TB_PCREL) { 102 env->pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 103 } else { 104 env->pc = data[0]; 105 } 106 env->condexec_bits = 0; 107 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 108 } else { 109 if (TARGET_TB_PCREL) { 110 env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0]; 111 } else { 112 env->regs[15] = data[0]; 113 } 114 env->condexec_bits = data[1]; 115 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 116 } 117 } 118 #endif /* CONFIG_TCG */ 119 120 static bool arm_cpu_has_work(CPUState *cs) 121 { 122 ARMCPU *cpu = ARM_CPU(cs); 123 124 return (cpu->power_state != PSCI_OFF) 125 && cs->interrupt_request & 126 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 127 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR 128 | CPU_INTERRUPT_EXITTB); 129 } 130 131 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 132 void *opaque) 133 { 134 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 135 136 entry->hook = hook; 137 entry->opaque = opaque; 138 139 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 140 } 141 142 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 143 void *opaque) 144 { 145 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 146 147 entry->hook = hook; 148 entry->opaque = opaque; 149 150 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 151 } 152 153 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 154 { 155 /* Reset a single ARMCPRegInfo register */ 156 ARMCPRegInfo *ri = value; 157 ARMCPU *cpu = opaque; 158 159 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { 160 return; 161 } 162 163 if (ri->resetfn) { 164 ri->resetfn(&cpu->env, ri); 165 return; 166 } 167 168 /* A zero offset is never possible as it would be regs[0] 169 * so we use it to indicate that reset is being handled elsewhere. 170 * This is basically only used for fields in non-core coprocessors 171 * (like the pxa2xx ones). 172 */ 173 if (!ri->fieldoffset) { 174 return; 175 } 176 177 if (cpreg_field_is_64bit(ri)) { 178 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 179 } else { 180 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 181 } 182 } 183 184 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 185 { 186 /* Purely an assertion check: we've already done reset once, 187 * so now check that running the reset for the cpreg doesn't 188 * change its value. This traps bugs where two different cpregs 189 * both try to reset the same state field but to different values. 190 */ 191 ARMCPRegInfo *ri = value; 192 ARMCPU *cpu = opaque; 193 uint64_t oldvalue, newvalue; 194 195 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 196 return; 197 } 198 199 oldvalue = read_raw_cp_reg(&cpu->env, ri); 200 cp_reg_reset(key, value, opaque); 201 newvalue = read_raw_cp_reg(&cpu->env, ri); 202 assert(oldvalue == newvalue); 203 } 204 205 static void arm_cpu_reset(DeviceState *dev) 206 { 207 CPUState *s = CPU(dev); 208 ARMCPU *cpu = ARM_CPU(s); 209 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 210 CPUARMState *env = &cpu->env; 211 212 acc->parent_reset(dev); 213 214 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 215 216 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 217 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 218 219 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 220 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 221 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 222 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 223 224 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; 225 226 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 227 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 228 } 229 230 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 231 /* 64 bit CPUs always start in 64 bit mode */ 232 env->aarch64 = true; 233 #if defined(CONFIG_USER_ONLY) 234 env->pstate = PSTATE_MODE_EL0t; 235 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 236 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 237 /* Enable all PAC keys. */ 238 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 239 SCTLR_EnDA | SCTLR_EnDB); 240 /* Trap on btype=3 for PACIxSP. */ 241 env->cp15.sctlr_el[1] |= SCTLR_BT0; 242 /* and to the FP/Neon instructions */ 243 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 244 CPACR_EL1, FPEN, 3); 245 /* and to the SVE instructions, with default vector length */ 246 if (cpu_isar_feature(aa64_sve, cpu)) { 247 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 248 CPACR_EL1, ZEN, 3); 249 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; 250 } 251 /* and for SME instructions, with default vector length, and TPIDR2 */ 252 if (cpu_isar_feature(aa64_sme, cpu)) { 253 env->cp15.sctlr_el[1] |= SCTLR_EnTP2; 254 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 255 CPACR_EL1, SMEN, 3); 256 env->vfp.smcr_el[1] = cpu->sme_default_vq - 1; 257 if (cpu_isar_feature(aa64_sme_fa64, cpu)) { 258 env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1], 259 SMCR, FA64, 1); 260 } 261 } 262 /* 263 * Enable 48-bit address space (TODO: take reserved_va into account). 264 * Enable TBI0 but not TBI1. 265 * Note that this must match useronly_clean_ptr. 266 */ 267 env->cp15.tcr_el[1] = 5 | (1ULL << 37); 268 269 /* Enable MTE */ 270 if (cpu_isar_feature(aa64_mte, cpu)) { 271 /* Enable tag access, but leave TCF0 as No Effect (0). */ 272 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 273 /* 274 * Exclude all tags, so that tag 0 is always used. 275 * This corresponds to Linux current->thread.gcr_incl = 0. 276 * 277 * Set RRND, so that helper_irg() will generate a seed later. 278 * Here in cpu_reset(), the crypto subsystem has not yet been 279 * initialized. 280 */ 281 env->cp15.gcr_el1 = 0x1ffff; 282 } 283 /* 284 * Disable access to SCXTNUM_EL0 from CSV2_1p2. 285 * This is not yet exposed from the Linux kernel in any way. 286 */ 287 env->cp15.sctlr_el[1] |= SCTLR_TSCXT; 288 #else 289 /* Reset into the highest available EL */ 290 if (arm_feature(env, ARM_FEATURE_EL3)) { 291 env->pstate = PSTATE_MODE_EL3h; 292 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 293 env->pstate = PSTATE_MODE_EL2h; 294 } else { 295 env->pstate = PSTATE_MODE_EL1h; 296 } 297 298 /* Sample rvbar at reset. */ 299 env->cp15.rvbar = cpu->rvbar_prop; 300 env->pc = env->cp15.rvbar; 301 #endif 302 } else { 303 #if defined(CONFIG_USER_ONLY) 304 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 305 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 306 CPACR, CP10, 3); 307 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 308 CPACR, CP11, 3); 309 #endif 310 } 311 312 #if defined(CONFIG_USER_ONLY) 313 env->uncached_cpsr = ARM_CPU_MODE_USR; 314 /* For user mode we must enable access to coprocessors */ 315 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 316 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 317 env->cp15.c15_cpar = 3; 318 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 319 env->cp15.c15_cpar = 1; 320 } 321 #else 322 323 /* 324 * If the highest available EL is EL2, AArch32 will start in Hyp 325 * mode; otherwise it starts in SVC. Note that if we start in 326 * AArch64 then these values in the uncached_cpsr will be ignored. 327 */ 328 if (arm_feature(env, ARM_FEATURE_EL2) && 329 !arm_feature(env, ARM_FEATURE_EL3)) { 330 env->uncached_cpsr = ARM_CPU_MODE_HYP; 331 } else { 332 env->uncached_cpsr = ARM_CPU_MODE_SVC; 333 } 334 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 335 336 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 337 * executing as AArch32 then check if highvecs are enabled and 338 * adjust the PC accordingly. 339 */ 340 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 341 env->regs[15] = 0xFFFF0000; 342 } 343 344 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 345 #endif 346 347 if (arm_feature(env, ARM_FEATURE_M)) { 348 #ifndef CONFIG_USER_ONLY 349 uint32_t initial_msp; /* Loaded from 0x0 */ 350 uint32_t initial_pc; /* Loaded from 0x4 */ 351 uint8_t *rom; 352 uint32_t vecbase; 353 #endif 354 355 if (cpu_isar_feature(aa32_lob, cpu)) { 356 /* 357 * LTPSIZE is constant 4 if MVE not implemented, and resets 358 * to an UNKNOWN value if MVE is implemented. We choose to 359 * always reset to 4. 360 */ 361 env->v7m.ltpsize = 4; 362 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 363 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 364 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 365 } 366 367 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 368 env->v7m.secure = true; 369 } else { 370 /* This bit resets to 0 if security is supported, but 1 if 371 * it is not. The bit is not present in v7M, but we set it 372 * here so we can avoid having to make checks on it conditional 373 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 374 */ 375 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 376 /* 377 * Set NSACR to indicate "NS access permitted to everything"; 378 * this avoids having to have all the tests of it being 379 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 380 * v8.1M the guest-visible value of NSACR in a CPU without the 381 * Security Extension is 0xcff. 382 */ 383 env->v7m.nsacr = 0xcff; 384 } 385 386 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 387 * that it resets to 1, so QEMU always does that rather than making 388 * it dependent on CPU model. In v8M it is RES1. 389 */ 390 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 391 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 392 if (arm_feature(env, ARM_FEATURE_V8)) { 393 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 394 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 395 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 396 } 397 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 398 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 399 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 400 } 401 402 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 403 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 404 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 405 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 406 } 407 408 #ifndef CONFIG_USER_ONLY 409 /* Unlike A/R profile, M profile defines the reset LR value */ 410 env->regs[14] = 0xffffffff; 411 412 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 413 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 414 415 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 416 vecbase = env->v7m.vecbase[env->v7m.secure]; 417 rom = rom_ptr_for_as(s->as, vecbase, 8); 418 if (rom) { 419 /* Address zero is covered by ROM which hasn't yet been 420 * copied into physical memory. 421 */ 422 initial_msp = ldl_p(rom); 423 initial_pc = ldl_p(rom + 4); 424 } else { 425 /* Address zero not covered by a ROM blob, or the ROM blob 426 * is in non-modifiable memory and this is a second reset after 427 * it got copied into memory. In the latter case, rom_ptr 428 * will return a NULL pointer and we should use ldl_phys instead. 429 */ 430 initial_msp = ldl_phys(s->as, vecbase); 431 initial_pc = ldl_phys(s->as, vecbase + 4); 432 } 433 434 qemu_log_mask(CPU_LOG_INT, 435 "Loaded reset SP 0x%x PC 0x%x from vector table\n", 436 initial_msp, initial_pc); 437 438 env->regs[13] = initial_msp & 0xFFFFFFFC; 439 env->regs[15] = initial_pc & ~1; 440 env->thumb = initial_pc & 1; 441 #else 442 /* 443 * For user mode we run non-secure and with access to the FPU. 444 * The FPU context is active (ie does not need further setup) 445 * and is owned by non-secure. 446 */ 447 env->v7m.secure = false; 448 env->v7m.nsacr = 0xcff; 449 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 450 env->v7m.fpccr[M_REG_S] &= 451 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 452 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 453 #endif 454 } 455 456 /* M profile requires that reset clears the exclusive monitor; 457 * A profile does not, but clearing it makes more sense than having it 458 * set with an exclusive access on address zero. 459 */ 460 arm_clear_exclusive(env); 461 462 if (arm_feature(env, ARM_FEATURE_PMSA)) { 463 if (cpu->pmsav7_dregion > 0) { 464 if (arm_feature(env, ARM_FEATURE_V8)) { 465 memset(env->pmsav8.rbar[M_REG_NS], 0, 466 sizeof(*env->pmsav8.rbar[M_REG_NS]) 467 * cpu->pmsav7_dregion); 468 memset(env->pmsav8.rlar[M_REG_NS], 0, 469 sizeof(*env->pmsav8.rlar[M_REG_NS]) 470 * cpu->pmsav7_dregion); 471 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 472 memset(env->pmsav8.rbar[M_REG_S], 0, 473 sizeof(*env->pmsav8.rbar[M_REG_S]) 474 * cpu->pmsav7_dregion); 475 memset(env->pmsav8.rlar[M_REG_S], 0, 476 sizeof(*env->pmsav8.rlar[M_REG_S]) 477 * cpu->pmsav7_dregion); 478 } 479 } else if (arm_feature(env, ARM_FEATURE_V7)) { 480 memset(env->pmsav7.drbar, 0, 481 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 482 memset(env->pmsav7.drsr, 0, 483 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 484 memset(env->pmsav7.dracr, 0, 485 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 486 } 487 } 488 env->pmsav7.rnr[M_REG_NS] = 0; 489 env->pmsav7.rnr[M_REG_S] = 0; 490 env->pmsav8.mair0[M_REG_NS] = 0; 491 env->pmsav8.mair0[M_REG_S] = 0; 492 env->pmsav8.mair1[M_REG_NS] = 0; 493 env->pmsav8.mair1[M_REG_S] = 0; 494 } 495 496 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 497 if (cpu->sau_sregion > 0) { 498 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 499 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 500 } 501 env->sau.rnr = 0; 502 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 503 * the Cortex-M33 does. 504 */ 505 env->sau.ctrl = 0; 506 } 507 508 set_flush_to_zero(1, &env->vfp.standard_fp_status); 509 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 510 set_default_nan_mode(1, &env->vfp.standard_fp_status); 511 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); 512 set_float_detect_tininess(float_tininess_before_rounding, 513 &env->vfp.fp_status); 514 set_float_detect_tininess(float_tininess_before_rounding, 515 &env->vfp.standard_fp_status); 516 set_float_detect_tininess(float_tininess_before_rounding, 517 &env->vfp.fp_status_f16); 518 set_float_detect_tininess(float_tininess_before_rounding, 519 &env->vfp.standard_fp_status_f16); 520 #ifndef CONFIG_USER_ONLY 521 if (kvm_enabled()) { 522 kvm_arm_reset_vcpu(cpu); 523 } 524 #endif 525 526 hw_breakpoint_update_all(cpu); 527 hw_watchpoint_update_all(cpu); 528 arm_rebuild_hflags(env); 529 } 530 531 #ifndef CONFIG_USER_ONLY 532 533 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 534 unsigned int target_el, 535 unsigned int cur_el, bool secure, 536 uint64_t hcr_el2) 537 { 538 CPUARMState *env = cs->env_ptr; 539 bool pstate_unmasked; 540 bool unmasked = false; 541 542 /* 543 * Don't take exceptions if they target a lower EL. 544 * This check should catch any exceptions that would not be taken 545 * but left pending. 546 */ 547 if (cur_el > target_el) { 548 return false; 549 } 550 551 switch (excp_idx) { 552 case EXCP_FIQ: 553 pstate_unmasked = !(env->daif & PSTATE_F); 554 break; 555 556 case EXCP_IRQ: 557 pstate_unmasked = !(env->daif & PSTATE_I); 558 break; 559 560 case EXCP_VFIQ: 561 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 562 /* VFIQs are only taken when hypervized. */ 563 return false; 564 } 565 return !(env->daif & PSTATE_F); 566 case EXCP_VIRQ: 567 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 568 /* VIRQs are only taken when hypervized. */ 569 return false; 570 } 571 return !(env->daif & PSTATE_I); 572 case EXCP_VSERR: 573 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { 574 /* VIRQs are only taken when hypervized. */ 575 return false; 576 } 577 return !(env->daif & PSTATE_A); 578 default: 579 g_assert_not_reached(); 580 } 581 582 /* 583 * Use the target EL, current execution state and SCR/HCR settings to 584 * determine whether the corresponding CPSR bit is used to mask the 585 * interrupt. 586 */ 587 if ((target_el > cur_el) && (target_el != 1)) { 588 /* Exceptions targeting a higher EL may not be maskable */ 589 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 590 /* 591 * 64-bit masking rules are simple: exceptions to EL3 592 * can't be masked, and exceptions to EL2 can only be 593 * masked from Secure state. The HCR and SCR settings 594 * don't affect the masking logic, only the interrupt routing. 595 */ 596 if (target_el == 3 || !secure || (env->cp15.scr_el3 & SCR_EEL2)) { 597 unmasked = true; 598 } 599 } else { 600 /* 601 * The old 32-bit-only environment has a more complicated 602 * masking setup. HCR and SCR bits not only affect interrupt 603 * routing but also change the behaviour of masking. 604 */ 605 bool hcr, scr; 606 607 switch (excp_idx) { 608 case EXCP_FIQ: 609 /* 610 * If FIQs are routed to EL3 or EL2 then there are cases where 611 * we override the CPSR.F in determining if the exception is 612 * masked or not. If neither of these are set then we fall back 613 * to the CPSR.F setting otherwise we further assess the state 614 * below. 615 */ 616 hcr = hcr_el2 & HCR_FMO; 617 scr = (env->cp15.scr_el3 & SCR_FIQ); 618 619 /* 620 * When EL3 is 32-bit, the SCR.FW bit controls whether the 621 * CPSR.F bit masks FIQ interrupts when taken in non-secure 622 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 623 * when non-secure but only when FIQs are only routed to EL3. 624 */ 625 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 626 break; 627 case EXCP_IRQ: 628 /* 629 * When EL3 execution state is 32-bit, if HCR.IMO is set then 630 * we may override the CPSR.I masking when in non-secure state. 631 * The SCR.IRQ setting has already been taken into consideration 632 * when setting the target EL, so it does not have a further 633 * affect here. 634 */ 635 hcr = hcr_el2 & HCR_IMO; 636 scr = false; 637 break; 638 default: 639 g_assert_not_reached(); 640 } 641 642 if ((scr || hcr) && !secure) { 643 unmasked = true; 644 } 645 } 646 } 647 648 /* 649 * The PSTATE bits only mask the interrupt if we have not overriden the 650 * ability above. 651 */ 652 return unmasked || pstate_unmasked; 653 } 654 655 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 656 { 657 CPUClass *cc = CPU_GET_CLASS(cs); 658 CPUARMState *env = cs->env_ptr; 659 uint32_t cur_el = arm_current_el(env); 660 bool secure = arm_is_secure(env); 661 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 662 uint32_t target_el; 663 uint32_t excp_idx; 664 665 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 666 667 if (interrupt_request & CPU_INTERRUPT_FIQ) { 668 excp_idx = EXCP_FIQ; 669 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 670 if (arm_excp_unmasked(cs, excp_idx, target_el, 671 cur_el, secure, hcr_el2)) { 672 goto found; 673 } 674 } 675 if (interrupt_request & CPU_INTERRUPT_HARD) { 676 excp_idx = EXCP_IRQ; 677 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 678 if (arm_excp_unmasked(cs, excp_idx, target_el, 679 cur_el, secure, hcr_el2)) { 680 goto found; 681 } 682 } 683 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 684 excp_idx = EXCP_VIRQ; 685 target_el = 1; 686 if (arm_excp_unmasked(cs, excp_idx, target_el, 687 cur_el, secure, hcr_el2)) { 688 goto found; 689 } 690 } 691 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 692 excp_idx = EXCP_VFIQ; 693 target_el = 1; 694 if (arm_excp_unmasked(cs, excp_idx, target_el, 695 cur_el, secure, hcr_el2)) { 696 goto found; 697 } 698 } 699 if (interrupt_request & CPU_INTERRUPT_VSERR) { 700 excp_idx = EXCP_VSERR; 701 target_el = 1; 702 if (arm_excp_unmasked(cs, excp_idx, target_el, 703 cur_el, secure, hcr_el2)) { 704 /* Taking a virtual abort clears HCR_EL2.VSE */ 705 env->cp15.hcr_el2 &= ~HCR_VSE; 706 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 707 goto found; 708 } 709 } 710 return false; 711 712 found: 713 cs->exception_index = excp_idx; 714 env->exception.target_el = target_el; 715 cc->tcg_ops->do_interrupt(cs); 716 return true; 717 } 718 #endif /* !CONFIG_USER_ONLY */ 719 720 void arm_cpu_update_virq(ARMCPU *cpu) 721 { 722 /* 723 * Update the interrupt level for VIRQ, which is the logical OR of 724 * the HCR_EL2.VI bit and the input line level from the GIC. 725 */ 726 CPUARMState *env = &cpu->env; 727 CPUState *cs = CPU(cpu); 728 729 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 730 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 731 732 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 733 if (new_state) { 734 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 735 } else { 736 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 737 } 738 } 739 } 740 741 void arm_cpu_update_vfiq(ARMCPU *cpu) 742 { 743 /* 744 * Update the interrupt level for VFIQ, which is the logical OR of 745 * the HCR_EL2.VF bit and the input line level from the GIC. 746 */ 747 CPUARMState *env = &cpu->env; 748 CPUState *cs = CPU(cpu); 749 750 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 751 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 752 753 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 754 if (new_state) { 755 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 756 } else { 757 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 758 } 759 } 760 } 761 762 void arm_cpu_update_vserr(ARMCPU *cpu) 763 { 764 /* 765 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. 766 */ 767 CPUARMState *env = &cpu->env; 768 CPUState *cs = CPU(cpu); 769 770 bool new_state = env->cp15.hcr_el2 & HCR_VSE; 771 772 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { 773 if (new_state) { 774 cpu_interrupt(cs, CPU_INTERRUPT_VSERR); 775 } else { 776 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 777 } 778 } 779 } 780 781 #ifndef CONFIG_USER_ONLY 782 static void arm_cpu_set_irq(void *opaque, int irq, int level) 783 { 784 ARMCPU *cpu = opaque; 785 CPUARMState *env = &cpu->env; 786 CPUState *cs = CPU(cpu); 787 static const int mask[] = { 788 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 789 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 790 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 791 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 792 }; 793 794 if (!arm_feature(env, ARM_FEATURE_EL2) && 795 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { 796 /* 797 * The GIC might tell us about VIRQ and VFIQ state, but if we don't 798 * have EL2 support we don't care. (Unless the guest is doing something 799 * silly this will only be calls saying "level is still 0".) 800 */ 801 return; 802 } 803 804 if (level) { 805 env->irq_line_state |= mask[irq]; 806 } else { 807 env->irq_line_state &= ~mask[irq]; 808 } 809 810 switch (irq) { 811 case ARM_CPU_VIRQ: 812 arm_cpu_update_virq(cpu); 813 break; 814 case ARM_CPU_VFIQ: 815 arm_cpu_update_vfiq(cpu); 816 break; 817 case ARM_CPU_IRQ: 818 case ARM_CPU_FIQ: 819 if (level) { 820 cpu_interrupt(cs, mask[irq]); 821 } else { 822 cpu_reset_interrupt(cs, mask[irq]); 823 } 824 break; 825 default: 826 g_assert_not_reached(); 827 } 828 } 829 830 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 831 { 832 #ifdef CONFIG_KVM 833 ARMCPU *cpu = opaque; 834 CPUARMState *env = &cpu->env; 835 CPUState *cs = CPU(cpu); 836 uint32_t linestate_bit; 837 int irq_id; 838 839 switch (irq) { 840 case ARM_CPU_IRQ: 841 irq_id = KVM_ARM_IRQ_CPU_IRQ; 842 linestate_bit = CPU_INTERRUPT_HARD; 843 break; 844 case ARM_CPU_FIQ: 845 irq_id = KVM_ARM_IRQ_CPU_FIQ; 846 linestate_bit = CPU_INTERRUPT_FIQ; 847 break; 848 default: 849 g_assert_not_reached(); 850 } 851 852 if (level) { 853 env->irq_line_state |= linestate_bit; 854 } else { 855 env->irq_line_state &= ~linestate_bit; 856 } 857 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 858 #endif 859 } 860 861 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 862 { 863 ARMCPU *cpu = ARM_CPU(cs); 864 CPUARMState *env = &cpu->env; 865 866 cpu_synchronize_state(cs); 867 return arm_cpu_data_is_big_endian(env); 868 } 869 870 #endif 871 872 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 873 { 874 ARMCPU *ac = ARM_CPU(cpu); 875 CPUARMState *env = &ac->env; 876 bool sctlr_b; 877 878 if (is_a64(env)) { 879 info->cap_arch = CS_ARCH_ARM64; 880 info->cap_insn_unit = 4; 881 info->cap_insn_split = 4; 882 } else { 883 int cap_mode; 884 if (env->thumb) { 885 info->cap_insn_unit = 2; 886 info->cap_insn_split = 4; 887 cap_mode = CS_MODE_THUMB; 888 } else { 889 info->cap_insn_unit = 4; 890 info->cap_insn_split = 4; 891 cap_mode = CS_MODE_ARM; 892 } 893 if (arm_feature(env, ARM_FEATURE_V8)) { 894 cap_mode |= CS_MODE_V8; 895 } 896 if (arm_feature(env, ARM_FEATURE_M)) { 897 cap_mode |= CS_MODE_MCLASS; 898 } 899 info->cap_arch = CS_ARCH_ARM; 900 info->cap_mode = cap_mode; 901 } 902 903 sctlr_b = arm_sctlr_b(env); 904 if (bswap_code(sctlr_b)) { 905 #if TARGET_BIG_ENDIAN 906 info->endian = BFD_ENDIAN_LITTLE; 907 #else 908 info->endian = BFD_ENDIAN_BIG; 909 #endif 910 } 911 info->flags &= ~INSN_ARM_BE32; 912 #ifndef CONFIG_USER_ONLY 913 if (sctlr_b) { 914 info->flags |= INSN_ARM_BE32; 915 } 916 #endif 917 } 918 919 #ifdef TARGET_AARCH64 920 921 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 922 { 923 ARMCPU *cpu = ARM_CPU(cs); 924 CPUARMState *env = &cpu->env; 925 uint32_t psr = pstate_read(env); 926 int i; 927 int el = arm_current_el(env); 928 const char *ns_status; 929 bool sve; 930 931 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 932 for (i = 0; i < 32; i++) { 933 if (i == 31) { 934 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 935 } else { 936 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 937 (i + 2) % 3 ? " " : "\n"); 938 } 939 } 940 941 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 942 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 943 } else { 944 ns_status = ""; 945 } 946 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 947 psr, 948 psr & PSTATE_N ? 'N' : '-', 949 psr & PSTATE_Z ? 'Z' : '-', 950 psr & PSTATE_C ? 'C' : '-', 951 psr & PSTATE_V ? 'V' : '-', 952 ns_status, 953 el, 954 psr & PSTATE_SP ? 'h' : 't'); 955 956 if (cpu_isar_feature(aa64_sme, cpu)) { 957 qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c", 958 env->svcr, 959 (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), 960 (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); 961 } 962 if (cpu_isar_feature(aa64_bti, cpu)) { 963 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 964 } 965 if (!(flags & CPU_DUMP_FPU)) { 966 qemu_fprintf(f, "\n"); 967 return; 968 } 969 if (fp_exception_el(env, el) != 0) { 970 qemu_fprintf(f, " FPU disabled\n"); 971 return; 972 } 973 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 974 vfp_get_fpcr(env), vfp_get_fpsr(env)); 975 976 if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) { 977 sve = sme_exception_el(env, el) == 0; 978 } else if (cpu_isar_feature(aa64_sve, cpu)) { 979 sve = sve_exception_el(env, el) == 0; 980 } else { 981 sve = false; 982 } 983 984 if (sve) { 985 int j, zcr_len = sve_vqm1_for_el(env, el); 986 987 for (i = 0; i <= FFR_PRED_NUM; i++) { 988 bool eol; 989 if (i == FFR_PRED_NUM) { 990 qemu_fprintf(f, "FFR="); 991 /* It's last, so end the line. */ 992 eol = true; 993 } else { 994 qemu_fprintf(f, "P%02d=", i); 995 switch (zcr_len) { 996 case 0: 997 eol = i % 8 == 7; 998 break; 999 case 1: 1000 eol = i % 6 == 5; 1001 break; 1002 case 2: 1003 case 3: 1004 eol = i % 3 == 2; 1005 break; 1006 default: 1007 /* More than one quadword per predicate. */ 1008 eol = true; 1009 break; 1010 } 1011 } 1012 for (j = zcr_len / 4; j >= 0; j--) { 1013 int digits; 1014 if (j * 4 + 4 <= zcr_len + 1) { 1015 digits = 16; 1016 } else { 1017 digits = (zcr_len % 4 + 1) * 4; 1018 } 1019 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 1020 env->vfp.pregs[i].p[j], 1021 j ? ":" : eol ? "\n" : " "); 1022 } 1023 } 1024 1025 for (i = 0; i < 32; i++) { 1026 if (zcr_len == 0) { 1027 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1028 i, env->vfp.zregs[i].d[1], 1029 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 1030 } else if (zcr_len == 1) { 1031 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 1032 ":%016" PRIx64 ":%016" PRIx64 "\n", 1033 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 1034 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 1035 } else { 1036 for (j = zcr_len; j >= 0; j--) { 1037 bool odd = (zcr_len - j) % 2 != 0; 1038 if (j == zcr_len) { 1039 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 1040 } else if (!odd) { 1041 if (j > 0) { 1042 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 1043 } else { 1044 qemu_fprintf(f, " [%x]=", j); 1045 } 1046 } 1047 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 1048 env->vfp.zregs[i].d[j * 2 + 1], 1049 env->vfp.zregs[i].d[j * 2], 1050 odd || j == 0 ? "\n" : ":"); 1051 } 1052 } 1053 } 1054 } else { 1055 for (i = 0; i < 32; i++) { 1056 uint64_t *q = aa64_vfp_qreg(env, i); 1057 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1058 i, q[1], q[0], (i & 1 ? "\n" : " ")); 1059 } 1060 } 1061 } 1062 1063 #else 1064 1065 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1066 { 1067 g_assert_not_reached(); 1068 } 1069 1070 #endif 1071 1072 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1073 { 1074 ARMCPU *cpu = ARM_CPU(cs); 1075 CPUARMState *env = &cpu->env; 1076 int i; 1077 1078 if (is_a64(env)) { 1079 aarch64_cpu_dump_state(cs, f, flags); 1080 return; 1081 } 1082 1083 for (i = 0; i < 16; i++) { 1084 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 1085 if ((i % 4) == 3) { 1086 qemu_fprintf(f, "\n"); 1087 } else { 1088 qemu_fprintf(f, " "); 1089 } 1090 } 1091 1092 if (arm_feature(env, ARM_FEATURE_M)) { 1093 uint32_t xpsr = xpsr_read(env); 1094 const char *mode; 1095 const char *ns_status = ""; 1096 1097 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1098 ns_status = env->v7m.secure ? "S " : "NS "; 1099 } 1100 1101 if (xpsr & XPSR_EXCP) { 1102 mode = "handler"; 1103 } else { 1104 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 1105 mode = "unpriv-thread"; 1106 } else { 1107 mode = "priv-thread"; 1108 } 1109 } 1110 1111 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 1112 xpsr, 1113 xpsr & XPSR_N ? 'N' : '-', 1114 xpsr & XPSR_Z ? 'Z' : '-', 1115 xpsr & XPSR_C ? 'C' : '-', 1116 xpsr & XPSR_V ? 'V' : '-', 1117 xpsr & XPSR_T ? 'T' : 'A', 1118 ns_status, 1119 mode); 1120 } else { 1121 uint32_t psr = cpsr_read(env); 1122 const char *ns_status = ""; 1123 1124 if (arm_feature(env, ARM_FEATURE_EL3) && 1125 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1126 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1127 } 1128 1129 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1130 psr, 1131 psr & CPSR_N ? 'N' : '-', 1132 psr & CPSR_Z ? 'Z' : '-', 1133 psr & CPSR_C ? 'C' : '-', 1134 psr & CPSR_V ? 'V' : '-', 1135 psr & CPSR_T ? 'T' : 'A', 1136 ns_status, 1137 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1138 } 1139 1140 if (flags & CPU_DUMP_FPU) { 1141 int numvfpregs = 0; 1142 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1143 numvfpregs = 32; 1144 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1145 numvfpregs = 16; 1146 } 1147 for (i = 0; i < numvfpregs; i++) { 1148 uint64_t v = *aa32_vfp_dreg(env, i); 1149 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1150 i * 2, (uint32_t)v, 1151 i * 2 + 1, (uint32_t)(v >> 32), 1152 i, v); 1153 } 1154 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1155 if (cpu_isar_feature(aa32_mve, cpu)) { 1156 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1157 } 1158 } 1159 } 1160 1161 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 1162 { 1163 uint32_t Aff1 = idx / clustersz; 1164 uint32_t Aff0 = idx % clustersz; 1165 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1166 } 1167 1168 static void arm_cpu_initfn(Object *obj) 1169 { 1170 ARMCPU *cpu = ARM_CPU(obj); 1171 1172 cpu_set_cpustate_pointers(cpu); 1173 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, 1174 NULL, g_free); 1175 1176 QLIST_INIT(&cpu->pre_el_change_hooks); 1177 QLIST_INIT(&cpu->el_change_hooks); 1178 1179 #ifdef CONFIG_USER_ONLY 1180 # ifdef TARGET_AARCH64 1181 /* 1182 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME. 1183 * These values were chosen to fit within the default signal frame. 1184 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length, 1185 * and our corresponding cpu property. 1186 */ 1187 cpu->sve_default_vq = 4; 1188 cpu->sme_default_vq = 2; 1189 # endif 1190 #else 1191 /* Our inbound IRQ and FIQ lines */ 1192 if (kvm_enabled()) { 1193 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1194 * the same interface as non-KVM CPUs. 1195 */ 1196 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1197 } else { 1198 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1199 } 1200 1201 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1202 ARRAY_SIZE(cpu->gt_timer_outputs)); 1203 1204 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1205 "gicv3-maintenance-interrupt", 1); 1206 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1207 "pmu-interrupt", 1); 1208 #endif 1209 1210 /* DTB consumers generally don't in fact care what the 'compatible' 1211 * string is, so always provide some string and trust that a hypothetical 1212 * picky DTB consumer will also provide a helpful error message. 1213 */ 1214 cpu->dtb_compatible = "qemu,unknown"; 1215 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ 1216 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1217 1218 if (tcg_enabled() || hvf_enabled()) { 1219 /* TCG and HVF implement PSCI 1.1 */ 1220 cpu->psci_version = QEMU_PSCI_VERSION_1_1; 1221 } 1222 } 1223 1224 static Property arm_cpu_gt_cntfrq_property = 1225 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1226 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1227 1228 static Property arm_cpu_reset_cbar_property = 1229 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1230 1231 static Property arm_cpu_reset_hivecs_property = 1232 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1233 1234 #ifndef CONFIG_USER_ONLY 1235 static Property arm_cpu_has_el2_property = 1236 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1237 1238 static Property arm_cpu_has_el3_property = 1239 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1240 #endif 1241 1242 static Property arm_cpu_cfgend_property = 1243 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1244 1245 static Property arm_cpu_has_vfp_property = 1246 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1247 1248 static Property arm_cpu_has_neon_property = 1249 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1250 1251 static Property arm_cpu_has_dsp_property = 1252 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1253 1254 static Property arm_cpu_has_mpu_property = 1255 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1256 1257 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1258 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1259 * the right value for that particular CPU type, and we don't want 1260 * to override that with an incorrect constant value. 1261 */ 1262 static Property arm_cpu_pmsav7_dregion_property = 1263 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1264 pmsav7_dregion, 1265 qdev_prop_uint32, uint32_t); 1266 1267 static bool arm_get_pmu(Object *obj, Error **errp) 1268 { 1269 ARMCPU *cpu = ARM_CPU(obj); 1270 1271 return cpu->has_pmu; 1272 } 1273 1274 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1275 { 1276 ARMCPU *cpu = ARM_CPU(obj); 1277 1278 if (value) { 1279 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1280 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1281 return; 1282 } 1283 set_feature(&cpu->env, ARM_FEATURE_PMU); 1284 } else { 1285 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1286 } 1287 cpu->has_pmu = value; 1288 } 1289 1290 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1291 { 1292 /* 1293 * The exact approach to calculating guest ticks is: 1294 * 1295 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1296 * NANOSECONDS_PER_SECOND); 1297 * 1298 * We don't do that. Rather we intentionally use integer division 1299 * truncation below and in the caller for the conversion of host monotonic 1300 * time to guest ticks to provide the exact inverse for the semantics of 1301 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1302 * it loses precision when representing frequencies where 1303 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1304 * provide an exact inverse leads to scheduling timers with negative 1305 * periods, which in turn leads to sticky behaviour in the guest. 1306 * 1307 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1308 * cannot become zero. 1309 */ 1310 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1311 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1312 } 1313 1314 void arm_cpu_post_init(Object *obj) 1315 { 1316 ARMCPU *cpu = ARM_CPU(obj); 1317 1318 /* M profile implies PMSA. We have to do this here rather than 1319 * in realize with the other feature-implication checks because 1320 * we look at the PMSA bit to see if we should add some properties. 1321 */ 1322 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1323 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1324 } 1325 1326 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1327 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1328 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1329 } 1330 1331 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1332 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1333 } 1334 1335 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1336 object_property_add_uint64_ptr(obj, "rvbar", 1337 &cpu->rvbar_prop, 1338 OBJ_PROP_FLAG_READWRITE); 1339 } 1340 1341 #ifndef CONFIG_USER_ONLY 1342 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1343 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1344 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1345 */ 1346 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1347 1348 object_property_add_link(obj, "secure-memory", 1349 TYPE_MEMORY_REGION, 1350 (Object **)&cpu->secure_memory, 1351 qdev_prop_allow_set_link_before_realize, 1352 OBJ_PROP_LINK_STRONG); 1353 } 1354 1355 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1356 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1357 } 1358 #endif 1359 1360 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1361 cpu->has_pmu = true; 1362 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1363 } 1364 1365 /* 1366 * Allow user to turn off VFP and Neon support, but only for TCG -- 1367 * KVM does not currently allow us to lie to the guest about its 1368 * ID/feature registers, so the guest always sees what the host has. 1369 */ 1370 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 1371 ? cpu_isar_feature(aa64_fp_simd, cpu) 1372 : cpu_isar_feature(aa32_vfp, cpu)) { 1373 cpu->has_vfp = true; 1374 if (!kvm_enabled()) { 1375 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1376 } 1377 } 1378 1379 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1380 cpu->has_neon = true; 1381 if (!kvm_enabled()) { 1382 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1383 } 1384 } 1385 1386 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1387 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1388 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1389 } 1390 1391 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1392 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1393 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1394 qdev_property_add_static(DEVICE(obj), 1395 &arm_cpu_pmsav7_dregion_property); 1396 } 1397 } 1398 1399 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1400 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1401 qdev_prop_allow_set_link_before_realize, 1402 OBJ_PROP_LINK_STRONG); 1403 /* 1404 * M profile: initial value of the Secure VTOR. We can't just use 1405 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1406 * the property to be set after realize. 1407 */ 1408 object_property_add_uint32_ptr(obj, "init-svtor", 1409 &cpu->init_svtor, 1410 OBJ_PROP_FLAG_READWRITE); 1411 } 1412 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1413 /* 1414 * Initial value of the NS VTOR (for cores without the Security 1415 * extension, this is the only VTOR) 1416 */ 1417 object_property_add_uint32_ptr(obj, "init-nsvtor", 1418 &cpu->init_nsvtor, 1419 OBJ_PROP_FLAG_READWRITE); 1420 } 1421 1422 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ 1423 object_property_add_uint32_ptr(obj, "psci-conduit", 1424 &cpu->psci_conduit, 1425 OBJ_PROP_FLAG_READWRITE); 1426 1427 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1428 1429 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1430 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1431 } 1432 1433 if (kvm_enabled()) { 1434 kvm_arm_add_vcpu_properties(obj); 1435 } 1436 1437 #ifndef CONFIG_USER_ONLY 1438 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1439 cpu_isar_feature(aa64_mte, cpu)) { 1440 object_property_add_link(obj, "tag-memory", 1441 TYPE_MEMORY_REGION, 1442 (Object **)&cpu->tag_memory, 1443 qdev_prop_allow_set_link_before_realize, 1444 OBJ_PROP_LINK_STRONG); 1445 1446 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1447 object_property_add_link(obj, "secure-tag-memory", 1448 TYPE_MEMORY_REGION, 1449 (Object **)&cpu->secure_tag_memory, 1450 qdev_prop_allow_set_link_before_realize, 1451 OBJ_PROP_LINK_STRONG); 1452 } 1453 } 1454 #endif 1455 } 1456 1457 static void arm_cpu_finalizefn(Object *obj) 1458 { 1459 ARMCPU *cpu = ARM_CPU(obj); 1460 ARMELChangeHook *hook, *next; 1461 1462 g_hash_table_destroy(cpu->cp_regs); 1463 1464 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1465 QLIST_REMOVE(hook, node); 1466 g_free(hook); 1467 } 1468 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1469 QLIST_REMOVE(hook, node); 1470 g_free(hook); 1471 } 1472 #ifndef CONFIG_USER_ONLY 1473 if (cpu->pmu_timer) { 1474 timer_free(cpu->pmu_timer); 1475 } 1476 #endif 1477 } 1478 1479 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1480 { 1481 Error *local_err = NULL; 1482 1483 #ifdef TARGET_AARCH64 1484 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1485 arm_cpu_sve_finalize(cpu, &local_err); 1486 if (local_err != NULL) { 1487 error_propagate(errp, local_err); 1488 return; 1489 } 1490 1491 arm_cpu_sme_finalize(cpu, &local_err); 1492 if (local_err != NULL) { 1493 error_propagate(errp, local_err); 1494 return; 1495 } 1496 1497 arm_cpu_pauth_finalize(cpu, &local_err); 1498 if (local_err != NULL) { 1499 error_propagate(errp, local_err); 1500 return; 1501 } 1502 1503 arm_cpu_lpa2_finalize(cpu, &local_err); 1504 if (local_err != NULL) { 1505 error_propagate(errp, local_err); 1506 return; 1507 } 1508 } 1509 #endif 1510 1511 if (kvm_enabled()) { 1512 kvm_arm_steal_time_finalize(cpu, &local_err); 1513 if (local_err != NULL) { 1514 error_propagate(errp, local_err); 1515 return; 1516 } 1517 } 1518 } 1519 1520 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1521 { 1522 CPUState *cs = CPU(dev); 1523 ARMCPU *cpu = ARM_CPU(dev); 1524 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1525 CPUARMState *env = &cpu->env; 1526 int pagebits; 1527 Error *local_err = NULL; 1528 bool no_aa32 = false; 1529 1530 /* If we needed to query the host kernel for the CPU features 1531 * then it's possible that might have failed in the initfn, but 1532 * this is the first point where we can report it. 1533 */ 1534 if (cpu->host_cpu_probe_failed) { 1535 if (!kvm_enabled() && !hvf_enabled()) { 1536 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1537 } else { 1538 error_setg(errp, "Failed to retrieve host CPU features"); 1539 } 1540 return; 1541 } 1542 1543 #ifndef CONFIG_USER_ONLY 1544 /* The NVIC and M-profile CPU are two halves of a single piece of 1545 * hardware; trying to use one without the other is a command line 1546 * error and will result in segfaults if not caught here. 1547 */ 1548 if (arm_feature(env, ARM_FEATURE_M)) { 1549 if (!env->nvic) { 1550 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1551 return; 1552 } 1553 } else { 1554 if (env->nvic) { 1555 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1556 return; 1557 } 1558 } 1559 1560 if (!tcg_enabled() && !qtest_enabled()) { 1561 /* 1562 * We assume that no accelerator except TCG (and the "not really an 1563 * accelerator" qtest) can handle these features, because Arm hardware 1564 * virtualization can't virtualize them. 1565 * 1566 * Catch all the cases which might cause us to create more than one 1567 * address space for the CPU (otherwise we will assert() later in 1568 * cpu_address_space_init()). 1569 */ 1570 if (arm_feature(env, ARM_FEATURE_M)) { 1571 error_setg(errp, 1572 "Cannot enable %s when using an M-profile guest CPU", 1573 current_accel_name()); 1574 return; 1575 } 1576 if (cpu->has_el3) { 1577 error_setg(errp, 1578 "Cannot enable %s when guest CPU has EL3 enabled", 1579 current_accel_name()); 1580 return; 1581 } 1582 if (cpu->tag_memory) { 1583 error_setg(errp, 1584 "Cannot enable %s when guest CPUs has MTE enabled", 1585 current_accel_name()); 1586 return; 1587 } 1588 } 1589 1590 { 1591 uint64_t scale; 1592 1593 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1594 if (!cpu->gt_cntfrq_hz) { 1595 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1596 cpu->gt_cntfrq_hz); 1597 return; 1598 } 1599 scale = gt_cntfrq_period_ns(cpu); 1600 } else { 1601 scale = GTIMER_SCALE; 1602 } 1603 1604 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1605 arm_gt_ptimer_cb, cpu); 1606 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1607 arm_gt_vtimer_cb, cpu); 1608 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1609 arm_gt_htimer_cb, cpu); 1610 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1611 arm_gt_stimer_cb, cpu); 1612 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1613 arm_gt_hvtimer_cb, cpu); 1614 } 1615 #endif 1616 1617 cpu_exec_realizefn(cs, &local_err); 1618 if (local_err != NULL) { 1619 error_propagate(errp, local_err); 1620 return; 1621 } 1622 1623 arm_cpu_finalize_features(cpu, &local_err); 1624 if (local_err != NULL) { 1625 error_propagate(errp, local_err); 1626 return; 1627 } 1628 1629 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1630 cpu->has_vfp != cpu->has_neon) { 1631 /* 1632 * This is an architectural requirement for AArch64; AArch32 is 1633 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1634 */ 1635 error_setg(errp, 1636 "AArch64 CPUs must have both VFP and Neon or neither"); 1637 return; 1638 } 1639 1640 if (!cpu->has_vfp) { 1641 uint64_t t; 1642 uint32_t u; 1643 1644 t = cpu->isar.id_aa64isar1; 1645 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1646 cpu->isar.id_aa64isar1 = t; 1647 1648 t = cpu->isar.id_aa64pfr0; 1649 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1650 cpu->isar.id_aa64pfr0 = t; 1651 1652 u = cpu->isar.id_isar6; 1653 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1654 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1655 cpu->isar.id_isar6 = u; 1656 1657 u = cpu->isar.mvfr0; 1658 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1659 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1660 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1661 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1662 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1663 if (!arm_feature(env, ARM_FEATURE_M)) { 1664 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1665 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1666 } 1667 cpu->isar.mvfr0 = u; 1668 1669 u = cpu->isar.mvfr1; 1670 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1671 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1672 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1673 if (arm_feature(env, ARM_FEATURE_M)) { 1674 u = FIELD_DP32(u, MVFR1, FP16, 0); 1675 } 1676 cpu->isar.mvfr1 = u; 1677 1678 u = cpu->isar.mvfr2; 1679 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1680 cpu->isar.mvfr2 = u; 1681 } 1682 1683 if (!cpu->has_neon) { 1684 uint64_t t; 1685 uint32_t u; 1686 1687 unset_feature(env, ARM_FEATURE_NEON); 1688 1689 t = cpu->isar.id_aa64isar0; 1690 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); 1691 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); 1692 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); 1693 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); 1694 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); 1695 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); 1696 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1697 cpu->isar.id_aa64isar0 = t; 1698 1699 t = cpu->isar.id_aa64isar1; 1700 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1701 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 1702 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 1703 cpu->isar.id_aa64isar1 = t; 1704 1705 t = cpu->isar.id_aa64pfr0; 1706 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1707 cpu->isar.id_aa64pfr0 = t; 1708 1709 u = cpu->isar.id_isar5; 1710 u = FIELD_DP32(u, ID_ISAR5, AES, 0); 1711 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); 1712 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); 1713 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1714 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1715 cpu->isar.id_isar5 = u; 1716 1717 u = cpu->isar.id_isar6; 1718 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1719 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1720 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1721 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 1722 cpu->isar.id_isar6 = u; 1723 1724 if (!arm_feature(env, ARM_FEATURE_M)) { 1725 u = cpu->isar.mvfr1; 1726 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1727 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1728 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1729 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1730 cpu->isar.mvfr1 = u; 1731 1732 u = cpu->isar.mvfr2; 1733 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1734 cpu->isar.mvfr2 = u; 1735 } 1736 } 1737 1738 if (!cpu->has_neon && !cpu->has_vfp) { 1739 uint64_t t; 1740 uint32_t u; 1741 1742 t = cpu->isar.id_aa64isar0; 1743 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1744 cpu->isar.id_aa64isar0 = t; 1745 1746 t = cpu->isar.id_aa64isar1; 1747 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1748 cpu->isar.id_aa64isar1 = t; 1749 1750 u = cpu->isar.mvfr0; 1751 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1752 cpu->isar.mvfr0 = u; 1753 1754 /* Despite the name, this field covers both VFP and Neon */ 1755 u = cpu->isar.mvfr1; 1756 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1757 cpu->isar.mvfr1 = u; 1758 } 1759 1760 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1761 uint32_t u; 1762 1763 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1764 1765 u = cpu->isar.id_isar1; 1766 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1767 cpu->isar.id_isar1 = u; 1768 1769 u = cpu->isar.id_isar2; 1770 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1771 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1772 cpu->isar.id_isar2 = u; 1773 1774 u = cpu->isar.id_isar3; 1775 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1776 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1777 cpu->isar.id_isar3 = u; 1778 } 1779 1780 /* Some features automatically imply others: */ 1781 if (arm_feature(env, ARM_FEATURE_V8)) { 1782 if (arm_feature(env, ARM_FEATURE_M)) { 1783 set_feature(env, ARM_FEATURE_V7); 1784 } else { 1785 set_feature(env, ARM_FEATURE_V7VE); 1786 } 1787 } 1788 1789 /* 1790 * There exist AArch64 cpus without AArch32 support. When KVM 1791 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1792 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1793 * As a general principle, we also do not make ID register 1794 * consistency checks anywhere unless using TCG, because only 1795 * for TCG would a consistency-check failure be a QEMU bug. 1796 */ 1797 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1798 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1799 } 1800 1801 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1802 /* v7 Virtualization Extensions. In real hardware this implies 1803 * EL2 and also the presence of the Security Extensions. 1804 * For QEMU, for backwards-compatibility we implement some 1805 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1806 * include the various other features that V7VE implies. 1807 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1808 * Security Extensions is ARM_FEATURE_EL3. 1809 */ 1810 assert(!tcg_enabled() || no_aa32 || 1811 cpu_isar_feature(aa32_arm_div, cpu)); 1812 set_feature(env, ARM_FEATURE_LPAE); 1813 set_feature(env, ARM_FEATURE_V7); 1814 } 1815 if (arm_feature(env, ARM_FEATURE_V7)) { 1816 set_feature(env, ARM_FEATURE_VAPA); 1817 set_feature(env, ARM_FEATURE_THUMB2); 1818 set_feature(env, ARM_FEATURE_MPIDR); 1819 if (!arm_feature(env, ARM_FEATURE_M)) { 1820 set_feature(env, ARM_FEATURE_V6K); 1821 } else { 1822 set_feature(env, ARM_FEATURE_V6); 1823 } 1824 1825 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1826 * non-EL3 configs. This is needed by some legacy boards. 1827 */ 1828 set_feature(env, ARM_FEATURE_VBAR); 1829 } 1830 if (arm_feature(env, ARM_FEATURE_V6K)) { 1831 set_feature(env, ARM_FEATURE_V6); 1832 set_feature(env, ARM_FEATURE_MVFR); 1833 } 1834 if (arm_feature(env, ARM_FEATURE_V6)) { 1835 set_feature(env, ARM_FEATURE_V5); 1836 if (!arm_feature(env, ARM_FEATURE_M)) { 1837 assert(!tcg_enabled() || no_aa32 || 1838 cpu_isar_feature(aa32_jazelle, cpu)); 1839 set_feature(env, ARM_FEATURE_AUXCR); 1840 } 1841 } 1842 if (arm_feature(env, ARM_FEATURE_V5)) { 1843 set_feature(env, ARM_FEATURE_V4T); 1844 } 1845 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1846 set_feature(env, ARM_FEATURE_V7MP); 1847 } 1848 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1849 set_feature(env, ARM_FEATURE_CBAR); 1850 } 1851 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1852 !arm_feature(env, ARM_FEATURE_M)) { 1853 set_feature(env, ARM_FEATURE_THUMB_DSP); 1854 } 1855 1856 /* 1857 * We rely on no XScale CPU having VFP so we can use the same bits in the 1858 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1859 */ 1860 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1861 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1862 !arm_feature(env, ARM_FEATURE_XSCALE)); 1863 1864 if (arm_feature(env, ARM_FEATURE_V7) && 1865 !arm_feature(env, ARM_FEATURE_M) && 1866 !arm_feature(env, ARM_FEATURE_PMSA)) { 1867 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1868 * can use 4K pages. 1869 */ 1870 pagebits = 12; 1871 } else { 1872 /* For CPUs which might have tiny 1K pages, or which have an 1873 * MPU and might have small region sizes, stick with 1K pages. 1874 */ 1875 pagebits = 10; 1876 } 1877 if (!set_preferred_target_page_bits(pagebits)) { 1878 /* This can only ever happen for hotplugging a CPU, or if 1879 * the board code incorrectly creates a CPU which it has 1880 * promised via minimum_page_size that it will not. 1881 */ 1882 error_setg(errp, "This CPU requires a smaller page size than the " 1883 "system is using"); 1884 return; 1885 } 1886 1887 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1888 * We don't support setting cluster ID ([16..23]) (known as Aff2 1889 * in later ARM ARM versions), or any of the higher affinity level fields, 1890 * so these bits always RAZ. 1891 */ 1892 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1893 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1894 ARM_DEFAULT_CPUS_PER_CLUSTER); 1895 } 1896 1897 if (cpu->reset_hivecs) { 1898 cpu->reset_sctlr |= (1 << 13); 1899 } 1900 1901 if (cpu->cfgend) { 1902 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1903 cpu->reset_sctlr |= SCTLR_EE; 1904 } else { 1905 cpu->reset_sctlr |= SCTLR_B; 1906 } 1907 } 1908 1909 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 1910 /* If the has_el3 CPU property is disabled then we need to disable the 1911 * feature. 1912 */ 1913 unset_feature(env, ARM_FEATURE_EL3); 1914 1915 /* 1916 * Disable the security extension feature bits in the processor 1917 * feature registers as well. 1918 */ 1919 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); 1920 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); 1921 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 1922 ID_AA64PFR0, EL3, 0); 1923 } 1924 1925 if (!cpu->has_el2) { 1926 unset_feature(env, ARM_FEATURE_EL2); 1927 } 1928 1929 if (!cpu->has_pmu) { 1930 unset_feature(env, ARM_FEATURE_PMU); 1931 } 1932 if (arm_feature(env, ARM_FEATURE_PMU)) { 1933 pmu_init(cpu); 1934 1935 if (!kvm_enabled()) { 1936 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1937 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1938 } 1939 1940 #ifndef CONFIG_USER_ONLY 1941 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1942 cpu); 1943 #endif 1944 } else { 1945 cpu->isar.id_aa64dfr0 = 1946 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 1947 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 1948 cpu->pmceid0 = 0; 1949 cpu->pmceid1 = 0; 1950 } 1951 1952 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1953 /* 1954 * Disable the hypervisor feature bits in the processor feature 1955 * registers if we don't have EL2. 1956 */ 1957 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 1958 ID_AA64PFR0, EL2, 0); 1959 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, 1960 ID_PFR1, VIRTUALIZATION, 0); 1961 } 1962 1963 #ifndef CONFIG_USER_ONLY 1964 if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { 1965 /* 1966 * Disable the MTE feature bits if we do not have tag-memory 1967 * provided by the machine. 1968 */ 1969 cpu->isar.id_aa64pfr1 = 1970 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 1971 } 1972 #endif 1973 1974 if (tcg_enabled()) { 1975 /* 1976 * Don't report the Statistical Profiling Extension in the ID 1977 * registers, because TCG doesn't implement it yet (not even a 1978 * minimal stub version) and guests will fall over when they 1979 * try to access the non-existent system registers for it. 1980 */ 1981 cpu->isar.id_aa64dfr0 = 1982 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); 1983 } 1984 1985 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1986 * to false or by setting pmsav7-dregion to 0. 1987 */ 1988 if (!cpu->has_mpu) { 1989 cpu->pmsav7_dregion = 0; 1990 } 1991 if (cpu->pmsav7_dregion == 0) { 1992 cpu->has_mpu = false; 1993 } 1994 1995 if (arm_feature(env, ARM_FEATURE_PMSA) && 1996 arm_feature(env, ARM_FEATURE_V7)) { 1997 uint32_t nr = cpu->pmsav7_dregion; 1998 1999 if (nr > 0xff) { 2000 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 2001 return; 2002 } 2003 2004 if (nr) { 2005 if (arm_feature(env, ARM_FEATURE_V8)) { 2006 /* PMSAv8 */ 2007 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 2008 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 2009 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2010 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 2011 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 2012 } 2013 } else { 2014 env->pmsav7.drbar = g_new0(uint32_t, nr); 2015 env->pmsav7.drsr = g_new0(uint32_t, nr); 2016 env->pmsav7.dracr = g_new0(uint32_t, nr); 2017 } 2018 } 2019 } 2020 2021 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2022 uint32_t nr = cpu->sau_sregion; 2023 2024 if (nr > 0xff) { 2025 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 2026 return; 2027 } 2028 2029 if (nr) { 2030 env->sau.rbar = g_new0(uint32_t, nr); 2031 env->sau.rlar = g_new0(uint32_t, nr); 2032 } 2033 } 2034 2035 if (arm_feature(env, ARM_FEATURE_EL3)) { 2036 set_feature(env, ARM_FEATURE_VBAR); 2037 } 2038 2039 register_cp_regs_for_features(cpu); 2040 arm_cpu_register_gdb_regs_for_features(cpu); 2041 2042 init_cpreg_list(cpu); 2043 2044 #ifndef CONFIG_USER_ONLY 2045 MachineState *ms = MACHINE(qdev_get_machine()); 2046 unsigned int smp_cpus = ms->smp.cpus; 2047 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 2048 2049 /* 2050 * We must set cs->num_ases to the final value before 2051 * the first call to cpu_address_space_init. 2052 */ 2053 if (cpu->tag_memory != NULL) { 2054 cs->num_ases = 3 + has_secure; 2055 } else { 2056 cs->num_ases = 1 + has_secure; 2057 } 2058 2059 if (has_secure) { 2060 if (!cpu->secure_memory) { 2061 cpu->secure_memory = cs->memory; 2062 } 2063 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 2064 cpu->secure_memory); 2065 } 2066 2067 if (cpu->tag_memory != NULL) { 2068 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 2069 cpu->tag_memory); 2070 if (has_secure) { 2071 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 2072 cpu->secure_tag_memory); 2073 } 2074 } 2075 2076 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 2077 2078 /* No core_count specified, default to smp_cpus. */ 2079 if (cpu->core_count == -1) { 2080 cpu->core_count = smp_cpus; 2081 } 2082 #endif 2083 2084 if (tcg_enabled()) { 2085 int dcz_blocklen = 4 << cpu->dcz_blocksize; 2086 2087 /* 2088 * We only support DCZ blocklen that fits on one page. 2089 * 2090 * Architectually this is always true. However TARGET_PAGE_SIZE 2091 * is variable and, for compatibility with -machine virt-2.7, 2092 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 2093 * But even then, while the largest architectural DCZ blocklen 2094 * is 2KiB, no cpu actually uses such a large blocklen. 2095 */ 2096 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 2097 2098 /* 2099 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 2100 * both nibbles of each byte storing tag data may be written at once. 2101 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 2102 */ 2103 if (cpu_isar_feature(aa64_mte, cpu)) { 2104 assert(dcz_blocklen >= 2 * TAG_GRANULE); 2105 } 2106 } 2107 2108 qemu_init_vcpu(cs); 2109 cpu_reset(cs); 2110 2111 acc->parent_realize(dev, errp); 2112 } 2113 2114 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 2115 { 2116 ObjectClass *oc; 2117 char *typename; 2118 char **cpuname; 2119 const char *cpunamestr; 2120 2121 cpuname = g_strsplit(cpu_model, ",", 1); 2122 cpunamestr = cpuname[0]; 2123 #ifdef CONFIG_USER_ONLY 2124 /* For backwards compatibility usermode emulation allows "-cpu any", 2125 * which has the same semantics as "-cpu max". 2126 */ 2127 if (!strcmp(cpunamestr, "any")) { 2128 cpunamestr = "max"; 2129 } 2130 #endif 2131 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 2132 oc = object_class_by_name(typename); 2133 g_strfreev(cpuname); 2134 g_free(typename); 2135 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 2136 object_class_is_abstract(oc)) { 2137 return NULL; 2138 } 2139 return oc; 2140 } 2141 2142 static Property arm_cpu_properties[] = { 2143 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2144 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2145 mp_affinity, ARM64_AFFINITY_INVALID), 2146 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2147 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2148 DEFINE_PROP_END_OF_LIST() 2149 }; 2150 2151 static gchar *arm_gdb_arch_name(CPUState *cs) 2152 { 2153 ARMCPU *cpu = ARM_CPU(cs); 2154 CPUARMState *env = &cpu->env; 2155 2156 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2157 return g_strdup("iwmmxt"); 2158 } 2159 return g_strdup("arm"); 2160 } 2161 2162 #ifndef CONFIG_USER_ONLY 2163 #include "hw/core/sysemu-cpu-ops.h" 2164 2165 static const struct SysemuCPUOps arm_sysemu_ops = { 2166 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2167 .asidx_from_attrs = arm_asidx_from_attrs, 2168 .write_elf32_note = arm_cpu_write_elf32_note, 2169 .write_elf64_note = arm_cpu_write_elf64_note, 2170 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2171 .legacy_vmsd = &vmstate_arm_cpu, 2172 }; 2173 #endif 2174 2175 #ifdef CONFIG_TCG 2176 static const struct TCGCPUOps arm_tcg_ops = { 2177 .initialize = arm_translate_init, 2178 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2179 .debug_excp_handler = arm_debug_excp_handler, 2180 .restore_state_to_opc = arm_restore_state_to_opc, 2181 2182 #ifdef CONFIG_USER_ONLY 2183 .record_sigsegv = arm_cpu_record_sigsegv, 2184 .record_sigbus = arm_cpu_record_sigbus, 2185 #else 2186 .tlb_fill = arm_cpu_tlb_fill, 2187 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2188 .do_interrupt = arm_cpu_do_interrupt, 2189 .do_transaction_failed = arm_cpu_do_transaction_failed, 2190 .do_unaligned_access = arm_cpu_do_unaligned_access, 2191 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2192 .debug_check_watchpoint = arm_debug_check_watchpoint, 2193 .debug_check_breakpoint = arm_debug_check_breakpoint, 2194 #endif /* !CONFIG_USER_ONLY */ 2195 }; 2196 #endif /* CONFIG_TCG */ 2197 2198 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2199 { 2200 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2201 CPUClass *cc = CPU_CLASS(acc); 2202 DeviceClass *dc = DEVICE_CLASS(oc); 2203 2204 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2205 &acc->parent_realize); 2206 2207 device_class_set_props(dc, arm_cpu_properties); 2208 device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); 2209 2210 cc->class_by_name = arm_cpu_class_by_name; 2211 cc->has_work = arm_cpu_has_work; 2212 cc->dump_state = arm_cpu_dump_state; 2213 cc->set_pc = arm_cpu_set_pc; 2214 cc->get_pc = arm_cpu_get_pc; 2215 cc->gdb_read_register = arm_cpu_gdb_read_register; 2216 cc->gdb_write_register = arm_cpu_gdb_write_register; 2217 #ifndef CONFIG_USER_ONLY 2218 cc->sysemu_ops = &arm_sysemu_ops; 2219 #endif 2220 cc->gdb_num_core_regs = 26; 2221 cc->gdb_core_xml_file = "arm-core.xml"; 2222 cc->gdb_arch_name = arm_gdb_arch_name; 2223 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2224 cc->gdb_stop_before_watchpoint = true; 2225 cc->disas_set_info = arm_disas_set_info; 2226 2227 #ifdef CONFIG_TCG 2228 cc->tcg_ops = &arm_tcg_ops; 2229 #endif /* CONFIG_TCG */ 2230 } 2231 2232 static void arm_cpu_instance_init(Object *obj) 2233 { 2234 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2235 2236 acc->info->initfn(obj); 2237 arm_cpu_post_init(obj); 2238 } 2239 2240 static void cpu_register_class_init(ObjectClass *oc, void *data) 2241 { 2242 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2243 2244 acc->info = data; 2245 } 2246 2247 void arm_cpu_register(const ARMCPUInfo *info) 2248 { 2249 TypeInfo type_info = { 2250 .parent = TYPE_ARM_CPU, 2251 .instance_size = sizeof(ARMCPU), 2252 .instance_align = __alignof__(ARMCPU), 2253 .instance_init = arm_cpu_instance_init, 2254 .class_size = sizeof(ARMCPUClass), 2255 .class_init = info->class_init ?: cpu_register_class_init, 2256 .class_data = (void *)info, 2257 }; 2258 2259 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2260 type_register(&type_info); 2261 g_free((void *)type_info.name); 2262 } 2263 2264 static const TypeInfo arm_cpu_type_info = { 2265 .name = TYPE_ARM_CPU, 2266 .parent = TYPE_CPU, 2267 .instance_size = sizeof(ARMCPU), 2268 .instance_align = __alignof__(ARMCPU), 2269 .instance_init = arm_cpu_initfn, 2270 .instance_finalize = arm_cpu_finalizefn, 2271 .abstract = true, 2272 .class_size = sizeof(ARMCPUClass), 2273 .class_init = arm_cpu_class_init, 2274 }; 2275 2276 static void arm_cpu_register_types(void) 2277 { 2278 type_register_static(&arm_cpu_type_info); 2279 } 2280 2281 type_init(arm_cpu_register_types) 2282