1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu-common.h" 24 #include "target/arm/idau.h" 25 #include "qemu/module.h" 26 #include "qapi/error.h" 27 #include "qapi/visitor.h" 28 #include "cpu.h" 29 #include "internals.h" 30 #include "exec/exec-all.h" 31 #include "hw/qdev-properties.h" 32 #if !defined(CONFIG_USER_ONLY) 33 #include "hw/loader.h" 34 #include "hw/boards.h" 35 #endif 36 #include "sysemu/sysemu.h" 37 #include "sysemu/tcg.h" 38 #include "sysemu/hw_accel.h" 39 #include "kvm_arm.h" 40 #include "disas/capstone.h" 41 #include "fpu/softfloat.h" 42 43 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 44 { 45 ARMCPU *cpu = ARM_CPU(cs); 46 CPUARMState *env = &cpu->env; 47 48 if (is_a64(env)) { 49 env->pc = value; 50 env->thumb = 0; 51 } else { 52 env->regs[15] = value & ~1; 53 env->thumb = value & 1; 54 } 55 } 56 57 static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 58 { 59 ARMCPU *cpu = ARM_CPU(cs); 60 CPUARMState *env = &cpu->env; 61 62 /* 63 * It's OK to look at env for the current mode here, because it's 64 * never possible for an AArch64 TB to chain to an AArch32 TB. 65 */ 66 if (is_a64(env)) { 67 env->pc = tb->pc; 68 } else { 69 env->regs[15] = tb->pc; 70 } 71 } 72 73 static bool arm_cpu_has_work(CPUState *cs) 74 { 75 ARMCPU *cpu = ARM_CPU(cs); 76 77 return (cpu->power_state != PSCI_OFF) 78 && cs->interrupt_request & 79 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 80 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 81 | CPU_INTERRUPT_EXITTB); 82 } 83 84 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 85 void *opaque) 86 { 87 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 88 89 entry->hook = hook; 90 entry->opaque = opaque; 91 92 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 93 } 94 95 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 96 void *opaque) 97 { 98 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 99 100 entry->hook = hook; 101 entry->opaque = opaque; 102 103 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 104 } 105 106 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 107 { 108 /* Reset a single ARMCPRegInfo register */ 109 ARMCPRegInfo *ri = value; 110 ARMCPU *cpu = opaque; 111 112 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 113 return; 114 } 115 116 if (ri->resetfn) { 117 ri->resetfn(&cpu->env, ri); 118 return; 119 } 120 121 /* A zero offset is never possible as it would be regs[0] 122 * so we use it to indicate that reset is being handled elsewhere. 123 * This is basically only used for fields in non-core coprocessors 124 * (like the pxa2xx ones). 125 */ 126 if (!ri->fieldoffset) { 127 return; 128 } 129 130 if (cpreg_field_is_64bit(ri)) { 131 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 132 } else { 133 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 134 } 135 } 136 137 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 138 { 139 /* Purely an assertion check: we've already done reset once, 140 * so now check that running the reset for the cpreg doesn't 141 * change its value. This traps bugs where two different cpregs 142 * both try to reset the same state field but to different values. 143 */ 144 ARMCPRegInfo *ri = value; 145 ARMCPU *cpu = opaque; 146 uint64_t oldvalue, newvalue; 147 148 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 149 return; 150 } 151 152 oldvalue = read_raw_cp_reg(&cpu->env, ri); 153 cp_reg_reset(key, value, opaque); 154 newvalue = read_raw_cp_reg(&cpu->env, ri); 155 assert(oldvalue == newvalue); 156 } 157 158 static void arm_cpu_reset(DeviceState *dev) 159 { 160 CPUState *s = CPU(dev); 161 ARMCPU *cpu = ARM_CPU(s); 162 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 163 CPUARMState *env = &cpu->env; 164 165 acc->parent_reset(dev); 166 167 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 168 169 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 170 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 171 172 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 173 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 174 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 175 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 176 177 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 178 s->halted = cpu->start_powered_off; 179 180 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 181 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 182 } 183 184 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 185 /* 64 bit CPUs always start in 64 bit mode */ 186 env->aarch64 = 1; 187 #if defined(CONFIG_USER_ONLY) 188 env->pstate = PSTATE_MODE_EL0t; 189 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 190 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 191 /* Enable all PAC keys. */ 192 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 193 SCTLR_EnDA | SCTLR_EnDB); 194 /* and to the FP/Neon instructions */ 195 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 196 /* and to the SVE instructions */ 197 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 198 /* with reasonable vector length */ 199 if (cpu_isar_feature(aa64_sve, cpu)) { 200 env->vfp.zcr_el[1] = MIN(cpu->sve_max_vq - 1, 3); 201 } 202 /* 203 * Enable TBI0 and TBI1. While the real kernel only enables TBI0, 204 * turning on both here will produce smaller code and otherwise 205 * make no difference to the user-level emulation. 206 */ 207 env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); 208 #else 209 /* Reset into the highest available EL */ 210 if (arm_feature(env, ARM_FEATURE_EL3)) { 211 env->pstate = PSTATE_MODE_EL3h; 212 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 213 env->pstate = PSTATE_MODE_EL2h; 214 } else { 215 env->pstate = PSTATE_MODE_EL1h; 216 } 217 env->pc = cpu->rvbar; 218 #endif 219 } else { 220 #if defined(CONFIG_USER_ONLY) 221 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 222 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 223 #endif 224 } 225 226 #if defined(CONFIG_USER_ONLY) 227 env->uncached_cpsr = ARM_CPU_MODE_USR; 228 /* For user mode we must enable access to coprocessors */ 229 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 230 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 231 env->cp15.c15_cpar = 3; 232 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 233 env->cp15.c15_cpar = 1; 234 } 235 #else 236 237 /* 238 * If the highest available EL is EL2, AArch32 will start in Hyp 239 * mode; otherwise it starts in SVC. Note that if we start in 240 * AArch64 then these values in the uncached_cpsr will be ignored. 241 */ 242 if (arm_feature(env, ARM_FEATURE_EL2) && 243 !arm_feature(env, ARM_FEATURE_EL3)) { 244 env->uncached_cpsr = ARM_CPU_MODE_HYP; 245 } else { 246 env->uncached_cpsr = ARM_CPU_MODE_SVC; 247 } 248 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 249 250 if (arm_feature(env, ARM_FEATURE_M)) { 251 uint32_t initial_msp; /* Loaded from 0x0 */ 252 uint32_t initial_pc; /* Loaded from 0x4 */ 253 uint8_t *rom; 254 uint32_t vecbase; 255 256 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 257 env->v7m.secure = true; 258 } else { 259 /* This bit resets to 0 if security is supported, but 1 if 260 * it is not. The bit is not present in v7M, but we set it 261 * here so we can avoid having to make checks on it conditional 262 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 263 */ 264 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 265 /* 266 * Set NSACR to indicate "NS access permitted to everything"; 267 * this avoids having to have all the tests of it being 268 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 269 * v8.1M the guest-visible value of NSACR in a CPU without the 270 * Security Extension is 0xcff. 271 */ 272 env->v7m.nsacr = 0xcff; 273 } 274 275 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 276 * that it resets to 1, so QEMU always does that rather than making 277 * it dependent on CPU model. In v8M it is RES1. 278 */ 279 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 280 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 281 if (arm_feature(env, ARM_FEATURE_V8)) { 282 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 283 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 284 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 285 } 286 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 287 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 288 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 289 } 290 291 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 292 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 293 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 294 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 295 } 296 /* Unlike A/R profile, M profile defines the reset LR value */ 297 env->regs[14] = 0xffffffff; 298 299 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 300 301 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 302 vecbase = env->v7m.vecbase[env->v7m.secure]; 303 rom = rom_ptr(vecbase, 8); 304 if (rom) { 305 /* Address zero is covered by ROM which hasn't yet been 306 * copied into physical memory. 307 */ 308 initial_msp = ldl_p(rom); 309 initial_pc = ldl_p(rom + 4); 310 } else { 311 /* Address zero not covered by a ROM blob, or the ROM blob 312 * is in non-modifiable memory and this is a second reset after 313 * it got copied into memory. In the latter case, rom_ptr 314 * will return a NULL pointer and we should use ldl_phys instead. 315 */ 316 initial_msp = ldl_phys(s->as, vecbase); 317 initial_pc = ldl_phys(s->as, vecbase + 4); 318 } 319 320 env->regs[13] = initial_msp & 0xFFFFFFFC; 321 env->regs[15] = initial_pc & ~1; 322 env->thumb = initial_pc & 1; 323 } 324 325 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 326 * executing as AArch32 then check if highvecs are enabled and 327 * adjust the PC accordingly. 328 */ 329 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 330 env->regs[15] = 0xFFFF0000; 331 } 332 333 /* M profile requires that reset clears the exclusive monitor; 334 * A profile does not, but clearing it makes more sense than having it 335 * set with an exclusive access on address zero. 336 */ 337 arm_clear_exclusive(env); 338 339 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 340 #endif 341 342 if (arm_feature(env, ARM_FEATURE_PMSA)) { 343 if (cpu->pmsav7_dregion > 0) { 344 if (arm_feature(env, ARM_FEATURE_V8)) { 345 memset(env->pmsav8.rbar[M_REG_NS], 0, 346 sizeof(*env->pmsav8.rbar[M_REG_NS]) 347 * cpu->pmsav7_dregion); 348 memset(env->pmsav8.rlar[M_REG_NS], 0, 349 sizeof(*env->pmsav8.rlar[M_REG_NS]) 350 * cpu->pmsav7_dregion); 351 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 352 memset(env->pmsav8.rbar[M_REG_S], 0, 353 sizeof(*env->pmsav8.rbar[M_REG_S]) 354 * cpu->pmsav7_dregion); 355 memset(env->pmsav8.rlar[M_REG_S], 0, 356 sizeof(*env->pmsav8.rlar[M_REG_S]) 357 * cpu->pmsav7_dregion); 358 } 359 } else if (arm_feature(env, ARM_FEATURE_V7)) { 360 memset(env->pmsav7.drbar, 0, 361 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 362 memset(env->pmsav7.drsr, 0, 363 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 364 memset(env->pmsav7.dracr, 0, 365 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 366 } 367 } 368 env->pmsav7.rnr[M_REG_NS] = 0; 369 env->pmsav7.rnr[M_REG_S] = 0; 370 env->pmsav8.mair0[M_REG_NS] = 0; 371 env->pmsav8.mair0[M_REG_S] = 0; 372 env->pmsav8.mair1[M_REG_NS] = 0; 373 env->pmsav8.mair1[M_REG_S] = 0; 374 } 375 376 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 377 if (cpu->sau_sregion > 0) { 378 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 379 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 380 } 381 env->sau.rnr = 0; 382 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 383 * the Cortex-M33 does. 384 */ 385 env->sau.ctrl = 0; 386 } 387 388 set_flush_to_zero(1, &env->vfp.standard_fp_status); 389 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 390 set_default_nan_mode(1, &env->vfp.standard_fp_status); 391 set_float_detect_tininess(float_tininess_before_rounding, 392 &env->vfp.fp_status); 393 set_float_detect_tininess(float_tininess_before_rounding, 394 &env->vfp.standard_fp_status); 395 set_float_detect_tininess(float_tininess_before_rounding, 396 &env->vfp.fp_status_f16); 397 #ifndef CONFIG_USER_ONLY 398 if (kvm_enabled()) { 399 kvm_arm_reset_vcpu(cpu); 400 } 401 #endif 402 403 hw_breakpoint_update_all(cpu); 404 hw_watchpoint_update_all(cpu); 405 arm_rebuild_hflags(env); 406 } 407 408 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 409 unsigned int target_el, 410 unsigned int cur_el, bool secure, 411 uint64_t hcr_el2) 412 { 413 CPUARMState *env = cs->env_ptr; 414 bool pstate_unmasked; 415 bool unmasked = false; 416 417 /* 418 * Don't take exceptions if they target a lower EL. 419 * This check should catch any exceptions that would not be taken 420 * but left pending. 421 */ 422 if (cur_el > target_el) { 423 return false; 424 } 425 426 switch (excp_idx) { 427 case EXCP_FIQ: 428 pstate_unmasked = !(env->daif & PSTATE_F); 429 break; 430 431 case EXCP_IRQ: 432 pstate_unmasked = !(env->daif & PSTATE_I); 433 break; 434 435 case EXCP_VFIQ: 436 if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 437 /* VFIQs are only taken when hypervized and non-secure. */ 438 return false; 439 } 440 return !(env->daif & PSTATE_F); 441 case EXCP_VIRQ: 442 if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 443 /* VIRQs are only taken when hypervized and non-secure. */ 444 return false; 445 } 446 return !(env->daif & PSTATE_I); 447 default: 448 g_assert_not_reached(); 449 } 450 451 /* 452 * Use the target EL, current execution state and SCR/HCR settings to 453 * determine whether the corresponding CPSR bit is used to mask the 454 * interrupt. 455 */ 456 if ((target_el > cur_el) && (target_el != 1)) { 457 /* Exceptions targeting a higher EL may not be maskable */ 458 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 459 /* 460 * 64-bit masking rules are simple: exceptions to EL3 461 * can't be masked, and exceptions to EL2 can only be 462 * masked from Secure state. The HCR and SCR settings 463 * don't affect the masking logic, only the interrupt routing. 464 */ 465 if (target_el == 3 || !secure) { 466 unmasked = true; 467 } 468 } else { 469 /* 470 * The old 32-bit-only environment has a more complicated 471 * masking setup. HCR and SCR bits not only affect interrupt 472 * routing but also change the behaviour of masking. 473 */ 474 bool hcr, scr; 475 476 switch (excp_idx) { 477 case EXCP_FIQ: 478 /* 479 * If FIQs are routed to EL3 or EL2 then there are cases where 480 * we override the CPSR.F in determining if the exception is 481 * masked or not. If neither of these are set then we fall back 482 * to the CPSR.F setting otherwise we further assess the state 483 * below. 484 */ 485 hcr = hcr_el2 & HCR_FMO; 486 scr = (env->cp15.scr_el3 & SCR_FIQ); 487 488 /* 489 * When EL3 is 32-bit, the SCR.FW bit controls whether the 490 * CPSR.F bit masks FIQ interrupts when taken in non-secure 491 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 492 * when non-secure but only when FIQs are only routed to EL3. 493 */ 494 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 495 break; 496 case EXCP_IRQ: 497 /* 498 * When EL3 execution state is 32-bit, if HCR.IMO is set then 499 * we may override the CPSR.I masking when in non-secure state. 500 * The SCR.IRQ setting has already been taken into consideration 501 * when setting the target EL, so it does not have a further 502 * affect here. 503 */ 504 hcr = hcr_el2 & HCR_IMO; 505 scr = false; 506 break; 507 default: 508 g_assert_not_reached(); 509 } 510 511 if ((scr || hcr) && !secure) { 512 unmasked = true; 513 } 514 } 515 } 516 517 /* 518 * The PSTATE bits only mask the interrupt if we have not overriden the 519 * ability above. 520 */ 521 return unmasked || pstate_unmasked; 522 } 523 524 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 525 { 526 CPUClass *cc = CPU_GET_CLASS(cs); 527 CPUARMState *env = cs->env_ptr; 528 uint32_t cur_el = arm_current_el(env); 529 bool secure = arm_is_secure(env); 530 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 531 uint32_t target_el; 532 uint32_t excp_idx; 533 534 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 535 536 if (interrupt_request & CPU_INTERRUPT_FIQ) { 537 excp_idx = EXCP_FIQ; 538 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 539 if (arm_excp_unmasked(cs, excp_idx, target_el, 540 cur_el, secure, hcr_el2)) { 541 goto found; 542 } 543 } 544 if (interrupt_request & CPU_INTERRUPT_HARD) { 545 excp_idx = EXCP_IRQ; 546 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 547 if (arm_excp_unmasked(cs, excp_idx, target_el, 548 cur_el, secure, hcr_el2)) { 549 goto found; 550 } 551 } 552 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 553 excp_idx = EXCP_VIRQ; 554 target_el = 1; 555 if (arm_excp_unmasked(cs, excp_idx, target_el, 556 cur_el, secure, hcr_el2)) { 557 goto found; 558 } 559 } 560 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 561 excp_idx = EXCP_VFIQ; 562 target_el = 1; 563 if (arm_excp_unmasked(cs, excp_idx, target_el, 564 cur_el, secure, hcr_el2)) { 565 goto found; 566 } 567 } 568 return false; 569 570 found: 571 cs->exception_index = excp_idx; 572 env->exception.target_el = target_el; 573 cc->do_interrupt(cs); 574 return true; 575 } 576 577 void arm_cpu_update_virq(ARMCPU *cpu) 578 { 579 /* 580 * Update the interrupt level for VIRQ, which is the logical OR of 581 * the HCR_EL2.VI bit and the input line level from the GIC. 582 */ 583 CPUARMState *env = &cpu->env; 584 CPUState *cs = CPU(cpu); 585 586 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 587 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 588 589 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 590 if (new_state) { 591 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 592 } else { 593 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 594 } 595 } 596 } 597 598 void arm_cpu_update_vfiq(ARMCPU *cpu) 599 { 600 /* 601 * Update the interrupt level for VFIQ, which is the logical OR of 602 * the HCR_EL2.VF bit and the input line level from the GIC. 603 */ 604 CPUARMState *env = &cpu->env; 605 CPUState *cs = CPU(cpu); 606 607 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 608 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 609 610 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 611 if (new_state) { 612 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 613 } else { 614 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 615 } 616 } 617 } 618 619 #ifndef CONFIG_USER_ONLY 620 static void arm_cpu_set_irq(void *opaque, int irq, int level) 621 { 622 ARMCPU *cpu = opaque; 623 CPUARMState *env = &cpu->env; 624 CPUState *cs = CPU(cpu); 625 static const int mask[] = { 626 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 627 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 628 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 629 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 630 }; 631 632 if (level) { 633 env->irq_line_state |= mask[irq]; 634 } else { 635 env->irq_line_state &= ~mask[irq]; 636 } 637 638 switch (irq) { 639 case ARM_CPU_VIRQ: 640 assert(arm_feature(env, ARM_FEATURE_EL2)); 641 arm_cpu_update_virq(cpu); 642 break; 643 case ARM_CPU_VFIQ: 644 assert(arm_feature(env, ARM_FEATURE_EL2)); 645 arm_cpu_update_vfiq(cpu); 646 break; 647 case ARM_CPU_IRQ: 648 case ARM_CPU_FIQ: 649 if (level) { 650 cpu_interrupt(cs, mask[irq]); 651 } else { 652 cpu_reset_interrupt(cs, mask[irq]); 653 } 654 break; 655 default: 656 g_assert_not_reached(); 657 } 658 } 659 660 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 661 { 662 #ifdef CONFIG_KVM 663 ARMCPU *cpu = opaque; 664 CPUARMState *env = &cpu->env; 665 CPUState *cs = CPU(cpu); 666 uint32_t linestate_bit; 667 int irq_id; 668 669 switch (irq) { 670 case ARM_CPU_IRQ: 671 irq_id = KVM_ARM_IRQ_CPU_IRQ; 672 linestate_bit = CPU_INTERRUPT_HARD; 673 break; 674 case ARM_CPU_FIQ: 675 irq_id = KVM_ARM_IRQ_CPU_FIQ; 676 linestate_bit = CPU_INTERRUPT_FIQ; 677 break; 678 default: 679 g_assert_not_reached(); 680 } 681 682 if (level) { 683 env->irq_line_state |= linestate_bit; 684 } else { 685 env->irq_line_state &= ~linestate_bit; 686 } 687 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 688 #endif 689 } 690 691 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 692 { 693 ARMCPU *cpu = ARM_CPU(cs); 694 CPUARMState *env = &cpu->env; 695 696 cpu_synchronize_state(cs); 697 return arm_cpu_data_is_big_endian(env); 698 } 699 700 #endif 701 702 static int 703 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 704 { 705 return print_insn_arm(pc | 1, info); 706 } 707 708 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 709 { 710 ARMCPU *ac = ARM_CPU(cpu); 711 CPUARMState *env = &ac->env; 712 bool sctlr_b; 713 714 if (is_a64(env)) { 715 /* We might not be compiled with the A64 disassembler 716 * because it needs a C++ compiler. Leave print_insn 717 * unset in this case to use the caller default behaviour. 718 */ 719 #if defined(CONFIG_ARM_A64_DIS) 720 info->print_insn = print_insn_arm_a64; 721 #endif 722 info->cap_arch = CS_ARCH_ARM64; 723 info->cap_insn_unit = 4; 724 info->cap_insn_split = 4; 725 } else { 726 int cap_mode; 727 if (env->thumb) { 728 info->print_insn = print_insn_thumb1; 729 info->cap_insn_unit = 2; 730 info->cap_insn_split = 4; 731 cap_mode = CS_MODE_THUMB; 732 } else { 733 info->print_insn = print_insn_arm; 734 info->cap_insn_unit = 4; 735 info->cap_insn_split = 4; 736 cap_mode = CS_MODE_ARM; 737 } 738 if (arm_feature(env, ARM_FEATURE_V8)) { 739 cap_mode |= CS_MODE_V8; 740 } 741 if (arm_feature(env, ARM_FEATURE_M)) { 742 cap_mode |= CS_MODE_MCLASS; 743 } 744 info->cap_arch = CS_ARCH_ARM; 745 info->cap_mode = cap_mode; 746 } 747 748 sctlr_b = arm_sctlr_b(env); 749 if (bswap_code(sctlr_b)) { 750 #ifdef TARGET_WORDS_BIGENDIAN 751 info->endian = BFD_ENDIAN_LITTLE; 752 #else 753 info->endian = BFD_ENDIAN_BIG; 754 #endif 755 } 756 info->flags &= ~INSN_ARM_BE32; 757 #ifndef CONFIG_USER_ONLY 758 if (sctlr_b) { 759 info->flags |= INSN_ARM_BE32; 760 } 761 #endif 762 } 763 764 #ifdef TARGET_AARCH64 765 766 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 767 { 768 ARMCPU *cpu = ARM_CPU(cs); 769 CPUARMState *env = &cpu->env; 770 uint32_t psr = pstate_read(env); 771 int i; 772 int el = arm_current_el(env); 773 const char *ns_status; 774 775 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 776 for (i = 0; i < 32; i++) { 777 if (i == 31) { 778 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 779 } else { 780 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 781 (i + 2) % 3 ? " " : "\n"); 782 } 783 } 784 785 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 786 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 787 } else { 788 ns_status = ""; 789 } 790 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 791 psr, 792 psr & PSTATE_N ? 'N' : '-', 793 psr & PSTATE_Z ? 'Z' : '-', 794 psr & PSTATE_C ? 'C' : '-', 795 psr & PSTATE_V ? 'V' : '-', 796 ns_status, 797 el, 798 psr & PSTATE_SP ? 'h' : 't'); 799 800 if (cpu_isar_feature(aa64_bti, cpu)) { 801 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 802 } 803 if (!(flags & CPU_DUMP_FPU)) { 804 qemu_fprintf(f, "\n"); 805 return; 806 } 807 if (fp_exception_el(env, el) != 0) { 808 qemu_fprintf(f, " FPU disabled\n"); 809 return; 810 } 811 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 812 vfp_get_fpcr(env), vfp_get_fpsr(env)); 813 814 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { 815 int j, zcr_len = sve_zcr_len_for_el(env, el); 816 817 for (i = 0; i <= FFR_PRED_NUM; i++) { 818 bool eol; 819 if (i == FFR_PRED_NUM) { 820 qemu_fprintf(f, "FFR="); 821 /* It's last, so end the line. */ 822 eol = true; 823 } else { 824 qemu_fprintf(f, "P%02d=", i); 825 switch (zcr_len) { 826 case 0: 827 eol = i % 8 == 7; 828 break; 829 case 1: 830 eol = i % 6 == 5; 831 break; 832 case 2: 833 case 3: 834 eol = i % 3 == 2; 835 break; 836 default: 837 /* More than one quadword per predicate. */ 838 eol = true; 839 break; 840 } 841 } 842 for (j = zcr_len / 4; j >= 0; j--) { 843 int digits; 844 if (j * 4 + 4 <= zcr_len + 1) { 845 digits = 16; 846 } else { 847 digits = (zcr_len % 4 + 1) * 4; 848 } 849 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 850 env->vfp.pregs[i].p[j], 851 j ? ":" : eol ? "\n" : " "); 852 } 853 } 854 855 for (i = 0; i < 32; i++) { 856 if (zcr_len == 0) { 857 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 858 i, env->vfp.zregs[i].d[1], 859 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 860 } else if (zcr_len == 1) { 861 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 862 ":%016" PRIx64 ":%016" PRIx64 "\n", 863 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 864 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 865 } else { 866 for (j = zcr_len; j >= 0; j--) { 867 bool odd = (zcr_len - j) % 2 != 0; 868 if (j == zcr_len) { 869 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 870 } else if (!odd) { 871 if (j > 0) { 872 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 873 } else { 874 qemu_fprintf(f, " [%x]=", j); 875 } 876 } 877 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 878 env->vfp.zregs[i].d[j * 2 + 1], 879 env->vfp.zregs[i].d[j * 2], 880 odd || j == 0 ? "\n" : ":"); 881 } 882 } 883 } 884 } else { 885 for (i = 0; i < 32; i++) { 886 uint64_t *q = aa64_vfp_qreg(env, i); 887 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 888 i, q[1], q[0], (i & 1 ? "\n" : " ")); 889 } 890 } 891 } 892 893 #else 894 895 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 896 { 897 g_assert_not_reached(); 898 } 899 900 #endif 901 902 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 903 { 904 ARMCPU *cpu = ARM_CPU(cs); 905 CPUARMState *env = &cpu->env; 906 int i; 907 908 if (is_a64(env)) { 909 aarch64_cpu_dump_state(cs, f, flags); 910 return; 911 } 912 913 for (i = 0; i < 16; i++) { 914 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 915 if ((i % 4) == 3) { 916 qemu_fprintf(f, "\n"); 917 } else { 918 qemu_fprintf(f, " "); 919 } 920 } 921 922 if (arm_feature(env, ARM_FEATURE_M)) { 923 uint32_t xpsr = xpsr_read(env); 924 const char *mode; 925 const char *ns_status = ""; 926 927 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 928 ns_status = env->v7m.secure ? "S " : "NS "; 929 } 930 931 if (xpsr & XPSR_EXCP) { 932 mode = "handler"; 933 } else { 934 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 935 mode = "unpriv-thread"; 936 } else { 937 mode = "priv-thread"; 938 } 939 } 940 941 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 942 xpsr, 943 xpsr & XPSR_N ? 'N' : '-', 944 xpsr & XPSR_Z ? 'Z' : '-', 945 xpsr & XPSR_C ? 'C' : '-', 946 xpsr & XPSR_V ? 'V' : '-', 947 xpsr & XPSR_T ? 'T' : 'A', 948 ns_status, 949 mode); 950 } else { 951 uint32_t psr = cpsr_read(env); 952 const char *ns_status = ""; 953 954 if (arm_feature(env, ARM_FEATURE_EL3) && 955 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 956 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 957 } 958 959 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 960 psr, 961 psr & CPSR_N ? 'N' : '-', 962 psr & CPSR_Z ? 'Z' : '-', 963 psr & CPSR_C ? 'C' : '-', 964 psr & CPSR_V ? 'V' : '-', 965 psr & CPSR_T ? 'T' : 'A', 966 ns_status, 967 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 968 } 969 970 if (flags & CPU_DUMP_FPU) { 971 int numvfpregs = 0; 972 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 973 numvfpregs = 32; 974 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 975 numvfpregs = 16; 976 } 977 for (i = 0; i < numvfpregs; i++) { 978 uint64_t v = *aa32_vfp_dreg(env, i); 979 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 980 i * 2, (uint32_t)v, 981 i * 2 + 1, (uint32_t)(v >> 32), 982 i, v); 983 } 984 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 985 } 986 } 987 988 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 989 { 990 uint32_t Aff1 = idx / clustersz; 991 uint32_t Aff0 = idx % clustersz; 992 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 993 } 994 995 static void cpreg_hashtable_data_destroy(gpointer data) 996 { 997 /* 998 * Destroy function for cpu->cp_regs hashtable data entries. 999 * We must free the name string because it was g_strdup()ed in 1000 * add_cpreg_to_hashtable(). It's OK to cast away the 'const' 1001 * from r->name because we know we definitely allocated it. 1002 */ 1003 ARMCPRegInfo *r = data; 1004 1005 g_free((void *)r->name); 1006 g_free(r); 1007 } 1008 1009 static void arm_cpu_initfn(Object *obj) 1010 { 1011 ARMCPU *cpu = ARM_CPU(obj); 1012 1013 cpu_set_cpustate_pointers(cpu); 1014 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 1015 g_free, cpreg_hashtable_data_destroy); 1016 1017 QLIST_INIT(&cpu->pre_el_change_hooks); 1018 QLIST_INIT(&cpu->el_change_hooks); 1019 1020 #ifndef CONFIG_USER_ONLY 1021 /* Our inbound IRQ and FIQ lines */ 1022 if (kvm_enabled()) { 1023 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1024 * the same interface as non-KVM CPUs. 1025 */ 1026 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1027 } else { 1028 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1029 } 1030 1031 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1032 ARRAY_SIZE(cpu->gt_timer_outputs)); 1033 1034 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1035 "gicv3-maintenance-interrupt", 1); 1036 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1037 "pmu-interrupt", 1); 1038 #endif 1039 1040 /* DTB consumers generally don't in fact care what the 'compatible' 1041 * string is, so always provide some string and trust that a hypothetical 1042 * picky DTB consumer will also provide a helpful error message. 1043 */ 1044 cpu->dtb_compatible = "qemu,unknown"; 1045 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 1046 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1047 1048 if (tcg_enabled()) { 1049 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 1050 } 1051 } 1052 1053 static Property arm_cpu_gt_cntfrq_property = 1054 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1055 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1056 1057 static Property arm_cpu_reset_cbar_property = 1058 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1059 1060 static Property arm_cpu_reset_hivecs_property = 1061 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1062 1063 static Property arm_cpu_rvbar_property = 1064 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 1065 1066 #ifndef CONFIG_USER_ONLY 1067 static Property arm_cpu_has_el2_property = 1068 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1069 1070 static Property arm_cpu_has_el3_property = 1071 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1072 #endif 1073 1074 static Property arm_cpu_cfgend_property = 1075 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1076 1077 static Property arm_cpu_has_vfp_property = 1078 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1079 1080 static Property arm_cpu_has_neon_property = 1081 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1082 1083 static Property arm_cpu_has_dsp_property = 1084 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1085 1086 static Property arm_cpu_has_mpu_property = 1087 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1088 1089 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1090 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1091 * the right value for that particular CPU type, and we don't want 1092 * to override that with an incorrect constant value. 1093 */ 1094 static Property arm_cpu_pmsav7_dregion_property = 1095 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1096 pmsav7_dregion, 1097 qdev_prop_uint32, uint32_t); 1098 1099 static bool arm_get_pmu(Object *obj, Error **errp) 1100 { 1101 ARMCPU *cpu = ARM_CPU(obj); 1102 1103 return cpu->has_pmu; 1104 } 1105 1106 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1107 { 1108 ARMCPU *cpu = ARM_CPU(obj); 1109 1110 if (value) { 1111 if (kvm_enabled() && !kvm_arm_pmu_supported(CPU(cpu))) { 1112 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1113 return; 1114 } 1115 set_feature(&cpu->env, ARM_FEATURE_PMU); 1116 } else { 1117 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1118 } 1119 cpu->has_pmu = value; 1120 } 1121 1122 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1123 { 1124 /* 1125 * The exact approach to calculating guest ticks is: 1126 * 1127 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1128 * NANOSECONDS_PER_SECOND); 1129 * 1130 * We don't do that. Rather we intentionally use integer division 1131 * truncation below and in the caller for the conversion of host monotonic 1132 * time to guest ticks to provide the exact inverse for the semantics of 1133 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1134 * it loses precision when representing frequencies where 1135 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1136 * provide an exact inverse leads to scheduling timers with negative 1137 * periods, which in turn leads to sticky behaviour in the guest. 1138 * 1139 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1140 * cannot become zero. 1141 */ 1142 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1143 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1144 } 1145 1146 void arm_cpu_post_init(Object *obj) 1147 { 1148 ARMCPU *cpu = ARM_CPU(obj); 1149 1150 /* M profile implies PMSA. We have to do this here rather than 1151 * in realize with the other feature-implication checks because 1152 * we look at the PMSA bit to see if we should add some properties. 1153 */ 1154 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1155 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1156 } 1157 1158 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1159 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1160 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1161 } 1162 1163 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1164 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1165 } 1166 1167 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1168 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property); 1169 } 1170 1171 #ifndef CONFIG_USER_ONLY 1172 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1173 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1174 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1175 */ 1176 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1177 1178 object_property_add_link(obj, "secure-memory", 1179 TYPE_MEMORY_REGION, 1180 (Object **)&cpu->secure_memory, 1181 qdev_prop_allow_set_link_before_realize, 1182 OBJ_PROP_LINK_STRONG); 1183 } 1184 1185 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1186 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1187 } 1188 #endif 1189 1190 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1191 cpu->has_pmu = true; 1192 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1193 } 1194 1195 /* 1196 * Allow user to turn off VFP and Neon support, but only for TCG -- 1197 * KVM does not currently allow us to lie to the guest about its 1198 * ID/feature registers, so the guest always sees what the host has. 1199 */ 1200 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 1201 ? cpu_isar_feature(aa64_fp_simd, cpu) 1202 : cpu_isar_feature(aa32_vfp, cpu)) { 1203 cpu->has_vfp = true; 1204 if (!kvm_enabled()) { 1205 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1206 } 1207 } 1208 1209 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1210 cpu->has_neon = true; 1211 if (!kvm_enabled()) { 1212 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1213 } 1214 } 1215 1216 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1217 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1218 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1219 } 1220 1221 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1222 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1223 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1224 qdev_property_add_static(DEVICE(obj), 1225 &arm_cpu_pmsav7_dregion_property); 1226 } 1227 } 1228 1229 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1230 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1231 qdev_prop_allow_set_link_before_realize, 1232 OBJ_PROP_LINK_STRONG); 1233 /* 1234 * M profile: initial value of the Secure VTOR. We can't just use 1235 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1236 * the property to be set after realize. 1237 */ 1238 object_property_add_uint32_ptr(obj, "init-svtor", 1239 &cpu->init_svtor, 1240 OBJ_PROP_FLAG_READWRITE); 1241 } 1242 1243 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1244 1245 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1246 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1247 } 1248 } 1249 1250 static void arm_cpu_finalizefn(Object *obj) 1251 { 1252 ARMCPU *cpu = ARM_CPU(obj); 1253 ARMELChangeHook *hook, *next; 1254 1255 g_hash_table_destroy(cpu->cp_regs); 1256 1257 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1258 QLIST_REMOVE(hook, node); 1259 g_free(hook); 1260 } 1261 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1262 QLIST_REMOVE(hook, node); 1263 g_free(hook); 1264 } 1265 #ifndef CONFIG_USER_ONLY 1266 if (cpu->pmu_timer) { 1267 timer_del(cpu->pmu_timer); 1268 timer_deinit(cpu->pmu_timer); 1269 timer_free(cpu->pmu_timer); 1270 } 1271 #endif 1272 } 1273 1274 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1275 { 1276 Error *local_err = NULL; 1277 1278 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1279 arm_cpu_sve_finalize(cpu, &local_err); 1280 if (local_err != NULL) { 1281 error_propagate(errp, local_err); 1282 return; 1283 } 1284 } 1285 } 1286 1287 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1288 { 1289 CPUState *cs = CPU(dev); 1290 ARMCPU *cpu = ARM_CPU(dev); 1291 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1292 CPUARMState *env = &cpu->env; 1293 int pagebits; 1294 Error *local_err = NULL; 1295 bool no_aa32 = false; 1296 1297 /* If we needed to query the host kernel for the CPU features 1298 * then it's possible that might have failed in the initfn, but 1299 * this is the first point where we can report it. 1300 */ 1301 if (cpu->host_cpu_probe_failed) { 1302 if (!kvm_enabled()) { 1303 error_setg(errp, "The 'host' CPU type can only be used with KVM"); 1304 } else { 1305 error_setg(errp, "Failed to retrieve host CPU features"); 1306 } 1307 return; 1308 } 1309 1310 #ifndef CONFIG_USER_ONLY 1311 /* The NVIC and M-profile CPU are two halves of a single piece of 1312 * hardware; trying to use one without the other is a command line 1313 * error and will result in segfaults if not caught here. 1314 */ 1315 if (arm_feature(env, ARM_FEATURE_M)) { 1316 if (!env->nvic) { 1317 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1318 return; 1319 } 1320 } else { 1321 if (env->nvic) { 1322 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1323 return; 1324 } 1325 } 1326 1327 { 1328 uint64_t scale; 1329 1330 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1331 if (!cpu->gt_cntfrq_hz) { 1332 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1333 cpu->gt_cntfrq_hz); 1334 return; 1335 } 1336 scale = gt_cntfrq_period_ns(cpu); 1337 } else { 1338 scale = GTIMER_SCALE; 1339 } 1340 1341 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1342 arm_gt_ptimer_cb, cpu); 1343 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1344 arm_gt_vtimer_cb, cpu); 1345 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1346 arm_gt_htimer_cb, cpu); 1347 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1348 arm_gt_stimer_cb, cpu); 1349 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1350 arm_gt_hvtimer_cb, cpu); 1351 } 1352 #endif 1353 1354 cpu_exec_realizefn(cs, &local_err); 1355 if (local_err != NULL) { 1356 error_propagate(errp, local_err); 1357 return; 1358 } 1359 1360 arm_cpu_finalize_features(cpu, &local_err); 1361 if (local_err != NULL) { 1362 error_propagate(errp, local_err); 1363 return; 1364 } 1365 1366 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1367 cpu->has_vfp != cpu->has_neon) { 1368 /* 1369 * This is an architectural requirement for AArch64; AArch32 is 1370 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1371 */ 1372 error_setg(errp, 1373 "AArch64 CPUs must have both VFP and Neon or neither"); 1374 return; 1375 } 1376 1377 if (!cpu->has_vfp) { 1378 uint64_t t; 1379 uint32_t u; 1380 1381 t = cpu->isar.id_aa64isar1; 1382 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1383 cpu->isar.id_aa64isar1 = t; 1384 1385 t = cpu->isar.id_aa64pfr0; 1386 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1387 cpu->isar.id_aa64pfr0 = t; 1388 1389 u = cpu->isar.id_isar6; 1390 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1391 cpu->isar.id_isar6 = u; 1392 1393 u = cpu->isar.mvfr0; 1394 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1395 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1396 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1397 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1398 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1399 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1400 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1401 cpu->isar.mvfr0 = u; 1402 1403 u = cpu->isar.mvfr1; 1404 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1405 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1406 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1407 cpu->isar.mvfr1 = u; 1408 1409 u = cpu->isar.mvfr2; 1410 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1411 cpu->isar.mvfr2 = u; 1412 } 1413 1414 if (!cpu->has_neon) { 1415 uint64_t t; 1416 uint32_t u; 1417 1418 unset_feature(env, ARM_FEATURE_NEON); 1419 1420 t = cpu->isar.id_aa64isar0; 1421 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1422 cpu->isar.id_aa64isar0 = t; 1423 1424 t = cpu->isar.id_aa64isar1; 1425 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1426 cpu->isar.id_aa64isar1 = t; 1427 1428 t = cpu->isar.id_aa64pfr0; 1429 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1430 cpu->isar.id_aa64pfr0 = t; 1431 1432 u = cpu->isar.id_isar5; 1433 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1434 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1435 cpu->isar.id_isar5 = u; 1436 1437 u = cpu->isar.id_isar6; 1438 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1439 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1440 cpu->isar.id_isar6 = u; 1441 1442 u = cpu->isar.mvfr1; 1443 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1444 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1445 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1446 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1447 cpu->isar.mvfr1 = u; 1448 1449 u = cpu->isar.mvfr2; 1450 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1451 cpu->isar.mvfr2 = u; 1452 } 1453 1454 if (!cpu->has_neon && !cpu->has_vfp) { 1455 uint64_t t; 1456 uint32_t u; 1457 1458 t = cpu->isar.id_aa64isar0; 1459 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1460 cpu->isar.id_aa64isar0 = t; 1461 1462 t = cpu->isar.id_aa64isar1; 1463 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1464 cpu->isar.id_aa64isar1 = t; 1465 1466 u = cpu->isar.mvfr0; 1467 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1468 cpu->isar.mvfr0 = u; 1469 1470 /* Despite the name, this field covers both VFP and Neon */ 1471 u = cpu->isar.mvfr1; 1472 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1473 cpu->isar.mvfr1 = u; 1474 } 1475 1476 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1477 uint32_t u; 1478 1479 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1480 1481 u = cpu->isar.id_isar1; 1482 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1483 cpu->isar.id_isar1 = u; 1484 1485 u = cpu->isar.id_isar2; 1486 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1487 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1488 cpu->isar.id_isar2 = u; 1489 1490 u = cpu->isar.id_isar3; 1491 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1492 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1493 cpu->isar.id_isar3 = u; 1494 } 1495 1496 /* Some features automatically imply others: */ 1497 if (arm_feature(env, ARM_FEATURE_V8)) { 1498 if (arm_feature(env, ARM_FEATURE_M)) { 1499 set_feature(env, ARM_FEATURE_V7); 1500 } else { 1501 set_feature(env, ARM_FEATURE_V7VE); 1502 } 1503 } 1504 1505 /* 1506 * There exist AArch64 cpus without AArch32 support. When KVM 1507 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1508 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1509 * As a general principle, we also do not make ID register 1510 * consistency checks anywhere unless using TCG, because only 1511 * for TCG would a consistency-check failure be a QEMU bug. 1512 */ 1513 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1514 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1515 } 1516 1517 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1518 /* v7 Virtualization Extensions. In real hardware this implies 1519 * EL2 and also the presence of the Security Extensions. 1520 * For QEMU, for backwards-compatibility we implement some 1521 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1522 * include the various other features that V7VE implies. 1523 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1524 * Security Extensions is ARM_FEATURE_EL3. 1525 */ 1526 assert(!tcg_enabled() || no_aa32 || 1527 cpu_isar_feature(aa32_arm_div, cpu)); 1528 set_feature(env, ARM_FEATURE_LPAE); 1529 set_feature(env, ARM_FEATURE_V7); 1530 } 1531 if (arm_feature(env, ARM_FEATURE_V7)) { 1532 set_feature(env, ARM_FEATURE_VAPA); 1533 set_feature(env, ARM_FEATURE_THUMB2); 1534 set_feature(env, ARM_FEATURE_MPIDR); 1535 if (!arm_feature(env, ARM_FEATURE_M)) { 1536 set_feature(env, ARM_FEATURE_V6K); 1537 } else { 1538 set_feature(env, ARM_FEATURE_V6); 1539 } 1540 1541 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1542 * non-EL3 configs. This is needed by some legacy boards. 1543 */ 1544 set_feature(env, ARM_FEATURE_VBAR); 1545 } 1546 if (arm_feature(env, ARM_FEATURE_V6K)) { 1547 set_feature(env, ARM_FEATURE_V6); 1548 set_feature(env, ARM_FEATURE_MVFR); 1549 } 1550 if (arm_feature(env, ARM_FEATURE_V6)) { 1551 set_feature(env, ARM_FEATURE_V5); 1552 if (!arm_feature(env, ARM_FEATURE_M)) { 1553 assert(!tcg_enabled() || no_aa32 || 1554 cpu_isar_feature(aa32_jazelle, cpu)); 1555 set_feature(env, ARM_FEATURE_AUXCR); 1556 } 1557 } 1558 if (arm_feature(env, ARM_FEATURE_V5)) { 1559 set_feature(env, ARM_FEATURE_V4T); 1560 } 1561 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1562 set_feature(env, ARM_FEATURE_V7MP); 1563 set_feature(env, ARM_FEATURE_PXN); 1564 } 1565 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1566 set_feature(env, ARM_FEATURE_CBAR); 1567 } 1568 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1569 !arm_feature(env, ARM_FEATURE_M)) { 1570 set_feature(env, ARM_FEATURE_THUMB_DSP); 1571 } 1572 1573 /* 1574 * We rely on no XScale CPU having VFP so we can use the same bits in the 1575 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1576 */ 1577 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1578 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1579 !arm_feature(env, ARM_FEATURE_XSCALE)); 1580 1581 if (arm_feature(env, ARM_FEATURE_V7) && 1582 !arm_feature(env, ARM_FEATURE_M) && 1583 !arm_feature(env, ARM_FEATURE_PMSA)) { 1584 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1585 * can use 4K pages. 1586 */ 1587 pagebits = 12; 1588 } else { 1589 /* For CPUs which might have tiny 1K pages, or which have an 1590 * MPU and might have small region sizes, stick with 1K pages. 1591 */ 1592 pagebits = 10; 1593 } 1594 if (!set_preferred_target_page_bits(pagebits)) { 1595 /* This can only ever happen for hotplugging a CPU, or if 1596 * the board code incorrectly creates a CPU which it has 1597 * promised via minimum_page_size that it will not. 1598 */ 1599 error_setg(errp, "This CPU requires a smaller page size than the " 1600 "system is using"); 1601 return; 1602 } 1603 1604 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1605 * We don't support setting cluster ID ([16..23]) (known as Aff2 1606 * in later ARM ARM versions), or any of the higher affinity level fields, 1607 * so these bits always RAZ. 1608 */ 1609 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1610 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1611 ARM_DEFAULT_CPUS_PER_CLUSTER); 1612 } 1613 1614 if (cpu->reset_hivecs) { 1615 cpu->reset_sctlr |= (1 << 13); 1616 } 1617 1618 if (cpu->cfgend) { 1619 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1620 cpu->reset_sctlr |= SCTLR_EE; 1621 } else { 1622 cpu->reset_sctlr |= SCTLR_B; 1623 } 1624 } 1625 1626 if (!cpu->has_el3) { 1627 /* If the has_el3 CPU property is disabled then we need to disable the 1628 * feature. 1629 */ 1630 unset_feature(env, ARM_FEATURE_EL3); 1631 1632 /* Disable the security extension feature bits in the processor feature 1633 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 1634 */ 1635 cpu->id_pfr1 &= ~0xf0; 1636 cpu->isar.id_aa64pfr0 &= ~0xf000; 1637 } 1638 1639 if (!cpu->has_el2) { 1640 unset_feature(env, ARM_FEATURE_EL2); 1641 } 1642 1643 if (!cpu->has_pmu) { 1644 unset_feature(env, ARM_FEATURE_PMU); 1645 } 1646 if (arm_feature(env, ARM_FEATURE_PMU)) { 1647 pmu_init(cpu); 1648 1649 if (!kvm_enabled()) { 1650 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1651 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1652 } 1653 1654 #ifndef CONFIG_USER_ONLY 1655 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1656 cpu); 1657 #endif 1658 } else { 1659 cpu->isar.id_aa64dfr0 = 1660 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 1661 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 1662 cpu->pmceid0 = 0; 1663 cpu->pmceid1 = 0; 1664 } 1665 1666 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1667 /* Disable the hypervisor feature bits in the processor feature 1668 * registers if we don't have EL2. These are id_pfr1[15:12] and 1669 * id_aa64pfr0_el1[11:8]. 1670 */ 1671 cpu->isar.id_aa64pfr0 &= ~0xf00; 1672 cpu->id_pfr1 &= ~0xf000; 1673 } 1674 1675 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1676 * to false or by setting pmsav7-dregion to 0. 1677 */ 1678 if (!cpu->has_mpu) { 1679 cpu->pmsav7_dregion = 0; 1680 } 1681 if (cpu->pmsav7_dregion == 0) { 1682 cpu->has_mpu = false; 1683 } 1684 1685 if (arm_feature(env, ARM_FEATURE_PMSA) && 1686 arm_feature(env, ARM_FEATURE_V7)) { 1687 uint32_t nr = cpu->pmsav7_dregion; 1688 1689 if (nr > 0xff) { 1690 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1691 return; 1692 } 1693 1694 if (nr) { 1695 if (arm_feature(env, ARM_FEATURE_V8)) { 1696 /* PMSAv8 */ 1697 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1698 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1699 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1700 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1701 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1702 } 1703 } else { 1704 env->pmsav7.drbar = g_new0(uint32_t, nr); 1705 env->pmsav7.drsr = g_new0(uint32_t, nr); 1706 env->pmsav7.dracr = g_new0(uint32_t, nr); 1707 } 1708 } 1709 } 1710 1711 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1712 uint32_t nr = cpu->sau_sregion; 1713 1714 if (nr > 0xff) { 1715 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1716 return; 1717 } 1718 1719 if (nr) { 1720 env->sau.rbar = g_new0(uint32_t, nr); 1721 env->sau.rlar = g_new0(uint32_t, nr); 1722 } 1723 } 1724 1725 if (arm_feature(env, ARM_FEATURE_EL3)) { 1726 set_feature(env, ARM_FEATURE_VBAR); 1727 } 1728 1729 register_cp_regs_for_features(cpu); 1730 arm_cpu_register_gdb_regs_for_features(cpu); 1731 1732 init_cpreg_list(cpu); 1733 1734 #ifndef CONFIG_USER_ONLY 1735 MachineState *ms = MACHINE(qdev_get_machine()); 1736 unsigned int smp_cpus = ms->smp.cpus; 1737 1738 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1739 cs->num_ases = 2; 1740 1741 if (!cpu->secure_memory) { 1742 cpu->secure_memory = cs->memory; 1743 } 1744 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1745 cpu->secure_memory); 1746 } else { 1747 cs->num_ases = 1; 1748 } 1749 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1750 1751 /* No core_count specified, default to smp_cpus. */ 1752 if (cpu->core_count == -1) { 1753 cpu->core_count = smp_cpus; 1754 } 1755 #endif 1756 1757 qemu_init_vcpu(cs); 1758 cpu_reset(cs); 1759 1760 acc->parent_realize(dev, errp); 1761 } 1762 1763 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1764 { 1765 ObjectClass *oc; 1766 char *typename; 1767 char **cpuname; 1768 const char *cpunamestr; 1769 1770 cpuname = g_strsplit(cpu_model, ",", 1); 1771 cpunamestr = cpuname[0]; 1772 #ifdef CONFIG_USER_ONLY 1773 /* For backwards compatibility usermode emulation allows "-cpu any", 1774 * which has the same semantics as "-cpu max". 1775 */ 1776 if (!strcmp(cpunamestr, "any")) { 1777 cpunamestr = "max"; 1778 } 1779 #endif 1780 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 1781 oc = object_class_by_name(typename); 1782 g_strfreev(cpuname); 1783 g_free(typename); 1784 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 1785 object_class_is_abstract(oc)) { 1786 return NULL; 1787 } 1788 return oc; 1789 } 1790 1791 /* CPU models. These are not needed for the AArch64 linux-user build. */ 1792 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1793 1794 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1795 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1796 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1797 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1798 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1799 REGINFO_SENTINEL 1800 }; 1801 1802 static void cortex_a8_initfn(Object *obj) 1803 { 1804 ARMCPU *cpu = ARM_CPU(obj); 1805 1806 cpu->dtb_compatible = "arm,cortex-a8"; 1807 set_feature(&cpu->env, ARM_FEATURE_V7); 1808 set_feature(&cpu->env, ARM_FEATURE_NEON); 1809 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1810 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1811 set_feature(&cpu->env, ARM_FEATURE_EL3); 1812 cpu->midr = 0x410fc080; 1813 cpu->reset_fpsid = 0x410330c0; 1814 cpu->isar.mvfr0 = 0x11110222; 1815 cpu->isar.mvfr1 = 0x00011111; 1816 cpu->ctr = 0x82048004; 1817 cpu->reset_sctlr = 0x00c50078; 1818 cpu->id_pfr0 = 0x1031; 1819 cpu->id_pfr1 = 0x11; 1820 cpu->isar.id_dfr0 = 0x400; 1821 cpu->id_afr0 = 0; 1822 cpu->isar.id_mmfr0 = 0x31100003; 1823 cpu->isar.id_mmfr1 = 0x20000000; 1824 cpu->isar.id_mmfr2 = 0x01202000; 1825 cpu->isar.id_mmfr3 = 0x11; 1826 cpu->isar.id_isar0 = 0x00101111; 1827 cpu->isar.id_isar1 = 0x12112111; 1828 cpu->isar.id_isar2 = 0x21232031; 1829 cpu->isar.id_isar3 = 0x11112131; 1830 cpu->isar.id_isar4 = 0x00111142; 1831 cpu->isar.dbgdidr = 0x15141000; 1832 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1833 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1834 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1835 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1836 cpu->reset_auxcr = 2; 1837 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1838 } 1839 1840 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1841 /* power_control should be set to maximum latency. Again, 1842 * default to 0 and set by private hook 1843 */ 1844 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1845 .access = PL1_RW, .resetvalue = 0, 1846 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1847 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1848 .access = PL1_RW, .resetvalue = 0, 1849 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1850 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1851 .access = PL1_RW, .resetvalue = 0, 1852 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1853 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1854 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1855 /* TLB lockdown control */ 1856 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1857 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1858 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1859 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1860 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1861 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1862 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1863 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1864 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1865 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1866 REGINFO_SENTINEL 1867 }; 1868 1869 static void cortex_a9_initfn(Object *obj) 1870 { 1871 ARMCPU *cpu = ARM_CPU(obj); 1872 1873 cpu->dtb_compatible = "arm,cortex-a9"; 1874 set_feature(&cpu->env, ARM_FEATURE_V7); 1875 set_feature(&cpu->env, ARM_FEATURE_NEON); 1876 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1877 set_feature(&cpu->env, ARM_FEATURE_EL3); 1878 /* Note that A9 supports the MP extensions even for 1879 * A9UP and single-core A9MP (which are both different 1880 * and valid configurations; we don't model A9UP). 1881 */ 1882 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1883 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1884 cpu->midr = 0x410fc090; 1885 cpu->reset_fpsid = 0x41033090; 1886 cpu->isar.mvfr0 = 0x11110222; 1887 cpu->isar.mvfr1 = 0x01111111; 1888 cpu->ctr = 0x80038003; 1889 cpu->reset_sctlr = 0x00c50078; 1890 cpu->id_pfr0 = 0x1031; 1891 cpu->id_pfr1 = 0x11; 1892 cpu->isar.id_dfr0 = 0x000; 1893 cpu->id_afr0 = 0; 1894 cpu->isar.id_mmfr0 = 0x00100103; 1895 cpu->isar.id_mmfr1 = 0x20000000; 1896 cpu->isar.id_mmfr2 = 0x01230000; 1897 cpu->isar.id_mmfr3 = 0x00002111; 1898 cpu->isar.id_isar0 = 0x00101111; 1899 cpu->isar.id_isar1 = 0x13112111; 1900 cpu->isar.id_isar2 = 0x21232041; 1901 cpu->isar.id_isar3 = 0x11112131; 1902 cpu->isar.id_isar4 = 0x00111142; 1903 cpu->isar.dbgdidr = 0x35141000; 1904 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1905 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1906 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1907 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1908 } 1909 1910 #ifndef CONFIG_USER_ONLY 1911 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1912 { 1913 MachineState *ms = MACHINE(qdev_get_machine()); 1914 1915 /* Linux wants the number of processors from here. 1916 * Might as well set the interrupt-controller bit too. 1917 */ 1918 return ((ms->smp.cpus - 1) << 24) | (1 << 23); 1919 } 1920 #endif 1921 1922 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1923 #ifndef CONFIG_USER_ONLY 1924 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1925 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1926 .writefn = arm_cp_write_ignore, }, 1927 #endif 1928 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1929 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1930 REGINFO_SENTINEL 1931 }; 1932 1933 static void cortex_a7_initfn(Object *obj) 1934 { 1935 ARMCPU *cpu = ARM_CPU(obj); 1936 1937 cpu->dtb_compatible = "arm,cortex-a7"; 1938 set_feature(&cpu->env, ARM_FEATURE_V7VE); 1939 set_feature(&cpu->env, ARM_FEATURE_NEON); 1940 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1941 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1942 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1943 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1944 set_feature(&cpu->env, ARM_FEATURE_EL2); 1945 set_feature(&cpu->env, ARM_FEATURE_EL3); 1946 set_feature(&cpu->env, ARM_FEATURE_PMU); 1947 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1948 cpu->midr = 0x410fc075; 1949 cpu->reset_fpsid = 0x41023075; 1950 cpu->isar.mvfr0 = 0x10110222; 1951 cpu->isar.mvfr1 = 0x11111111; 1952 cpu->ctr = 0x84448003; 1953 cpu->reset_sctlr = 0x00c50078; 1954 cpu->id_pfr0 = 0x00001131; 1955 cpu->id_pfr1 = 0x00011011; 1956 cpu->isar.id_dfr0 = 0x02010555; 1957 cpu->id_afr0 = 0x00000000; 1958 cpu->isar.id_mmfr0 = 0x10101105; 1959 cpu->isar.id_mmfr1 = 0x40000000; 1960 cpu->isar.id_mmfr2 = 0x01240000; 1961 cpu->isar.id_mmfr3 = 0x02102211; 1962 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but 1963 * table 4-41 gives 0x02101110, which includes the arm div insns. 1964 */ 1965 cpu->isar.id_isar0 = 0x02101110; 1966 cpu->isar.id_isar1 = 0x13112111; 1967 cpu->isar.id_isar2 = 0x21232041; 1968 cpu->isar.id_isar3 = 0x11112131; 1969 cpu->isar.id_isar4 = 0x10011142; 1970 cpu->isar.dbgdidr = 0x3515f005; 1971 cpu->clidr = 0x0a200023; 1972 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1973 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1974 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1975 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1976 } 1977 1978 static void cortex_a15_initfn(Object *obj) 1979 { 1980 ARMCPU *cpu = ARM_CPU(obj); 1981 1982 cpu->dtb_compatible = "arm,cortex-a15"; 1983 set_feature(&cpu->env, ARM_FEATURE_V7VE); 1984 set_feature(&cpu->env, ARM_FEATURE_NEON); 1985 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1986 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1987 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1988 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1989 set_feature(&cpu->env, ARM_FEATURE_EL2); 1990 set_feature(&cpu->env, ARM_FEATURE_EL3); 1991 set_feature(&cpu->env, ARM_FEATURE_PMU); 1992 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1993 cpu->midr = 0x412fc0f1; 1994 cpu->reset_fpsid = 0x410430f0; 1995 cpu->isar.mvfr0 = 0x10110222; 1996 cpu->isar.mvfr1 = 0x11111111; 1997 cpu->ctr = 0x8444c004; 1998 cpu->reset_sctlr = 0x00c50078; 1999 cpu->id_pfr0 = 0x00001131; 2000 cpu->id_pfr1 = 0x00011011; 2001 cpu->isar.id_dfr0 = 0x02010555; 2002 cpu->id_afr0 = 0x00000000; 2003 cpu->isar.id_mmfr0 = 0x10201105; 2004 cpu->isar.id_mmfr1 = 0x20000000; 2005 cpu->isar.id_mmfr2 = 0x01240000; 2006 cpu->isar.id_mmfr3 = 0x02102211; 2007 cpu->isar.id_isar0 = 0x02101110; 2008 cpu->isar.id_isar1 = 0x13112111; 2009 cpu->isar.id_isar2 = 0x21232041; 2010 cpu->isar.id_isar3 = 0x11112131; 2011 cpu->isar.id_isar4 = 0x10011142; 2012 cpu->isar.dbgdidr = 0x3515f021; 2013 cpu->clidr = 0x0a200023; 2014 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 2015 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 2016 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 2017 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 2018 } 2019 2020 #ifndef TARGET_AARCH64 2021 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 2022 * otherwise, a CPU with as many features enabled as our emulation supports. 2023 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; 2024 * this only needs to handle 32 bits. 2025 */ 2026 static void arm_max_initfn(Object *obj) 2027 { 2028 ARMCPU *cpu = ARM_CPU(obj); 2029 2030 if (kvm_enabled()) { 2031 kvm_arm_set_cpu_features_from_host(cpu); 2032 kvm_arm_add_vcpu_properties(obj); 2033 } else { 2034 cortex_a15_initfn(obj); 2035 2036 /* old-style VFP short-vector support */ 2037 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 2038 2039 #ifdef CONFIG_USER_ONLY 2040 /* We don't set these in system emulation mode for the moment, 2041 * since we don't correctly set (all of) the ID registers to 2042 * advertise them. 2043 */ 2044 set_feature(&cpu->env, ARM_FEATURE_V8); 2045 { 2046 uint32_t t; 2047 2048 t = cpu->isar.id_isar5; 2049 t = FIELD_DP32(t, ID_ISAR5, AES, 2); 2050 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); 2051 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); 2052 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); 2053 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); 2054 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); 2055 cpu->isar.id_isar5 = t; 2056 2057 t = cpu->isar.id_isar6; 2058 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); 2059 t = FIELD_DP32(t, ID_ISAR6, DP, 1); 2060 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); 2061 t = FIELD_DP32(t, ID_ISAR6, SB, 1); 2062 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); 2063 cpu->isar.id_isar6 = t; 2064 2065 t = cpu->isar.mvfr1; 2066 t = FIELD_DP32(t, MVFR1, FPHP, 2); /* v8.0 FP support */ 2067 cpu->isar.mvfr1 = t; 2068 2069 t = cpu->isar.mvfr2; 2070 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ 2071 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ 2072 cpu->isar.mvfr2 = t; 2073 2074 t = cpu->isar.id_mmfr3; 2075 t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ 2076 cpu->isar.id_mmfr3 = t; 2077 2078 t = cpu->isar.id_mmfr4; 2079 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ 2080 t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ 2081 t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ 2082 t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ 2083 cpu->isar.id_mmfr4 = t; 2084 } 2085 #endif 2086 } 2087 } 2088 #endif 2089 2090 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 2091 2092 static const ARMCPUInfo arm_cpus[] = { 2093 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 2094 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 2095 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 2096 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 2097 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 2098 #ifndef TARGET_AARCH64 2099 { .name = "max", .initfn = arm_max_initfn }, 2100 #endif 2101 #ifdef CONFIG_USER_ONLY 2102 { .name = "any", .initfn = arm_max_initfn }, 2103 #endif 2104 #endif 2105 }; 2106 2107 static Property arm_cpu_properties[] = { 2108 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 2109 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 2110 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2111 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2112 mp_affinity, ARM64_AFFINITY_INVALID), 2113 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2114 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2115 DEFINE_PROP_END_OF_LIST() 2116 }; 2117 2118 static gchar *arm_gdb_arch_name(CPUState *cs) 2119 { 2120 ARMCPU *cpu = ARM_CPU(cs); 2121 CPUARMState *env = &cpu->env; 2122 2123 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2124 return g_strdup("iwmmxt"); 2125 } 2126 return g_strdup("arm"); 2127 } 2128 2129 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2130 { 2131 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2132 CPUClass *cc = CPU_CLASS(acc); 2133 DeviceClass *dc = DEVICE_CLASS(oc); 2134 2135 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2136 &acc->parent_realize); 2137 2138 device_class_set_props(dc, arm_cpu_properties); 2139 device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); 2140 2141 cc->class_by_name = arm_cpu_class_by_name; 2142 cc->has_work = arm_cpu_has_work; 2143 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 2144 cc->dump_state = arm_cpu_dump_state; 2145 cc->set_pc = arm_cpu_set_pc; 2146 cc->synchronize_from_tb = arm_cpu_synchronize_from_tb; 2147 cc->gdb_read_register = arm_cpu_gdb_read_register; 2148 cc->gdb_write_register = arm_cpu_gdb_write_register; 2149 #ifndef CONFIG_USER_ONLY 2150 cc->do_interrupt = arm_cpu_do_interrupt; 2151 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 2152 cc->asidx_from_attrs = arm_asidx_from_attrs; 2153 cc->vmsd = &vmstate_arm_cpu; 2154 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 2155 cc->write_elf64_note = arm_cpu_write_elf64_note; 2156 cc->write_elf32_note = arm_cpu_write_elf32_note; 2157 #endif 2158 cc->gdb_num_core_regs = 26; 2159 cc->gdb_core_xml_file = "arm-core.xml"; 2160 cc->gdb_arch_name = arm_gdb_arch_name; 2161 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2162 cc->gdb_stop_before_watchpoint = true; 2163 cc->disas_set_info = arm_disas_set_info; 2164 #ifdef CONFIG_TCG 2165 cc->tcg_initialize = arm_translate_init; 2166 cc->tlb_fill = arm_cpu_tlb_fill; 2167 cc->debug_excp_handler = arm_debug_excp_handler; 2168 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 2169 #if !defined(CONFIG_USER_ONLY) 2170 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 2171 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 2172 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 2173 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 2174 #endif 2175 } 2176 2177 #ifdef CONFIG_KVM 2178 static void arm_host_initfn(Object *obj) 2179 { 2180 ARMCPU *cpu = ARM_CPU(obj); 2181 2182 kvm_arm_set_cpu_features_from_host(cpu); 2183 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 2184 aarch64_add_sve_properties(obj); 2185 } 2186 kvm_arm_add_vcpu_properties(obj); 2187 arm_cpu_post_init(obj); 2188 } 2189 2190 static const TypeInfo host_arm_cpu_type_info = { 2191 .name = TYPE_ARM_HOST_CPU, 2192 #ifdef TARGET_AARCH64 2193 .parent = TYPE_AARCH64_CPU, 2194 #else 2195 .parent = TYPE_ARM_CPU, 2196 #endif 2197 .instance_init = arm_host_initfn, 2198 }; 2199 2200 #endif 2201 2202 static void arm_cpu_instance_init(Object *obj) 2203 { 2204 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2205 2206 acc->info->initfn(obj); 2207 arm_cpu_post_init(obj); 2208 } 2209 2210 static void cpu_register_class_init(ObjectClass *oc, void *data) 2211 { 2212 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2213 2214 acc->info = data; 2215 } 2216 2217 void arm_cpu_register(const ARMCPUInfo *info) 2218 { 2219 TypeInfo type_info = { 2220 .parent = TYPE_ARM_CPU, 2221 .instance_size = sizeof(ARMCPU), 2222 .instance_init = arm_cpu_instance_init, 2223 .class_size = sizeof(ARMCPUClass), 2224 .class_init = info->class_init ?: cpu_register_class_init, 2225 .class_data = (void *)info, 2226 }; 2227 2228 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2229 type_register(&type_info); 2230 g_free((void *)type_info.name); 2231 } 2232 2233 static const TypeInfo arm_cpu_type_info = { 2234 .name = TYPE_ARM_CPU, 2235 .parent = TYPE_CPU, 2236 .instance_size = sizeof(ARMCPU), 2237 .instance_init = arm_cpu_initfn, 2238 .instance_finalize = arm_cpu_finalizefn, 2239 .abstract = true, 2240 .class_size = sizeof(ARMCPUClass), 2241 .class_init = arm_cpu_class_init, 2242 }; 2243 2244 static const TypeInfo idau_interface_type_info = { 2245 .name = TYPE_IDAU_INTERFACE, 2246 .parent = TYPE_INTERFACE, 2247 .class_size = sizeof(IDAUInterfaceClass), 2248 }; 2249 2250 static void arm_cpu_register_types(void) 2251 { 2252 const size_t cpu_count = ARRAY_SIZE(arm_cpus); 2253 2254 type_register_static(&arm_cpu_type_info); 2255 2256 #ifdef CONFIG_KVM 2257 type_register_static(&host_arm_cpu_type_info); 2258 #endif 2259 2260 if (cpu_count) { 2261 size_t i; 2262 2263 type_register_static(&idau_interface_type_info); 2264 for (i = 0; i < cpu_count; ++i) { 2265 arm_cpu_register(&arm_cpus[i]); 2266 } 2267 } 2268 } 2269 2270 type_init(arm_cpu_register_types) 2271