1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu/timer.h" 24 #include "qemu/log.h" 25 #include "exec/page-vary.h" 26 #include "target/arm/idau.h" 27 #include "qemu/module.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "cpu.h" 31 #ifdef CONFIG_TCG 32 #include "hw/core/tcg-cpu-ops.h" 33 #endif /* CONFIG_TCG */ 34 #include "internals.h" 35 #include "exec/exec-all.h" 36 #include "hw/qdev-properties.h" 37 #if !defined(CONFIG_USER_ONLY) 38 #include "hw/loader.h" 39 #include "hw/boards.h" 40 #endif 41 #include "sysemu/tcg.h" 42 #include "sysemu/hw_accel.h" 43 #include "kvm_arm.h" 44 #include "disas/capstone.h" 45 #include "fpu/softfloat.h" 46 #include "cpregs.h" 47 48 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 49 { 50 ARMCPU *cpu = ARM_CPU(cs); 51 CPUARMState *env = &cpu->env; 52 53 if (is_a64(env)) { 54 env->pc = value; 55 env->thumb = false; 56 } else { 57 env->regs[15] = value & ~1; 58 env->thumb = value & 1; 59 } 60 } 61 62 #ifdef CONFIG_TCG 63 void arm_cpu_synchronize_from_tb(CPUState *cs, 64 const TranslationBlock *tb) 65 { 66 ARMCPU *cpu = ARM_CPU(cs); 67 CPUARMState *env = &cpu->env; 68 69 /* 70 * It's OK to look at env for the current mode here, because it's 71 * never possible for an AArch64 TB to chain to an AArch32 TB. 72 */ 73 if (is_a64(env)) { 74 env->pc = tb->pc; 75 } else { 76 env->regs[15] = tb->pc; 77 } 78 } 79 #endif /* CONFIG_TCG */ 80 81 static bool arm_cpu_has_work(CPUState *cs) 82 { 83 ARMCPU *cpu = ARM_CPU(cs); 84 85 return (cpu->power_state != PSCI_OFF) 86 && cs->interrupt_request & 87 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 88 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 89 | CPU_INTERRUPT_EXITTB); 90 } 91 92 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 93 void *opaque) 94 { 95 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 96 97 entry->hook = hook; 98 entry->opaque = opaque; 99 100 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 101 } 102 103 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 104 void *opaque) 105 { 106 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 107 108 entry->hook = hook; 109 entry->opaque = opaque; 110 111 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 112 } 113 114 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 115 { 116 /* Reset a single ARMCPRegInfo register */ 117 ARMCPRegInfo *ri = value; 118 ARMCPU *cpu = opaque; 119 120 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { 121 return; 122 } 123 124 if (ri->resetfn) { 125 ri->resetfn(&cpu->env, ri); 126 return; 127 } 128 129 /* A zero offset is never possible as it would be regs[0] 130 * so we use it to indicate that reset is being handled elsewhere. 131 * This is basically only used for fields in non-core coprocessors 132 * (like the pxa2xx ones). 133 */ 134 if (!ri->fieldoffset) { 135 return; 136 } 137 138 if (cpreg_field_is_64bit(ri)) { 139 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 140 } else { 141 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 142 } 143 } 144 145 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 146 { 147 /* Purely an assertion check: we've already done reset once, 148 * so now check that running the reset for the cpreg doesn't 149 * change its value. This traps bugs where two different cpregs 150 * both try to reset the same state field but to different values. 151 */ 152 ARMCPRegInfo *ri = value; 153 ARMCPU *cpu = opaque; 154 uint64_t oldvalue, newvalue; 155 156 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 157 return; 158 } 159 160 oldvalue = read_raw_cp_reg(&cpu->env, ri); 161 cp_reg_reset(key, value, opaque); 162 newvalue = read_raw_cp_reg(&cpu->env, ri); 163 assert(oldvalue == newvalue); 164 } 165 166 static void arm_cpu_reset(DeviceState *dev) 167 { 168 CPUState *s = CPU(dev); 169 ARMCPU *cpu = ARM_CPU(s); 170 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 171 CPUARMState *env = &cpu->env; 172 173 acc->parent_reset(dev); 174 175 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 176 177 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 178 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 179 180 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 181 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 182 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 183 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 184 185 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; 186 187 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 188 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 189 } 190 191 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 192 /* 64 bit CPUs always start in 64 bit mode */ 193 env->aarch64 = true; 194 #if defined(CONFIG_USER_ONLY) 195 env->pstate = PSTATE_MODE_EL0t; 196 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 197 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 198 /* Enable all PAC keys. */ 199 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 200 SCTLR_EnDA | SCTLR_EnDB); 201 /* Trap on btype=3 for PACIxSP. */ 202 env->cp15.sctlr_el[1] |= SCTLR_BT0; 203 /* and to the FP/Neon instructions */ 204 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 205 /* and to the SVE instructions */ 206 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 207 /* with reasonable vector length */ 208 if (cpu_isar_feature(aa64_sve, cpu)) { 209 env->vfp.zcr_el[1] = 210 aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1); 211 } 212 /* 213 * Enable 48-bit address space (TODO: take reserved_va into account). 214 * Enable TBI0 but not TBI1. 215 * Note that this must match useronly_clean_ptr. 216 */ 217 env->cp15.tcr_el[1].raw_tcr = 5 | (1ULL << 37); 218 219 /* Enable MTE */ 220 if (cpu_isar_feature(aa64_mte, cpu)) { 221 /* Enable tag access, but leave TCF0 as No Effect (0). */ 222 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 223 /* 224 * Exclude all tags, so that tag 0 is always used. 225 * This corresponds to Linux current->thread.gcr_incl = 0. 226 * 227 * Set RRND, so that helper_irg() will generate a seed later. 228 * Here in cpu_reset(), the crypto subsystem has not yet been 229 * initialized. 230 */ 231 env->cp15.gcr_el1 = 0x1ffff; 232 } 233 #else 234 /* Reset into the highest available EL */ 235 if (arm_feature(env, ARM_FEATURE_EL3)) { 236 env->pstate = PSTATE_MODE_EL3h; 237 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 238 env->pstate = PSTATE_MODE_EL2h; 239 } else { 240 env->pstate = PSTATE_MODE_EL1h; 241 } 242 243 /* Sample rvbar at reset. */ 244 env->cp15.rvbar = cpu->rvbar_prop; 245 env->pc = env->cp15.rvbar; 246 #endif 247 } else { 248 #if defined(CONFIG_USER_ONLY) 249 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 250 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 251 #endif 252 } 253 254 #if defined(CONFIG_USER_ONLY) 255 env->uncached_cpsr = ARM_CPU_MODE_USR; 256 /* For user mode we must enable access to coprocessors */ 257 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 258 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 259 env->cp15.c15_cpar = 3; 260 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 261 env->cp15.c15_cpar = 1; 262 } 263 #else 264 265 /* 266 * If the highest available EL is EL2, AArch32 will start in Hyp 267 * mode; otherwise it starts in SVC. Note that if we start in 268 * AArch64 then these values in the uncached_cpsr will be ignored. 269 */ 270 if (arm_feature(env, ARM_FEATURE_EL2) && 271 !arm_feature(env, ARM_FEATURE_EL3)) { 272 env->uncached_cpsr = ARM_CPU_MODE_HYP; 273 } else { 274 env->uncached_cpsr = ARM_CPU_MODE_SVC; 275 } 276 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 277 278 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 279 * executing as AArch32 then check if highvecs are enabled and 280 * adjust the PC accordingly. 281 */ 282 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 283 env->regs[15] = 0xFFFF0000; 284 } 285 286 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 287 #endif 288 289 if (arm_feature(env, ARM_FEATURE_M)) { 290 #ifndef CONFIG_USER_ONLY 291 uint32_t initial_msp; /* Loaded from 0x0 */ 292 uint32_t initial_pc; /* Loaded from 0x4 */ 293 uint8_t *rom; 294 uint32_t vecbase; 295 #endif 296 297 if (cpu_isar_feature(aa32_lob, cpu)) { 298 /* 299 * LTPSIZE is constant 4 if MVE not implemented, and resets 300 * to an UNKNOWN value if MVE is implemented. We choose to 301 * always reset to 4. 302 */ 303 env->v7m.ltpsize = 4; 304 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 305 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 306 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 307 } 308 309 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 310 env->v7m.secure = true; 311 } else { 312 /* This bit resets to 0 if security is supported, but 1 if 313 * it is not. The bit is not present in v7M, but we set it 314 * here so we can avoid having to make checks on it conditional 315 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 316 */ 317 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 318 /* 319 * Set NSACR to indicate "NS access permitted to everything"; 320 * this avoids having to have all the tests of it being 321 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 322 * v8.1M the guest-visible value of NSACR in a CPU without the 323 * Security Extension is 0xcff. 324 */ 325 env->v7m.nsacr = 0xcff; 326 } 327 328 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 329 * that it resets to 1, so QEMU always does that rather than making 330 * it dependent on CPU model. In v8M it is RES1. 331 */ 332 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 333 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 334 if (arm_feature(env, ARM_FEATURE_V8)) { 335 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 336 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 337 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 338 } 339 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 340 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 341 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 342 } 343 344 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 345 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 346 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 347 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 348 } 349 350 #ifndef CONFIG_USER_ONLY 351 /* Unlike A/R profile, M profile defines the reset LR value */ 352 env->regs[14] = 0xffffffff; 353 354 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 355 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 356 357 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 358 vecbase = env->v7m.vecbase[env->v7m.secure]; 359 rom = rom_ptr_for_as(s->as, vecbase, 8); 360 if (rom) { 361 /* Address zero is covered by ROM which hasn't yet been 362 * copied into physical memory. 363 */ 364 initial_msp = ldl_p(rom); 365 initial_pc = ldl_p(rom + 4); 366 } else { 367 /* Address zero not covered by a ROM blob, or the ROM blob 368 * is in non-modifiable memory and this is a second reset after 369 * it got copied into memory. In the latter case, rom_ptr 370 * will return a NULL pointer and we should use ldl_phys instead. 371 */ 372 initial_msp = ldl_phys(s->as, vecbase); 373 initial_pc = ldl_phys(s->as, vecbase + 4); 374 } 375 376 qemu_log_mask(CPU_LOG_INT, 377 "Loaded reset SP 0x%x PC 0x%x from vector table\n", 378 initial_msp, initial_pc); 379 380 env->regs[13] = initial_msp & 0xFFFFFFFC; 381 env->regs[15] = initial_pc & ~1; 382 env->thumb = initial_pc & 1; 383 #else 384 /* 385 * For user mode we run non-secure and with access to the FPU. 386 * The FPU context is active (ie does not need further setup) 387 * and is owned by non-secure. 388 */ 389 env->v7m.secure = false; 390 env->v7m.nsacr = 0xcff; 391 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 392 env->v7m.fpccr[M_REG_S] &= 393 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 394 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 395 #endif 396 } 397 398 /* M profile requires that reset clears the exclusive monitor; 399 * A profile does not, but clearing it makes more sense than having it 400 * set with an exclusive access on address zero. 401 */ 402 arm_clear_exclusive(env); 403 404 if (arm_feature(env, ARM_FEATURE_PMSA)) { 405 if (cpu->pmsav7_dregion > 0) { 406 if (arm_feature(env, ARM_FEATURE_V8)) { 407 memset(env->pmsav8.rbar[M_REG_NS], 0, 408 sizeof(*env->pmsav8.rbar[M_REG_NS]) 409 * cpu->pmsav7_dregion); 410 memset(env->pmsav8.rlar[M_REG_NS], 0, 411 sizeof(*env->pmsav8.rlar[M_REG_NS]) 412 * cpu->pmsav7_dregion); 413 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 414 memset(env->pmsav8.rbar[M_REG_S], 0, 415 sizeof(*env->pmsav8.rbar[M_REG_S]) 416 * cpu->pmsav7_dregion); 417 memset(env->pmsav8.rlar[M_REG_S], 0, 418 sizeof(*env->pmsav8.rlar[M_REG_S]) 419 * cpu->pmsav7_dregion); 420 } 421 } else if (arm_feature(env, ARM_FEATURE_V7)) { 422 memset(env->pmsav7.drbar, 0, 423 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 424 memset(env->pmsav7.drsr, 0, 425 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 426 memset(env->pmsav7.dracr, 0, 427 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 428 } 429 } 430 env->pmsav7.rnr[M_REG_NS] = 0; 431 env->pmsav7.rnr[M_REG_S] = 0; 432 env->pmsav8.mair0[M_REG_NS] = 0; 433 env->pmsav8.mair0[M_REG_S] = 0; 434 env->pmsav8.mair1[M_REG_NS] = 0; 435 env->pmsav8.mair1[M_REG_S] = 0; 436 } 437 438 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 439 if (cpu->sau_sregion > 0) { 440 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 441 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 442 } 443 env->sau.rnr = 0; 444 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 445 * the Cortex-M33 does. 446 */ 447 env->sau.ctrl = 0; 448 } 449 450 set_flush_to_zero(1, &env->vfp.standard_fp_status); 451 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 452 set_default_nan_mode(1, &env->vfp.standard_fp_status); 453 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); 454 set_float_detect_tininess(float_tininess_before_rounding, 455 &env->vfp.fp_status); 456 set_float_detect_tininess(float_tininess_before_rounding, 457 &env->vfp.standard_fp_status); 458 set_float_detect_tininess(float_tininess_before_rounding, 459 &env->vfp.fp_status_f16); 460 set_float_detect_tininess(float_tininess_before_rounding, 461 &env->vfp.standard_fp_status_f16); 462 #ifndef CONFIG_USER_ONLY 463 if (kvm_enabled()) { 464 kvm_arm_reset_vcpu(cpu); 465 } 466 #endif 467 468 hw_breakpoint_update_all(cpu); 469 hw_watchpoint_update_all(cpu); 470 arm_rebuild_hflags(env); 471 } 472 473 #ifndef CONFIG_USER_ONLY 474 475 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 476 unsigned int target_el, 477 unsigned int cur_el, bool secure, 478 uint64_t hcr_el2) 479 { 480 CPUARMState *env = cs->env_ptr; 481 bool pstate_unmasked; 482 bool unmasked = false; 483 484 /* 485 * Don't take exceptions if they target a lower EL. 486 * This check should catch any exceptions that would not be taken 487 * but left pending. 488 */ 489 if (cur_el > target_el) { 490 return false; 491 } 492 493 switch (excp_idx) { 494 case EXCP_FIQ: 495 pstate_unmasked = !(env->daif & PSTATE_F); 496 break; 497 498 case EXCP_IRQ: 499 pstate_unmasked = !(env->daif & PSTATE_I); 500 break; 501 502 case EXCP_VFIQ: 503 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 504 /* VFIQs are only taken when hypervized. */ 505 return false; 506 } 507 return !(env->daif & PSTATE_F); 508 case EXCP_VIRQ: 509 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 510 /* VIRQs are only taken when hypervized. */ 511 return false; 512 } 513 return !(env->daif & PSTATE_I); 514 default: 515 g_assert_not_reached(); 516 } 517 518 /* 519 * Use the target EL, current execution state and SCR/HCR settings to 520 * determine whether the corresponding CPSR bit is used to mask the 521 * interrupt. 522 */ 523 if ((target_el > cur_el) && (target_el != 1)) { 524 /* Exceptions targeting a higher EL may not be maskable */ 525 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 526 /* 527 * 64-bit masking rules are simple: exceptions to EL3 528 * can't be masked, and exceptions to EL2 can only be 529 * masked from Secure state. The HCR and SCR settings 530 * don't affect the masking logic, only the interrupt routing. 531 */ 532 if (target_el == 3 || !secure || (env->cp15.scr_el3 & SCR_EEL2)) { 533 unmasked = true; 534 } 535 } else { 536 /* 537 * The old 32-bit-only environment has a more complicated 538 * masking setup. HCR and SCR bits not only affect interrupt 539 * routing but also change the behaviour of masking. 540 */ 541 bool hcr, scr; 542 543 switch (excp_idx) { 544 case EXCP_FIQ: 545 /* 546 * If FIQs are routed to EL3 or EL2 then there are cases where 547 * we override the CPSR.F in determining if the exception is 548 * masked or not. If neither of these are set then we fall back 549 * to the CPSR.F setting otherwise we further assess the state 550 * below. 551 */ 552 hcr = hcr_el2 & HCR_FMO; 553 scr = (env->cp15.scr_el3 & SCR_FIQ); 554 555 /* 556 * When EL3 is 32-bit, the SCR.FW bit controls whether the 557 * CPSR.F bit masks FIQ interrupts when taken in non-secure 558 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 559 * when non-secure but only when FIQs are only routed to EL3. 560 */ 561 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 562 break; 563 case EXCP_IRQ: 564 /* 565 * When EL3 execution state is 32-bit, if HCR.IMO is set then 566 * we may override the CPSR.I masking when in non-secure state. 567 * The SCR.IRQ setting has already been taken into consideration 568 * when setting the target EL, so it does not have a further 569 * affect here. 570 */ 571 hcr = hcr_el2 & HCR_IMO; 572 scr = false; 573 break; 574 default: 575 g_assert_not_reached(); 576 } 577 578 if ((scr || hcr) && !secure) { 579 unmasked = true; 580 } 581 } 582 } 583 584 /* 585 * The PSTATE bits only mask the interrupt if we have not overriden the 586 * ability above. 587 */ 588 return unmasked || pstate_unmasked; 589 } 590 591 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 592 { 593 CPUClass *cc = CPU_GET_CLASS(cs); 594 CPUARMState *env = cs->env_ptr; 595 uint32_t cur_el = arm_current_el(env); 596 bool secure = arm_is_secure(env); 597 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 598 uint32_t target_el; 599 uint32_t excp_idx; 600 601 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 602 603 if (interrupt_request & CPU_INTERRUPT_FIQ) { 604 excp_idx = EXCP_FIQ; 605 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 606 if (arm_excp_unmasked(cs, excp_idx, target_el, 607 cur_el, secure, hcr_el2)) { 608 goto found; 609 } 610 } 611 if (interrupt_request & CPU_INTERRUPT_HARD) { 612 excp_idx = EXCP_IRQ; 613 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 614 if (arm_excp_unmasked(cs, excp_idx, target_el, 615 cur_el, secure, hcr_el2)) { 616 goto found; 617 } 618 } 619 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 620 excp_idx = EXCP_VIRQ; 621 target_el = 1; 622 if (arm_excp_unmasked(cs, excp_idx, target_el, 623 cur_el, secure, hcr_el2)) { 624 goto found; 625 } 626 } 627 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 628 excp_idx = EXCP_VFIQ; 629 target_el = 1; 630 if (arm_excp_unmasked(cs, excp_idx, target_el, 631 cur_el, secure, hcr_el2)) { 632 goto found; 633 } 634 } 635 return false; 636 637 found: 638 cs->exception_index = excp_idx; 639 env->exception.target_el = target_el; 640 cc->tcg_ops->do_interrupt(cs); 641 return true; 642 } 643 #endif /* !CONFIG_USER_ONLY */ 644 645 void arm_cpu_update_virq(ARMCPU *cpu) 646 { 647 /* 648 * Update the interrupt level for VIRQ, which is the logical OR of 649 * the HCR_EL2.VI bit and the input line level from the GIC. 650 */ 651 CPUARMState *env = &cpu->env; 652 CPUState *cs = CPU(cpu); 653 654 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 655 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 656 657 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 658 if (new_state) { 659 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 660 } else { 661 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 662 } 663 } 664 } 665 666 void arm_cpu_update_vfiq(ARMCPU *cpu) 667 { 668 /* 669 * Update the interrupt level for VFIQ, which is the logical OR of 670 * the HCR_EL2.VF bit and the input line level from the GIC. 671 */ 672 CPUARMState *env = &cpu->env; 673 CPUState *cs = CPU(cpu); 674 675 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 676 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 677 678 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 679 if (new_state) { 680 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 681 } else { 682 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 683 } 684 } 685 } 686 687 #ifndef CONFIG_USER_ONLY 688 static void arm_cpu_set_irq(void *opaque, int irq, int level) 689 { 690 ARMCPU *cpu = opaque; 691 CPUARMState *env = &cpu->env; 692 CPUState *cs = CPU(cpu); 693 static const int mask[] = { 694 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 695 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 696 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 697 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 698 }; 699 700 if (!arm_feature(env, ARM_FEATURE_EL2) && 701 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { 702 /* 703 * The GIC might tell us about VIRQ and VFIQ state, but if we don't 704 * have EL2 support we don't care. (Unless the guest is doing something 705 * silly this will only be calls saying "level is still 0".) 706 */ 707 return; 708 } 709 710 if (level) { 711 env->irq_line_state |= mask[irq]; 712 } else { 713 env->irq_line_state &= ~mask[irq]; 714 } 715 716 switch (irq) { 717 case ARM_CPU_VIRQ: 718 arm_cpu_update_virq(cpu); 719 break; 720 case ARM_CPU_VFIQ: 721 arm_cpu_update_vfiq(cpu); 722 break; 723 case ARM_CPU_IRQ: 724 case ARM_CPU_FIQ: 725 if (level) { 726 cpu_interrupt(cs, mask[irq]); 727 } else { 728 cpu_reset_interrupt(cs, mask[irq]); 729 } 730 break; 731 default: 732 g_assert_not_reached(); 733 } 734 } 735 736 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 737 { 738 #ifdef CONFIG_KVM 739 ARMCPU *cpu = opaque; 740 CPUARMState *env = &cpu->env; 741 CPUState *cs = CPU(cpu); 742 uint32_t linestate_bit; 743 int irq_id; 744 745 switch (irq) { 746 case ARM_CPU_IRQ: 747 irq_id = KVM_ARM_IRQ_CPU_IRQ; 748 linestate_bit = CPU_INTERRUPT_HARD; 749 break; 750 case ARM_CPU_FIQ: 751 irq_id = KVM_ARM_IRQ_CPU_FIQ; 752 linestate_bit = CPU_INTERRUPT_FIQ; 753 break; 754 default: 755 g_assert_not_reached(); 756 } 757 758 if (level) { 759 env->irq_line_state |= linestate_bit; 760 } else { 761 env->irq_line_state &= ~linestate_bit; 762 } 763 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 764 #endif 765 } 766 767 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 768 { 769 ARMCPU *cpu = ARM_CPU(cs); 770 CPUARMState *env = &cpu->env; 771 772 cpu_synchronize_state(cs); 773 return arm_cpu_data_is_big_endian(env); 774 } 775 776 #endif 777 778 static int 779 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 780 { 781 return print_insn_arm(pc | 1, info); 782 } 783 784 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 785 { 786 ARMCPU *ac = ARM_CPU(cpu); 787 CPUARMState *env = &ac->env; 788 bool sctlr_b; 789 790 if (is_a64(env)) { 791 /* We might not be compiled with the A64 disassembler 792 * because it needs a C++ compiler. Leave print_insn 793 * unset in this case to use the caller default behaviour. 794 */ 795 #if defined(CONFIG_ARM_A64_DIS) 796 info->print_insn = print_insn_arm_a64; 797 #endif 798 info->cap_arch = CS_ARCH_ARM64; 799 info->cap_insn_unit = 4; 800 info->cap_insn_split = 4; 801 } else { 802 int cap_mode; 803 if (env->thumb) { 804 info->print_insn = print_insn_thumb1; 805 info->cap_insn_unit = 2; 806 info->cap_insn_split = 4; 807 cap_mode = CS_MODE_THUMB; 808 } else { 809 info->print_insn = print_insn_arm; 810 info->cap_insn_unit = 4; 811 info->cap_insn_split = 4; 812 cap_mode = CS_MODE_ARM; 813 } 814 if (arm_feature(env, ARM_FEATURE_V8)) { 815 cap_mode |= CS_MODE_V8; 816 } 817 if (arm_feature(env, ARM_FEATURE_M)) { 818 cap_mode |= CS_MODE_MCLASS; 819 } 820 info->cap_arch = CS_ARCH_ARM; 821 info->cap_mode = cap_mode; 822 } 823 824 sctlr_b = arm_sctlr_b(env); 825 if (bswap_code(sctlr_b)) { 826 #if TARGET_BIG_ENDIAN 827 info->endian = BFD_ENDIAN_LITTLE; 828 #else 829 info->endian = BFD_ENDIAN_BIG; 830 #endif 831 } 832 info->flags &= ~INSN_ARM_BE32; 833 #ifndef CONFIG_USER_ONLY 834 if (sctlr_b) { 835 info->flags |= INSN_ARM_BE32; 836 } 837 #endif 838 } 839 840 #ifdef TARGET_AARCH64 841 842 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 843 { 844 ARMCPU *cpu = ARM_CPU(cs); 845 CPUARMState *env = &cpu->env; 846 uint32_t psr = pstate_read(env); 847 int i; 848 int el = arm_current_el(env); 849 const char *ns_status; 850 851 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 852 for (i = 0; i < 32; i++) { 853 if (i == 31) { 854 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 855 } else { 856 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 857 (i + 2) % 3 ? " " : "\n"); 858 } 859 } 860 861 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 862 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 863 } else { 864 ns_status = ""; 865 } 866 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 867 psr, 868 psr & PSTATE_N ? 'N' : '-', 869 psr & PSTATE_Z ? 'Z' : '-', 870 psr & PSTATE_C ? 'C' : '-', 871 psr & PSTATE_V ? 'V' : '-', 872 ns_status, 873 el, 874 psr & PSTATE_SP ? 'h' : 't'); 875 876 if (cpu_isar_feature(aa64_bti, cpu)) { 877 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 878 } 879 if (!(flags & CPU_DUMP_FPU)) { 880 qemu_fprintf(f, "\n"); 881 return; 882 } 883 if (fp_exception_el(env, el) != 0) { 884 qemu_fprintf(f, " FPU disabled\n"); 885 return; 886 } 887 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 888 vfp_get_fpcr(env), vfp_get_fpsr(env)); 889 890 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { 891 int j, zcr_len = sve_zcr_len_for_el(env, el); 892 893 for (i = 0; i <= FFR_PRED_NUM; i++) { 894 bool eol; 895 if (i == FFR_PRED_NUM) { 896 qemu_fprintf(f, "FFR="); 897 /* It's last, so end the line. */ 898 eol = true; 899 } else { 900 qemu_fprintf(f, "P%02d=", i); 901 switch (zcr_len) { 902 case 0: 903 eol = i % 8 == 7; 904 break; 905 case 1: 906 eol = i % 6 == 5; 907 break; 908 case 2: 909 case 3: 910 eol = i % 3 == 2; 911 break; 912 default: 913 /* More than one quadword per predicate. */ 914 eol = true; 915 break; 916 } 917 } 918 for (j = zcr_len / 4; j >= 0; j--) { 919 int digits; 920 if (j * 4 + 4 <= zcr_len + 1) { 921 digits = 16; 922 } else { 923 digits = (zcr_len % 4 + 1) * 4; 924 } 925 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 926 env->vfp.pregs[i].p[j], 927 j ? ":" : eol ? "\n" : " "); 928 } 929 } 930 931 for (i = 0; i < 32; i++) { 932 if (zcr_len == 0) { 933 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 934 i, env->vfp.zregs[i].d[1], 935 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 936 } else if (zcr_len == 1) { 937 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 938 ":%016" PRIx64 ":%016" PRIx64 "\n", 939 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 940 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 941 } else { 942 for (j = zcr_len; j >= 0; j--) { 943 bool odd = (zcr_len - j) % 2 != 0; 944 if (j == zcr_len) { 945 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 946 } else if (!odd) { 947 if (j > 0) { 948 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 949 } else { 950 qemu_fprintf(f, " [%x]=", j); 951 } 952 } 953 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 954 env->vfp.zregs[i].d[j * 2 + 1], 955 env->vfp.zregs[i].d[j * 2], 956 odd || j == 0 ? "\n" : ":"); 957 } 958 } 959 } 960 } else { 961 for (i = 0; i < 32; i++) { 962 uint64_t *q = aa64_vfp_qreg(env, i); 963 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 964 i, q[1], q[0], (i & 1 ? "\n" : " ")); 965 } 966 } 967 } 968 969 #else 970 971 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 972 { 973 g_assert_not_reached(); 974 } 975 976 #endif 977 978 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 979 { 980 ARMCPU *cpu = ARM_CPU(cs); 981 CPUARMState *env = &cpu->env; 982 int i; 983 984 if (is_a64(env)) { 985 aarch64_cpu_dump_state(cs, f, flags); 986 return; 987 } 988 989 for (i = 0; i < 16; i++) { 990 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 991 if ((i % 4) == 3) { 992 qemu_fprintf(f, "\n"); 993 } else { 994 qemu_fprintf(f, " "); 995 } 996 } 997 998 if (arm_feature(env, ARM_FEATURE_M)) { 999 uint32_t xpsr = xpsr_read(env); 1000 const char *mode; 1001 const char *ns_status = ""; 1002 1003 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1004 ns_status = env->v7m.secure ? "S " : "NS "; 1005 } 1006 1007 if (xpsr & XPSR_EXCP) { 1008 mode = "handler"; 1009 } else { 1010 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 1011 mode = "unpriv-thread"; 1012 } else { 1013 mode = "priv-thread"; 1014 } 1015 } 1016 1017 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 1018 xpsr, 1019 xpsr & XPSR_N ? 'N' : '-', 1020 xpsr & XPSR_Z ? 'Z' : '-', 1021 xpsr & XPSR_C ? 'C' : '-', 1022 xpsr & XPSR_V ? 'V' : '-', 1023 xpsr & XPSR_T ? 'T' : 'A', 1024 ns_status, 1025 mode); 1026 } else { 1027 uint32_t psr = cpsr_read(env); 1028 const char *ns_status = ""; 1029 1030 if (arm_feature(env, ARM_FEATURE_EL3) && 1031 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1032 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1033 } 1034 1035 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1036 psr, 1037 psr & CPSR_N ? 'N' : '-', 1038 psr & CPSR_Z ? 'Z' : '-', 1039 psr & CPSR_C ? 'C' : '-', 1040 psr & CPSR_V ? 'V' : '-', 1041 psr & CPSR_T ? 'T' : 'A', 1042 ns_status, 1043 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1044 } 1045 1046 if (flags & CPU_DUMP_FPU) { 1047 int numvfpregs = 0; 1048 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1049 numvfpregs = 32; 1050 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1051 numvfpregs = 16; 1052 } 1053 for (i = 0; i < numvfpregs; i++) { 1054 uint64_t v = *aa32_vfp_dreg(env, i); 1055 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1056 i * 2, (uint32_t)v, 1057 i * 2 + 1, (uint32_t)(v >> 32), 1058 i, v); 1059 } 1060 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1061 if (cpu_isar_feature(aa32_mve, cpu)) { 1062 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1063 } 1064 } 1065 } 1066 1067 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 1068 { 1069 uint32_t Aff1 = idx / clustersz; 1070 uint32_t Aff0 = idx % clustersz; 1071 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1072 } 1073 1074 static void arm_cpu_initfn(Object *obj) 1075 { 1076 ARMCPU *cpu = ARM_CPU(obj); 1077 1078 cpu_set_cpustate_pointers(cpu); 1079 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, 1080 NULL, g_free); 1081 1082 QLIST_INIT(&cpu->pre_el_change_hooks); 1083 QLIST_INIT(&cpu->el_change_hooks); 1084 1085 #ifdef CONFIG_USER_ONLY 1086 # ifdef TARGET_AARCH64 1087 /* 1088 * The linux kernel defaults to 512-bit vectors, when sve is supported. 1089 * See documentation for /proc/sys/abi/sve_default_vector_length, and 1090 * our corresponding sve-default-vector-length cpu property. 1091 */ 1092 cpu->sve_default_vq = 4; 1093 # endif 1094 #else 1095 /* Our inbound IRQ and FIQ lines */ 1096 if (kvm_enabled()) { 1097 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1098 * the same interface as non-KVM CPUs. 1099 */ 1100 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1101 } else { 1102 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1103 } 1104 1105 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1106 ARRAY_SIZE(cpu->gt_timer_outputs)); 1107 1108 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1109 "gicv3-maintenance-interrupt", 1); 1110 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1111 "pmu-interrupt", 1); 1112 #endif 1113 1114 /* DTB consumers generally don't in fact care what the 'compatible' 1115 * string is, so always provide some string and trust that a hypothetical 1116 * picky DTB consumer will also provide a helpful error message. 1117 */ 1118 cpu->dtb_compatible = "qemu,unknown"; 1119 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ 1120 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1121 1122 if (tcg_enabled() || hvf_enabled()) { 1123 /* TCG and HVF implement PSCI 1.1 */ 1124 cpu->psci_version = QEMU_PSCI_VERSION_1_1; 1125 } 1126 } 1127 1128 static Property arm_cpu_gt_cntfrq_property = 1129 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1130 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1131 1132 static Property arm_cpu_reset_cbar_property = 1133 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1134 1135 static Property arm_cpu_reset_hivecs_property = 1136 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1137 1138 #ifndef CONFIG_USER_ONLY 1139 static Property arm_cpu_has_el2_property = 1140 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1141 1142 static Property arm_cpu_has_el3_property = 1143 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1144 #endif 1145 1146 static Property arm_cpu_cfgend_property = 1147 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1148 1149 static Property arm_cpu_has_vfp_property = 1150 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1151 1152 static Property arm_cpu_has_neon_property = 1153 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1154 1155 static Property arm_cpu_has_dsp_property = 1156 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1157 1158 static Property arm_cpu_has_mpu_property = 1159 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1160 1161 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1162 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1163 * the right value for that particular CPU type, and we don't want 1164 * to override that with an incorrect constant value. 1165 */ 1166 static Property arm_cpu_pmsav7_dregion_property = 1167 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1168 pmsav7_dregion, 1169 qdev_prop_uint32, uint32_t); 1170 1171 static bool arm_get_pmu(Object *obj, Error **errp) 1172 { 1173 ARMCPU *cpu = ARM_CPU(obj); 1174 1175 return cpu->has_pmu; 1176 } 1177 1178 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1179 { 1180 ARMCPU *cpu = ARM_CPU(obj); 1181 1182 if (value) { 1183 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1184 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1185 return; 1186 } 1187 set_feature(&cpu->env, ARM_FEATURE_PMU); 1188 } else { 1189 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1190 } 1191 cpu->has_pmu = value; 1192 } 1193 1194 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1195 { 1196 /* 1197 * The exact approach to calculating guest ticks is: 1198 * 1199 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1200 * NANOSECONDS_PER_SECOND); 1201 * 1202 * We don't do that. Rather we intentionally use integer division 1203 * truncation below and in the caller for the conversion of host monotonic 1204 * time to guest ticks to provide the exact inverse for the semantics of 1205 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1206 * it loses precision when representing frequencies where 1207 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1208 * provide an exact inverse leads to scheduling timers with negative 1209 * periods, which in turn leads to sticky behaviour in the guest. 1210 * 1211 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1212 * cannot become zero. 1213 */ 1214 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1215 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1216 } 1217 1218 void arm_cpu_post_init(Object *obj) 1219 { 1220 ARMCPU *cpu = ARM_CPU(obj); 1221 1222 /* M profile implies PMSA. We have to do this here rather than 1223 * in realize with the other feature-implication checks because 1224 * we look at the PMSA bit to see if we should add some properties. 1225 */ 1226 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1227 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1228 } 1229 1230 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1231 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1232 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1233 } 1234 1235 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1236 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1237 } 1238 1239 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1240 object_property_add_uint64_ptr(obj, "rvbar", 1241 &cpu->rvbar_prop, 1242 OBJ_PROP_FLAG_READWRITE); 1243 } 1244 1245 #ifndef CONFIG_USER_ONLY 1246 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1247 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1248 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1249 */ 1250 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1251 1252 object_property_add_link(obj, "secure-memory", 1253 TYPE_MEMORY_REGION, 1254 (Object **)&cpu->secure_memory, 1255 qdev_prop_allow_set_link_before_realize, 1256 OBJ_PROP_LINK_STRONG); 1257 } 1258 1259 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1260 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1261 } 1262 #endif 1263 1264 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1265 cpu->has_pmu = true; 1266 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1267 } 1268 1269 /* 1270 * Allow user to turn off VFP and Neon support, but only for TCG -- 1271 * KVM does not currently allow us to lie to the guest about its 1272 * ID/feature registers, so the guest always sees what the host has. 1273 */ 1274 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 1275 ? cpu_isar_feature(aa64_fp_simd, cpu) 1276 : cpu_isar_feature(aa32_vfp, cpu)) { 1277 cpu->has_vfp = true; 1278 if (!kvm_enabled()) { 1279 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1280 } 1281 } 1282 1283 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1284 cpu->has_neon = true; 1285 if (!kvm_enabled()) { 1286 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1287 } 1288 } 1289 1290 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1291 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1292 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1293 } 1294 1295 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1296 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1297 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1298 qdev_property_add_static(DEVICE(obj), 1299 &arm_cpu_pmsav7_dregion_property); 1300 } 1301 } 1302 1303 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1304 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1305 qdev_prop_allow_set_link_before_realize, 1306 OBJ_PROP_LINK_STRONG); 1307 /* 1308 * M profile: initial value of the Secure VTOR. We can't just use 1309 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1310 * the property to be set after realize. 1311 */ 1312 object_property_add_uint32_ptr(obj, "init-svtor", 1313 &cpu->init_svtor, 1314 OBJ_PROP_FLAG_READWRITE); 1315 } 1316 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1317 /* 1318 * Initial value of the NS VTOR (for cores without the Security 1319 * extension, this is the only VTOR) 1320 */ 1321 object_property_add_uint32_ptr(obj, "init-nsvtor", 1322 &cpu->init_nsvtor, 1323 OBJ_PROP_FLAG_READWRITE); 1324 } 1325 1326 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ 1327 object_property_add_uint32_ptr(obj, "psci-conduit", 1328 &cpu->psci_conduit, 1329 OBJ_PROP_FLAG_READWRITE); 1330 1331 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1332 1333 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1334 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1335 } 1336 1337 if (kvm_enabled()) { 1338 kvm_arm_add_vcpu_properties(obj); 1339 } 1340 1341 #ifndef CONFIG_USER_ONLY 1342 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1343 cpu_isar_feature(aa64_mte, cpu)) { 1344 object_property_add_link(obj, "tag-memory", 1345 TYPE_MEMORY_REGION, 1346 (Object **)&cpu->tag_memory, 1347 qdev_prop_allow_set_link_before_realize, 1348 OBJ_PROP_LINK_STRONG); 1349 1350 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1351 object_property_add_link(obj, "secure-tag-memory", 1352 TYPE_MEMORY_REGION, 1353 (Object **)&cpu->secure_tag_memory, 1354 qdev_prop_allow_set_link_before_realize, 1355 OBJ_PROP_LINK_STRONG); 1356 } 1357 } 1358 #endif 1359 } 1360 1361 static void arm_cpu_finalizefn(Object *obj) 1362 { 1363 ARMCPU *cpu = ARM_CPU(obj); 1364 ARMELChangeHook *hook, *next; 1365 1366 g_hash_table_destroy(cpu->cp_regs); 1367 1368 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1369 QLIST_REMOVE(hook, node); 1370 g_free(hook); 1371 } 1372 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1373 QLIST_REMOVE(hook, node); 1374 g_free(hook); 1375 } 1376 #ifndef CONFIG_USER_ONLY 1377 if (cpu->pmu_timer) { 1378 timer_free(cpu->pmu_timer); 1379 } 1380 #endif 1381 } 1382 1383 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1384 { 1385 Error *local_err = NULL; 1386 1387 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1388 arm_cpu_sve_finalize(cpu, &local_err); 1389 if (local_err != NULL) { 1390 error_propagate(errp, local_err); 1391 return; 1392 } 1393 1394 arm_cpu_pauth_finalize(cpu, &local_err); 1395 if (local_err != NULL) { 1396 error_propagate(errp, local_err); 1397 return; 1398 } 1399 1400 arm_cpu_lpa2_finalize(cpu, &local_err); 1401 if (local_err != NULL) { 1402 error_propagate(errp, local_err); 1403 return; 1404 } 1405 } 1406 1407 if (kvm_enabled()) { 1408 kvm_arm_steal_time_finalize(cpu, &local_err); 1409 if (local_err != NULL) { 1410 error_propagate(errp, local_err); 1411 return; 1412 } 1413 } 1414 } 1415 1416 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1417 { 1418 CPUState *cs = CPU(dev); 1419 ARMCPU *cpu = ARM_CPU(dev); 1420 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1421 CPUARMState *env = &cpu->env; 1422 int pagebits; 1423 Error *local_err = NULL; 1424 bool no_aa32 = false; 1425 1426 /* If we needed to query the host kernel for the CPU features 1427 * then it's possible that might have failed in the initfn, but 1428 * this is the first point where we can report it. 1429 */ 1430 if (cpu->host_cpu_probe_failed) { 1431 if (!kvm_enabled() && !hvf_enabled()) { 1432 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1433 } else { 1434 error_setg(errp, "Failed to retrieve host CPU features"); 1435 } 1436 return; 1437 } 1438 1439 #ifndef CONFIG_USER_ONLY 1440 /* The NVIC and M-profile CPU are two halves of a single piece of 1441 * hardware; trying to use one without the other is a command line 1442 * error and will result in segfaults if not caught here. 1443 */ 1444 if (arm_feature(env, ARM_FEATURE_M)) { 1445 if (!env->nvic) { 1446 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1447 return; 1448 } 1449 } else { 1450 if (env->nvic) { 1451 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1452 return; 1453 } 1454 } 1455 1456 if (kvm_enabled()) { 1457 /* 1458 * Catch all the cases which might cause us to create more than one 1459 * address space for the CPU (otherwise we will assert() later in 1460 * cpu_address_space_init()). 1461 */ 1462 if (arm_feature(env, ARM_FEATURE_M)) { 1463 error_setg(errp, 1464 "Cannot enable KVM when using an M-profile guest CPU"); 1465 return; 1466 } 1467 if (cpu->has_el3) { 1468 error_setg(errp, 1469 "Cannot enable KVM when guest CPU has EL3 enabled"); 1470 return; 1471 } 1472 if (cpu->tag_memory) { 1473 error_setg(errp, 1474 "Cannot enable KVM when guest CPUs has MTE enabled"); 1475 return; 1476 } 1477 } 1478 1479 { 1480 uint64_t scale; 1481 1482 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1483 if (!cpu->gt_cntfrq_hz) { 1484 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1485 cpu->gt_cntfrq_hz); 1486 return; 1487 } 1488 scale = gt_cntfrq_period_ns(cpu); 1489 } else { 1490 scale = GTIMER_SCALE; 1491 } 1492 1493 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1494 arm_gt_ptimer_cb, cpu); 1495 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1496 arm_gt_vtimer_cb, cpu); 1497 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1498 arm_gt_htimer_cb, cpu); 1499 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1500 arm_gt_stimer_cb, cpu); 1501 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1502 arm_gt_hvtimer_cb, cpu); 1503 } 1504 #endif 1505 1506 cpu_exec_realizefn(cs, &local_err); 1507 if (local_err != NULL) { 1508 error_propagate(errp, local_err); 1509 return; 1510 } 1511 1512 arm_cpu_finalize_features(cpu, &local_err); 1513 if (local_err != NULL) { 1514 error_propagate(errp, local_err); 1515 return; 1516 } 1517 1518 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1519 cpu->has_vfp != cpu->has_neon) { 1520 /* 1521 * This is an architectural requirement for AArch64; AArch32 is 1522 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1523 */ 1524 error_setg(errp, 1525 "AArch64 CPUs must have both VFP and Neon or neither"); 1526 return; 1527 } 1528 1529 if (!cpu->has_vfp) { 1530 uint64_t t; 1531 uint32_t u; 1532 1533 t = cpu->isar.id_aa64isar1; 1534 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1535 cpu->isar.id_aa64isar1 = t; 1536 1537 t = cpu->isar.id_aa64pfr0; 1538 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1539 cpu->isar.id_aa64pfr0 = t; 1540 1541 u = cpu->isar.id_isar6; 1542 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1543 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1544 cpu->isar.id_isar6 = u; 1545 1546 u = cpu->isar.mvfr0; 1547 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1548 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1549 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1550 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1551 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1552 if (!arm_feature(env, ARM_FEATURE_M)) { 1553 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1554 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1555 } 1556 cpu->isar.mvfr0 = u; 1557 1558 u = cpu->isar.mvfr1; 1559 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1560 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1561 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1562 if (arm_feature(env, ARM_FEATURE_M)) { 1563 u = FIELD_DP32(u, MVFR1, FP16, 0); 1564 } 1565 cpu->isar.mvfr1 = u; 1566 1567 u = cpu->isar.mvfr2; 1568 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1569 cpu->isar.mvfr2 = u; 1570 } 1571 1572 if (!cpu->has_neon) { 1573 uint64_t t; 1574 uint32_t u; 1575 1576 unset_feature(env, ARM_FEATURE_NEON); 1577 1578 t = cpu->isar.id_aa64isar0; 1579 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); 1580 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); 1581 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); 1582 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); 1583 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); 1584 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); 1585 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1586 cpu->isar.id_aa64isar0 = t; 1587 1588 t = cpu->isar.id_aa64isar1; 1589 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1590 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 1591 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 1592 cpu->isar.id_aa64isar1 = t; 1593 1594 t = cpu->isar.id_aa64pfr0; 1595 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1596 cpu->isar.id_aa64pfr0 = t; 1597 1598 u = cpu->isar.id_isar5; 1599 u = FIELD_DP32(u, ID_ISAR5, AES, 0); 1600 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); 1601 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); 1602 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1603 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1604 cpu->isar.id_isar5 = u; 1605 1606 u = cpu->isar.id_isar6; 1607 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1608 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1609 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1610 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 1611 cpu->isar.id_isar6 = u; 1612 1613 if (!arm_feature(env, ARM_FEATURE_M)) { 1614 u = cpu->isar.mvfr1; 1615 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1616 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1617 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1618 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1619 cpu->isar.mvfr1 = u; 1620 1621 u = cpu->isar.mvfr2; 1622 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1623 cpu->isar.mvfr2 = u; 1624 } 1625 } 1626 1627 if (!cpu->has_neon && !cpu->has_vfp) { 1628 uint64_t t; 1629 uint32_t u; 1630 1631 t = cpu->isar.id_aa64isar0; 1632 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1633 cpu->isar.id_aa64isar0 = t; 1634 1635 t = cpu->isar.id_aa64isar1; 1636 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1637 cpu->isar.id_aa64isar1 = t; 1638 1639 u = cpu->isar.mvfr0; 1640 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1641 cpu->isar.mvfr0 = u; 1642 1643 /* Despite the name, this field covers both VFP and Neon */ 1644 u = cpu->isar.mvfr1; 1645 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1646 cpu->isar.mvfr1 = u; 1647 } 1648 1649 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1650 uint32_t u; 1651 1652 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1653 1654 u = cpu->isar.id_isar1; 1655 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1656 cpu->isar.id_isar1 = u; 1657 1658 u = cpu->isar.id_isar2; 1659 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1660 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1661 cpu->isar.id_isar2 = u; 1662 1663 u = cpu->isar.id_isar3; 1664 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1665 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1666 cpu->isar.id_isar3 = u; 1667 } 1668 1669 /* Some features automatically imply others: */ 1670 if (arm_feature(env, ARM_FEATURE_V8)) { 1671 if (arm_feature(env, ARM_FEATURE_M)) { 1672 set_feature(env, ARM_FEATURE_V7); 1673 } else { 1674 set_feature(env, ARM_FEATURE_V7VE); 1675 } 1676 } 1677 1678 /* 1679 * There exist AArch64 cpus without AArch32 support. When KVM 1680 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1681 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1682 * As a general principle, we also do not make ID register 1683 * consistency checks anywhere unless using TCG, because only 1684 * for TCG would a consistency-check failure be a QEMU bug. 1685 */ 1686 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1687 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1688 } 1689 1690 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1691 /* v7 Virtualization Extensions. In real hardware this implies 1692 * EL2 and also the presence of the Security Extensions. 1693 * For QEMU, for backwards-compatibility we implement some 1694 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1695 * include the various other features that V7VE implies. 1696 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1697 * Security Extensions is ARM_FEATURE_EL3. 1698 */ 1699 assert(!tcg_enabled() || no_aa32 || 1700 cpu_isar_feature(aa32_arm_div, cpu)); 1701 set_feature(env, ARM_FEATURE_LPAE); 1702 set_feature(env, ARM_FEATURE_V7); 1703 } 1704 if (arm_feature(env, ARM_FEATURE_V7)) { 1705 set_feature(env, ARM_FEATURE_VAPA); 1706 set_feature(env, ARM_FEATURE_THUMB2); 1707 set_feature(env, ARM_FEATURE_MPIDR); 1708 if (!arm_feature(env, ARM_FEATURE_M)) { 1709 set_feature(env, ARM_FEATURE_V6K); 1710 } else { 1711 set_feature(env, ARM_FEATURE_V6); 1712 } 1713 1714 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1715 * non-EL3 configs. This is needed by some legacy boards. 1716 */ 1717 set_feature(env, ARM_FEATURE_VBAR); 1718 } 1719 if (arm_feature(env, ARM_FEATURE_V6K)) { 1720 set_feature(env, ARM_FEATURE_V6); 1721 set_feature(env, ARM_FEATURE_MVFR); 1722 } 1723 if (arm_feature(env, ARM_FEATURE_V6)) { 1724 set_feature(env, ARM_FEATURE_V5); 1725 if (!arm_feature(env, ARM_FEATURE_M)) { 1726 assert(!tcg_enabled() || no_aa32 || 1727 cpu_isar_feature(aa32_jazelle, cpu)); 1728 set_feature(env, ARM_FEATURE_AUXCR); 1729 } 1730 } 1731 if (arm_feature(env, ARM_FEATURE_V5)) { 1732 set_feature(env, ARM_FEATURE_V4T); 1733 } 1734 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1735 set_feature(env, ARM_FEATURE_V7MP); 1736 } 1737 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1738 set_feature(env, ARM_FEATURE_CBAR); 1739 } 1740 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1741 !arm_feature(env, ARM_FEATURE_M)) { 1742 set_feature(env, ARM_FEATURE_THUMB_DSP); 1743 } 1744 1745 /* 1746 * We rely on no XScale CPU having VFP so we can use the same bits in the 1747 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1748 */ 1749 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1750 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1751 !arm_feature(env, ARM_FEATURE_XSCALE)); 1752 1753 if (arm_feature(env, ARM_FEATURE_V7) && 1754 !arm_feature(env, ARM_FEATURE_M) && 1755 !arm_feature(env, ARM_FEATURE_PMSA)) { 1756 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1757 * can use 4K pages. 1758 */ 1759 pagebits = 12; 1760 } else { 1761 /* For CPUs which might have tiny 1K pages, or which have an 1762 * MPU and might have small region sizes, stick with 1K pages. 1763 */ 1764 pagebits = 10; 1765 } 1766 if (!set_preferred_target_page_bits(pagebits)) { 1767 /* This can only ever happen for hotplugging a CPU, or if 1768 * the board code incorrectly creates a CPU which it has 1769 * promised via minimum_page_size that it will not. 1770 */ 1771 error_setg(errp, "This CPU requires a smaller page size than the " 1772 "system is using"); 1773 return; 1774 } 1775 1776 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1777 * We don't support setting cluster ID ([16..23]) (known as Aff2 1778 * in later ARM ARM versions), or any of the higher affinity level fields, 1779 * so these bits always RAZ. 1780 */ 1781 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1782 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1783 ARM_DEFAULT_CPUS_PER_CLUSTER); 1784 } 1785 1786 if (cpu->reset_hivecs) { 1787 cpu->reset_sctlr |= (1 << 13); 1788 } 1789 1790 if (cpu->cfgend) { 1791 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1792 cpu->reset_sctlr |= SCTLR_EE; 1793 } else { 1794 cpu->reset_sctlr |= SCTLR_B; 1795 } 1796 } 1797 1798 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 1799 /* If the has_el3 CPU property is disabled then we need to disable the 1800 * feature. 1801 */ 1802 unset_feature(env, ARM_FEATURE_EL3); 1803 1804 /* Disable the security extension feature bits in the processor feature 1805 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 1806 */ 1807 cpu->isar.id_pfr1 &= ~0xf0; 1808 cpu->isar.id_aa64pfr0 &= ~0xf000; 1809 } 1810 1811 if (!cpu->has_el2) { 1812 unset_feature(env, ARM_FEATURE_EL2); 1813 } 1814 1815 if (!cpu->has_pmu) { 1816 unset_feature(env, ARM_FEATURE_PMU); 1817 } 1818 if (arm_feature(env, ARM_FEATURE_PMU)) { 1819 pmu_init(cpu); 1820 1821 if (!kvm_enabled()) { 1822 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1823 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1824 } 1825 1826 #ifndef CONFIG_USER_ONLY 1827 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1828 cpu); 1829 #endif 1830 } else { 1831 cpu->isar.id_aa64dfr0 = 1832 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 1833 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 1834 cpu->pmceid0 = 0; 1835 cpu->pmceid1 = 0; 1836 } 1837 1838 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1839 /* Disable the hypervisor feature bits in the processor feature 1840 * registers if we don't have EL2. These are id_pfr1[15:12] and 1841 * id_aa64pfr0_el1[11:8]. 1842 */ 1843 cpu->isar.id_aa64pfr0 &= ~0xf00; 1844 cpu->isar.id_pfr1 &= ~0xf000; 1845 } 1846 1847 #ifndef CONFIG_USER_ONLY 1848 if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { 1849 /* 1850 * Disable the MTE feature bits if we do not have tag-memory 1851 * provided by the machine. 1852 */ 1853 cpu->isar.id_aa64pfr1 = 1854 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 1855 } 1856 #endif 1857 1858 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1859 * to false or by setting pmsav7-dregion to 0. 1860 */ 1861 if (!cpu->has_mpu) { 1862 cpu->pmsav7_dregion = 0; 1863 } 1864 if (cpu->pmsav7_dregion == 0) { 1865 cpu->has_mpu = false; 1866 } 1867 1868 if (arm_feature(env, ARM_FEATURE_PMSA) && 1869 arm_feature(env, ARM_FEATURE_V7)) { 1870 uint32_t nr = cpu->pmsav7_dregion; 1871 1872 if (nr > 0xff) { 1873 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1874 return; 1875 } 1876 1877 if (nr) { 1878 if (arm_feature(env, ARM_FEATURE_V8)) { 1879 /* PMSAv8 */ 1880 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1881 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1882 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1883 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1884 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1885 } 1886 } else { 1887 env->pmsav7.drbar = g_new0(uint32_t, nr); 1888 env->pmsav7.drsr = g_new0(uint32_t, nr); 1889 env->pmsav7.dracr = g_new0(uint32_t, nr); 1890 } 1891 } 1892 } 1893 1894 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1895 uint32_t nr = cpu->sau_sregion; 1896 1897 if (nr > 0xff) { 1898 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1899 return; 1900 } 1901 1902 if (nr) { 1903 env->sau.rbar = g_new0(uint32_t, nr); 1904 env->sau.rlar = g_new0(uint32_t, nr); 1905 } 1906 } 1907 1908 if (arm_feature(env, ARM_FEATURE_EL3)) { 1909 set_feature(env, ARM_FEATURE_VBAR); 1910 } 1911 1912 register_cp_regs_for_features(cpu); 1913 arm_cpu_register_gdb_regs_for_features(cpu); 1914 1915 init_cpreg_list(cpu); 1916 1917 #ifndef CONFIG_USER_ONLY 1918 MachineState *ms = MACHINE(qdev_get_machine()); 1919 unsigned int smp_cpus = ms->smp.cpus; 1920 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 1921 1922 /* 1923 * We must set cs->num_ases to the final value before 1924 * the first call to cpu_address_space_init. 1925 */ 1926 if (cpu->tag_memory != NULL) { 1927 cs->num_ases = 3 + has_secure; 1928 } else { 1929 cs->num_ases = 1 + has_secure; 1930 } 1931 1932 if (has_secure) { 1933 if (!cpu->secure_memory) { 1934 cpu->secure_memory = cs->memory; 1935 } 1936 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1937 cpu->secure_memory); 1938 } 1939 1940 if (cpu->tag_memory != NULL) { 1941 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 1942 cpu->tag_memory); 1943 if (has_secure) { 1944 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 1945 cpu->secure_tag_memory); 1946 } 1947 } 1948 1949 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1950 1951 /* No core_count specified, default to smp_cpus. */ 1952 if (cpu->core_count == -1) { 1953 cpu->core_count = smp_cpus; 1954 } 1955 #endif 1956 1957 if (tcg_enabled()) { 1958 int dcz_blocklen = 4 << cpu->dcz_blocksize; 1959 1960 /* 1961 * We only support DCZ blocklen that fits on one page. 1962 * 1963 * Architectually this is always true. However TARGET_PAGE_SIZE 1964 * is variable and, for compatibility with -machine virt-2.7, 1965 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 1966 * But even then, while the largest architectural DCZ blocklen 1967 * is 2KiB, no cpu actually uses such a large blocklen. 1968 */ 1969 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 1970 1971 /* 1972 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 1973 * both nibbles of each byte storing tag data may be written at once. 1974 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 1975 */ 1976 if (cpu_isar_feature(aa64_mte, cpu)) { 1977 assert(dcz_blocklen >= 2 * TAG_GRANULE); 1978 } 1979 } 1980 1981 qemu_init_vcpu(cs); 1982 cpu_reset(cs); 1983 1984 acc->parent_realize(dev, errp); 1985 } 1986 1987 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1988 { 1989 ObjectClass *oc; 1990 char *typename; 1991 char **cpuname; 1992 const char *cpunamestr; 1993 1994 cpuname = g_strsplit(cpu_model, ",", 1); 1995 cpunamestr = cpuname[0]; 1996 #ifdef CONFIG_USER_ONLY 1997 /* For backwards compatibility usermode emulation allows "-cpu any", 1998 * which has the same semantics as "-cpu max". 1999 */ 2000 if (!strcmp(cpunamestr, "any")) { 2001 cpunamestr = "max"; 2002 } 2003 #endif 2004 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 2005 oc = object_class_by_name(typename); 2006 g_strfreev(cpuname); 2007 g_free(typename); 2008 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 2009 object_class_is_abstract(oc)) { 2010 return NULL; 2011 } 2012 return oc; 2013 } 2014 2015 static Property arm_cpu_properties[] = { 2016 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2017 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2018 mp_affinity, ARM64_AFFINITY_INVALID), 2019 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2020 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2021 DEFINE_PROP_END_OF_LIST() 2022 }; 2023 2024 static gchar *arm_gdb_arch_name(CPUState *cs) 2025 { 2026 ARMCPU *cpu = ARM_CPU(cs); 2027 CPUARMState *env = &cpu->env; 2028 2029 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2030 return g_strdup("iwmmxt"); 2031 } 2032 return g_strdup("arm"); 2033 } 2034 2035 #ifndef CONFIG_USER_ONLY 2036 #include "hw/core/sysemu-cpu-ops.h" 2037 2038 static const struct SysemuCPUOps arm_sysemu_ops = { 2039 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2040 .asidx_from_attrs = arm_asidx_from_attrs, 2041 .write_elf32_note = arm_cpu_write_elf32_note, 2042 .write_elf64_note = arm_cpu_write_elf64_note, 2043 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2044 .legacy_vmsd = &vmstate_arm_cpu, 2045 }; 2046 #endif 2047 2048 #ifdef CONFIG_TCG 2049 static const struct TCGCPUOps arm_tcg_ops = { 2050 .initialize = arm_translate_init, 2051 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2052 .debug_excp_handler = arm_debug_excp_handler, 2053 2054 #ifdef CONFIG_USER_ONLY 2055 .record_sigsegv = arm_cpu_record_sigsegv, 2056 .record_sigbus = arm_cpu_record_sigbus, 2057 #else 2058 .tlb_fill = arm_cpu_tlb_fill, 2059 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2060 .do_interrupt = arm_cpu_do_interrupt, 2061 .do_transaction_failed = arm_cpu_do_transaction_failed, 2062 .do_unaligned_access = arm_cpu_do_unaligned_access, 2063 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2064 .debug_check_watchpoint = arm_debug_check_watchpoint, 2065 .debug_check_breakpoint = arm_debug_check_breakpoint, 2066 #endif /* !CONFIG_USER_ONLY */ 2067 }; 2068 #endif /* CONFIG_TCG */ 2069 2070 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2071 { 2072 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2073 CPUClass *cc = CPU_CLASS(acc); 2074 DeviceClass *dc = DEVICE_CLASS(oc); 2075 2076 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2077 &acc->parent_realize); 2078 2079 device_class_set_props(dc, arm_cpu_properties); 2080 device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); 2081 2082 cc->class_by_name = arm_cpu_class_by_name; 2083 cc->has_work = arm_cpu_has_work; 2084 cc->dump_state = arm_cpu_dump_state; 2085 cc->set_pc = arm_cpu_set_pc; 2086 cc->gdb_read_register = arm_cpu_gdb_read_register; 2087 cc->gdb_write_register = arm_cpu_gdb_write_register; 2088 #ifndef CONFIG_USER_ONLY 2089 cc->sysemu_ops = &arm_sysemu_ops; 2090 #endif 2091 cc->gdb_num_core_regs = 26; 2092 cc->gdb_core_xml_file = "arm-core.xml"; 2093 cc->gdb_arch_name = arm_gdb_arch_name; 2094 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2095 cc->gdb_stop_before_watchpoint = true; 2096 cc->disas_set_info = arm_disas_set_info; 2097 2098 #ifdef CONFIG_TCG 2099 cc->tcg_ops = &arm_tcg_ops; 2100 #endif /* CONFIG_TCG */ 2101 } 2102 2103 static void arm_cpu_instance_init(Object *obj) 2104 { 2105 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2106 2107 acc->info->initfn(obj); 2108 arm_cpu_post_init(obj); 2109 } 2110 2111 static void cpu_register_class_init(ObjectClass *oc, void *data) 2112 { 2113 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2114 2115 acc->info = data; 2116 } 2117 2118 void arm_cpu_register(const ARMCPUInfo *info) 2119 { 2120 TypeInfo type_info = { 2121 .parent = TYPE_ARM_CPU, 2122 .instance_size = sizeof(ARMCPU), 2123 .instance_align = __alignof__(ARMCPU), 2124 .instance_init = arm_cpu_instance_init, 2125 .class_size = sizeof(ARMCPUClass), 2126 .class_init = info->class_init ?: cpu_register_class_init, 2127 .class_data = (void *)info, 2128 }; 2129 2130 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2131 type_register(&type_info); 2132 g_free((void *)type_info.name); 2133 } 2134 2135 static const TypeInfo arm_cpu_type_info = { 2136 .name = TYPE_ARM_CPU, 2137 .parent = TYPE_CPU, 2138 .instance_size = sizeof(ARMCPU), 2139 .instance_align = __alignof__(ARMCPU), 2140 .instance_init = arm_cpu_initfn, 2141 .instance_finalize = arm_cpu_finalizefn, 2142 .abstract = true, 2143 .class_size = sizeof(ARMCPUClass), 2144 .class_init = arm_cpu_class_init, 2145 }; 2146 2147 static void arm_cpu_register_types(void) 2148 { 2149 type_register_static(&arm_cpu_type_info); 2150 } 2151 2152 type_init(arm_cpu_register_types) 2153