1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/error-report.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "qemu-common.h" 27 #include "exec/exec-all.h" 28 #include "hw/qdev-properties.h" 29 #if !defined(CONFIG_USER_ONLY) 30 #include "hw/loader.h" 31 #endif 32 #include "hw/arm/arm.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/hw_accel.h" 35 #include "kvm_arm.h" 36 37 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 38 { 39 ARMCPU *cpu = ARM_CPU(cs); 40 41 cpu->env.regs[15] = value; 42 } 43 44 static bool arm_cpu_has_work(CPUState *cs) 45 { 46 ARMCPU *cpu = ARM_CPU(cs); 47 48 return (cpu->power_state != PSCI_OFF) 49 && cs->interrupt_request & 50 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 51 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 52 | CPU_INTERRUPT_EXITTB); 53 } 54 55 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 56 void *opaque) 57 { 58 /* We currently only support registering a single hook function */ 59 assert(!cpu->el_change_hook); 60 cpu->el_change_hook = hook; 61 cpu->el_change_hook_opaque = opaque; 62 } 63 64 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 65 { 66 /* Reset a single ARMCPRegInfo register */ 67 ARMCPRegInfo *ri = value; 68 ARMCPU *cpu = opaque; 69 70 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 71 return; 72 } 73 74 if (ri->resetfn) { 75 ri->resetfn(&cpu->env, ri); 76 return; 77 } 78 79 /* A zero offset is never possible as it would be regs[0] 80 * so we use it to indicate that reset is being handled elsewhere. 81 * This is basically only used for fields in non-core coprocessors 82 * (like the pxa2xx ones). 83 */ 84 if (!ri->fieldoffset) { 85 return; 86 } 87 88 if (cpreg_field_is_64bit(ri)) { 89 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 90 } else { 91 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 92 } 93 } 94 95 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 96 { 97 /* Purely an assertion check: we've already done reset once, 98 * so now check that running the reset for the cpreg doesn't 99 * change its value. This traps bugs where two different cpregs 100 * both try to reset the same state field but to different values. 101 */ 102 ARMCPRegInfo *ri = value; 103 ARMCPU *cpu = opaque; 104 uint64_t oldvalue, newvalue; 105 106 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 107 return; 108 } 109 110 oldvalue = read_raw_cp_reg(&cpu->env, ri); 111 cp_reg_reset(key, value, opaque); 112 newvalue = read_raw_cp_reg(&cpu->env, ri); 113 assert(oldvalue == newvalue); 114 } 115 116 /* CPUClass::reset() */ 117 static void arm_cpu_reset(CPUState *s) 118 { 119 ARMCPU *cpu = ARM_CPU(s); 120 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 121 CPUARMState *env = &cpu->env; 122 123 acc->parent_reset(s); 124 125 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 126 127 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 128 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 129 130 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 131 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; 132 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; 133 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; 134 135 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 136 s->halted = cpu->start_powered_off; 137 138 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 139 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 140 } 141 142 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 143 /* 64 bit CPUs always start in 64 bit mode */ 144 env->aarch64 = 1; 145 #if defined(CONFIG_USER_ONLY) 146 env->pstate = PSTATE_MODE_EL0t; 147 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 148 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 149 /* and to the FP/Neon instructions */ 150 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 151 #else 152 /* Reset into the highest available EL */ 153 if (arm_feature(env, ARM_FEATURE_EL3)) { 154 env->pstate = PSTATE_MODE_EL3h; 155 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 156 env->pstate = PSTATE_MODE_EL2h; 157 } else { 158 env->pstate = PSTATE_MODE_EL1h; 159 } 160 env->pc = cpu->rvbar; 161 #endif 162 } else { 163 #if defined(CONFIG_USER_ONLY) 164 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 165 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 166 #endif 167 } 168 169 #if defined(CONFIG_USER_ONLY) 170 env->uncached_cpsr = ARM_CPU_MODE_USR; 171 /* For user mode we must enable access to coprocessors */ 172 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 173 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 174 env->cp15.c15_cpar = 3; 175 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 176 env->cp15.c15_cpar = 1; 177 } 178 #else 179 /* SVC mode with interrupts disabled. */ 180 env->uncached_cpsr = ARM_CPU_MODE_SVC; 181 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 182 183 if (arm_feature(env, ARM_FEATURE_M)) { 184 uint32_t initial_msp; /* Loaded from 0x0 */ 185 uint32_t initial_pc; /* Loaded from 0x4 */ 186 uint8_t *rom; 187 188 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 189 env->v7m.secure = true; 190 } else { 191 /* This bit resets to 0 if security is supported, but 1 if 192 * it is not. The bit is not present in v7M, but we set it 193 * here so we can avoid having to make checks on it conditional 194 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 195 */ 196 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 197 } 198 199 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 200 * that it resets to 1, so QEMU always does that rather than making 201 * it dependent on CPU model. In v8M it is RES1. 202 */ 203 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 204 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 205 if (arm_feature(env, ARM_FEATURE_V8)) { 206 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 207 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 208 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 209 } 210 211 /* Unlike A/R profile, M profile defines the reset LR value */ 212 env->regs[14] = 0xffffffff; 213 214 /* Load the initial SP and PC from the vector table at address 0 */ 215 rom = rom_ptr(0); 216 if (rom) { 217 /* Address zero is covered by ROM which hasn't yet been 218 * copied into physical memory. 219 */ 220 initial_msp = ldl_p(rom); 221 initial_pc = ldl_p(rom + 4); 222 } else { 223 /* Address zero not covered by a ROM blob, or the ROM blob 224 * is in non-modifiable memory and this is a second reset after 225 * it got copied into memory. In the latter case, rom_ptr 226 * will return a NULL pointer and we should use ldl_phys instead. 227 */ 228 initial_msp = ldl_phys(s->as, 0); 229 initial_pc = ldl_phys(s->as, 4); 230 } 231 232 env->regs[13] = initial_msp & 0xFFFFFFFC; 233 env->regs[15] = initial_pc & ~1; 234 env->thumb = initial_pc & 1; 235 } 236 237 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 238 * executing as AArch32 then check if highvecs are enabled and 239 * adjust the PC accordingly. 240 */ 241 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 242 env->regs[15] = 0xFFFF0000; 243 } 244 245 /* M profile requires that reset clears the exclusive monitor; 246 * A profile does not, but clearing it makes more sense than having it 247 * set with an exclusive access on address zero. 248 */ 249 arm_clear_exclusive(env); 250 251 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 252 #endif 253 254 if (arm_feature(env, ARM_FEATURE_PMSA)) { 255 if (cpu->pmsav7_dregion > 0) { 256 if (arm_feature(env, ARM_FEATURE_V8)) { 257 memset(env->pmsav8.rbar[M_REG_NS], 0, 258 sizeof(*env->pmsav8.rbar[M_REG_NS]) 259 * cpu->pmsav7_dregion); 260 memset(env->pmsav8.rlar[M_REG_NS], 0, 261 sizeof(*env->pmsav8.rlar[M_REG_NS]) 262 * cpu->pmsav7_dregion); 263 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 264 memset(env->pmsav8.rbar[M_REG_S], 0, 265 sizeof(*env->pmsav8.rbar[M_REG_S]) 266 * cpu->pmsav7_dregion); 267 memset(env->pmsav8.rlar[M_REG_S], 0, 268 sizeof(*env->pmsav8.rlar[M_REG_S]) 269 * cpu->pmsav7_dregion); 270 } 271 } else if (arm_feature(env, ARM_FEATURE_V7)) { 272 memset(env->pmsav7.drbar, 0, 273 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 274 memset(env->pmsav7.drsr, 0, 275 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 276 memset(env->pmsav7.dracr, 0, 277 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 278 } 279 } 280 env->pmsav7.rnr[M_REG_NS] = 0; 281 env->pmsav7.rnr[M_REG_S] = 0; 282 env->pmsav8.mair0[M_REG_NS] = 0; 283 env->pmsav8.mair0[M_REG_S] = 0; 284 env->pmsav8.mair1[M_REG_NS] = 0; 285 env->pmsav8.mair1[M_REG_S] = 0; 286 } 287 288 set_flush_to_zero(1, &env->vfp.standard_fp_status); 289 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 290 set_default_nan_mode(1, &env->vfp.standard_fp_status); 291 set_float_detect_tininess(float_tininess_before_rounding, 292 &env->vfp.fp_status); 293 set_float_detect_tininess(float_tininess_before_rounding, 294 &env->vfp.standard_fp_status); 295 #ifndef CONFIG_USER_ONLY 296 if (kvm_enabled()) { 297 kvm_arm_reset_vcpu(cpu); 298 } 299 #endif 300 301 hw_breakpoint_update_all(cpu); 302 hw_watchpoint_update_all(cpu); 303 } 304 305 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 306 { 307 CPUClass *cc = CPU_GET_CLASS(cs); 308 CPUARMState *env = cs->env_ptr; 309 uint32_t cur_el = arm_current_el(env); 310 bool secure = arm_is_secure(env); 311 uint32_t target_el; 312 uint32_t excp_idx; 313 bool ret = false; 314 315 if (interrupt_request & CPU_INTERRUPT_FIQ) { 316 excp_idx = EXCP_FIQ; 317 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 318 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 319 cs->exception_index = excp_idx; 320 env->exception.target_el = target_el; 321 cc->do_interrupt(cs); 322 ret = true; 323 } 324 } 325 if (interrupt_request & CPU_INTERRUPT_HARD) { 326 excp_idx = EXCP_IRQ; 327 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 328 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 329 cs->exception_index = excp_idx; 330 env->exception.target_el = target_el; 331 cc->do_interrupt(cs); 332 ret = true; 333 } 334 } 335 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 336 excp_idx = EXCP_VIRQ; 337 target_el = 1; 338 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 339 cs->exception_index = excp_idx; 340 env->exception.target_el = target_el; 341 cc->do_interrupt(cs); 342 ret = true; 343 } 344 } 345 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 346 excp_idx = EXCP_VFIQ; 347 target_el = 1; 348 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 349 cs->exception_index = excp_idx; 350 env->exception.target_el = target_el; 351 cc->do_interrupt(cs); 352 ret = true; 353 } 354 } 355 356 return ret; 357 } 358 359 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 360 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 361 { 362 CPUClass *cc = CPU_GET_CLASS(cs); 363 ARMCPU *cpu = ARM_CPU(cs); 364 CPUARMState *env = &cpu->env; 365 bool ret = false; 366 367 /* ARMv7-M interrupt masking works differently than -A or -R. 368 * There is no FIQ/IRQ distinction. Instead of I and F bits 369 * masking FIQ and IRQ interrupts, an exception is taken only 370 * if it is higher priority than the current execution priority 371 * (which depends on state like BASEPRI, FAULTMASK and the 372 * currently active exception). 373 */ 374 if (interrupt_request & CPU_INTERRUPT_HARD 375 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 376 cs->exception_index = EXCP_IRQ; 377 cc->do_interrupt(cs); 378 ret = true; 379 } 380 return ret; 381 } 382 #endif 383 384 #ifndef CONFIG_USER_ONLY 385 static void arm_cpu_set_irq(void *opaque, int irq, int level) 386 { 387 ARMCPU *cpu = opaque; 388 CPUARMState *env = &cpu->env; 389 CPUState *cs = CPU(cpu); 390 static const int mask[] = { 391 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 392 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 393 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 394 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 395 }; 396 397 switch (irq) { 398 case ARM_CPU_VIRQ: 399 case ARM_CPU_VFIQ: 400 assert(arm_feature(env, ARM_FEATURE_EL2)); 401 /* fall through */ 402 case ARM_CPU_IRQ: 403 case ARM_CPU_FIQ: 404 if (level) { 405 cpu_interrupt(cs, mask[irq]); 406 } else { 407 cpu_reset_interrupt(cs, mask[irq]); 408 } 409 break; 410 default: 411 g_assert_not_reached(); 412 } 413 } 414 415 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 416 { 417 #ifdef CONFIG_KVM 418 ARMCPU *cpu = opaque; 419 CPUState *cs = CPU(cpu); 420 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 421 422 switch (irq) { 423 case ARM_CPU_IRQ: 424 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 425 break; 426 case ARM_CPU_FIQ: 427 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 428 break; 429 default: 430 g_assert_not_reached(); 431 } 432 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 433 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 434 #endif 435 } 436 437 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 438 { 439 ARMCPU *cpu = ARM_CPU(cs); 440 CPUARMState *env = &cpu->env; 441 442 cpu_synchronize_state(cs); 443 return arm_cpu_data_is_big_endian(env); 444 } 445 446 #endif 447 448 static inline void set_feature(CPUARMState *env, int feature) 449 { 450 env->features |= 1ULL << feature; 451 } 452 453 static inline void unset_feature(CPUARMState *env, int feature) 454 { 455 env->features &= ~(1ULL << feature); 456 } 457 458 static int 459 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 460 { 461 return print_insn_arm(pc | 1, info); 462 } 463 464 static int arm_read_memory_func(bfd_vma memaddr, bfd_byte *b, 465 int length, struct disassemble_info *info) 466 { 467 assert(info->read_memory_inner_func); 468 assert((info->flags & INSN_ARM_BE32) == 0 || length == 2 || length == 4); 469 470 if ((info->flags & INSN_ARM_BE32) != 0 && length == 2) { 471 assert(info->endian == BFD_ENDIAN_LITTLE); 472 return info->read_memory_inner_func(memaddr ^ 2, (bfd_byte *)b, 2, 473 info); 474 } else { 475 return info->read_memory_inner_func(memaddr, b, length, info); 476 } 477 } 478 479 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 480 { 481 ARMCPU *ac = ARM_CPU(cpu); 482 CPUARMState *env = &ac->env; 483 484 if (is_a64(env)) { 485 /* We might not be compiled with the A64 disassembler 486 * because it needs a C++ compiler. Leave print_insn 487 * unset in this case to use the caller default behaviour. 488 */ 489 #if defined(CONFIG_ARM_A64_DIS) 490 info->print_insn = print_insn_arm_a64; 491 #endif 492 } else if (env->thumb) { 493 info->print_insn = print_insn_thumb1; 494 } else { 495 info->print_insn = print_insn_arm; 496 } 497 if (bswap_code(arm_sctlr_b(env))) { 498 #ifdef TARGET_WORDS_BIGENDIAN 499 info->endian = BFD_ENDIAN_LITTLE; 500 #else 501 info->endian = BFD_ENDIAN_BIG; 502 #endif 503 } 504 if (info->read_memory_inner_func == NULL) { 505 info->read_memory_inner_func = info->read_memory_func; 506 info->read_memory_func = arm_read_memory_func; 507 } 508 info->flags &= ~INSN_ARM_BE32; 509 if (arm_sctlr_b(env)) { 510 info->flags |= INSN_ARM_BE32; 511 } 512 } 513 514 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 515 { 516 uint32_t Aff1 = idx / clustersz; 517 uint32_t Aff0 = idx % clustersz; 518 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 519 } 520 521 static void arm_cpu_initfn(Object *obj) 522 { 523 CPUState *cs = CPU(obj); 524 ARMCPU *cpu = ARM_CPU(obj); 525 static bool inited; 526 527 cs->env_ptr = &cpu->env; 528 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 529 g_free, g_free); 530 531 #ifndef CONFIG_USER_ONLY 532 /* Our inbound IRQ and FIQ lines */ 533 if (kvm_enabled()) { 534 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 535 * the same interface as non-KVM CPUs. 536 */ 537 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 538 } else { 539 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 540 } 541 542 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 543 arm_gt_ptimer_cb, cpu); 544 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 545 arm_gt_vtimer_cb, cpu); 546 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 547 arm_gt_htimer_cb, cpu); 548 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 549 arm_gt_stimer_cb, cpu); 550 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 551 ARRAY_SIZE(cpu->gt_timer_outputs)); 552 553 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 554 "gicv3-maintenance-interrupt", 1); 555 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 556 "pmu-interrupt", 1); 557 #endif 558 559 /* DTB consumers generally don't in fact care what the 'compatible' 560 * string is, so always provide some string and trust that a hypothetical 561 * picky DTB consumer will also provide a helpful error message. 562 */ 563 cpu->dtb_compatible = "qemu,unknown"; 564 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 565 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 566 567 if (tcg_enabled()) { 568 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 569 if (!inited) { 570 inited = true; 571 arm_translate_init(); 572 } 573 } 574 } 575 576 static Property arm_cpu_reset_cbar_property = 577 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 578 579 static Property arm_cpu_reset_hivecs_property = 580 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 581 582 static Property arm_cpu_rvbar_property = 583 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 584 585 static Property arm_cpu_has_el2_property = 586 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 587 588 static Property arm_cpu_has_el3_property = 589 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 590 591 static Property arm_cpu_cfgend_property = 592 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 593 594 /* use property name "pmu" to match other archs and virt tools */ 595 static Property arm_cpu_has_pmu_property = 596 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 597 598 static Property arm_cpu_has_mpu_property = 599 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 600 601 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 602 * because the CPU initfn will have already set cpu->pmsav7_dregion to 603 * the right value for that particular CPU type, and we don't want 604 * to override that with an incorrect constant value. 605 */ 606 static Property arm_cpu_pmsav7_dregion_property = 607 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 608 pmsav7_dregion, 609 qdev_prop_uint32, uint32_t); 610 611 static void arm_cpu_post_init(Object *obj) 612 { 613 ARMCPU *cpu = ARM_CPU(obj); 614 615 /* M profile implies PMSA. We have to do this here rather than 616 * in realize with the other feature-implication checks because 617 * we look at the PMSA bit to see if we should add some properties. 618 */ 619 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 620 set_feature(&cpu->env, ARM_FEATURE_PMSA); 621 } 622 623 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 624 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 625 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 626 &error_abort); 627 } 628 629 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 630 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 631 &error_abort); 632 } 633 634 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 635 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 636 &error_abort); 637 } 638 639 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 640 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 641 * prevent "has_el3" from existing on CPUs which cannot support EL3. 642 */ 643 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 644 &error_abort); 645 646 #ifndef CONFIG_USER_ONLY 647 object_property_add_link(obj, "secure-memory", 648 TYPE_MEMORY_REGION, 649 (Object **)&cpu->secure_memory, 650 qdev_prop_allow_set_link_before_realize, 651 OBJ_PROP_LINK_UNREF_ON_RELEASE, 652 &error_abort); 653 #endif 654 } 655 656 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 657 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 658 &error_abort); 659 } 660 661 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 662 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 663 &error_abort); 664 } 665 666 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 667 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 668 &error_abort); 669 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 670 qdev_property_add_static(DEVICE(obj), 671 &arm_cpu_pmsav7_dregion_property, 672 &error_abort); 673 } 674 } 675 676 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 677 &error_abort); 678 } 679 680 static void arm_cpu_finalizefn(Object *obj) 681 { 682 ARMCPU *cpu = ARM_CPU(obj); 683 g_hash_table_destroy(cpu->cp_regs); 684 } 685 686 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 687 { 688 CPUState *cs = CPU(dev); 689 ARMCPU *cpu = ARM_CPU(dev); 690 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 691 CPUARMState *env = &cpu->env; 692 int pagebits; 693 Error *local_err = NULL; 694 695 cpu_exec_realizefn(cs, &local_err); 696 if (local_err != NULL) { 697 error_propagate(errp, local_err); 698 return; 699 } 700 701 /* Some features automatically imply others: */ 702 if (arm_feature(env, ARM_FEATURE_V8)) { 703 set_feature(env, ARM_FEATURE_V7); 704 set_feature(env, ARM_FEATURE_ARM_DIV); 705 set_feature(env, ARM_FEATURE_LPAE); 706 } 707 if (arm_feature(env, ARM_FEATURE_V7)) { 708 set_feature(env, ARM_FEATURE_VAPA); 709 set_feature(env, ARM_FEATURE_THUMB2); 710 set_feature(env, ARM_FEATURE_MPIDR); 711 if (!arm_feature(env, ARM_FEATURE_M)) { 712 set_feature(env, ARM_FEATURE_V6K); 713 } else { 714 set_feature(env, ARM_FEATURE_V6); 715 } 716 717 /* Always define VBAR for V7 CPUs even if it doesn't exist in 718 * non-EL3 configs. This is needed by some legacy boards. 719 */ 720 set_feature(env, ARM_FEATURE_VBAR); 721 } 722 if (arm_feature(env, ARM_FEATURE_V6K)) { 723 set_feature(env, ARM_FEATURE_V6); 724 set_feature(env, ARM_FEATURE_MVFR); 725 } 726 if (arm_feature(env, ARM_FEATURE_V6)) { 727 set_feature(env, ARM_FEATURE_V5); 728 set_feature(env, ARM_FEATURE_JAZELLE); 729 if (!arm_feature(env, ARM_FEATURE_M)) { 730 set_feature(env, ARM_FEATURE_AUXCR); 731 } 732 } 733 if (arm_feature(env, ARM_FEATURE_V5)) { 734 set_feature(env, ARM_FEATURE_V4T); 735 } 736 if (arm_feature(env, ARM_FEATURE_M)) { 737 set_feature(env, ARM_FEATURE_THUMB_DIV); 738 } 739 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { 740 set_feature(env, ARM_FEATURE_THUMB_DIV); 741 } 742 if (arm_feature(env, ARM_FEATURE_VFP4)) { 743 set_feature(env, ARM_FEATURE_VFP3); 744 set_feature(env, ARM_FEATURE_VFP_FP16); 745 } 746 if (arm_feature(env, ARM_FEATURE_VFP3)) { 747 set_feature(env, ARM_FEATURE_VFP); 748 } 749 if (arm_feature(env, ARM_FEATURE_LPAE)) { 750 set_feature(env, ARM_FEATURE_V7MP); 751 set_feature(env, ARM_FEATURE_PXN); 752 } 753 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 754 set_feature(env, ARM_FEATURE_CBAR); 755 } 756 if (arm_feature(env, ARM_FEATURE_THUMB2) && 757 !arm_feature(env, ARM_FEATURE_M)) { 758 set_feature(env, ARM_FEATURE_THUMB_DSP); 759 } 760 761 if (arm_feature(env, ARM_FEATURE_V7) && 762 !arm_feature(env, ARM_FEATURE_M) && 763 !arm_feature(env, ARM_FEATURE_PMSA)) { 764 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 765 * can use 4K pages. 766 */ 767 pagebits = 12; 768 } else { 769 /* For CPUs which might have tiny 1K pages, or which have an 770 * MPU and might have small region sizes, stick with 1K pages. 771 */ 772 pagebits = 10; 773 } 774 if (!set_preferred_target_page_bits(pagebits)) { 775 /* This can only ever happen for hotplugging a CPU, or if 776 * the board code incorrectly creates a CPU which it has 777 * promised via minimum_page_size that it will not. 778 */ 779 error_setg(errp, "This CPU requires a smaller page size than the " 780 "system is using"); 781 return; 782 } 783 784 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 785 * We don't support setting cluster ID ([16..23]) (known as Aff2 786 * in later ARM ARM versions), or any of the higher affinity level fields, 787 * so these bits always RAZ. 788 */ 789 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 790 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 791 ARM_DEFAULT_CPUS_PER_CLUSTER); 792 } 793 794 if (cpu->reset_hivecs) { 795 cpu->reset_sctlr |= (1 << 13); 796 } 797 798 if (cpu->cfgend) { 799 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 800 cpu->reset_sctlr |= SCTLR_EE; 801 } else { 802 cpu->reset_sctlr |= SCTLR_B; 803 } 804 } 805 806 if (!cpu->has_el3) { 807 /* If the has_el3 CPU property is disabled then we need to disable the 808 * feature. 809 */ 810 unset_feature(env, ARM_FEATURE_EL3); 811 812 /* Disable the security extension feature bits in the processor feature 813 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 814 */ 815 cpu->id_pfr1 &= ~0xf0; 816 cpu->id_aa64pfr0 &= ~0xf000; 817 } 818 819 if (!cpu->has_el2) { 820 unset_feature(env, ARM_FEATURE_EL2); 821 } 822 823 if (!cpu->has_pmu) { 824 unset_feature(env, ARM_FEATURE_PMU); 825 cpu->id_aa64dfr0 &= ~0xf00; 826 } 827 828 if (!arm_feature(env, ARM_FEATURE_EL2)) { 829 /* Disable the hypervisor feature bits in the processor feature 830 * registers if we don't have EL2. These are id_pfr1[15:12] and 831 * id_aa64pfr0_el1[11:8]. 832 */ 833 cpu->id_aa64pfr0 &= ~0xf00; 834 cpu->id_pfr1 &= ~0xf000; 835 } 836 837 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 838 * to false or by setting pmsav7-dregion to 0. 839 */ 840 if (!cpu->has_mpu) { 841 cpu->pmsav7_dregion = 0; 842 } 843 if (cpu->pmsav7_dregion == 0) { 844 cpu->has_mpu = false; 845 } 846 847 if (arm_feature(env, ARM_FEATURE_PMSA) && 848 arm_feature(env, ARM_FEATURE_V7)) { 849 uint32_t nr = cpu->pmsav7_dregion; 850 851 if (nr > 0xff) { 852 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 853 return; 854 } 855 856 if (nr) { 857 if (arm_feature(env, ARM_FEATURE_V8)) { 858 /* PMSAv8 */ 859 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 860 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 861 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 862 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 863 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 864 } 865 } else { 866 env->pmsav7.drbar = g_new0(uint32_t, nr); 867 env->pmsav7.drsr = g_new0(uint32_t, nr); 868 env->pmsav7.dracr = g_new0(uint32_t, nr); 869 } 870 } 871 } 872 873 if (arm_feature(env, ARM_FEATURE_EL3)) { 874 set_feature(env, ARM_FEATURE_VBAR); 875 } 876 877 register_cp_regs_for_features(cpu); 878 arm_cpu_register_gdb_regs_for_features(cpu); 879 880 init_cpreg_list(cpu); 881 882 #ifndef CONFIG_USER_ONLY 883 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 884 AddressSpace *as; 885 886 cs->num_ases = 2; 887 888 if (!cpu->secure_memory) { 889 cpu->secure_memory = cs->memory; 890 } 891 as = address_space_init_shareable(cpu->secure_memory, 892 "cpu-secure-memory"); 893 cpu_address_space_init(cs, as, ARMASIdx_S); 894 } else { 895 cs->num_ases = 1; 896 } 897 898 cpu_address_space_init(cs, 899 address_space_init_shareable(cs->memory, 900 "cpu-memory"), 901 ARMASIdx_NS); 902 #endif 903 904 qemu_init_vcpu(cs); 905 cpu_reset(cs); 906 907 acc->parent_realize(dev, errp); 908 } 909 910 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 911 { 912 ObjectClass *oc; 913 char *typename; 914 char **cpuname; 915 916 if (!cpu_model) { 917 return NULL; 918 } 919 920 cpuname = g_strsplit(cpu_model, ",", 1); 921 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpuname[0]); 922 oc = object_class_by_name(typename); 923 g_strfreev(cpuname); 924 g_free(typename); 925 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 926 object_class_is_abstract(oc)) { 927 return NULL; 928 } 929 return oc; 930 } 931 932 /* CPU models. These are not needed for the AArch64 linux-user build. */ 933 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 934 935 static void arm926_initfn(Object *obj) 936 { 937 ARMCPU *cpu = ARM_CPU(obj); 938 939 cpu->dtb_compatible = "arm,arm926"; 940 set_feature(&cpu->env, ARM_FEATURE_V5); 941 set_feature(&cpu->env, ARM_FEATURE_VFP); 942 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 943 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 944 set_feature(&cpu->env, ARM_FEATURE_JAZELLE); 945 cpu->midr = 0x41069265; 946 cpu->reset_fpsid = 0x41011090; 947 cpu->ctr = 0x1dd20d2; 948 cpu->reset_sctlr = 0x00090078; 949 } 950 951 static void arm946_initfn(Object *obj) 952 { 953 ARMCPU *cpu = ARM_CPU(obj); 954 955 cpu->dtb_compatible = "arm,arm946"; 956 set_feature(&cpu->env, ARM_FEATURE_V5); 957 set_feature(&cpu->env, ARM_FEATURE_PMSA); 958 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 959 cpu->midr = 0x41059461; 960 cpu->ctr = 0x0f004006; 961 cpu->reset_sctlr = 0x00000078; 962 } 963 964 static void arm1026_initfn(Object *obj) 965 { 966 ARMCPU *cpu = ARM_CPU(obj); 967 968 cpu->dtb_compatible = "arm,arm1026"; 969 set_feature(&cpu->env, ARM_FEATURE_V5); 970 set_feature(&cpu->env, ARM_FEATURE_VFP); 971 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 972 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 973 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 974 set_feature(&cpu->env, ARM_FEATURE_JAZELLE); 975 cpu->midr = 0x4106a262; 976 cpu->reset_fpsid = 0x410110a0; 977 cpu->ctr = 0x1dd20d2; 978 cpu->reset_sctlr = 0x00090078; 979 cpu->reset_auxcr = 1; 980 { 981 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 982 ARMCPRegInfo ifar = { 983 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 984 .access = PL1_RW, 985 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 986 .resetvalue = 0 987 }; 988 define_one_arm_cp_reg(cpu, &ifar); 989 } 990 } 991 992 static void arm1136_r2_initfn(Object *obj) 993 { 994 ARMCPU *cpu = ARM_CPU(obj); 995 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 996 * older core than plain "arm1136". In particular this does not 997 * have the v6K features. 998 * These ID register values are correct for 1136 but may be wrong 999 * for 1136_r2 (in particular r0p2 does not actually implement most 1000 * of the ID registers). 1001 */ 1002 1003 cpu->dtb_compatible = "arm,arm1136"; 1004 set_feature(&cpu->env, ARM_FEATURE_V6); 1005 set_feature(&cpu->env, ARM_FEATURE_VFP); 1006 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1007 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1008 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1009 cpu->midr = 0x4107b362; 1010 cpu->reset_fpsid = 0x410120b4; 1011 cpu->mvfr0 = 0x11111111; 1012 cpu->mvfr1 = 0x00000000; 1013 cpu->ctr = 0x1dd20d2; 1014 cpu->reset_sctlr = 0x00050078; 1015 cpu->id_pfr0 = 0x111; 1016 cpu->id_pfr1 = 0x1; 1017 cpu->id_dfr0 = 0x2; 1018 cpu->id_afr0 = 0x3; 1019 cpu->id_mmfr0 = 0x01130003; 1020 cpu->id_mmfr1 = 0x10030302; 1021 cpu->id_mmfr2 = 0x01222110; 1022 cpu->id_isar0 = 0x00140011; 1023 cpu->id_isar1 = 0x12002111; 1024 cpu->id_isar2 = 0x11231111; 1025 cpu->id_isar3 = 0x01102131; 1026 cpu->id_isar4 = 0x141; 1027 cpu->reset_auxcr = 7; 1028 } 1029 1030 static void arm1136_initfn(Object *obj) 1031 { 1032 ARMCPU *cpu = ARM_CPU(obj); 1033 1034 cpu->dtb_compatible = "arm,arm1136"; 1035 set_feature(&cpu->env, ARM_FEATURE_V6K); 1036 set_feature(&cpu->env, ARM_FEATURE_V6); 1037 set_feature(&cpu->env, ARM_FEATURE_VFP); 1038 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1039 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1040 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1041 cpu->midr = 0x4117b363; 1042 cpu->reset_fpsid = 0x410120b4; 1043 cpu->mvfr0 = 0x11111111; 1044 cpu->mvfr1 = 0x00000000; 1045 cpu->ctr = 0x1dd20d2; 1046 cpu->reset_sctlr = 0x00050078; 1047 cpu->id_pfr0 = 0x111; 1048 cpu->id_pfr1 = 0x1; 1049 cpu->id_dfr0 = 0x2; 1050 cpu->id_afr0 = 0x3; 1051 cpu->id_mmfr0 = 0x01130003; 1052 cpu->id_mmfr1 = 0x10030302; 1053 cpu->id_mmfr2 = 0x01222110; 1054 cpu->id_isar0 = 0x00140011; 1055 cpu->id_isar1 = 0x12002111; 1056 cpu->id_isar2 = 0x11231111; 1057 cpu->id_isar3 = 0x01102131; 1058 cpu->id_isar4 = 0x141; 1059 cpu->reset_auxcr = 7; 1060 } 1061 1062 static void arm1176_initfn(Object *obj) 1063 { 1064 ARMCPU *cpu = ARM_CPU(obj); 1065 1066 cpu->dtb_compatible = "arm,arm1176"; 1067 set_feature(&cpu->env, ARM_FEATURE_V6K); 1068 set_feature(&cpu->env, ARM_FEATURE_VFP); 1069 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1070 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1071 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1072 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1073 set_feature(&cpu->env, ARM_FEATURE_EL3); 1074 cpu->midr = 0x410fb767; 1075 cpu->reset_fpsid = 0x410120b5; 1076 cpu->mvfr0 = 0x11111111; 1077 cpu->mvfr1 = 0x00000000; 1078 cpu->ctr = 0x1dd20d2; 1079 cpu->reset_sctlr = 0x00050078; 1080 cpu->id_pfr0 = 0x111; 1081 cpu->id_pfr1 = 0x11; 1082 cpu->id_dfr0 = 0x33; 1083 cpu->id_afr0 = 0; 1084 cpu->id_mmfr0 = 0x01130003; 1085 cpu->id_mmfr1 = 0x10030302; 1086 cpu->id_mmfr2 = 0x01222100; 1087 cpu->id_isar0 = 0x0140011; 1088 cpu->id_isar1 = 0x12002111; 1089 cpu->id_isar2 = 0x11231121; 1090 cpu->id_isar3 = 0x01102131; 1091 cpu->id_isar4 = 0x01141; 1092 cpu->reset_auxcr = 7; 1093 } 1094 1095 static void arm11mpcore_initfn(Object *obj) 1096 { 1097 ARMCPU *cpu = ARM_CPU(obj); 1098 1099 cpu->dtb_compatible = "arm,arm11mpcore"; 1100 set_feature(&cpu->env, ARM_FEATURE_V6K); 1101 set_feature(&cpu->env, ARM_FEATURE_VFP); 1102 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1103 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1104 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1105 cpu->midr = 0x410fb022; 1106 cpu->reset_fpsid = 0x410120b4; 1107 cpu->mvfr0 = 0x11111111; 1108 cpu->mvfr1 = 0x00000000; 1109 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1110 cpu->id_pfr0 = 0x111; 1111 cpu->id_pfr1 = 0x1; 1112 cpu->id_dfr0 = 0; 1113 cpu->id_afr0 = 0x2; 1114 cpu->id_mmfr0 = 0x01100103; 1115 cpu->id_mmfr1 = 0x10020302; 1116 cpu->id_mmfr2 = 0x01222000; 1117 cpu->id_isar0 = 0x00100011; 1118 cpu->id_isar1 = 0x12002111; 1119 cpu->id_isar2 = 0x11221011; 1120 cpu->id_isar3 = 0x01102131; 1121 cpu->id_isar4 = 0x141; 1122 cpu->reset_auxcr = 1; 1123 } 1124 1125 static void cortex_m3_initfn(Object *obj) 1126 { 1127 ARMCPU *cpu = ARM_CPU(obj); 1128 set_feature(&cpu->env, ARM_FEATURE_V7); 1129 set_feature(&cpu->env, ARM_FEATURE_M); 1130 cpu->midr = 0x410fc231; 1131 cpu->pmsav7_dregion = 8; 1132 } 1133 1134 static void cortex_m4_initfn(Object *obj) 1135 { 1136 ARMCPU *cpu = ARM_CPU(obj); 1137 1138 set_feature(&cpu->env, ARM_FEATURE_V7); 1139 set_feature(&cpu->env, ARM_FEATURE_M); 1140 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1141 cpu->midr = 0x410fc240; /* r0p0 */ 1142 cpu->pmsav7_dregion = 8; 1143 } 1144 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1145 { 1146 CPUClass *cc = CPU_CLASS(oc); 1147 1148 #ifndef CONFIG_USER_ONLY 1149 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1150 #endif 1151 1152 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1153 } 1154 1155 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1156 /* Dummy the TCM region regs for the moment */ 1157 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1158 .access = PL1_RW, .type = ARM_CP_CONST }, 1159 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1160 .access = PL1_RW, .type = ARM_CP_CONST }, 1161 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 1162 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 1163 REGINFO_SENTINEL 1164 }; 1165 1166 static void cortex_r5_initfn(Object *obj) 1167 { 1168 ARMCPU *cpu = ARM_CPU(obj); 1169 1170 set_feature(&cpu->env, ARM_FEATURE_V7); 1171 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); 1172 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1173 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1174 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1175 cpu->midr = 0x411fc153; /* r1p3 */ 1176 cpu->id_pfr0 = 0x0131; 1177 cpu->id_pfr1 = 0x001; 1178 cpu->id_dfr0 = 0x010400; 1179 cpu->id_afr0 = 0x0; 1180 cpu->id_mmfr0 = 0x0210030; 1181 cpu->id_mmfr1 = 0x00000000; 1182 cpu->id_mmfr2 = 0x01200000; 1183 cpu->id_mmfr3 = 0x0211; 1184 cpu->id_isar0 = 0x2101111; 1185 cpu->id_isar1 = 0x13112111; 1186 cpu->id_isar2 = 0x21232141; 1187 cpu->id_isar3 = 0x01112131; 1188 cpu->id_isar4 = 0x0010142; 1189 cpu->id_isar5 = 0x0; 1190 cpu->mp_is_up = true; 1191 cpu->pmsav7_dregion = 16; 1192 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1193 } 1194 1195 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1196 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1197 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1198 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1199 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1200 REGINFO_SENTINEL 1201 }; 1202 1203 static void cortex_a8_initfn(Object *obj) 1204 { 1205 ARMCPU *cpu = ARM_CPU(obj); 1206 1207 cpu->dtb_compatible = "arm,cortex-a8"; 1208 set_feature(&cpu->env, ARM_FEATURE_V7); 1209 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1210 set_feature(&cpu->env, ARM_FEATURE_NEON); 1211 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1212 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1213 set_feature(&cpu->env, ARM_FEATURE_EL3); 1214 cpu->midr = 0x410fc080; 1215 cpu->reset_fpsid = 0x410330c0; 1216 cpu->mvfr0 = 0x11110222; 1217 cpu->mvfr1 = 0x00011111; 1218 cpu->ctr = 0x82048004; 1219 cpu->reset_sctlr = 0x00c50078; 1220 cpu->id_pfr0 = 0x1031; 1221 cpu->id_pfr1 = 0x11; 1222 cpu->id_dfr0 = 0x400; 1223 cpu->id_afr0 = 0; 1224 cpu->id_mmfr0 = 0x31100003; 1225 cpu->id_mmfr1 = 0x20000000; 1226 cpu->id_mmfr2 = 0x01202000; 1227 cpu->id_mmfr3 = 0x11; 1228 cpu->id_isar0 = 0x00101111; 1229 cpu->id_isar1 = 0x12112111; 1230 cpu->id_isar2 = 0x21232031; 1231 cpu->id_isar3 = 0x11112131; 1232 cpu->id_isar4 = 0x00111142; 1233 cpu->dbgdidr = 0x15141000; 1234 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1235 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1236 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1237 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1238 cpu->reset_auxcr = 2; 1239 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1240 } 1241 1242 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1243 /* power_control should be set to maximum latency. Again, 1244 * default to 0 and set by private hook 1245 */ 1246 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1247 .access = PL1_RW, .resetvalue = 0, 1248 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1249 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1250 .access = PL1_RW, .resetvalue = 0, 1251 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1252 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1253 .access = PL1_RW, .resetvalue = 0, 1254 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1255 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1256 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1257 /* TLB lockdown control */ 1258 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1259 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1260 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1261 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1262 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1263 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1264 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1265 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1266 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1267 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1268 REGINFO_SENTINEL 1269 }; 1270 1271 static void cortex_a9_initfn(Object *obj) 1272 { 1273 ARMCPU *cpu = ARM_CPU(obj); 1274 1275 cpu->dtb_compatible = "arm,cortex-a9"; 1276 set_feature(&cpu->env, ARM_FEATURE_V7); 1277 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1278 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); 1279 set_feature(&cpu->env, ARM_FEATURE_NEON); 1280 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1281 set_feature(&cpu->env, ARM_FEATURE_EL3); 1282 /* Note that A9 supports the MP extensions even for 1283 * A9UP and single-core A9MP (which are both different 1284 * and valid configurations; we don't model A9UP). 1285 */ 1286 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1287 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1288 cpu->midr = 0x410fc090; 1289 cpu->reset_fpsid = 0x41033090; 1290 cpu->mvfr0 = 0x11110222; 1291 cpu->mvfr1 = 0x01111111; 1292 cpu->ctr = 0x80038003; 1293 cpu->reset_sctlr = 0x00c50078; 1294 cpu->id_pfr0 = 0x1031; 1295 cpu->id_pfr1 = 0x11; 1296 cpu->id_dfr0 = 0x000; 1297 cpu->id_afr0 = 0; 1298 cpu->id_mmfr0 = 0x00100103; 1299 cpu->id_mmfr1 = 0x20000000; 1300 cpu->id_mmfr2 = 0x01230000; 1301 cpu->id_mmfr3 = 0x00002111; 1302 cpu->id_isar0 = 0x00101111; 1303 cpu->id_isar1 = 0x13112111; 1304 cpu->id_isar2 = 0x21232041; 1305 cpu->id_isar3 = 0x11112131; 1306 cpu->id_isar4 = 0x00111142; 1307 cpu->dbgdidr = 0x35141000; 1308 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1309 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1310 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1311 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1312 } 1313 1314 #ifndef CONFIG_USER_ONLY 1315 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1316 { 1317 /* Linux wants the number of processors from here. 1318 * Might as well set the interrupt-controller bit too. 1319 */ 1320 return ((smp_cpus - 1) << 24) | (1 << 23); 1321 } 1322 #endif 1323 1324 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1325 #ifndef CONFIG_USER_ONLY 1326 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1327 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1328 .writefn = arm_cp_write_ignore, }, 1329 #endif 1330 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1331 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1332 REGINFO_SENTINEL 1333 }; 1334 1335 static void cortex_a7_initfn(Object *obj) 1336 { 1337 ARMCPU *cpu = ARM_CPU(obj); 1338 1339 cpu->dtb_compatible = "arm,cortex-a7"; 1340 set_feature(&cpu->env, ARM_FEATURE_V7); 1341 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1342 set_feature(&cpu->env, ARM_FEATURE_NEON); 1343 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1344 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1345 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1346 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1347 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1348 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1349 set_feature(&cpu->env, ARM_FEATURE_EL3); 1350 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1351 cpu->midr = 0x410fc075; 1352 cpu->reset_fpsid = 0x41023075; 1353 cpu->mvfr0 = 0x10110222; 1354 cpu->mvfr1 = 0x11111111; 1355 cpu->ctr = 0x84448003; 1356 cpu->reset_sctlr = 0x00c50078; 1357 cpu->id_pfr0 = 0x00001131; 1358 cpu->id_pfr1 = 0x00011011; 1359 cpu->id_dfr0 = 0x02010555; 1360 cpu->pmceid0 = 0x00000000; 1361 cpu->pmceid1 = 0x00000000; 1362 cpu->id_afr0 = 0x00000000; 1363 cpu->id_mmfr0 = 0x10101105; 1364 cpu->id_mmfr1 = 0x40000000; 1365 cpu->id_mmfr2 = 0x01240000; 1366 cpu->id_mmfr3 = 0x02102211; 1367 cpu->id_isar0 = 0x01101110; 1368 cpu->id_isar1 = 0x13112111; 1369 cpu->id_isar2 = 0x21232041; 1370 cpu->id_isar3 = 0x11112131; 1371 cpu->id_isar4 = 0x10011142; 1372 cpu->dbgdidr = 0x3515f005; 1373 cpu->clidr = 0x0a200023; 1374 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1375 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1376 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1377 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1378 } 1379 1380 static void cortex_a15_initfn(Object *obj) 1381 { 1382 ARMCPU *cpu = ARM_CPU(obj); 1383 1384 cpu->dtb_compatible = "arm,cortex-a15"; 1385 set_feature(&cpu->env, ARM_FEATURE_V7); 1386 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1387 set_feature(&cpu->env, ARM_FEATURE_NEON); 1388 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1389 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1390 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1391 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1392 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1393 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1394 set_feature(&cpu->env, ARM_FEATURE_EL3); 1395 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1396 cpu->midr = 0x412fc0f1; 1397 cpu->reset_fpsid = 0x410430f0; 1398 cpu->mvfr0 = 0x10110222; 1399 cpu->mvfr1 = 0x11111111; 1400 cpu->ctr = 0x8444c004; 1401 cpu->reset_sctlr = 0x00c50078; 1402 cpu->id_pfr0 = 0x00001131; 1403 cpu->id_pfr1 = 0x00011011; 1404 cpu->id_dfr0 = 0x02010555; 1405 cpu->pmceid0 = 0x0000000; 1406 cpu->pmceid1 = 0x00000000; 1407 cpu->id_afr0 = 0x00000000; 1408 cpu->id_mmfr0 = 0x10201105; 1409 cpu->id_mmfr1 = 0x20000000; 1410 cpu->id_mmfr2 = 0x01240000; 1411 cpu->id_mmfr3 = 0x02102211; 1412 cpu->id_isar0 = 0x02101110; 1413 cpu->id_isar1 = 0x13112111; 1414 cpu->id_isar2 = 0x21232041; 1415 cpu->id_isar3 = 0x11112131; 1416 cpu->id_isar4 = 0x10011142; 1417 cpu->dbgdidr = 0x3515f021; 1418 cpu->clidr = 0x0a200023; 1419 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1420 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1421 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1422 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 1423 } 1424 1425 static void ti925t_initfn(Object *obj) 1426 { 1427 ARMCPU *cpu = ARM_CPU(obj); 1428 set_feature(&cpu->env, ARM_FEATURE_V4T); 1429 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 1430 cpu->midr = ARM_CPUID_TI925T; 1431 cpu->ctr = 0x5109149; 1432 cpu->reset_sctlr = 0x00000070; 1433 } 1434 1435 static void sa1100_initfn(Object *obj) 1436 { 1437 ARMCPU *cpu = ARM_CPU(obj); 1438 1439 cpu->dtb_compatible = "intel,sa1100"; 1440 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1441 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1442 cpu->midr = 0x4401A11B; 1443 cpu->reset_sctlr = 0x00000070; 1444 } 1445 1446 static void sa1110_initfn(Object *obj) 1447 { 1448 ARMCPU *cpu = ARM_CPU(obj); 1449 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1450 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1451 cpu->midr = 0x6901B119; 1452 cpu->reset_sctlr = 0x00000070; 1453 } 1454 1455 static void pxa250_initfn(Object *obj) 1456 { 1457 ARMCPU *cpu = ARM_CPU(obj); 1458 1459 cpu->dtb_compatible = "marvell,xscale"; 1460 set_feature(&cpu->env, ARM_FEATURE_V5); 1461 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1462 cpu->midr = 0x69052100; 1463 cpu->ctr = 0xd172172; 1464 cpu->reset_sctlr = 0x00000078; 1465 } 1466 1467 static void pxa255_initfn(Object *obj) 1468 { 1469 ARMCPU *cpu = ARM_CPU(obj); 1470 1471 cpu->dtb_compatible = "marvell,xscale"; 1472 set_feature(&cpu->env, ARM_FEATURE_V5); 1473 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1474 cpu->midr = 0x69052d00; 1475 cpu->ctr = 0xd172172; 1476 cpu->reset_sctlr = 0x00000078; 1477 } 1478 1479 static void pxa260_initfn(Object *obj) 1480 { 1481 ARMCPU *cpu = ARM_CPU(obj); 1482 1483 cpu->dtb_compatible = "marvell,xscale"; 1484 set_feature(&cpu->env, ARM_FEATURE_V5); 1485 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1486 cpu->midr = 0x69052903; 1487 cpu->ctr = 0xd172172; 1488 cpu->reset_sctlr = 0x00000078; 1489 } 1490 1491 static void pxa261_initfn(Object *obj) 1492 { 1493 ARMCPU *cpu = ARM_CPU(obj); 1494 1495 cpu->dtb_compatible = "marvell,xscale"; 1496 set_feature(&cpu->env, ARM_FEATURE_V5); 1497 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1498 cpu->midr = 0x69052d05; 1499 cpu->ctr = 0xd172172; 1500 cpu->reset_sctlr = 0x00000078; 1501 } 1502 1503 static void pxa262_initfn(Object *obj) 1504 { 1505 ARMCPU *cpu = ARM_CPU(obj); 1506 1507 cpu->dtb_compatible = "marvell,xscale"; 1508 set_feature(&cpu->env, ARM_FEATURE_V5); 1509 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1510 cpu->midr = 0x69052d06; 1511 cpu->ctr = 0xd172172; 1512 cpu->reset_sctlr = 0x00000078; 1513 } 1514 1515 static void pxa270a0_initfn(Object *obj) 1516 { 1517 ARMCPU *cpu = ARM_CPU(obj); 1518 1519 cpu->dtb_compatible = "marvell,xscale"; 1520 set_feature(&cpu->env, ARM_FEATURE_V5); 1521 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1522 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1523 cpu->midr = 0x69054110; 1524 cpu->ctr = 0xd172172; 1525 cpu->reset_sctlr = 0x00000078; 1526 } 1527 1528 static void pxa270a1_initfn(Object *obj) 1529 { 1530 ARMCPU *cpu = ARM_CPU(obj); 1531 1532 cpu->dtb_compatible = "marvell,xscale"; 1533 set_feature(&cpu->env, ARM_FEATURE_V5); 1534 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1535 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1536 cpu->midr = 0x69054111; 1537 cpu->ctr = 0xd172172; 1538 cpu->reset_sctlr = 0x00000078; 1539 } 1540 1541 static void pxa270b0_initfn(Object *obj) 1542 { 1543 ARMCPU *cpu = ARM_CPU(obj); 1544 1545 cpu->dtb_compatible = "marvell,xscale"; 1546 set_feature(&cpu->env, ARM_FEATURE_V5); 1547 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1548 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1549 cpu->midr = 0x69054112; 1550 cpu->ctr = 0xd172172; 1551 cpu->reset_sctlr = 0x00000078; 1552 } 1553 1554 static void pxa270b1_initfn(Object *obj) 1555 { 1556 ARMCPU *cpu = ARM_CPU(obj); 1557 1558 cpu->dtb_compatible = "marvell,xscale"; 1559 set_feature(&cpu->env, ARM_FEATURE_V5); 1560 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1561 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1562 cpu->midr = 0x69054113; 1563 cpu->ctr = 0xd172172; 1564 cpu->reset_sctlr = 0x00000078; 1565 } 1566 1567 static void pxa270c0_initfn(Object *obj) 1568 { 1569 ARMCPU *cpu = ARM_CPU(obj); 1570 1571 cpu->dtb_compatible = "marvell,xscale"; 1572 set_feature(&cpu->env, ARM_FEATURE_V5); 1573 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1574 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1575 cpu->midr = 0x69054114; 1576 cpu->ctr = 0xd172172; 1577 cpu->reset_sctlr = 0x00000078; 1578 } 1579 1580 static void pxa270c5_initfn(Object *obj) 1581 { 1582 ARMCPU *cpu = ARM_CPU(obj); 1583 1584 cpu->dtb_compatible = "marvell,xscale"; 1585 set_feature(&cpu->env, ARM_FEATURE_V5); 1586 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1587 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1588 cpu->midr = 0x69054117; 1589 cpu->ctr = 0xd172172; 1590 cpu->reset_sctlr = 0x00000078; 1591 } 1592 1593 #ifdef CONFIG_USER_ONLY 1594 static void arm_any_initfn(Object *obj) 1595 { 1596 ARMCPU *cpu = ARM_CPU(obj); 1597 set_feature(&cpu->env, ARM_FEATURE_V8); 1598 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1599 set_feature(&cpu->env, ARM_FEATURE_NEON); 1600 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1601 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 1602 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 1603 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 1604 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 1605 set_feature(&cpu->env, ARM_FEATURE_CRC); 1606 cpu->midr = 0xffffffff; 1607 } 1608 #endif 1609 1610 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 1611 1612 typedef struct ARMCPUInfo { 1613 const char *name; 1614 void (*initfn)(Object *obj); 1615 void (*class_init)(ObjectClass *oc, void *data); 1616 } ARMCPUInfo; 1617 1618 static const ARMCPUInfo arm_cpus[] = { 1619 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1620 { .name = "arm926", .initfn = arm926_initfn }, 1621 { .name = "arm946", .initfn = arm946_initfn }, 1622 { .name = "arm1026", .initfn = arm1026_initfn }, 1623 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1624 * older core than plain "arm1136". In particular this does not 1625 * have the v6K features. 1626 */ 1627 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1628 { .name = "arm1136", .initfn = arm1136_initfn }, 1629 { .name = "arm1176", .initfn = arm1176_initfn }, 1630 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1631 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 1632 .class_init = arm_v7m_class_init }, 1633 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 1634 .class_init = arm_v7m_class_init }, 1635 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1636 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1637 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1638 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1639 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1640 { .name = "ti925t", .initfn = ti925t_initfn }, 1641 { .name = "sa1100", .initfn = sa1100_initfn }, 1642 { .name = "sa1110", .initfn = sa1110_initfn }, 1643 { .name = "pxa250", .initfn = pxa250_initfn }, 1644 { .name = "pxa255", .initfn = pxa255_initfn }, 1645 { .name = "pxa260", .initfn = pxa260_initfn }, 1646 { .name = "pxa261", .initfn = pxa261_initfn }, 1647 { .name = "pxa262", .initfn = pxa262_initfn }, 1648 /* "pxa270" is an alias for "pxa270-a0" */ 1649 { .name = "pxa270", .initfn = pxa270a0_initfn }, 1650 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 1651 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 1652 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 1653 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 1654 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 1655 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 1656 #ifdef CONFIG_USER_ONLY 1657 { .name = "any", .initfn = arm_any_initfn }, 1658 #endif 1659 #endif 1660 { .name = NULL } 1661 }; 1662 1663 static Property arm_cpu_properties[] = { 1664 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 1665 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 1666 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 1667 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 1668 mp_affinity, ARM64_AFFINITY_INVALID), 1669 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 1670 DEFINE_PROP_END_OF_LIST() 1671 }; 1672 1673 #ifdef CONFIG_USER_ONLY 1674 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, 1675 int mmu_idx) 1676 { 1677 ARMCPU *cpu = ARM_CPU(cs); 1678 CPUARMState *env = &cpu->env; 1679 1680 env->exception.vaddress = address; 1681 if (rw == 2) { 1682 cs->exception_index = EXCP_PREFETCH_ABORT; 1683 } else { 1684 cs->exception_index = EXCP_DATA_ABORT; 1685 } 1686 return 1; 1687 } 1688 #endif 1689 1690 static gchar *arm_gdb_arch_name(CPUState *cs) 1691 { 1692 ARMCPU *cpu = ARM_CPU(cs); 1693 CPUARMState *env = &cpu->env; 1694 1695 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 1696 return g_strdup("iwmmxt"); 1697 } 1698 return g_strdup("arm"); 1699 } 1700 1701 static void arm_cpu_class_init(ObjectClass *oc, void *data) 1702 { 1703 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1704 CPUClass *cc = CPU_CLASS(acc); 1705 DeviceClass *dc = DEVICE_CLASS(oc); 1706 1707 acc->parent_realize = dc->realize; 1708 dc->realize = arm_cpu_realizefn; 1709 dc->props = arm_cpu_properties; 1710 1711 acc->parent_reset = cc->reset; 1712 cc->reset = arm_cpu_reset; 1713 1714 cc->class_by_name = arm_cpu_class_by_name; 1715 cc->has_work = arm_cpu_has_work; 1716 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 1717 cc->dump_state = arm_cpu_dump_state; 1718 cc->set_pc = arm_cpu_set_pc; 1719 cc->gdb_read_register = arm_cpu_gdb_read_register; 1720 cc->gdb_write_register = arm_cpu_gdb_write_register; 1721 #ifdef CONFIG_USER_ONLY 1722 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; 1723 #else 1724 cc->do_interrupt = arm_cpu_do_interrupt; 1725 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 1726 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 1727 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 1728 cc->asidx_from_attrs = arm_asidx_from_attrs; 1729 cc->vmsd = &vmstate_arm_cpu; 1730 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 1731 cc->write_elf64_note = arm_cpu_write_elf64_note; 1732 cc->write_elf32_note = arm_cpu_write_elf32_note; 1733 #endif 1734 cc->gdb_num_core_regs = 26; 1735 cc->gdb_core_xml_file = "arm-core.xml"; 1736 cc->gdb_arch_name = arm_gdb_arch_name; 1737 cc->gdb_stop_before_watchpoint = true; 1738 cc->debug_excp_handler = arm_debug_excp_handler; 1739 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 1740 #if !defined(CONFIG_USER_ONLY) 1741 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 1742 #endif 1743 1744 cc->disas_set_info = arm_disas_set_info; 1745 } 1746 1747 static void cpu_register(const ARMCPUInfo *info) 1748 { 1749 TypeInfo type_info = { 1750 .parent = TYPE_ARM_CPU, 1751 .instance_size = sizeof(ARMCPU), 1752 .instance_init = info->initfn, 1753 .class_size = sizeof(ARMCPUClass), 1754 .class_init = info->class_init, 1755 }; 1756 1757 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 1758 type_register(&type_info); 1759 g_free((void *)type_info.name); 1760 } 1761 1762 static const TypeInfo arm_cpu_type_info = { 1763 .name = TYPE_ARM_CPU, 1764 .parent = TYPE_CPU, 1765 .instance_size = sizeof(ARMCPU), 1766 .instance_init = arm_cpu_initfn, 1767 .instance_post_init = arm_cpu_post_init, 1768 .instance_finalize = arm_cpu_finalizefn, 1769 .abstract = true, 1770 .class_size = sizeof(ARMCPUClass), 1771 .class_init = arm_cpu_class_init, 1772 }; 1773 1774 static void arm_cpu_register_types(void) 1775 { 1776 const ARMCPUInfo *info = arm_cpus; 1777 1778 type_register_static(&arm_cpu_type_info); 1779 1780 while (info->name) { 1781 cpu_register(info); 1782 info++; 1783 } 1784 } 1785 1786 type_init(arm_cpu_register_types) 1787