1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/error-report.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "qemu-common.h" 27 #include "exec/exec-all.h" 28 #include "hw/qdev-properties.h" 29 #if !defined(CONFIG_USER_ONLY) 30 #include "hw/loader.h" 31 #endif 32 #include "hw/arm/arm.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/hw_accel.h" 35 #include "kvm_arm.h" 36 37 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 38 { 39 ARMCPU *cpu = ARM_CPU(cs); 40 41 cpu->env.regs[15] = value; 42 } 43 44 static bool arm_cpu_has_work(CPUState *cs) 45 { 46 ARMCPU *cpu = ARM_CPU(cs); 47 48 return (cpu->power_state != PSCI_OFF) 49 && cs->interrupt_request & 50 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 51 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 52 | CPU_INTERRUPT_EXITTB); 53 } 54 55 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 56 void *opaque) 57 { 58 /* We currently only support registering a single hook function */ 59 assert(!cpu->el_change_hook); 60 cpu->el_change_hook = hook; 61 cpu->el_change_hook_opaque = opaque; 62 } 63 64 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 65 { 66 /* Reset a single ARMCPRegInfo register */ 67 ARMCPRegInfo *ri = value; 68 ARMCPU *cpu = opaque; 69 70 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 71 return; 72 } 73 74 if (ri->resetfn) { 75 ri->resetfn(&cpu->env, ri); 76 return; 77 } 78 79 /* A zero offset is never possible as it would be regs[0] 80 * so we use it to indicate that reset is being handled elsewhere. 81 * This is basically only used for fields in non-core coprocessors 82 * (like the pxa2xx ones). 83 */ 84 if (!ri->fieldoffset) { 85 return; 86 } 87 88 if (cpreg_field_is_64bit(ri)) { 89 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 90 } else { 91 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 92 } 93 } 94 95 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 96 { 97 /* Purely an assertion check: we've already done reset once, 98 * so now check that running the reset for the cpreg doesn't 99 * change its value. This traps bugs where two different cpregs 100 * both try to reset the same state field but to different values. 101 */ 102 ARMCPRegInfo *ri = value; 103 ARMCPU *cpu = opaque; 104 uint64_t oldvalue, newvalue; 105 106 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 107 return; 108 } 109 110 oldvalue = read_raw_cp_reg(&cpu->env, ri); 111 cp_reg_reset(key, value, opaque); 112 newvalue = read_raw_cp_reg(&cpu->env, ri); 113 assert(oldvalue == newvalue); 114 } 115 116 /* CPUClass::reset() */ 117 static void arm_cpu_reset(CPUState *s) 118 { 119 ARMCPU *cpu = ARM_CPU(s); 120 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 121 CPUARMState *env = &cpu->env; 122 123 acc->parent_reset(s); 124 125 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 126 127 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 128 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 129 130 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 131 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; 132 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; 133 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; 134 135 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 136 s->halted = cpu->start_powered_off; 137 138 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 139 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 140 } 141 142 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 143 /* 64 bit CPUs always start in 64 bit mode */ 144 env->aarch64 = 1; 145 #if defined(CONFIG_USER_ONLY) 146 env->pstate = PSTATE_MODE_EL0t; 147 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 148 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 149 /* and to the FP/Neon instructions */ 150 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 151 #else 152 /* Reset into the highest available EL */ 153 if (arm_feature(env, ARM_FEATURE_EL3)) { 154 env->pstate = PSTATE_MODE_EL3h; 155 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 156 env->pstate = PSTATE_MODE_EL2h; 157 } else { 158 env->pstate = PSTATE_MODE_EL1h; 159 } 160 env->pc = cpu->rvbar; 161 #endif 162 } else { 163 #if defined(CONFIG_USER_ONLY) 164 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 165 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 166 #endif 167 } 168 169 #if defined(CONFIG_USER_ONLY) 170 env->uncached_cpsr = ARM_CPU_MODE_USR; 171 /* For user mode we must enable access to coprocessors */ 172 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 173 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 174 env->cp15.c15_cpar = 3; 175 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 176 env->cp15.c15_cpar = 1; 177 } 178 #else 179 /* SVC mode with interrupts disabled. */ 180 env->uncached_cpsr = ARM_CPU_MODE_SVC; 181 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 182 183 if (arm_feature(env, ARM_FEATURE_M)) { 184 uint32_t initial_msp; /* Loaded from 0x0 */ 185 uint32_t initial_pc; /* Loaded from 0x4 */ 186 uint8_t *rom; 187 188 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 189 env->v7m.secure = true; 190 } else { 191 /* This bit resets to 0 if security is supported, but 1 if 192 * it is not. The bit is not present in v7M, but we set it 193 * here so we can avoid having to make checks on it conditional 194 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 195 */ 196 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 197 } 198 199 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 200 * that it resets to 1, so QEMU always does that rather than making 201 * it dependent on CPU model. In v8M it is RES1. 202 */ 203 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 204 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 205 if (arm_feature(env, ARM_FEATURE_V8)) { 206 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 207 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 208 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 209 } 210 211 /* Unlike A/R profile, M profile defines the reset LR value */ 212 env->regs[14] = 0xffffffff; 213 214 /* Load the initial SP and PC from the vector table at address 0 */ 215 rom = rom_ptr(0); 216 if (rom) { 217 /* Address zero is covered by ROM which hasn't yet been 218 * copied into physical memory. 219 */ 220 initial_msp = ldl_p(rom); 221 initial_pc = ldl_p(rom + 4); 222 } else { 223 /* Address zero not covered by a ROM blob, or the ROM blob 224 * is in non-modifiable memory and this is a second reset after 225 * it got copied into memory. In the latter case, rom_ptr 226 * will return a NULL pointer and we should use ldl_phys instead. 227 */ 228 initial_msp = ldl_phys(s->as, 0); 229 initial_pc = ldl_phys(s->as, 4); 230 } 231 232 env->regs[13] = initial_msp & 0xFFFFFFFC; 233 env->regs[15] = initial_pc & ~1; 234 env->thumb = initial_pc & 1; 235 } 236 237 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 238 * executing as AArch32 then check if highvecs are enabled and 239 * adjust the PC accordingly. 240 */ 241 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 242 env->regs[15] = 0xFFFF0000; 243 } 244 245 /* M profile requires that reset clears the exclusive monitor; 246 * A profile does not, but clearing it makes more sense than having it 247 * set with an exclusive access on address zero. 248 */ 249 arm_clear_exclusive(env); 250 251 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 252 #endif 253 254 if (arm_feature(env, ARM_FEATURE_PMSA)) { 255 if (cpu->pmsav7_dregion > 0) { 256 if (arm_feature(env, ARM_FEATURE_V8)) { 257 memset(env->pmsav8.rbar[M_REG_NS], 0, 258 sizeof(*env->pmsav8.rbar[M_REG_NS]) 259 * cpu->pmsav7_dregion); 260 memset(env->pmsav8.rlar[M_REG_NS], 0, 261 sizeof(*env->pmsav8.rlar[M_REG_NS]) 262 * cpu->pmsav7_dregion); 263 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 264 memset(env->pmsav8.rbar[M_REG_S], 0, 265 sizeof(*env->pmsav8.rbar[M_REG_S]) 266 * cpu->pmsav7_dregion); 267 memset(env->pmsav8.rlar[M_REG_S], 0, 268 sizeof(*env->pmsav8.rlar[M_REG_S]) 269 * cpu->pmsav7_dregion); 270 } 271 } else if (arm_feature(env, ARM_FEATURE_V7)) { 272 memset(env->pmsav7.drbar, 0, 273 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 274 memset(env->pmsav7.drsr, 0, 275 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 276 memset(env->pmsav7.dracr, 0, 277 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 278 } 279 } 280 env->pmsav7.rnr[M_REG_NS] = 0; 281 env->pmsav7.rnr[M_REG_S] = 0; 282 env->pmsav8.mair0[M_REG_NS] = 0; 283 env->pmsav8.mair0[M_REG_S] = 0; 284 env->pmsav8.mair1[M_REG_NS] = 0; 285 env->pmsav8.mair1[M_REG_S] = 0; 286 } 287 288 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 289 if (cpu->sau_sregion > 0) { 290 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 291 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 292 } 293 env->sau.rnr = 0; 294 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 295 * the Cortex-M33 does. 296 */ 297 env->sau.ctrl = 0; 298 } 299 300 set_flush_to_zero(1, &env->vfp.standard_fp_status); 301 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 302 set_default_nan_mode(1, &env->vfp.standard_fp_status); 303 set_float_detect_tininess(float_tininess_before_rounding, 304 &env->vfp.fp_status); 305 set_float_detect_tininess(float_tininess_before_rounding, 306 &env->vfp.standard_fp_status); 307 #ifndef CONFIG_USER_ONLY 308 if (kvm_enabled()) { 309 kvm_arm_reset_vcpu(cpu); 310 } 311 #endif 312 313 hw_breakpoint_update_all(cpu); 314 hw_watchpoint_update_all(cpu); 315 } 316 317 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 318 { 319 CPUClass *cc = CPU_GET_CLASS(cs); 320 CPUARMState *env = cs->env_ptr; 321 uint32_t cur_el = arm_current_el(env); 322 bool secure = arm_is_secure(env); 323 uint32_t target_el; 324 uint32_t excp_idx; 325 bool ret = false; 326 327 if (interrupt_request & CPU_INTERRUPT_FIQ) { 328 excp_idx = EXCP_FIQ; 329 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 330 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 331 cs->exception_index = excp_idx; 332 env->exception.target_el = target_el; 333 cc->do_interrupt(cs); 334 ret = true; 335 } 336 } 337 if (interrupt_request & CPU_INTERRUPT_HARD) { 338 excp_idx = EXCP_IRQ; 339 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 340 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 341 cs->exception_index = excp_idx; 342 env->exception.target_el = target_el; 343 cc->do_interrupt(cs); 344 ret = true; 345 } 346 } 347 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 348 excp_idx = EXCP_VIRQ; 349 target_el = 1; 350 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 351 cs->exception_index = excp_idx; 352 env->exception.target_el = target_el; 353 cc->do_interrupt(cs); 354 ret = true; 355 } 356 } 357 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 358 excp_idx = EXCP_VFIQ; 359 target_el = 1; 360 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 361 cs->exception_index = excp_idx; 362 env->exception.target_el = target_el; 363 cc->do_interrupt(cs); 364 ret = true; 365 } 366 } 367 368 return ret; 369 } 370 371 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 372 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 373 { 374 CPUClass *cc = CPU_GET_CLASS(cs); 375 ARMCPU *cpu = ARM_CPU(cs); 376 CPUARMState *env = &cpu->env; 377 bool ret = false; 378 379 /* ARMv7-M interrupt masking works differently than -A or -R. 380 * There is no FIQ/IRQ distinction. Instead of I and F bits 381 * masking FIQ and IRQ interrupts, an exception is taken only 382 * if it is higher priority than the current execution priority 383 * (which depends on state like BASEPRI, FAULTMASK and the 384 * currently active exception). 385 */ 386 if (interrupt_request & CPU_INTERRUPT_HARD 387 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 388 cs->exception_index = EXCP_IRQ; 389 cc->do_interrupt(cs); 390 ret = true; 391 } 392 return ret; 393 } 394 #endif 395 396 #ifndef CONFIG_USER_ONLY 397 static void arm_cpu_set_irq(void *opaque, int irq, int level) 398 { 399 ARMCPU *cpu = opaque; 400 CPUARMState *env = &cpu->env; 401 CPUState *cs = CPU(cpu); 402 static const int mask[] = { 403 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 404 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 405 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 406 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 407 }; 408 409 switch (irq) { 410 case ARM_CPU_VIRQ: 411 case ARM_CPU_VFIQ: 412 assert(arm_feature(env, ARM_FEATURE_EL2)); 413 /* fall through */ 414 case ARM_CPU_IRQ: 415 case ARM_CPU_FIQ: 416 if (level) { 417 cpu_interrupt(cs, mask[irq]); 418 } else { 419 cpu_reset_interrupt(cs, mask[irq]); 420 } 421 break; 422 default: 423 g_assert_not_reached(); 424 } 425 } 426 427 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 428 { 429 #ifdef CONFIG_KVM 430 ARMCPU *cpu = opaque; 431 CPUState *cs = CPU(cpu); 432 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 433 434 switch (irq) { 435 case ARM_CPU_IRQ: 436 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 437 break; 438 case ARM_CPU_FIQ: 439 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 440 break; 441 default: 442 g_assert_not_reached(); 443 } 444 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 445 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 446 #endif 447 } 448 449 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 450 { 451 ARMCPU *cpu = ARM_CPU(cs); 452 CPUARMState *env = &cpu->env; 453 454 cpu_synchronize_state(cs); 455 return arm_cpu_data_is_big_endian(env); 456 } 457 458 #endif 459 460 static inline void set_feature(CPUARMState *env, int feature) 461 { 462 env->features |= 1ULL << feature; 463 } 464 465 static inline void unset_feature(CPUARMState *env, int feature) 466 { 467 env->features &= ~(1ULL << feature); 468 } 469 470 static int 471 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 472 { 473 return print_insn_arm(pc | 1, info); 474 } 475 476 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 477 { 478 ARMCPU *ac = ARM_CPU(cpu); 479 CPUARMState *env = &ac->env; 480 bool sctlr_b; 481 482 if (is_a64(env)) { 483 /* We might not be compiled with the A64 disassembler 484 * because it needs a C++ compiler. Leave print_insn 485 * unset in this case to use the caller default behaviour. 486 */ 487 #if defined(CONFIG_ARM_A64_DIS) 488 info->print_insn = print_insn_arm_a64; 489 #endif 490 } else if (env->thumb) { 491 info->print_insn = print_insn_thumb1; 492 } else { 493 info->print_insn = print_insn_arm; 494 } 495 496 sctlr_b = arm_sctlr_b(env); 497 if (bswap_code(sctlr_b)) { 498 #ifdef TARGET_WORDS_BIGENDIAN 499 info->endian = BFD_ENDIAN_LITTLE; 500 #else 501 info->endian = BFD_ENDIAN_BIG; 502 #endif 503 } 504 info->flags &= ~INSN_ARM_BE32; 505 #ifndef CONFIG_USER_ONLY 506 if (sctlr_b) { 507 info->flags |= INSN_ARM_BE32; 508 } 509 #endif 510 } 511 512 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 513 { 514 uint32_t Aff1 = idx / clustersz; 515 uint32_t Aff0 = idx % clustersz; 516 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 517 } 518 519 static void arm_cpu_initfn(Object *obj) 520 { 521 CPUState *cs = CPU(obj); 522 ARMCPU *cpu = ARM_CPU(obj); 523 static bool inited; 524 525 cs->env_ptr = &cpu->env; 526 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 527 g_free, g_free); 528 529 #ifndef CONFIG_USER_ONLY 530 /* Our inbound IRQ and FIQ lines */ 531 if (kvm_enabled()) { 532 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 533 * the same interface as non-KVM CPUs. 534 */ 535 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 536 } else { 537 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 538 } 539 540 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 541 arm_gt_ptimer_cb, cpu); 542 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 543 arm_gt_vtimer_cb, cpu); 544 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 545 arm_gt_htimer_cb, cpu); 546 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 547 arm_gt_stimer_cb, cpu); 548 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 549 ARRAY_SIZE(cpu->gt_timer_outputs)); 550 551 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 552 "gicv3-maintenance-interrupt", 1); 553 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 554 "pmu-interrupt", 1); 555 #endif 556 557 /* DTB consumers generally don't in fact care what the 'compatible' 558 * string is, so always provide some string and trust that a hypothetical 559 * picky DTB consumer will also provide a helpful error message. 560 */ 561 cpu->dtb_compatible = "qemu,unknown"; 562 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 563 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 564 565 if (tcg_enabled()) { 566 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 567 if (!inited) { 568 inited = true; 569 arm_translate_init(); 570 } 571 } 572 } 573 574 static Property arm_cpu_reset_cbar_property = 575 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 576 577 static Property arm_cpu_reset_hivecs_property = 578 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 579 580 static Property arm_cpu_rvbar_property = 581 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 582 583 static Property arm_cpu_has_el2_property = 584 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 585 586 static Property arm_cpu_has_el3_property = 587 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 588 589 static Property arm_cpu_cfgend_property = 590 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 591 592 /* use property name "pmu" to match other archs and virt tools */ 593 static Property arm_cpu_has_pmu_property = 594 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 595 596 static Property arm_cpu_has_mpu_property = 597 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 598 599 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 600 * because the CPU initfn will have already set cpu->pmsav7_dregion to 601 * the right value for that particular CPU type, and we don't want 602 * to override that with an incorrect constant value. 603 */ 604 static Property arm_cpu_pmsav7_dregion_property = 605 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 606 pmsav7_dregion, 607 qdev_prop_uint32, uint32_t); 608 609 static void arm_cpu_post_init(Object *obj) 610 { 611 ARMCPU *cpu = ARM_CPU(obj); 612 613 /* M profile implies PMSA. We have to do this here rather than 614 * in realize with the other feature-implication checks because 615 * we look at the PMSA bit to see if we should add some properties. 616 */ 617 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 618 set_feature(&cpu->env, ARM_FEATURE_PMSA); 619 } 620 621 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 622 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 623 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 624 &error_abort); 625 } 626 627 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 628 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 629 &error_abort); 630 } 631 632 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 633 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 634 &error_abort); 635 } 636 637 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 638 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 639 * prevent "has_el3" from existing on CPUs which cannot support EL3. 640 */ 641 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 642 &error_abort); 643 644 #ifndef CONFIG_USER_ONLY 645 object_property_add_link(obj, "secure-memory", 646 TYPE_MEMORY_REGION, 647 (Object **)&cpu->secure_memory, 648 qdev_prop_allow_set_link_before_realize, 649 OBJ_PROP_LINK_UNREF_ON_RELEASE, 650 &error_abort); 651 #endif 652 } 653 654 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 655 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 656 &error_abort); 657 } 658 659 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 660 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 661 &error_abort); 662 } 663 664 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 665 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 666 &error_abort); 667 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 668 qdev_property_add_static(DEVICE(obj), 669 &arm_cpu_pmsav7_dregion_property, 670 &error_abort); 671 } 672 } 673 674 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 675 &error_abort); 676 } 677 678 static void arm_cpu_finalizefn(Object *obj) 679 { 680 ARMCPU *cpu = ARM_CPU(obj); 681 g_hash_table_destroy(cpu->cp_regs); 682 } 683 684 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 685 { 686 CPUState *cs = CPU(dev); 687 ARMCPU *cpu = ARM_CPU(dev); 688 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 689 CPUARMState *env = &cpu->env; 690 int pagebits; 691 Error *local_err = NULL; 692 #ifndef CONFIG_USER_ONLY 693 AddressSpace *as; 694 #endif 695 696 cpu_exec_realizefn(cs, &local_err); 697 if (local_err != NULL) { 698 error_propagate(errp, local_err); 699 return; 700 } 701 702 /* Some features automatically imply others: */ 703 if (arm_feature(env, ARM_FEATURE_V8)) { 704 set_feature(env, ARM_FEATURE_V7); 705 set_feature(env, ARM_FEATURE_ARM_DIV); 706 set_feature(env, ARM_FEATURE_LPAE); 707 } 708 if (arm_feature(env, ARM_FEATURE_V7)) { 709 set_feature(env, ARM_FEATURE_VAPA); 710 set_feature(env, ARM_FEATURE_THUMB2); 711 set_feature(env, ARM_FEATURE_MPIDR); 712 if (!arm_feature(env, ARM_FEATURE_M)) { 713 set_feature(env, ARM_FEATURE_V6K); 714 } else { 715 set_feature(env, ARM_FEATURE_V6); 716 } 717 718 /* Always define VBAR for V7 CPUs even if it doesn't exist in 719 * non-EL3 configs. This is needed by some legacy boards. 720 */ 721 set_feature(env, ARM_FEATURE_VBAR); 722 } 723 if (arm_feature(env, ARM_FEATURE_V6K)) { 724 set_feature(env, ARM_FEATURE_V6); 725 set_feature(env, ARM_FEATURE_MVFR); 726 } 727 if (arm_feature(env, ARM_FEATURE_V6)) { 728 set_feature(env, ARM_FEATURE_V5); 729 set_feature(env, ARM_FEATURE_JAZELLE); 730 if (!arm_feature(env, ARM_FEATURE_M)) { 731 set_feature(env, ARM_FEATURE_AUXCR); 732 } 733 } 734 if (arm_feature(env, ARM_FEATURE_V5)) { 735 set_feature(env, ARM_FEATURE_V4T); 736 } 737 if (arm_feature(env, ARM_FEATURE_M)) { 738 set_feature(env, ARM_FEATURE_THUMB_DIV); 739 } 740 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { 741 set_feature(env, ARM_FEATURE_THUMB_DIV); 742 } 743 if (arm_feature(env, ARM_FEATURE_VFP4)) { 744 set_feature(env, ARM_FEATURE_VFP3); 745 set_feature(env, ARM_FEATURE_VFP_FP16); 746 } 747 if (arm_feature(env, ARM_FEATURE_VFP3)) { 748 set_feature(env, ARM_FEATURE_VFP); 749 } 750 if (arm_feature(env, ARM_FEATURE_LPAE)) { 751 set_feature(env, ARM_FEATURE_V7MP); 752 set_feature(env, ARM_FEATURE_PXN); 753 } 754 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 755 set_feature(env, ARM_FEATURE_CBAR); 756 } 757 if (arm_feature(env, ARM_FEATURE_THUMB2) && 758 !arm_feature(env, ARM_FEATURE_M)) { 759 set_feature(env, ARM_FEATURE_THUMB_DSP); 760 } 761 762 if (arm_feature(env, ARM_FEATURE_V7) && 763 !arm_feature(env, ARM_FEATURE_M) && 764 !arm_feature(env, ARM_FEATURE_PMSA)) { 765 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 766 * can use 4K pages. 767 */ 768 pagebits = 12; 769 } else { 770 /* For CPUs which might have tiny 1K pages, or which have an 771 * MPU and might have small region sizes, stick with 1K pages. 772 */ 773 pagebits = 10; 774 } 775 if (!set_preferred_target_page_bits(pagebits)) { 776 /* This can only ever happen for hotplugging a CPU, or if 777 * the board code incorrectly creates a CPU which it has 778 * promised via minimum_page_size that it will not. 779 */ 780 error_setg(errp, "This CPU requires a smaller page size than the " 781 "system is using"); 782 return; 783 } 784 785 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 786 * We don't support setting cluster ID ([16..23]) (known as Aff2 787 * in later ARM ARM versions), or any of the higher affinity level fields, 788 * so these bits always RAZ. 789 */ 790 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 791 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 792 ARM_DEFAULT_CPUS_PER_CLUSTER); 793 } 794 795 if (cpu->reset_hivecs) { 796 cpu->reset_sctlr |= (1 << 13); 797 } 798 799 if (cpu->cfgend) { 800 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 801 cpu->reset_sctlr |= SCTLR_EE; 802 } else { 803 cpu->reset_sctlr |= SCTLR_B; 804 } 805 } 806 807 if (!cpu->has_el3) { 808 /* If the has_el3 CPU property is disabled then we need to disable the 809 * feature. 810 */ 811 unset_feature(env, ARM_FEATURE_EL3); 812 813 /* Disable the security extension feature bits in the processor feature 814 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 815 */ 816 cpu->id_pfr1 &= ~0xf0; 817 cpu->id_aa64pfr0 &= ~0xf000; 818 } 819 820 if (!cpu->has_el2) { 821 unset_feature(env, ARM_FEATURE_EL2); 822 } 823 824 if (!cpu->has_pmu) { 825 unset_feature(env, ARM_FEATURE_PMU); 826 cpu->id_aa64dfr0 &= ~0xf00; 827 } 828 829 if (!arm_feature(env, ARM_FEATURE_EL2)) { 830 /* Disable the hypervisor feature bits in the processor feature 831 * registers if we don't have EL2. These are id_pfr1[15:12] and 832 * id_aa64pfr0_el1[11:8]. 833 */ 834 cpu->id_aa64pfr0 &= ~0xf00; 835 cpu->id_pfr1 &= ~0xf000; 836 } 837 838 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 839 * to false or by setting pmsav7-dregion to 0. 840 */ 841 if (!cpu->has_mpu) { 842 cpu->pmsav7_dregion = 0; 843 } 844 if (cpu->pmsav7_dregion == 0) { 845 cpu->has_mpu = false; 846 } 847 848 if (arm_feature(env, ARM_FEATURE_PMSA) && 849 arm_feature(env, ARM_FEATURE_V7)) { 850 uint32_t nr = cpu->pmsav7_dregion; 851 852 if (nr > 0xff) { 853 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 854 return; 855 } 856 857 if (nr) { 858 if (arm_feature(env, ARM_FEATURE_V8)) { 859 /* PMSAv8 */ 860 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 861 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 862 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 863 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 864 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 865 } 866 } else { 867 env->pmsav7.drbar = g_new0(uint32_t, nr); 868 env->pmsav7.drsr = g_new0(uint32_t, nr); 869 env->pmsav7.dracr = g_new0(uint32_t, nr); 870 } 871 } 872 } 873 874 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 875 uint32_t nr = cpu->sau_sregion; 876 877 if (nr > 0xff) { 878 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 879 return; 880 } 881 882 if (nr) { 883 env->sau.rbar = g_new0(uint32_t, nr); 884 env->sau.rlar = g_new0(uint32_t, nr); 885 } 886 } 887 888 if (arm_feature(env, ARM_FEATURE_EL3)) { 889 set_feature(env, ARM_FEATURE_VBAR); 890 } 891 892 register_cp_regs_for_features(cpu); 893 arm_cpu_register_gdb_regs_for_features(cpu); 894 895 init_cpreg_list(cpu); 896 897 #ifndef CONFIG_USER_ONLY 898 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 899 as = g_new0(AddressSpace, 1); 900 901 cs->num_ases = 2; 902 903 if (!cpu->secure_memory) { 904 cpu->secure_memory = cs->memory; 905 } 906 address_space_init(as, cpu->secure_memory, "cpu-secure-memory"); 907 cpu_address_space_init(cs, as, ARMASIdx_S); 908 } else { 909 cs->num_ases = 1; 910 } 911 as = g_new0(AddressSpace, 1); 912 address_space_init(as, cs->memory, "cpu-memory"); 913 cpu_address_space_init(cs, as, ARMASIdx_NS); 914 #endif 915 916 qemu_init_vcpu(cs); 917 cpu_reset(cs); 918 919 acc->parent_realize(dev, errp); 920 } 921 922 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 923 { 924 ObjectClass *oc; 925 char *typename; 926 char **cpuname; 927 928 cpuname = g_strsplit(cpu_model, ",", 1); 929 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpuname[0]); 930 oc = object_class_by_name(typename); 931 g_strfreev(cpuname); 932 g_free(typename); 933 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 934 object_class_is_abstract(oc)) { 935 return NULL; 936 } 937 return oc; 938 } 939 940 /* CPU models. These are not needed for the AArch64 linux-user build. */ 941 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 942 943 static void arm926_initfn(Object *obj) 944 { 945 ARMCPU *cpu = ARM_CPU(obj); 946 947 cpu->dtb_compatible = "arm,arm926"; 948 set_feature(&cpu->env, ARM_FEATURE_V5); 949 set_feature(&cpu->env, ARM_FEATURE_VFP); 950 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 951 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 952 set_feature(&cpu->env, ARM_FEATURE_JAZELLE); 953 cpu->midr = 0x41069265; 954 cpu->reset_fpsid = 0x41011090; 955 cpu->ctr = 0x1dd20d2; 956 cpu->reset_sctlr = 0x00090078; 957 } 958 959 static void arm946_initfn(Object *obj) 960 { 961 ARMCPU *cpu = ARM_CPU(obj); 962 963 cpu->dtb_compatible = "arm,arm946"; 964 set_feature(&cpu->env, ARM_FEATURE_V5); 965 set_feature(&cpu->env, ARM_FEATURE_PMSA); 966 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 967 cpu->midr = 0x41059461; 968 cpu->ctr = 0x0f004006; 969 cpu->reset_sctlr = 0x00000078; 970 } 971 972 static void arm1026_initfn(Object *obj) 973 { 974 ARMCPU *cpu = ARM_CPU(obj); 975 976 cpu->dtb_compatible = "arm,arm1026"; 977 set_feature(&cpu->env, ARM_FEATURE_V5); 978 set_feature(&cpu->env, ARM_FEATURE_VFP); 979 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 980 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 981 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 982 set_feature(&cpu->env, ARM_FEATURE_JAZELLE); 983 cpu->midr = 0x4106a262; 984 cpu->reset_fpsid = 0x410110a0; 985 cpu->ctr = 0x1dd20d2; 986 cpu->reset_sctlr = 0x00090078; 987 cpu->reset_auxcr = 1; 988 { 989 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 990 ARMCPRegInfo ifar = { 991 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 992 .access = PL1_RW, 993 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 994 .resetvalue = 0 995 }; 996 define_one_arm_cp_reg(cpu, &ifar); 997 } 998 } 999 1000 static void arm1136_r2_initfn(Object *obj) 1001 { 1002 ARMCPU *cpu = ARM_CPU(obj); 1003 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 1004 * older core than plain "arm1136". In particular this does not 1005 * have the v6K features. 1006 * These ID register values are correct for 1136 but may be wrong 1007 * for 1136_r2 (in particular r0p2 does not actually implement most 1008 * of the ID registers). 1009 */ 1010 1011 cpu->dtb_compatible = "arm,arm1136"; 1012 set_feature(&cpu->env, ARM_FEATURE_V6); 1013 set_feature(&cpu->env, ARM_FEATURE_VFP); 1014 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1015 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1016 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1017 cpu->midr = 0x4107b362; 1018 cpu->reset_fpsid = 0x410120b4; 1019 cpu->mvfr0 = 0x11111111; 1020 cpu->mvfr1 = 0x00000000; 1021 cpu->ctr = 0x1dd20d2; 1022 cpu->reset_sctlr = 0x00050078; 1023 cpu->id_pfr0 = 0x111; 1024 cpu->id_pfr1 = 0x1; 1025 cpu->id_dfr0 = 0x2; 1026 cpu->id_afr0 = 0x3; 1027 cpu->id_mmfr0 = 0x01130003; 1028 cpu->id_mmfr1 = 0x10030302; 1029 cpu->id_mmfr2 = 0x01222110; 1030 cpu->id_isar0 = 0x00140011; 1031 cpu->id_isar1 = 0x12002111; 1032 cpu->id_isar2 = 0x11231111; 1033 cpu->id_isar3 = 0x01102131; 1034 cpu->id_isar4 = 0x141; 1035 cpu->reset_auxcr = 7; 1036 } 1037 1038 static void arm1136_initfn(Object *obj) 1039 { 1040 ARMCPU *cpu = ARM_CPU(obj); 1041 1042 cpu->dtb_compatible = "arm,arm1136"; 1043 set_feature(&cpu->env, ARM_FEATURE_V6K); 1044 set_feature(&cpu->env, ARM_FEATURE_V6); 1045 set_feature(&cpu->env, ARM_FEATURE_VFP); 1046 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1047 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1048 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1049 cpu->midr = 0x4117b363; 1050 cpu->reset_fpsid = 0x410120b4; 1051 cpu->mvfr0 = 0x11111111; 1052 cpu->mvfr1 = 0x00000000; 1053 cpu->ctr = 0x1dd20d2; 1054 cpu->reset_sctlr = 0x00050078; 1055 cpu->id_pfr0 = 0x111; 1056 cpu->id_pfr1 = 0x1; 1057 cpu->id_dfr0 = 0x2; 1058 cpu->id_afr0 = 0x3; 1059 cpu->id_mmfr0 = 0x01130003; 1060 cpu->id_mmfr1 = 0x10030302; 1061 cpu->id_mmfr2 = 0x01222110; 1062 cpu->id_isar0 = 0x00140011; 1063 cpu->id_isar1 = 0x12002111; 1064 cpu->id_isar2 = 0x11231111; 1065 cpu->id_isar3 = 0x01102131; 1066 cpu->id_isar4 = 0x141; 1067 cpu->reset_auxcr = 7; 1068 } 1069 1070 static void arm1176_initfn(Object *obj) 1071 { 1072 ARMCPU *cpu = ARM_CPU(obj); 1073 1074 cpu->dtb_compatible = "arm,arm1176"; 1075 set_feature(&cpu->env, ARM_FEATURE_V6K); 1076 set_feature(&cpu->env, ARM_FEATURE_VFP); 1077 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1078 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1079 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1080 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1081 set_feature(&cpu->env, ARM_FEATURE_EL3); 1082 cpu->midr = 0x410fb767; 1083 cpu->reset_fpsid = 0x410120b5; 1084 cpu->mvfr0 = 0x11111111; 1085 cpu->mvfr1 = 0x00000000; 1086 cpu->ctr = 0x1dd20d2; 1087 cpu->reset_sctlr = 0x00050078; 1088 cpu->id_pfr0 = 0x111; 1089 cpu->id_pfr1 = 0x11; 1090 cpu->id_dfr0 = 0x33; 1091 cpu->id_afr0 = 0; 1092 cpu->id_mmfr0 = 0x01130003; 1093 cpu->id_mmfr1 = 0x10030302; 1094 cpu->id_mmfr2 = 0x01222100; 1095 cpu->id_isar0 = 0x0140011; 1096 cpu->id_isar1 = 0x12002111; 1097 cpu->id_isar2 = 0x11231121; 1098 cpu->id_isar3 = 0x01102131; 1099 cpu->id_isar4 = 0x01141; 1100 cpu->reset_auxcr = 7; 1101 } 1102 1103 static void arm11mpcore_initfn(Object *obj) 1104 { 1105 ARMCPU *cpu = ARM_CPU(obj); 1106 1107 cpu->dtb_compatible = "arm,arm11mpcore"; 1108 set_feature(&cpu->env, ARM_FEATURE_V6K); 1109 set_feature(&cpu->env, ARM_FEATURE_VFP); 1110 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1111 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1112 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1113 cpu->midr = 0x410fb022; 1114 cpu->reset_fpsid = 0x410120b4; 1115 cpu->mvfr0 = 0x11111111; 1116 cpu->mvfr1 = 0x00000000; 1117 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1118 cpu->id_pfr0 = 0x111; 1119 cpu->id_pfr1 = 0x1; 1120 cpu->id_dfr0 = 0; 1121 cpu->id_afr0 = 0x2; 1122 cpu->id_mmfr0 = 0x01100103; 1123 cpu->id_mmfr1 = 0x10020302; 1124 cpu->id_mmfr2 = 0x01222000; 1125 cpu->id_isar0 = 0x00100011; 1126 cpu->id_isar1 = 0x12002111; 1127 cpu->id_isar2 = 0x11221011; 1128 cpu->id_isar3 = 0x01102131; 1129 cpu->id_isar4 = 0x141; 1130 cpu->reset_auxcr = 1; 1131 } 1132 1133 static void cortex_m3_initfn(Object *obj) 1134 { 1135 ARMCPU *cpu = ARM_CPU(obj); 1136 set_feature(&cpu->env, ARM_FEATURE_V7); 1137 set_feature(&cpu->env, ARM_FEATURE_M); 1138 cpu->midr = 0x410fc231; 1139 cpu->pmsav7_dregion = 8; 1140 } 1141 1142 static void cortex_m4_initfn(Object *obj) 1143 { 1144 ARMCPU *cpu = ARM_CPU(obj); 1145 1146 set_feature(&cpu->env, ARM_FEATURE_V7); 1147 set_feature(&cpu->env, ARM_FEATURE_M); 1148 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1149 cpu->midr = 0x410fc240; /* r0p0 */ 1150 cpu->pmsav7_dregion = 8; 1151 } 1152 1153 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1154 { 1155 CPUClass *cc = CPU_CLASS(oc); 1156 1157 #ifndef CONFIG_USER_ONLY 1158 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1159 #endif 1160 1161 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1162 } 1163 1164 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1165 /* Dummy the TCM region regs for the moment */ 1166 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1167 .access = PL1_RW, .type = ARM_CP_CONST }, 1168 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1169 .access = PL1_RW, .type = ARM_CP_CONST }, 1170 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 1171 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 1172 REGINFO_SENTINEL 1173 }; 1174 1175 static void cortex_r5_initfn(Object *obj) 1176 { 1177 ARMCPU *cpu = ARM_CPU(obj); 1178 1179 set_feature(&cpu->env, ARM_FEATURE_V7); 1180 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); 1181 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1182 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1183 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1184 cpu->midr = 0x411fc153; /* r1p3 */ 1185 cpu->id_pfr0 = 0x0131; 1186 cpu->id_pfr1 = 0x001; 1187 cpu->id_dfr0 = 0x010400; 1188 cpu->id_afr0 = 0x0; 1189 cpu->id_mmfr0 = 0x0210030; 1190 cpu->id_mmfr1 = 0x00000000; 1191 cpu->id_mmfr2 = 0x01200000; 1192 cpu->id_mmfr3 = 0x0211; 1193 cpu->id_isar0 = 0x2101111; 1194 cpu->id_isar1 = 0x13112111; 1195 cpu->id_isar2 = 0x21232141; 1196 cpu->id_isar3 = 0x01112131; 1197 cpu->id_isar4 = 0x0010142; 1198 cpu->id_isar5 = 0x0; 1199 cpu->mp_is_up = true; 1200 cpu->pmsav7_dregion = 16; 1201 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1202 } 1203 1204 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1205 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1206 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1207 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1208 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1209 REGINFO_SENTINEL 1210 }; 1211 1212 static void cortex_a8_initfn(Object *obj) 1213 { 1214 ARMCPU *cpu = ARM_CPU(obj); 1215 1216 cpu->dtb_compatible = "arm,cortex-a8"; 1217 set_feature(&cpu->env, ARM_FEATURE_V7); 1218 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1219 set_feature(&cpu->env, ARM_FEATURE_NEON); 1220 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1221 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1222 set_feature(&cpu->env, ARM_FEATURE_EL3); 1223 cpu->midr = 0x410fc080; 1224 cpu->reset_fpsid = 0x410330c0; 1225 cpu->mvfr0 = 0x11110222; 1226 cpu->mvfr1 = 0x00011111; 1227 cpu->ctr = 0x82048004; 1228 cpu->reset_sctlr = 0x00c50078; 1229 cpu->id_pfr0 = 0x1031; 1230 cpu->id_pfr1 = 0x11; 1231 cpu->id_dfr0 = 0x400; 1232 cpu->id_afr0 = 0; 1233 cpu->id_mmfr0 = 0x31100003; 1234 cpu->id_mmfr1 = 0x20000000; 1235 cpu->id_mmfr2 = 0x01202000; 1236 cpu->id_mmfr3 = 0x11; 1237 cpu->id_isar0 = 0x00101111; 1238 cpu->id_isar1 = 0x12112111; 1239 cpu->id_isar2 = 0x21232031; 1240 cpu->id_isar3 = 0x11112131; 1241 cpu->id_isar4 = 0x00111142; 1242 cpu->dbgdidr = 0x15141000; 1243 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1244 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1245 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1246 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1247 cpu->reset_auxcr = 2; 1248 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1249 } 1250 1251 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1252 /* power_control should be set to maximum latency. Again, 1253 * default to 0 and set by private hook 1254 */ 1255 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1256 .access = PL1_RW, .resetvalue = 0, 1257 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1258 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1259 .access = PL1_RW, .resetvalue = 0, 1260 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1261 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1262 .access = PL1_RW, .resetvalue = 0, 1263 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1264 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1265 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1266 /* TLB lockdown control */ 1267 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1268 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1269 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1270 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1271 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1272 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1273 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1274 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1275 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1276 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1277 REGINFO_SENTINEL 1278 }; 1279 1280 static void cortex_a9_initfn(Object *obj) 1281 { 1282 ARMCPU *cpu = ARM_CPU(obj); 1283 1284 cpu->dtb_compatible = "arm,cortex-a9"; 1285 set_feature(&cpu->env, ARM_FEATURE_V7); 1286 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1287 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); 1288 set_feature(&cpu->env, ARM_FEATURE_NEON); 1289 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1290 set_feature(&cpu->env, ARM_FEATURE_EL3); 1291 /* Note that A9 supports the MP extensions even for 1292 * A9UP and single-core A9MP (which are both different 1293 * and valid configurations; we don't model A9UP). 1294 */ 1295 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1296 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1297 cpu->midr = 0x410fc090; 1298 cpu->reset_fpsid = 0x41033090; 1299 cpu->mvfr0 = 0x11110222; 1300 cpu->mvfr1 = 0x01111111; 1301 cpu->ctr = 0x80038003; 1302 cpu->reset_sctlr = 0x00c50078; 1303 cpu->id_pfr0 = 0x1031; 1304 cpu->id_pfr1 = 0x11; 1305 cpu->id_dfr0 = 0x000; 1306 cpu->id_afr0 = 0; 1307 cpu->id_mmfr0 = 0x00100103; 1308 cpu->id_mmfr1 = 0x20000000; 1309 cpu->id_mmfr2 = 0x01230000; 1310 cpu->id_mmfr3 = 0x00002111; 1311 cpu->id_isar0 = 0x00101111; 1312 cpu->id_isar1 = 0x13112111; 1313 cpu->id_isar2 = 0x21232041; 1314 cpu->id_isar3 = 0x11112131; 1315 cpu->id_isar4 = 0x00111142; 1316 cpu->dbgdidr = 0x35141000; 1317 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1318 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1319 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1320 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1321 } 1322 1323 #ifndef CONFIG_USER_ONLY 1324 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1325 { 1326 /* Linux wants the number of processors from here. 1327 * Might as well set the interrupt-controller bit too. 1328 */ 1329 return ((smp_cpus - 1) << 24) | (1 << 23); 1330 } 1331 #endif 1332 1333 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1334 #ifndef CONFIG_USER_ONLY 1335 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1336 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1337 .writefn = arm_cp_write_ignore, }, 1338 #endif 1339 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1340 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1341 REGINFO_SENTINEL 1342 }; 1343 1344 static void cortex_a7_initfn(Object *obj) 1345 { 1346 ARMCPU *cpu = ARM_CPU(obj); 1347 1348 cpu->dtb_compatible = "arm,cortex-a7"; 1349 set_feature(&cpu->env, ARM_FEATURE_V7); 1350 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1351 set_feature(&cpu->env, ARM_FEATURE_NEON); 1352 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1353 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1354 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1355 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1356 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1357 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1358 set_feature(&cpu->env, ARM_FEATURE_EL3); 1359 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1360 cpu->midr = 0x410fc075; 1361 cpu->reset_fpsid = 0x41023075; 1362 cpu->mvfr0 = 0x10110222; 1363 cpu->mvfr1 = 0x11111111; 1364 cpu->ctr = 0x84448003; 1365 cpu->reset_sctlr = 0x00c50078; 1366 cpu->id_pfr0 = 0x00001131; 1367 cpu->id_pfr1 = 0x00011011; 1368 cpu->id_dfr0 = 0x02010555; 1369 cpu->pmceid0 = 0x00000000; 1370 cpu->pmceid1 = 0x00000000; 1371 cpu->id_afr0 = 0x00000000; 1372 cpu->id_mmfr0 = 0x10101105; 1373 cpu->id_mmfr1 = 0x40000000; 1374 cpu->id_mmfr2 = 0x01240000; 1375 cpu->id_mmfr3 = 0x02102211; 1376 cpu->id_isar0 = 0x01101110; 1377 cpu->id_isar1 = 0x13112111; 1378 cpu->id_isar2 = 0x21232041; 1379 cpu->id_isar3 = 0x11112131; 1380 cpu->id_isar4 = 0x10011142; 1381 cpu->dbgdidr = 0x3515f005; 1382 cpu->clidr = 0x0a200023; 1383 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1384 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1385 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1386 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1387 } 1388 1389 static void cortex_a15_initfn(Object *obj) 1390 { 1391 ARMCPU *cpu = ARM_CPU(obj); 1392 1393 cpu->dtb_compatible = "arm,cortex-a15"; 1394 set_feature(&cpu->env, ARM_FEATURE_V7); 1395 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1396 set_feature(&cpu->env, ARM_FEATURE_NEON); 1397 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1398 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1399 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1400 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1401 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1402 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1403 set_feature(&cpu->env, ARM_FEATURE_EL3); 1404 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1405 cpu->midr = 0x412fc0f1; 1406 cpu->reset_fpsid = 0x410430f0; 1407 cpu->mvfr0 = 0x10110222; 1408 cpu->mvfr1 = 0x11111111; 1409 cpu->ctr = 0x8444c004; 1410 cpu->reset_sctlr = 0x00c50078; 1411 cpu->id_pfr0 = 0x00001131; 1412 cpu->id_pfr1 = 0x00011011; 1413 cpu->id_dfr0 = 0x02010555; 1414 cpu->pmceid0 = 0x0000000; 1415 cpu->pmceid1 = 0x00000000; 1416 cpu->id_afr0 = 0x00000000; 1417 cpu->id_mmfr0 = 0x10201105; 1418 cpu->id_mmfr1 = 0x20000000; 1419 cpu->id_mmfr2 = 0x01240000; 1420 cpu->id_mmfr3 = 0x02102211; 1421 cpu->id_isar0 = 0x02101110; 1422 cpu->id_isar1 = 0x13112111; 1423 cpu->id_isar2 = 0x21232041; 1424 cpu->id_isar3 = 0x11112131; 1425 cpu->id_isar4 = 0x10011142; 1426 cpu->dbgdidr = 0x3515f021; 1427 cpu->clidr = 0x0a200023; 1428 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1429 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1430 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1431 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 1432 } 1433 1434 static void ti925t_initfn(Object *obj) 1435 { 1436 ARMCPU *cpu = ARM_CPU(obj); 1437 set_feature(&cpu->env, ARM_FEATURE_V4T); 1438 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 1439 cpu->midr = ARM_CPUID_TI925T; 1440 cpu->ctr = 0x5109149; 1441 cpu->reset_sctlr = 0x00000070; 1442 } 1443 1444 static void sa1100_initfn(Object *obj) 1445 { 1446 ARMCPU *cpu = ARM_CPU(obj); 1447 1448 cpu->dtb_compatible = "intel,sa1100"; 1449 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1450 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1451 cpu->midr = 0x4401A11B; 1452 cpu->reset_sctlr = 0x00000070; 1453 } 1454 1455 static void sa1110_initfn(Object *obj) 1456 { 1457 ARMCPU *cpu = ARM_CPU(obj); 1458 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1459 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1460 cpu->midr = 0x6901B119; 1461 cpu->reset_sctlr = 0x00000070; 1462 } 1463 1464 static void pxa250_initfn(Object *obj) 1465 { 1466 ARMCPU *cpu = ARM_CPU(obj); 1467 1468 cpu->dtb_compatible = "marvell,xscale"; 1469 set_feature(&cpu->env, ARM_FEATURE_V5); 1470 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1471 cpu->midr = 0x69052100; 1472 cpu->ctr = 0xd172172; 1473 cpu->reset_sctlr = 0x00000078; 1474 } 1475 1476 static void pxa255_initfn(Object *obj) 1477 { 1478 ARMCPU *cpu = ARM_CPU(obj); 1479 1480 cpu->dtb_compatible = "marvell,xscale"; 1481 set_feature(&cpu->env, ARM_FEATURE_V5); 1482 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1483 cpu->midr = 0x69052d00; 1484 cpu->ctr = 0xd172172; 1485 cpu->reset_sctlr = 0x00000078; 1486 } 1487 1488 static void pxa260_initfn(Object *obj) 1489 { 1490 ARMCPU *cpu = ARM_CPU(obj); 1491 1492 cpu->dtb_compatible = "marvell,xscale"; 1493 set_feature(&cpu->env, ARM_FEATURE_V5); 1494 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1495 cpu->midr = 0x69052903; 1496 cpu->ctr = 0xd172172; 1497 cpu->reset_sctlr = 0x00000078; 1498 } 1499 1500 static void pxa261_initfn(Object *obj) 1501 { 1502 ARMCPU *cpu = ARM_CPU(obj); 1503 1504 cpu->dtb_compatible = "marvell,xscale"; 1505 set_feature(&cpu->env, ARM_FEATURE_V5); 1506 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1507 cpu->midr = 0x69052d05; 1508 cpu->ctr = 0xd172172; 1509 cpu->reset_sctlr = 0x00000078; 1510 } 1511 1512 static void pxa262_initfn(Object *obj) 1513 { 1514 ARMCPU *cpu = ARM_CPU(obj); 1515 1516 cpu->dtb_compatible = "marvell,xscale"; 1517 set_feature(&cpu->env, ARM_FEATURE_V5); 1518 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1519 cpu->midr = 0x69052d06; 1520 cpu->ctr = 0xd172172; 1521 cpu->reset_sctlr = 0x00000078; 1522 } 1523 1524 static void pxa270a0_initfn(Object *obj) 1525 { 1526 ARMCPU *cpu = ARM_CPU(obj); 1527 1528 cpu->dtb_compatible = "marvell,xscale"; 1529 set_feature(&cpu->env, ARM_FEATURE_V5); 1530 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1531 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1532 cpu->midr = 0x69054110; 1533 cpu->ctr = 0xd172172; 1534 cpu->reset_sctlr = 0x00000078; 1535 } 1536 1537 static void pxa270a1_initfn(Object *obj) 1538 { 1539 ARMCPU *cpu = ARM_CPU(obj); 1540 1541 cpu->dtb_compatible = "marvell,xscale"; 1542 set_feature(&cpu->env, ARM_FEATURE_V5); 1543 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1544 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1545 cpu->midr = 0x69054111; 1546 cpu->ctr = 0xd172172; 1547 cpu->reset_sctlr = 0x00000078; 1548 } 1549 1550 static void pxa270b0_initfn(Object *obj) 1551 { 1552 ARMCPU *cpu = ARM_CPU(obj); 1553 1554 cpu->dtb_compatible = "marvell,xscale"; 1555 set_feature(&cpu->env, ARM_FEATURE_V5); 1556 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1557 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1558 cpu->midr = 0x69054112; 1559 cpu->ctr = 0xd172172; 1560 cpu->reset_sctlr = 0x00000078; 1561 } 1562 1563 static void pxa270b1_initfn(Object *obj) 1564 { 1565 ARMCPU *cpu = ARM_CPU(obj); 1566 1567 cpu->dtb_compatible = "marvell,xscale"; 1568 set_feature(&cpu->env, ARM_FEATURE_V5); 1569 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1570 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1571 cpu->midr = 0x69054113; 1572 cpu->ctr = 0xd172172; 1573 cpu->reset_sctlr = 0x00000078; 1574 } 1575 1576 static void pxa270c0_initfn(Object *obj) 1577 { 1578 ARMCPU *cpu = ARM_CPU(obj); 1579 1580 cpu->dtb_compatible = "marvell,xscale"; 1581 set_feature(&cpu->env, ARM_FEATURE_V5); 1582 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1583 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1584 cpu->midr = 0x69054114; 1585 cpu->ctr = 0xd172172; 1586 cpu->reset_sctlr = 0x00000078; 1587 } 1588 1589 static void pxa270c5_initfn(Object *obj) 1590 { 1591 ARMCPU *cpu = ARM_CPU(obj); 1592 1593 cpu->dtb_compatible = "marvell,xscale"; 1594 set_feature(&cpu->env, ARM_FEATURE_V5); 1595 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1596 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1597 cpu->midr = 0x69054117; 1598 cpu->ctr = 0xd172172; 1599 cpu->reset_sctlr = 0x00000078; 1600 } 1601 1602 #ifdef CONFIG_USER_ONLY 1603 static void arm_any_initfn(Object *obj) 1604 { 1605 ARMCPU *cpu = ARM_CPU(obj); 1606 set_feature(&cpu->env, ARM_FEATURE_V8); 1607 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1608 set_feature(&cpu->env, ARM_FEATURE_NEON); 1609 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1610 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 1611 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 1612 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 1613 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 1614 set_feature(&cpu->env, ARM_FEATURE_CRC); 1615 cpu->midr = 0xffffffff; 1616 } 1617 #endif 1618 1619 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 1620 1621 typedef struct ARMCPUInfo { 1622 const char *name; 1623 void (*initfn)(Object *obj); 1624 void (*class_init)(ObjectClass *oc, void *data); 1625 } ARMCPUInfo; 1626 1627 static const ARMCPUInfo arm_cpus[] = { 1628 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1629 { .name = "arm926", .initfn = arm926_initfn }, 1630 { .name = "arm946", .initfn = arm946_initfn }, 1631 { .name = "arm1026", .initfn = arm1026_initfn }, 1632 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1633 * older core than plain "arm1136". In particular this does not 1634 * have the v6K features. 1635 */ 1636 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1637 { .name = "arm1136", .initfn = arm1136_initfn }, 1638 { .name = "arm1176", .initfn = arm1176_initfn }, 1639 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1640 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 1641 .class_init = arm_v7m_class_init }, 1642 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 1643 .class_init = arm_v7m_class_init }, 1644 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1645 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1646 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1647 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1648 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1649 { .name = "ti925t", .initfn = ti925t_initfn }, 1650 { .name = "sa1100", .initfn = sa1100_initfn }, 1651 { .name = "sa1110", .initfn = sa1110_initfn }, 1652 { .name = "pxa250", .initfn = pxa250_initfn }, 1653 { .name = "pxa255", .initfn = pxa255_initfn }, 1654 { .name = "pxa260", .initfn = pxa260_initfn }, 1655 { .name = "pxa261", .initfn = pxa261_initfn }, 1656 { .name = "pxa262", .initfn = pxa262_initfn }, 1657 /* "pxa270" is an alias for "pxa270-a0" */ 1658 { .name = "pxa270", .initfn = pxa270a0_initfn }, 1659 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 1660 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 1661 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 1662 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 1663 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 1664 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 1665 #ifdef CONFIG_USER_ONLY 1666 { .name = "any", .initfn = arm_any_initfn }, 1667 #endif 1668 #endif 1669 { .name = NULL } 1670 }; 1671 1672 static Property arm_cpu_properties[] = { 1673 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 1674 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 1675 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 1676 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 1677 mp_affinity, ARM64_AFFINITY_INVALID), 1678 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 1679 DEFINE_PROP_END_OF_LIST() 1680 }; 1681 1682 #ifdef CONFIG_USER_ONLY 1683 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, 1684 int mmu_idx) 1685 { 1686 ARMCPU *cpu = ARM_CPU(cs); 1687 CPUARMState *env = &cpu->env; 1688 1689 env->exception.vaddress = address; 1690 if (rw == 2) { 1691 cs->exception_index = EXCP_PREFETCH_ABORT; 1692 } else { 1693 cs->exception_index = EXCP_DATA_ABORT; 1694 } 1695 return 1; 1696 } 1697 #endif 1698 1699 static gchar *arm_gdb_arch_name(CPUState *cs) 1700 { 1701 ARMCPU *cpu = ARM_CPU(cs); 1702 CPUARMState *env = &cpu->env; 1703 1704 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 1705 return g_strdup("iwmmxt"); 1706 } 1707 return g_strdup("arm"); 1708 } 1709 1710 static void arm_cpu_class_init(ObjectClass *oc, void *data) 1711 { 1712 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1713 CPUClass *cc = CPU_CLASS(acc); 1714 DeviceClass *dc = DEVICE_CLASS(oc); 1715 1716 acc->parent_realize = dc->realize; 1717 dc->realize = arm_cpu_realizefn; 1718 dc->props = arm_cpu_properties; 1719 1720 acc->parent_reset = cc->reset; 1721 cc->reset = arm_cpu_reset; 1722 1723 cc->class_by_name = arm_cpu_class_by_name; 1724 cc->has_work = arm_cpu_has_work; 1725 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 1726 cc->dump_state = arm_cpu_dump_state; 1727 cc->set_pc = arm_cpu_set_pc; 1728 cc->gdb_read_register = arm_cpu_gdb_read_register; 1729 cc->gdb_write_register = arm_cpu_gdb_write_register; 1730 #ifdef CONFIG_USER_ONLY 1731 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; 1732 #else 1733 cc->do_interrupt = arm_cpu_do_interrupt; 1734 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 1735 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 1736 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 1737 cc->asidx_from_attrs = arm_asidx_from_attrs; 1738 cc->vmsd = &vmstate_arm_cpu; 1739 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 1740 cc->write_elf64_note = arm_cpu_write_elf64_note; 1741 cc->write_elf32_note = arm_cpu_write_elf32_note; 1742 #endif 1743 cc->gdb_num_core_regs = 26; 1744 cc->gdb_core_xml_file = "arm-core.xml"; 1745 cc->gdb_arch_name = arm_gdb_arch_name; 1746 cc->gdb_stop_before_watchpoint = true; 1747 cc->debug_excp_handler = arm_debug_excp_handler; 1748 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 1749 #if !defined(CONFIG_USER_ONLY) 1750 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 1751 #endif 1752 1753 cc->disas_set_info = arm_disas_set_info; 1754 } 1755 1756 static void cpu_register(const ARMCPUInfo *info) 1757 { 1758 TypeInfo type_info = { 1759 .parent = TYPE_ARM_CPU, 1760 .instance_size = sizeof(ARMCPU), 1761 .instance_init = info->initfn, 1762 .class_size = sizeof(ARMCPUClass), 1763 .class_init = info->class_init, 1764 }; 1765 1766 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 1767 type_register(&type_info); 1768 g_free((void *)type_info.name); 1769 } 1770 1771 static const TypeInfo arm_cpu_type_info = { 1772 .name = TYPE_ARM_CPU, 1773 .parent = TYPE_CPU, 1774 .instance_size = sizeof(ARMCPU), 1775 .instance_init = arm_cpu_initfn, 1776 .instance_post_init = arm_cpu_post_init, 1777 .instance_finalize = arm_cpu_finalizefn, 1778 .abstract = true, 1779 .class_size = sizeof(ARMCPUClass), 1780 .class_init = arm_cpu_class_init, 1781 }; 1782 1783 static void arm_cpu_register_types(void) 1784 { 1785 const ARMCPUInfo *info = arm_cpus; 1786 1787 type_register_static(&arm_cpu_type_info); 1788 1789 while (info->name) { 1790 cpu_register(info); 1791 info++; 1792 } 1793 } 1794 1795 type_init(arm_cpu_register_types) 1796