1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/error-report.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "qemu-common.h" 27 #include "exec/exec-all.h" 28 #include "hw/qdev-properties.h" 29 #if !defined(CONFIG_USER_ONLY) 30 #include "hw/loader.h" 31 #endif 32 #include "hw/arm/arm.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/hw_accel.h" 35 #include "kvm_arm.h" 36 37 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 38 { 39 ARMCPU *cpu = ARM_CPU(cs); 40 41 cpu->env.regs[15] = value; 42 } 43 44 static bool arm_cpu_has_work(CPUState *cs) 45 { 46 ARMCPU *cpu = ARM_CPU(cs); 47 48 return (cpu->power_state != PSCI_OFF) 49 && cs->interrupt_request & 50 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 51 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 52 | CPU_INTERRUPT_EXITTB); 53 } 54 55 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 56 void *opaque) 57 { 58 /* We currently only support registering a single hook function */ 59 assert(!cpu->el_change_hook); 60 cpu->el_change_hook = hook; 61 cpu->el_change_hook_opaque = opaque; 62 } 63 64 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 65 { 66 /* Reset a single ARMCPRegInfo register */ 67 ARMCPRegInfo *ri = value; 68 ARMCPU *cpu = opaque; 69 70 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 71 return; 72 } 73 74 if (ri->resetfn) { 75 ri->resetfn(&cpu->env, ri); 76 return; 77 } 78 79 /* A zero offset is never possible as it would be regs[0] 80 * so we use it to indicate that reset is being handled elsewhere. 81 * This is basically only used for fields in non-core coprocessors 82 * (like the pxa2xx ones). 83 */ 84 if (!ri->fieldoffset) { 85 return; 86 } 87 88 if (cpreg_field_is_64bit(ri)) { 89 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 90 } else { 91 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 92 } 93 } 94 95 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 96 { 97 /* Purely an assertion check: we've already done reset once, 98 * so now check that running the reset for the cpreg doesn't 99 * change its value. This traps bugs where two different cpregs 100 * both try to reset the same state field but to different values. 101 */ 102 ARMCPRegInfo *ri = value; 103 ARMCPU *cpu = opaque; 104 uint64_t oldvalue, newvalue; 105 106 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 107 return; 108 } 109 110 oldvalue = read_raw_cp_reg(&cpu->env, ri); 111 cp_reg_reset(key, value, opaque); 112 newvalue = read_raw_cp_reg(&cpu->env, ri); 113 assert(oldvalue == newvalue); 114 } 115 116 /* CPUClass::reset() */ 117 static void arm_cpu_reset(CPUState *s) 118 { 119 ARMCPU *cpu = ARM_CPU(s); 120 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 121 CPUARMState *env = &cpu->env; 122 123 acc->parent_reset(s); 124 125 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 126 127 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 128 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 129 130 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 131 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; 132 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; 133 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; 134 135 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 136 s->halted = cpu->start_powered_off; 137 138 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 139 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 140 } 141 142 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 143 /* 64 bit CPUs always start in 64 bit mode */ 144 env->aarch64 = 1; 145 #if defined(CONFIG_USER_ONLY) 146 env->pstate = PSTATE_MODE_EL0t; 147 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 148 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 149 /* and to the FP/Neon instructions */ 150 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 151 #else 152 /* Reset into the highest available EL */ 153 if (arm_feature(env, ARM_FEATURE_EL3)) { 154 env->pstate = PSTATE_MODE_EL3h; 155 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 156 env->pstate = PSTATE_MODE_EL2h; 157 } else { 158 env->pstate = PSTATE_MODE_EL1h; 159 } 160 env->pc = cpu->rvbar; 161 #endif 162 } else { 163 #if defined(CONFIG_USER_ONLY) 164 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 165 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 166 #endif 167 } 168 169 #if defined(CONFIG_USER_ONLY) 170 env->uncached_cpsr = ARM_CPU_MODE_USR; 171 /* For user mode we must enable access to coprocessors */ 172 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 173 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 174 env->cp15.c15_cpar = 3; 175 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 176 env->cp15.c15_cpar = 1; 177 } 178 #else 179 /* SVC mode with interrupts disabled. */ 180 env->uncached_cpsr = ARM_CPU_MODE_SVC; 181 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 182 183 if (arm_feature(env, ARM_FEATURE_M)) { 184 uint32_t initial_msp; /* Loaded from 0x0 */ 185 uint32_t initial_pc; /* Loaded from 0x4 */ 186 uint8_t *rom; 187 188 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 189 env->v7m.secure = true; 190 } 191 192 /* The reset value of this bit is IMPDEF, but ARM recommends 193 * that it resets to 1, so QEMU always does that rather than making 194 * it dependent on CPU model. 195 */ 196 env->v7m.ccr = R_V7M_CCR_STKALIGN_MASK; 197 198 /* Unlike A/R profile, M profile defines the reset LR value */ 199 env->regs[14] = 0xffffffff; 200 201 /* Load the initial SP and PC from the vector table at address 0 */ 202 rom = rom_ptr(0); 203 if (rom) { 204 /* Address zero is covered by ROM which hasn't yet been 205 * copied into physical memory. 206 */ 207 initial_msp = ldl_p(rom); 208 initial_pc = ldl_p(rom + 4); 209 } else { 210 /* Address zero not covered by a ROM blob, or the ROM blob 211 * is in non-modifiable memory and this is a second reset after 212 * it got copied into memory. In the latter case, rom_ptr 213 * will return a NULL pointer and we should use ldl_phys instead. 214 */ 215 initial_msp = ldl_phys(s->as, 0); 216 initial_pc = ldl_phys(s->as, 4); 217 } 218 219 env->regs[13] = initial_msp & 0xFFFFFFFC; 220 env->regs[15] = initial_pc & ~1; 221 env->thumb = initial_pc & 1; 222 } 223 224 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 225 * executing as AArch32 then check if highvecs are enabled and 226 * adjust the PC accordingly. 227 */ 228 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 229 env->regs[15] = 0xFFFF0000; 230 } 231 232 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 233 #endif 234 235 if (arm_feature(env, ARM_FEATURE_PMSA)) { 236 if (cpu->pmsav7_dregion > 0) { 237 if (arm_feature(env, ARM_FEATURE_V8)) { 238 memset(env->pmsav8.rbar[M_REG_NS], 0, 239 sizeof(*env->pmsav8.rbar[M_REG_NS]) 240 * cpu->pmsav7_dregion); 241 memset(env->pmsav8.rlar[M_REG_NS], 0, 242 sizeof(*env->pmsav8.rlar[M_REG_NS]) 243 * cpu->pmsav7_dregion); 244 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 245 memset(env->pmsav8.rbar[M_REG_S], 0, 246 sizeof(*env->pmsav8.rbar[M_REG_S]) 247 * cpu->pmsav7_dregion); 248 memset(env->pmsav8.rlar[M_REG_S], 0, 249 sizeof(*env->pmsav8.rlar[M_REG_S]) 250 * cpu->pmsav7_dregion); 251 } 252 } else if (arm_feature(env, ARM_FEATURE_V7)) { 253 memset(env->pmsav7.drbar, 0, 254 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 255 memset(env->pmsav7.drsr, 0, 256 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 257 memset(env->pmsav7.dracr, 0, 258 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 259 } 260 } 261 env->pmsav7.rnr[M_REG_NS] = 0; 262 env->pmsav7.rnr[M_REG_S] = 0; 263 env->pmsav8.mair0[M_REG_NS] = 0; 264 env->pmsav8.mair0[M_REG_S] = 0; 265 env->pmsav8.mair1[M_REG_NS] = 0; 266 env->pmsav8.mair1[M_REG_S] = 0; 267 } 268 269 set_flush_to_zero(1, &env->vfp.standard_fp_status); 270 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 271 set_default_nan_mode(1, &env->vfp.standard_fp_status); 272 set_float_detect_tininess(float_tininess_before_rounding, 273 &env->vfp.fp_status); 274 set_float_detect_tininess(float_tininess_before_rounding, 275 &env->vfp.standard_fp_status); 276 #ifndef CONFIG_USER_ONLY 277 if (kvm_enabled()) { 278 kvm_arm_reset_vcpu(cpu); 279 } 280 #endif 281 282 hw_breakpoint_update_all(cpu); 283 hw_watchpoint_update_all(cpu); 284 } 285 286 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 287 { 288 CPUClass *cc = CPU_GET_CLASS(cs); 289 CPUARMState *env = cs->env_ptr; 290 uint32_t cur_el = arm_current_el(env); 291 bool secure = arm_is_secure(env); 292 uint32_t target_el; 293 uint32_t excp_idx; 294 bool ret = false; 295 296 if (interrupt_request & CPU_INTERRUPT_FIQ) { 297 excp_idx = EXCP_FIQ; 298 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 299 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 300 cs->exception_index = excp_idx; 301 env->exception.target_el = target_el; 302 cc->do_interrupt(cs); 303 ret = true; 304 } 305 } 306 if (interrupt_request & CPU_INTERRUPT_HARD) { 307 excp_idx = EXCP_IRQ; 308 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 309 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 310 cs->exception_index = excp_idx; 311 env->exception.target_el = target_el; 312 cc->do_interrupt(cs); 313 ret = true; 314 } 315 } 316 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 317 excp_idx = EXCP_VIRQ; 318 target_el = 1; 319 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 320 cs->exception_index = excp_idx; 321 env->exception.target_el = target_el; 322 cc->do_interrupt(cs); 323 ret = true; 324 } 325 } 326 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 327 excp_idx = EXCP_VFIQ; 328 target_el = 1; 329 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 330 cs->exception_index = excp_idx; 331 env->exception.target_el = target_el; 332 cc->do_interrupt(cs); 333 ret = true; 334 } 335 } 336 337 return ret; 338 } 339 340 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 341 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 342 { 343 CPUClass *cc = CPU_GET_CLASS(cs); 344 ARMCPU *cpu = ARM_CPU(cs); 345 CPUARMState *env = &cpu->env; 346 bool ret = false; 347 348 /* ARMv7-M interrupt masking works differently than -A or -R. 349 * There is no FIQ/IRQ distinction. Instead of I and F bits 350 * masking FIQ and IRQ interrupts, an exception is taken only 351 * if it is higher priority than the current execution priority 352 * (which depends on state like BASEPRI, FAULTMASK and the 353 * currently active exception). 354 */ 355 if (interrupt_request & CPU_INTERRUPT_HARD 356 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 357 cs->exception_index = EXCP_IRQ; 358 cc->do_interrupt(cs); 359 ret = true; 360 } 361 return ret; 362 } 363 #endif 364 365 #ifndef CONFIG_USER_ONLY 366 static void arm_cpu_set_irq(void *opaque, int irq, int level) 367 { 368 ARMCPU *cpu = opaque; 369 CPUARMState *env = &cpu->env; 370 CPUState *cs = CPU(cpu); 371 static const int mask[] = { 372 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 373 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 374 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 375 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 376 }; 377 378 switch (irq) { 379 case ARM_CPU_VIRQ: 380 case ARM_CPU_VFIQ: 381 assert(arm_feature(env, ARM_FEATURE_EL2)); 382 /* fall through */ 383 case ARM_CPU_IRQ: 384 case ARM_CPU_FIQ: 385 if (level) { 386 cpu_interrupt(cs, mask[irq]); 387 } else { 388 cpu_reset_interrupt(cs, mask[irq]); 389 } 390 break; 391 default: 392 g_assert_not_reached(); 393 } 394 } 395 396 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 397 { 398 #ifdef CONFIG_KVM 399 ARMCPU *cpu = opaque; 400 CPUState *cs = CPU(cpu); 401 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 402 403 switch (irq) { 404 case ARM_CPU_IRQ: 405 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 406 break; 407 case ARM_CPU_FIQ: 408 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 409 break; 410 default: 411 g_assert_not_reached(); 412 } 413 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 414 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 415 #endif 416 } 417 418 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 419 { 420 ARMCPU *cpu = ARM_CPU(cs); 421 CPUARMState *env = &cpu->env; 422 423 cpu_synchronize_state(cs); 424 return arm_cpu_data_is_big_endian(env); 425 } 426 427 #endif 428 429 static inline void set_feature(CPUARMState *env, int feature) 430 { 431 env->features |= 1ULL << feature; 432 } 433 434 static inline void unset_feature(CPUARMState *env, int feature) 435 { 436 env->features &= ~(1ULL << feature); 437 } 438 439 static int 440 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 441 { 442 return print_insn_arm(pc | 1, info); 443 } 444 445 static int arm_read_memory_func(bfd_vma memaddr, bfd_byte *b, 446 int length, struct disassemble_info *info) 447 { 448 assert(info->read_memory_inner_func); 449 assert((info->flags & INSN_ARM_BE32) == 0 || length == 2 || length == 4); 450 451 if ((info->flags & INSN_ARM_BE32) != 0 && length == 2) { 452 assert(info->endian == BFD_ENDIAN_LITTLE); 453 return info->read_memory_inner_func(memaddr ^ 2, (bfd_byte *)b, 2, 454 info); 455 } else { 456 return info->read_memory_inner_func(memaddr, b, length, info); 457 } 458 } 459 460 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 461 { 462 ARMCPU *ac = ARM_CPU(cpu); 463 CPUARMState *env = &ac->env; 464 465 if (is_a64(env)) { 466 /* We might not be compiled with the A64 disassembler 467 * because it needs a C++ compiler. Leave print_insn 468 * unset in this case to use the caller default behaviour. 469 */ 470 #if defined(CONFIG_ARM_A64_DIS) 471 info->print_insn = print_insn_arm_a64; 472 #endif 473 } else if (env->thumb) { 474 info->print_insn = print_insn_thumb1; 475 } else { 476 info->print_insn = print_insn_arm; 477 } 478 if (bswap_code(arm_sctlr_b(env))) { 479 #ifdef TARGET_WORDS_BIGENDIAN 480 info->endian = BFD_ENDIAN_LITTLE; 481 #else 482 info->endian = BFD_ENDIAN_BIG; 483 #endif 484 } 485 if (info->read_memory_inner_func == NULL) { 486 info->read_memory_inner_func = info->read_memory_func; 487 info->read_memory_func = arm_read_memory_func; 488 } 489 info->flags &= ~INSN_ARM_BE32; 490 if (arm_sctlr_b(env)) { 491 info->flags |= INSN_ARM_BE32; 492 } 493 } 494 495 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 496 { 497 uint32_t Aff1 = idx / clustersz; 498 uint32_t Aff0 = idx % clustersz; 499 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 500 } 501 502 static void arm_cpu_initfn(Object *obj) 503 { 504 CPUState *cs = CPU(obj); 505 ARMCPU *cpu = ARM_CPU(obj); 506 static bool inited; 507 508 cs->env_ptr = &cpu->env; 509 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 510 g_free, g_free); 511 512 #ifndef CONFIG_USER_ONLY 513 /* Our inbound IRQ and FIQ lines */ 514 if (kvm_enabled()) { 515 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 516 * the same interface as non-KVM CPUs. 517 */ 518 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 519 } else { 520 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 521 } 522 523 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 524 arm_gt_ptimer_cb, cpu); 525 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 526 arm_gt_vtimer_cb, cpu); 527 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 528 arm_gt_htimer_cb, cpu); 529 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 530 arm_gt_stimer_cb, cpu); 531 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 532 ARRAY_SIZE(cpu->gt_timer_outputs)); 533 534 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 535 "gicv3-maintenance-interrupt", 1); 536 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 537 "pmu-interrupt", 1); 538 #endif 539 540 /* DTB consumers generally don't in fact care what the 'compatible' 541 * string is, so always provide some string and trust that a hypothetical 542 * picky DTB consumer will also provide a helpful error message. 543 */ 544 cpu->dtb_compatible = "qemu,unknown"; 545 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 546 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 547 548 if (tcg_enabled()) { 549 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 550 if (!inited) { 551 inited = true; 552 arm_translate_init(); 553 } 554 } 555 } 556 557 static Property arm_cpu_reset_cbar_property = 558 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 559 560 static Property arm_cpu_reset_hivecs_property = 561 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 562 563 static Property arm_cpu_rvbar_property = 564 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 565 566 static Property arm_cpu_has_el2_property = 567 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 568 569 static Property arm_cpu_has_el3_property = 570 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 571 572 static Property arm_cpu_cfgend_property = 573 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 574 575 /* use property name "pmu" to match other archs and virt tools */ 576 static Property arm_cpu_has_pmu_property = 577 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 578 579 static Property arm_cpu_has_mpu_property = 580 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 581 582 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 583 * because the CPU initfn will have already set cpu->pmsav7_dregion to 584 * the right value for that particular CPU type, and we don't want 585 * to override that with an incorrect constant value. 586 */ 587 static Property arm_cpu_pmsav7_dregion_property = 588 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 589 pmsav7_dregion, 590 qdev_prop_uint32, uint32_t); 591 592 static void arm_cpu_post_init(Object *obj) 593 { 594 ARMCPU *cpu = ARM_CPU(obj); 595 596 /* M profile implies PMSA. We have to do this here rather than 597 * in realize with the other feature-implication checks because 598 * we look at the PMSA bit to see if we should add some properties. 599 */ 600 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 601 set_feature(&cpu->env, ARM_FEATURE_PMSA); 602 } 603 604 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 605 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 606 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 607 &error_abort); 608 } 609 610 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 611 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 612 &error_abort); 613 } 614 615 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 616 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 617 &error_abort); 618 } 619 620 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 621 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 622 * prevent "has_el3" from existing on CPUs which cannot support EL3. 623 */ 624 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 625 &error_abort); 626 627 #ifndef CONFIG_USER_ONLY 628 object_property_add_link(obj, "secure-memory", 629 TYPE_MEMORY_REGION, 630 (Object **)&cpu->secure_memory, 631 qdev_prop_allow_set_link_before_realize, 632 OBJ_PROP_LINK_UNREF_ON_RELEASE, 633 &error_abort); 634 #endif 635 } 636 637 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 638 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 639 &error_abort); 640 } 641 642 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 643 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 644 &error_abort); 645 } 646 647 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 648 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 649 &error_abort); 650 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 651 qdev_property_add_static(DEVICE(obj), 652 &arm_cpu_pmsav7_dregion_property, 653 &error_abort); 654 } 655 } 656 657 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 658 &error_abort); 659 } 660 661 static void arm_cpu_finalizefn(Object *obj) 662 { 663 ARMCPU *cpu = ARM_CPU(obj); 664 g_hash_table_destroy(cpu->cp_regs); 665 } 666 667 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 668 { 669 CPUState *cs = CPU(dev); 670 ARMCPU *cpu = ARM_CPU(dev); 671 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 672 CPUARMState *env = &cpu->env; 673 int pagebits; 674 Error *local_err = NULL; 675 676 cpu_exec_realizefn(cs, &local_err); 677 if (local_err != NULL) { 678 error_propagate(errp, local_err); 679 return; 680 } 681 682 /* Some features automatically imply others: */ 683 if (arm_feature(env, ARM_FEATURE_V8)) { 684 set_feature(env, ARM_FEATURE_V7); 685 set_feature(env, ARM_FEATURE_ARM_DIV); 686 set_feature(env, ARM_FEATURE_LPAE); 687 } 688 if (arm_feature(env, ARM_FEATURE_V7)) { 689 set_feature(env, ARM_FEATURE_VAPA); 690 set_feature(env, ARM_FEATURE_THUMB2); 691 set_feature(env, ARM_FEATURE_MPIDR); 692 if (!arm_feature(env, ARM_FEATURE_M)) { 693 set_feature(env, ARM_FEATURE_V6K); 694 } else { 695 set_feature(env, ARM_FEATURE_V6); 696 } 697 698 /* Always define VBAR for V7 CPUs even if it doesn't exist in 699 * non-EL3 configs. This is needed by some legacy boards. 700 */ 701 set_feature(env, ARM_FEATURE_VBAR); 702 } 703 if (arm_feature(env, ARM_FEATURE_V6K)) { 704 set_feature(env, ARM_FEATURE_V6); 705 set_feature(env, ARM_FEATURE_MVFR); 706 } 707 if (arm_feature(env, ARM_FEATURE_V6)) { 708 set_feature(env, ARM_FEATURE_V5); 709 if (!arm_feature(env, ARM_FEATURE_M)) { 710 set_feature(env, ARM_FEATURE_AUXCR); 711 } 712 } 713 if (arm_feature(env, ARM_FEATURE_V5)) { 714 set_feature(env, ARM_FEATURE_V4T); 715 } 716 if (arm_feature(env, ARM_FEATURE_M)) { 717 set_feature(env, ARM_FEATURE_THUMB_DIV); 718 } 719 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { 720 set_feature(env, ARM_FEATURE_THUMB_DIV); 721 } 722 if (arm_feature(env, ARM_FEATURE_VFP4)) { 723 set_feature(env, ARM_FEATURE_VFP3); 724 set_feature(env, ARM_FEATURE_VFP_FP16); 725 } 726 if (arm_feature(env, ARM_FEATURE_VFP3)) { 727 set_feature(env, ARM_FEATURE_VFP); 728 } 729 if (arm_feature(env, ARM_FEATURE_LPAE)) { 730 set_feature(env, ARM_FEATURE_V7MP); 731 set_feature(env, ARM_FEATURE_PXN); 732 } 733 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 734 set_feature(env, ARM_FEATURE_CBAR); 735 } 736 if (arm_feature(env, ARM_FEATURE_THUMB2) && 737 !arm_feature(env, ARM_FEATURE_M)) { 738 set_feature(env, ARM_FEATURE_THUMB_DSP); 739 } 740 741 if (arm_feature(env, ARM_FEATURE_V7) && 742 !arm_feature(env, ARM_FEATURE_M) && 743 !arm_feature(env, ARM_FEATURE_PMSA)) { 744 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 745 * can use 4K pages. 746 */ 747 pagebits = 12; 748 } else { 749 /* For CPUs which might have tiny 1K pages, or which have an 750 * MPU and might have small region sizes, stick with 1K pages. 751 */ 752 pagebits = 10; 753 } 754 if (!set_preferred_target_page_bits(pagebits)) { 755 /* This can only ever happen for hotplugging a CPU, or if 756 * the board code incorrectly creates a CPU which it has 757 * promised via minimum_page_size that it will not. 758 */ 759 error_setg(errp, "This CPU requires a smaller page size than the " 760 "system is using"); 761 return; 762 } 763 764 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 765 * We don't support setting cluster ID ([16..23]) (known as Aff2 766 * in later ARM ARM versions), or any of the higher affinity level fields, 767 * so these bits always RAZ. 768 */ 769 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 770 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 771 ARM_DEFAULT_CPUS_PER_CLUSTER); 772 } 773 774 if (cpu->reset_hivecs) { 775 cpu->reset_sctlr |= (1 << 13); 776 } 777 778 if (cpu->cfgend) { 779 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 780 cpu->reset_sctlr |= SCTLR_EE; 781 } else { 782 cpu->reset_sctlr |= SCTLR_B; 783 } 784 } 785 786 if (!cpu->has_el3) { 787 /* If the has_el3 CPU property is disabled then we need to disable the 788 * feature. 789 */ 790 unset_feature(env, ARM_FEATURE_EL3); 791 792 /* Disable the security extension feature bits in the processor feature 793 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 794 */ 795 cpu->id_pfr1 &= ~0xf0; 796 cpu->id_aa64pfr0 &= ~0xf000; 797 } 798 799 if (!cpu->has_el2) { 800 unset_feature(env, ARM_FEATURE_EL2); 801 } 802 803 if (!cpu->has_pmu) { 804 unset_feature(env, ARM_FEATURE_PMU); 805 cpu->id_aa64dfr0 &= ~0xf00; 806 } 807 808 if (!arm_feature(env, ARM_FEATURE_EL2)) { 809 /* Disable the hypervisor feature bits in the processor feature 810 * registers if we don't have EL2. These are id_pfr1[15:12] and 811 * id_aa64pfr0_el1[11:8]. 812 */ 813 cpu->id_aa64pfr0 &= ~0xf00; 814 cpu->id_pfr1 &= ~0xf000; 815 } 816 817 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 818 * to false or by setting pmsav7-dregion to 0. 819 */ 820 if (!cpu->has_mpu) { 821 cpu->pmsav7_dregion = 0; 822 } 823 if (cpu->pmsav7_dregion == 0) { 824 cpu->has_mpu = false; 825 } 826 827 if (arm_feature(env, ARM_FEATURE_PMSA) && 828 arm_feature(env, ARM_FEATURE_V7)) { 829 uint32_t nr = cpu->pmsav7_dregion; 830 831 if (nr > 0xff) { 832 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 833 return; 834 } 835 836 if (nr) { 837 if (arm_feature(env, ARM_FEATURE_V8)) { 838 /* PMSAv8 */ 839 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 840 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 841 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 842 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 843 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 844 } 845 } else { 846 env->pmsav7.drbar = g_new0(uint32_t, nr); 847 env->pmsav7.drsr = g_new0(uint32_t, nr); 848 env->pmsav7.dracr = g_new0(uint32_t, nr); 849 } 850 } 851 } 852 853 if (arm_feature(env, ARM_FEATURE_EL3)) { 854 set_feature(env, ARM_FEATURE_VBAR); 855 } 856 857 register_cp_regs_for_features(cpu); 858 arm_cpu_register_gdb_regs_for_features(cpu); 859 860 init_cpreg_list(cpu); 861 862 #ifndef CONFIG_USER_ONLY 863 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 864 AddressSpace *as; 865 866 cs->num_ases = 2; 867 868 if (!cpu->secure_memory) { 869 cpu->secure_memory = cs->memory; 870 } 871 as = address_space_init_shareable(cpu->secure_memory, 872 "cpu-secure-memory"); 873 cpu_address_space_init(cs, as, ARMASIdx_S); 874 } else { 875 cs->num_ases = 1; 876 } 877 878 cpu_address_space_init(cs, 879 address_space_init_shareable(cs->memory, 880 "cpu-memory"), 881 ARMASIdx_NS); 882 #endif 883 884 qemu_init_vcpu(cs); 885 cpu_reset(cs); 886 887 acc->parent_realize(dev, errp); 888 } 889 890 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 891 { 892 ObjectClass *oc; 893 char *typename; 894 char **cpuname; 895 896 if (!cpu_model) { 897 return NULL; 898 } 899 900 cpuname = g_strsplit(cpu_model, ",", 1); 901 typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]); 902 oc = object_class_by_name(typename); 903 g_strfreev(cpuname); 904 g_free(typename); 905 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 906 object_class_is_abstract(oc)) { 907 return NULL; 908 } 909 return oc; 910 } 911 912 /* CPU models. These are not needed for the AArch64 linux-user build. */ 913 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 914 915 static void arm926_initfn(Object *obj) 916 { 917 ARMCPU *cpu = ARM_CPU(obj); 918 919 cpu->dtb_compatible = "arm,arm926"; 920 set_feature(&cpu->env, ARM_FEATURE_V5); 921 set_feature(&cpu->env, ARM_FEATURE_VFP); 922 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 923 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 924 cpu->midr = 0x41069265; 925 cpu->reset_fpsid = 0x41011090; 926 cpu->ctr = 0x1dd20d2; 927 cpu->reset_sctlr = 0x00090078; 928 } 929 930 static void arm946_initfn(Object *obj) 931 { 932 ARMCPU *cpu = ARM_CPU(obj); 933 934 cpu->dtb_compatible = "arm,arm946"; 935 set_feature(&cpu->env, ARM_FEATURE_V5); 936 set_feature(&cpu->env, ARM_FEATURE_PMSA); 937 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 938 cpu->midr = 0x41059461; 939 cpu->ctr = 0x0f004006; 940 cpu->reset_sctlr = 0x00000078; 941 } 942 943 static void arm1026_initfn(Object *obj) 944 { 945 ARMCPU *cpu = ARM_CPU(obj); 946 947 cpu->dtb_compatible = "arm,arm1026"; 948 set_feature(&cpu->env, ARM_FEATURE_V5); 949 set_feature(&cpu->env, ARM_FEATURE_VFP); 950 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 951 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 952 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 953 cpu->midr = 0x4106a262; 954 cpu->reset_fpsid = 0x410110a0; 955 cpu->ctr = 0x1dd20d2; 956 cpu->reset_sctlr = 0x00090078; 957 cpu->reset_auxcr = 1; 958 { 959 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 960 ARMCPRegInfo ifar = { 961 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 962 .access = PL1_RW, 963 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 964 .resetvalue = 0 965 }; 966 define_one_arm_cp_reg(cpu, &ifar); 967 } 968 } 969 970 static void arm1136_r2_initfn(Object *obj) 971 { 972 ARMCPU *cpu = ARM_CPU(obj); 973 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 974 * older core than plain "arm1136". In particular this does not 975 * have the v6K features. 976 * These ID register values are correct for 1136 but may be wrong 977 * for 1136_r2 (in particular r0p2 does not actually implement most 978 * of the ID registers). 979 */ 980 981 cpu->dtb_compatible = "arm,arm1136"; 982 set_feature(&cpu->env, ARM_FEATURE_V6); 983 set_feature(&cpu->env, ARM_FEATURE_VFP); 984 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 985 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 986 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 987 cpu->midr = 0x4107b362; 988 cpu->reset_fpsid = 0x410120b4; 989 cpu->mvfr0 = 0x11111111; 990 cpu->mvfr1 = 0x00000000; 991 cpu->ctr = 0x1dd20d2; 992 cpu->reset_sctlr = 0x00050078; 993 cpu->id_pfr0 = 0x111; 994 cpu->id_pfr1 = 0x1; 995 cpu->id_dfr0 = 0x2; 996 cpu->id_afr0 = 0x3; 997 cpu->id_mmfr0 = 0x01130003; 998 cpu->id_mmfr1 = 0x10030302; 999 cpu->id_mmfr2 = 0x01222110; 1000 cpu->id_isar0 = 0x00140011; 1001 cpu->id_isar1 = 0x12002111; 1002 cpu->id_isar2 = 0x11231111; 1003 cpu->id_isar3 = 0x01102131; 1004 cpu->id_isar4 = 0x141; 1005 cpu->reset_auxcr = 7; 1006 } 1007 1008 static void arm1136_initfn(Object *obj) 1009 { 1010 ARMCPU *cpu = ARM_CPU(obj); 1011 1012 cpu->dtb_compatible = "arm,arm1136"; 1013 set_feature(&cpu->env, ARM_FEATURE_V6K); 1014 set_feature(&cpu->env, ARM_FEATURE_V6); 1015 set_feature(&cpu->env, ARM_FEATURE_VFP); 1016 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1017 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1018 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1019 cpu->midr = 0x4117b363; 1020 cpu->reset_fpsid = 0x410120b4; 1021 cpu->mvfr0 = 0x11111111; 1022 cpu->mvfr1 = 0x00000000; 1023 cpu->ctr = 0x1dd20d2; 1024 cpu->reset_sctlr = 0x00050078; 1025 cpu->id_pfr0 = 0x111; 1026 cpu->id_pfr1 = 0x1; 1027 cpu->id_dfr0 = 0x2; 1028 cpu->id_afr0 = 0x3; 1029 cpu->id_mmfr0 = 0x01130003; 1030 cpu->id_mmfr1 = 0x10030302; 1031 cpu->id_mmfr2 = 0x01222110; 1032 cpu->id_isar0 = 0x00140011; 1033 cpu->id_isar1 = 0x12002111; 1034 cpu->id_isar2 = 0x11231111; 1035 cpu->id_isar3 = 0x01102131; 1036 cpu->id_isar4 = 0x141; 1037 cpu->reset_auxcr = 7; 1038 } 1039 1040 static void arm1176_initfn(Object *obj) 1041 { 1042 ARMCPU *cpu = ARM_CPU(obj); 1043 1044 cpu->dtb_compatible = "arm,arm1176"; 1045 set_feature(&cpu->env, ARM_FEATURE_V6K); 1046 set_feature(&cpu->env, ARM_FEATURE_VFP); 1047 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1048 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1049 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1050 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1051 set_feature(&cpu->env, ARM_FEATURE_EL3); 1052 cpu->midr = 0x410fb767; 1053 cpu->reset_fpsid = 0x410120b5; 1054 cpu->mvfr0 = 0x11111111; 1055 cpu->mvfr1 = 0x00000000; 1056 cpu->ctr = 0x1dd20d2; 1057 cpu->reset_sctlr = 0x00050078; 1058 cpu->id_pfr0 = 0x111; 1059 cpu->id_pfr1 = 0x11; 1060 cpu->id_dfr0 = 0x33; 1061 cpu->id_afr0 = 0; 1062 cpu->id_mmfr0 = 0x01130003; 1063 cpu->id_mmfr1 = 0x10030302; 1064 cpu->id_mmfr2 = 0x01222100; 1065 cpu->id_isar0 = 0x0140011; 1066 cpu->id_isar1 = 0x12002111; 1067 cpu->id_isar2 = 0x11231121; 1068 cpu->id_isar3 = 0x01102131; 1069 cpu->id_isar4 = 0x01141; 1070 cpu->reset_auxcr = 7; 1071 } 1072 1073 static void arm11mpcore_initfn(Object *obj) 1074 { 1075 ARMCPU *cpu = ARM_CPU(obj); 1076 1077 cpu->dtb_compatible = "arm,arm11mpcore"; 1078 set_feature(&cpu->env, ARM_FEATURE_V6K); 1079 set_feature(&cpu->env, ARM_FEATURE_VFP); 1080 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1081 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1082 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1083 cpu->midr = 0x410fb022; 1084 cpu->reset_fpsid = 0x410120b4; 1085 cpu->mvfr0 = 0x11111111; 1086 cpu->mvfr1 = 0x00000000; 1087 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1088 cpu->id_pfr0 = 0x111; 1089 cpu->id_pfr1 = 0x1; 1090 cpu->id_dfr0 = 0; 1091 cpu->id_afr0 = 0x2; 1092 cpu->id_mmfr0 = 0x01100103; 1093 cpu->id_mmfr1 = 0x10020302; 1094 cpu->id_mmfr2 = 0x01222000; 1095 cpu->id_isar0 = 0x00100011; 1096 cpu->id_isar1 = 0x12002111; 1097 cpu->id_isar2 = 0x11221011; 1098 cpu->id_isar3 = 0x01102131; 1099 cpu->id_isar4 = 0x141; 1100 cpu->reset_auxcr = 1; 1101 } 1102 1103 static void cortex_m3_initfn(Object *obj) 1104 { 1105 ARMCPU *cpu = ARM_CPU(obj); 1106 set_feature(&cpu->env, ARM_FEATURE_V7); 1107 set_feature(&cpu->env, ARM_FEATURE_M); 1108 cpu->midr = 0x410fc231; 1109 cpu->pmsav7_dregion = 8; 1110 } 1111 1112 static void cortex_m4_initfn(Object *obj) 1113 { 1114 ARMCPU *cpu = ARM_CPU(obj); 1115 1116 set_feature(&cpu->env, ARM_FEATURE_V7); 1117 set_feature(&cpu->env, ARM_FEATURE_M); 1118 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1119 cpu->midr = 0x410fc240; /* r0p0 */ 1120 cpu->pmsav7_dregion = 8; 1121 } 1122 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1123 { 1124 CPUClass *cc = CPU_CLASS(oc); 1125 1126 #ifndef CONFIG_USER_ONLY 1127 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1128 #endif 1129 1130 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1131 } 1132 1133 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1134 /* Dummy the TCM region regs for the moment */ 1135 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1136 .access = PL1_RW, .type = ARM_CP_CONST }, 1137 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1138 .access = PL1_RW, .type = ARM_CP_CONST }, 1139 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 1140 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 1141 REGINFO_SENTINEL 1142 }; 1143 1144 static void cortex_r5_initfn(Object *obj) 1145 { 1146 ARMCPU *cpu = ARM_CPU(obj); 1147 1148 set_feature(&cpu->env, ARM_FEATURE_V7); 1149 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); 1150 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1151 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1152 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1153 cpu->midr = 0x411fc153; /* r1p3 */ 1154 cpu->id_pfr0 = 0x0131; 1155 cpu->id_pfr1 = 0x001; 1156 cpu->id_dfr0 = 0x010400; 1157 cpu->id_afr0 = 0x0; 1158 cpu->id_mmfr0 = 0x0210030; 1159 cpu->id_mmfr1 = 0x00000000; 1160 cpu->id_mmfr2 = 0x01200000; 1161 cpu->id_mmfr3 = 0x0211; 1162 cpu->id_isar0 = 0x2101111; 1163 cpu->id_isar1 = 0x13112111; 1164 cpu->id_isar2 = 0x21232141; 1165 cpu->id_isar3 = 0x01112131; 1166 cpu->id_isar4 = 0x0010142; 1167 cpu->id_isar5 = 0x0; 1168 cpu->mp_is_up = true; 1169 cpu->pmsav7_dregion = 16; 1170 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1171 } 1172 1173 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1174 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1175 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1176 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1177 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1178 REGINFO_SENTINEL 1179 }; 1180 1181 static void cortex_a8_initfn(Object *obj) 1182 { 1183 ARMCPU *cpu = ARM_CPU(obj); 1184 1185 cpu->dtb_compatible = "arm,cortex-a8"; 1186 set_feature(&cpu->env, ARM_FEATURE_V7); 1187 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1188 set_feature(&cpu->env, ARM_FEATURE_NEON); 1189 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1190 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1191 set_feature(&cpu->env, ARM_FEATURE_EL3); 1192 cpu->midr = 0x410fc080; 1193 cpu->reset_fpsid = 0x410330c0; 1194 cpu->mvfr0 = 0x11110222; 1195 cpu->mvfr1 = 0x00011111; 1196 cpu->ctr = 0x82048004; 1197 cpu->reset_sctlr = 0x00c50078; 1198 cpu->id_pfr0 = 0x1031; 1199 cpu->id_pfr1 = 0x11; 1200 cpu->id_dfr0 = 0x400; 1201 cpu->id_afr0 = 0; 1202 cpu->id_mmfr0 = 0x31100003; 1203 cpu->id_mmfr1 = 0x20000000; 1204 cpu->id_mmfr2 = 0x01202000; 1205 cpu->id_mmfr3 = 0x11; 1206 cpu->id_isar0 = 0x00101111; 1207 cpu->id_isar1 = 0x12112111; 1208 cpu->id_isar2 = 0x21232031; 1209 cpu->id_isar3 = 0x11112131; 1210 cpu->id_isar4 = 0x00111142; 1211 cpu->dbgdidr = 0x15141000; 1212 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1213 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1214 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1215 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1216 cpu->reset_auxcr = 2; 1217 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1218 } 1219 1220 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1221 /* power_control should be set to maximum latency. Again, 1222 * default to 0 and set by private hook 1223 */ 1224 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1225 .access = PL1_RW, .resetvalue = 0, 1226 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1227 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1228 .access = PL1_RW, .resetvalue = 0, 1229 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1230 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1231 .access = PL1_RW, .resetvalue = 0, 1232 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1233 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1234 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1235 /* TLB lockdown control */ 1236 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1237 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1238 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1239 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1240 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1241 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1242 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1243 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1244 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1245 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1246 REGINFO_SENTINEL 1247 }; 1248 1249 static void cortex_a9_initfn(Object *obj) 1250 { 1251 ARMCPU *cpu = ARM_CPU(obj); 1252 1253 cpu->dtb_compatible = "arm,cortex-a9"; 1254 set_feature(&cpu->env, ARM_FEATURE_V7); 1255 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1256 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); 1257 set_feature(&cpu->env, ARM_FEATURE_NEON); 1258 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1259 set_feature(&cpu->env, ARM_FEATURE_EL3); 1260 /* Note that A9 supports the MP extensions even for 1261 * A9UP and single-core A9MP (which are both different 1262 * and valid configurations; we don't model A9UP). 1263 */ 1264 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1265 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1266 cpu->midr = 0x410fc090; 1267 cpu->reset_fpsid = 0x41033090; 1268 cpu->mvfr0 = 0x11110222; 1269 cpu->mvfr1 = 0x01111111; 1270 cpu->ctr = 0x80038003; 1271 cpu->reset_sctlr = 0x00c50078; 1272 cpu->id_pfr0 = 0x1031; 1273 cpu->id_pfr1 = 0x11; 1274 cpu->id_dfr0 = 0x000; 1275 cpu->id_afr0 = 0; 1276 cpu->id_mmfr0 = 0x00100103; 1277 cpu->id_mmfr1 = 0x20000000; 1278 cpu->id_mmfr2 = 0x01230000; 1279 cpu->id_mmfr3 = 0x00002111; 1280 cpu->id_isar0 = 0x00101111; 1281 cpu->id_isar1 = 0x13112111; 1282 cpu->id_isar2 = 0x21232041; 1283 cpu->id_isar3 = 0x11112131; 1284 cpu->id_isar4 = 0x00111142; 1285 cpu->dbgdidr = 0x35141000; 1286 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1287 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1288 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1289 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1290 } 1291 1292 #ifndef CONFIG_USER_ONLY 1293 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1294 { 1295 /* Linux wants the number of processors from here. 1296 * Might as well set the interrupt-controller bit too. 1297 */ 1298 return ((smp_cpus - 1) << 24) | (1 << 23); 1299 } 1300 #endif 1301 1302 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1303 #ifndef CONFIG_USER_ONLY 1304 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1305 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1306 .writefn = arm_cp_write_ignore, }, 1307 #endif 1308 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1309 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1310 REGINFO_SENTINEL 1311 }; 1312 1313 static void cortex_a7_initfn(Object *obj) 1314 { 1315 ARMCPU *cpu = ARM_CPU(obj); 1316 1317 cpu->dtb_compatible = "arm,cortex-a7"; 1318 set_feature(&cpu->env, ARM_FEATURE_V7); 1319 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1320 set_feature(&cpu->env, ARM_FEATURE_NEON); 1321 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1322 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1323 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1324 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1325 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1326 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1327 set_feature(&cpu->env, ARM_FEATURE_EL3); 1328 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1329 cpu->midr = 0x410fc075; 1330 cpu->reset_fpsid = 0x41023075; 1331 cpu->mvfr0 = 0x10110222; 1332 cpu->mvfr1 = 0x11111111; 1333 cpu->ctr = 0x84448003; 1334 cpu->reset_sctlr = 0x00c50078; 1335 cpu->id_pfr0 = 0x00001131; 1336 cpu->id_pfr1 = 0x00011011; 1337 cpu->id_dfr0 = 0x02010555; 1338 cpu->pmceid0 = 0x00000000; 1339 cpu->pmceid1 = 0x00000000; 1340 cpu->id_afr0 = 0x00000000; 1341 cpu->id_mmfr0 = 0x10101105; 1342 cpu->id_mmfr1 = 0x40000000; 1343 cpu->id_mmfr2 = 0x01240000; 1344 cpu->id_mmfr3 = 0x02102211; 1345 cpu->id_isar0 = 0x01101110; 1346 cpu->id_isar1 = 0x13112111; 1347 cpu->id_isar2 = 0x21232041; 1348 cpu->id_isar3 = 0x11112131; 1349 cpu->id_isar4 = 0x10011142; 1350 cpu->dbgdidr = 0x3515f005; 1351 cpu->clidr = 0x0a200023; 1352 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1353 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1354 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1355 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1356 } 1357 1358 static void cortex_a15_initfn(Object *obj) 1359 { 1360 ARMCPU *cpu = ARM_CPU(obj); 1361 1362 cpu->dtb_compatible = "arm,cortex-a15"; 1363 set_feature(&cpu->env, ARM_FEATURE_V7); 1364 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1365 set_feature(&cpu->env, ARM_FEATURE_NEON); 1366 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1367 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1368 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1369 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1370 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1371 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1372 set_feature(&cpu->env, ARM_FEATURE_EL3); 1373 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1374 cpu->midr = 0x412fc0f1; 1375 cpu->reset_fpsid = 0x410430f0; 1376 cpu->mvfr0 = 0x10110222; 1377 cpu->mvfr1 = 0x11111111; 1378 cpu->ctr = 0x8444c004; 1379 cpu->reset_sctlr = 0x00c50078; 1380 cpu->id_pfr0 = 0x00001131; 1381 cpu->id_pfr1 = 0x00011011; 1382 cpu->id_dfr0 = 0x02010555; 1383 cpu->pmceid0 = 0x0000000; 1384 cpu->pmceid1 = 0x00000000; 1385 cpu->id_afr0 = 0x00000000; 1386 cpu->id_mmfr0 = 0x10201105; 1387 cpu->id_mmfr1 = 0x20000000; 1388 cpu->id_mmfr2 = 0x01240000; 1389 cpu->id_mmfr3 = 0x02102211; 1390 cpu->id_isar0 = 0x02101110; 1391 cpu->id_isar1 = 0x13112111; 1392 cpu->id_isar2 = 0x21232041; 1393 cpu->id_isar3 = 0x11112131; 1394 cpu->id_isar4 = 0x10011142; 1395 cpu->dbgdidr = 0x3515f021; 1396 cpu->clidr = 0x0a200023; 1397 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1398 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1399 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1400 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 1401 } 1402 1403 static void ti925t_initfn(Object *obj) 1404 { 1405 ARMCPU *cpu = ARM_CPU(obj); 1406 set_feature(&cpu->env, ARM_FEATURE_V4T); 1407 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 1408 cpu->midr = ARM_CPUID_TI925T; 1409 cpu->ctr = 0x5109149; 1410 cpu->reset_sctlr = 0x00000070; 1411 } 1412 1413 static void sa1100_initfn(Object *obj) 1414 { 1415 ARMCPU *cpu = ARM_CPU(obj); 1416 1417 cpu->dtb_compatible = "intel,sa1100"; 1418 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1419 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1420 cpu->midr = 0x4401A11B; 1421 cpu->reset_sctlr = 0x00000070; 1422 } 1423 1424 static void sa1110_initfn(Object *obj) 1425 { 1426 ARMCPU *cpu = ARM_CPU(obj); 1427 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1428 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1429 cpu->midr = 0x6901B119; 1430 cpu->reset_sctlr = 0x00000070; 1431 } 1432 1433 static void pxa250_initfn(Object *obj) 1434 { 1435 ARMCPU *cpu = ARM_CPU(obj); 1436 1437 cpu->dtb_compatible = "marvell,xscale"; 1438 set_feature(&cpu->env, ARM_FEATURE_V5); 1439 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1440 cpu->midr = 0x69052100; 1441 cpu->ctr = 0xd172172; 1442 cpu->reset_sctlr = 0x00000078; 1443 } 1444 1445 static void pxa255_initfn(Object *obj) 1446 { 1447 ARMCPU *cpu = ARM_CPU(obj); 1448 1449 cpu->dtb_compatible = "marvell,xscale"; 1450 set_feature(&cpu->env, ARM_FEATURE_V5); 1451 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1452 cpu->midr = 0x69052d00; 1453 cpu->ctr = 0xd172172; 1454 cpu->reset_sctlr = 0x00000078; 1455 } 1456 1457 static void pxa260_initfn(Object *obj) 1458 { 1459 ARMCPU *cpu = ARM_CPU(obj); 1460 1461 cpu->dtb_compatible = "marvell,xscale"; 1462 set_feature(&cpu->env, ARM_FEATURE_V5); 1463 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1464 cpu->midr = 0x69052903; 1465 cpu->ctr = 0xd172172; 1466 cpu->reset_sctlr = 0x00000078; 1467 } 1468 1469 static void pxa261_initfn(Object *obj) 1470 { 1471 ARMCPU *cpu = ARM_CPU(obj); 1472 1473 cpu->dtb_compatible = "marvell,xscale"; 1474 set_feature(&cpu->env, ARM_FEATURE_V5); 1475 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1476 cpu->midr = 0x69052d05; 1477 cpu->ctr = 0xd172172; 1478 cpu->reset_sctlr = 0x00000078; 1479 } 1480 1481 static void pxa262_initfn(Object *obj) 1482 { 1483 ARMCPU *cpu = ARM_CPU(obj); 1484 1485 cpu->dtb_compatible = "marvell,xscale"; 1486 set_feature(&cpu->env, ARM_FEATURE_V5); 1487 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1488 cpu->midr = 0x69052d06; 1489 cpu->ctr = 0xd172172; 1490 cpu->reset_sctlr = 0x00000078; 1491 } 1492 1493 static void pxa270a0_initfn(Object *obj) 1494 { 1495 ARMCPU *cpu = ARM_CPU(obj); 1496 1497 cpu->dtb_compatible = "marvell,xscale"; 1498 set_feature(&cpu->env, ARM_FEATURE_V5); 1499 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1500 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1501 cpu->midr = 0x69054110; 1502 cpu->ctr = 0xd172172; 1503 cpu->reset_sctlr = 0x00000078; 1504 } 1505 1506 static void pxa270a1_initfn(Object *obj) 1507 { 1508 ARMCPU *cpu = ARM_CPU(obj); 1509 1510 cpu->dtb_compatible = "marvell,xscale"; 1511 set_feature(&cpu->env, ARM_FEATURE_V5); 1512 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1513 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1514 cpu->midr = 0x69054111; 1515 cpu->ctr = 0xd172172; 1516 cpu->reset_sctlr = 0x00000078; 1517 } 1518 1519 static void pxa270b0_initfn(Object *obj) 1520 { 1521 ARMCPU *cpu = ARM_CPU(obj); 1522 1523 cpu->dtb_compatible = "marvell,xscale"; 1524 set_feature(&cpu->env, ARM_FEATURE_V5); 1525 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1526 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1527 cpu->midr = 0x69054112; 1528 cpu->ctr = 0xd172172; 1529 cpu->reset_sctlr = 0x00000078; 1530 } 1531 1532 static void pxa270b1_initfn(Object *obj) 1533 { 1534 ARMCPU *cpu = ARM_CPU(obj); 1535 1536 cpu->dtb_compatible = "marvell,xscale"; 1537 set_feature(&cpu->env, ARM_FEATURE_V5); 1538 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1539 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1540 cpu->midr = 0x69054113; 1541 cpu->ctr = 0xd172172; 1542 cpu->reset_sctlr = 0x00000078; 1543 } 1544 1545 static void pxa270c0_initfn(Object *obj) 1546 { 1547 ARMCPU *cpu = ARM_CPU(obj); 1548 1549 cpu->dtb_compatible = "marvell,xscale"; 1550 set_feature(&cpu->env, ARM_FEATURE_V5); 1551 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1552 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1553 cpu->midr = 0x69054114; 1554 cpu->ctr = 0xd172172; 1555 cpu->reset_sctlr = 0x00000078; 1556 } 1557 1558 static void pxa270c5_initfn(Object *obj) 1559 { 1560 ARMCPU *cpu = ARM_CPU(obj); 1561 1562 cpu->dtb_compatible = "marvell,xscale"; 1563 set_feature(&cpu->env, ARM_FEATURE_V5); 1564 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1565 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1566 cpu->midr = 0x69054117; 1567 cpu->ctr = 0xd172172; 1568 cpu->reset_sctlr = 0x00000078; 1569 } 1570 1571 #ifdef CONFIG_USER_ONLY 1572 static void arm_any_initfn(Object *obj) 1573 { 1574 ARMCPU *cpu = ARM_CPU(obj); 1575 set_feature(&cpu->env, ARM_FEATURE_V8); 1576 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1577 set_feature(&cpu->env, ARM_FEATURE_NEON); 1578 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1579 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 1580 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 1581 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 1582 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 1583 set_feature(&cpu->env, ARM_FEATURE_CRC); 1584 cpu->midr = 0xffffffff; 1585 } 1586 #endif 1587 1588 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 1589 1590 typedef struct ARMCPUInfo { 1591 const char *name; 1592 void (*initfn)(Object *obj); 1593 void (*class_init)(ObjectClass *oc, void *data); 1594 } ARMCPUInfo; 1595 1596 static const ARMCPUInfo arm_cpus[] = { 1597 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1598 { .name = "arm926", .initfn = arm926_initfn }, 1599 { .name = "arm946", .initfn = arm946_initfn }, 1600 { .name = "arm1026", .initfn = arm1026_initfn }, 1601 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1602 * older core than plain "arm1136". In particular this does not 1603 * have the v6K features. 1604 */ 1605 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1606 { .name = "arm1136", .initfn = arm1136_initfn }, 1607 { .name = "arm1176", .initfn = arm1176_initfn }, 1608 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1609 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 1610 .class_init = arm_v7m_class_init }, 1611 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 1612 .class_init = arm_v7m_class_init }, 1613 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1614 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1615 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1616 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1617 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1618 { .name = "ti925t", .initfn = ti925t_initfn }, 1619 { .name = "sa1100", .initfn = sa1100_initfn }, 1620 { .name = "sa1110", .initfn = sa1110_initfn }, 1621 { .name = "pxa250", .initfn = pxa250_initfn }, 1622 { .name = "pxa255", .initfn = pxa255_initfn }, 1623 { .name = "pxa260", .initfn = pxa260_initfn }, 1624 { .name = "pxa261", .initfn = pxa261_initfn }, 1625 { .name = "pxa262", .initfn = pxa262_initfn }, 1626 /* "pxa270" is an alias for "pxa270-a0" */ 1627 { .name = "pxa270", .initfn = pxa270a0_initfn }, 1628 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 1629 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 1630 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 1631 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 1632 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 1633 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 1634 #ifdef CONFIG_USER_ONLY 1635 { .name = "any", .initfn = arm_any_initfn }, 1636 #endif 1637 #endif 1638 { .name = NULL } 1639 }; 1640 1641 static Property arm_cpu_properties[] = { 1642 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 1643 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 1644 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 1645 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 1646 mp_affinity, ARM64_AFFINITY_INVALID), 1647 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 1648 DEFINE_PROP_END_OF_LIST() 1649 }; 1650 1651 #ifdef CONFIG_USER_ONLY 1652 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, 1653 int mmu_idx) 1654 { 1655 ARMCPU *cpu = ARM_CPU(cs); 1656 CPUARMState *env = &cpu->env; 1657 1658 env->exception.vaddress = address; 1659 if (rw == 2) { 1660 cs->exception_index = EXCP_PREFETCH_ABORT; 1661 } else { 1662 cs->exception_index = EXCP_DATA_ABORT; 1663 } 1664 return 1; 1665 } 1666 #endif 1667 1668 static gchar *arm_gdb_arch_name(CPUState *cs) 1669 { 1670 ARMCPU *cpu = ARM_CPU(cs); 1671 CPUARMState *env = &cpu->env; 1672 1673 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 1674 return g_strdup("iwmmxt"); 1675 } 1676 return g_strdup("arm"); 1677 } 1678 1679 static void arm_cpu_class_init(ObjectClass *oc, void *data) 1680 { 1681 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1682 CPUClass *cc = CPU_CLASS(acc); 1683 DeviceClass *dc = DEVICE_CLASS(oc); 1684 1685 acc->parent_realize = dc->realize; 1686 dc->realize = arm_cpu_realizefn; 1687 dc->props = arm_cpu_properties; 1688 1689 acc->parent_reset = cc->reset; 1690 cc->reset = arm_cpu_reset; 1691 1692 cc->class_by_name = arm_cpu_class_by_name; 1693 cc->has_work = arm_cpu_has_work; 1694 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 1695 cc->dump_state = arm_cpu_dump_state; 1696 cc->set_pc = arm_cpu_set_pc; 1697 cc->gdb_read_register = arm_cpu_gdb_read_register; 1698 cc->gdb_write_register = arm_cpu_gdb_write_register; 1699 #ifdef CONFIG_USER_ONLY 1700 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; 1701 #else 1702 cc->do_interrupt = arm_cpu_do_interrupt; 1703 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 1704 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 1705 cc->asidx_from_attrs = arm_asidx_from_attrs; 1706 cc->vmsd = &vmstate_arm_cpu; 1707 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 1708 cc->write_elf64_note = arm_cpu_write_elf64_note; 1709 cc->write_elf32_note = arm_cpu_write_elf32_note; 1710 #endif 1711 cc->gdb_num_core_regs = 26; 1712 cc->gdb_core_xml_file = "arm-core.xml"; 1713 cc->gdb_arch_name = arm_gdb_arch_name; 1714 cc->gdb_stop_before_watchpoint = true; 1715 cc->debug_excp_handler = arm_debug_excp_handler; 1716 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 1717 #if !defined(CONFIG_USER_ONLY) 1718 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 1719 #endif 1720 1721 cc->disas_set_info = arm_disas_set_info; 1722 } 1723 1724 static void cpu_register(const ARMCPUInfo *info) 1725 { 1726 TypeInfo type_info = { 1727 .parent = TYPE_ARM_CPU, 1728 .instance_size = sizeof(ARMCPU), 1729 .instance_init = info->initfn, 1730 .class_size = sizeof(ARMCPUClass), 1731 .class_init = info->class_init, 1732 }; 1733 1734 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 1735 type_register(&type_info); 1736 g_free((void *)type_info.name); 1737 } 1738 1739 static const TypeInfo arm_cpu_type_info = { 1740 .name = TYPE_ARM_CPU, 1741 .parent = TYPE_CPU, 1742 .instance_size = sizeof(ARMCPU), 1743 .instance_init = arm_cpu_initfn, 1744 .instance_post_init = arm_cpu_post_init, 1745 .instance_finalize = arm_cpu_finalizefn, 1746 .abstract = true, 1747 .class_size = sizeof(ARMCPUClass), 1748 .class_init = arm_cpu_class_init, 1749 }; 1750 1751 static void arm_cpu_register_types(void) 1752 { 1753 const ARMCPUInfo *info = arm_cpus; 1754 1755 type_register_static(&arm_cpu_type_info); 1756 1757 while (info->name) { 1758 cpu_register(info); 1759 info++; 1760 } 1761 } 1762 1763 type_init(arm_cpu_register_types) 1764