1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/error-report.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "qemu-common.h" 27 #include "exec/exec-all.h" 28 #include "hw/qdev-properties.h" 29 #if !defined(CONFIG_USER_ONLY) 30 #include "hw/loader.h" 31 #endif 32 #include "hw/arm/arm.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/hw_accel.h" 35 #include "kvm_arm.h" 36 #include "disas/capstone.h" 37 #include "fpu/softfloat.h" 38 39 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 40 { 41 ARMCPU *cpu = ARM_CPU(cs); 42 43 cpu->env.regs[15] = value; 44 } 45 46 static bool arm_cpu_has_work(CPUState *cs) 47 { 48 ARMCPU *cpu = ARM_CPU(cs); 49 50 return (cpu->power_state != PSCI_OFF) 51 && cs->interrupt_request & 52 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 53 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 54 | CPU_INTERRUPT_EXITTB); 55 } 56 57 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, 58 void *opaque) 59 { 60 /* We currently only support registering a single hook function */ 61 assert(!cpu->el_change_hook); 62 cpu->el_change_hook = hook; 63 cpu->el_change_hook_opaque = opaque; 64 } 65 66 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 67 { 68 /* Reset a single ARMCPRegInfo register */ 69 ARMCPRegInfo *ri = value; 70 ARMCPU *cpu = opaque; 71 72 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 73 return; 74 } 75 76 if (ri->resetfn) { 77 ri->resetfn(&cpu->env, ri); 78 return; 79 } 80 81 /* A zero offset is never possible as it would be regs[0] 82 * so we use it to indicate that reset is being handled elsewhere. 83 * This is basically only used for fields in non-core coprocessors 84 * (like the pxa2xx ones). 85 */ 86 if (!ri->fieldoffset) { 87 return; 88 } 89 90 if (cpreg_field_is_64bit(ri)) { 91 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 92 } else { 93 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 94 } 95 } 96 97 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 98 { 99 /* Purely an assertion check: we've already done reset once, 100 * so now check that running the reset for the cpreg doesn't 101 * change its value. This traps bugs where two different cpregs 102 * both try to reset the same state field but to different values. 103 */ 104 ARMCPRegInfo *ri = value; 105 ARMCPU *cpu = opaque; 106 uint64_t oldvalue, newvalue; 107 108 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 109 return; 110 } 111 112 oldvalue = read_raw_cp_reg(&cpu->env, ri); 113 cp_reg_reset(key, value, opaque); 114 newvalue = read_raw_cp_reg(&cpu->env, ri); 115 assert(oldvalue == newvalue); 116 } 117 118 /* CPUClass::reset() */ 119 static void arm_cpu_reset(CPUState *s) 120 { 121 ARMCPU *cpu = ARM_CPU(s); 122 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 123 CPUARMState *env = &cpu->env; 124 125 acc->parent_reset(s); 126 127 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 128 129 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 130 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 131 132 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 133 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; 134 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; 135 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; 136 137 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 138 s->halted = cpu->start_powered_off; 139 140 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 141 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 142 } 143 144 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 145 /* 64 bit CPUs always start in 64 bit mode */ 146 env->aarch64 = 1; 147 #if defined(CONFIG_USER_ONLY) 148 env->pstate = PSTATE_MODE_EL0t; 149 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 150 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 151 /* and to the FP/Neon instructions */ 152 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 153 #else 154 /* Reset into the highest available EL */ 155 if (arm_feature(env, ARM_FEATURE_EL3)) { 156 env->pstate = PSTATE_MODE_EL3h; 157 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 158 env->pstate = PSTATE_MODE_EL2h; 159 } else { 160 env->pstate = PSTATE_MODE_EL1h; 161 } 162 env->pc = cpu->rvbar; 163 #endif 164 } else { 165 #if defined(CONFIG_USER_ONLY) 166 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 167 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 168 #endif 169 } 170 171 #if defined(CONFIG_USER_ONLY) 172 env->uncached_cpsr = ARM_CPU_MODE_USR; 173 /* For user mode we must enable access to coprocessors */ 174 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 175 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 176 env->cp15.c15_cpar = 3; 177 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 178 env->cp15.c15_cpar = 1; 179 } 180 #else 181 /* SVC mode with interrupts disabled. */ 182 env->uncached_cpsr = ARM_CPU_MODE_SVC; 183 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 184 185 if (arm_feature(env, ARM_FEATURE_M)) { 186 uint32_t initial_msp; /* Loaded from 0x0 */ 187 uint32_t initial_pc; /* Loaded from 0x4 */ 188 uint8_t *rom; 189 190 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 191 env->v7m.secure = true; 192 } else { 193 /* This bit resets to 0 if security is supported, but 1 if 194 * it is not. The bit is not present in v7M, but we set it 195 * here so we can avoid having to make checks on it conditional 196 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 197 */ 198 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 199 } 200 201 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 202 * that it resets to 1, so QEMU always does that rather than making 203 * it dependent on CPU model. In v8M it is RES1. 204 */ 205 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 206 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 207 if (arm_feature(env, ARM_FEATURE_V8)) { 208 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 209 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 210 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 211 } 212 213 /* Unlike A/R profile, M profile defines the reset LR value */ 214 env->regs[14] = 0xffffffff; 215 216 /* Load the initial SP and PC from the vector table at address 0 */ 217 rom = rom_ptr(0); 218 if (rom) { 219 /* Address zero is covered by ROM which hasn't yet been 220 * copied into physical memory. 221 */ 222 initial_msp = ldl_p(rom); 223 initial_pc = ldl_p(rom + 4); 224 } else { 225 /* Address zero not covered by a ROM blob, or the ROM blob 226 * is in non-modifiable memory and this is a second reset after 227 * it got copied into memory. In the latter case, rom_ptr 228 * will return a NULL pointer and we should use ldl_phys instead. 229 */ 230 initial_msp = ldl_phys(s->as, 0); 231 initial_pc = ldl_phys(s->as, 4); 232 } 233 234 env->regs[13] = initial_msp & 0xFFFFFFFC; 235 env->regs[15] = initial_pc & ~1; 236 env->thumb = initial_pc & 1; 237 } 238 239 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 240 * executing as AArch32 then check if highvecs are enabled and 241 * adjust the PC accordingly. 242 */ 243 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 244 env->regs[15] = 0xFFFF0000; 245 } 246 247 /* M profile requires that reset clears the exclusive monitor; 248 * A profile does not, but clearing it makes more sense than having it 249 * set with an exclusive access on address zero. 250 */ 251 arm_clear_exclusive(env); 252 253 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 254 #endif 255 256 if (arm_feature(env, ARM_FEATURE_PMSA)) { 257 if (cpu->pmsav7_dregion > 0) { 258 if (arm_feature(env, ARM_FEATURE_V8)) { 259 memset(env->pmsav8.rbar[M_REG_NS], 0, 260 sizeof(*env->pmsav8.rbar[M_REG_NS]) 261 * cpu->pmsav7_dregion); 262 memset(env->pmsav8.rlar[M_REG_NS], 0, 263 sizeof(*env->pmsav8.rlar[M_REG_NS]) 264 * cpu->pmsav7_dregion); 265 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 266 memset(env->pmsav8.rbar[M_REG_S], 0, 267 sizeof(*env->pmsav8.rbar[M_REG_S]) 268 * cpu->pmsav7_dregion); 269 memset(env->pmsav8.rlar[M_REG_S], 0, 270 sizeof(*env->pmsav8.rlar[M_REG_S]) 271 * cpu->pmsav7_dregion); 272 } 273 } else if (arm_feature(env, ARM_FEATURE_V7)) { 274 memset(env->pmsav7.drbar, 0, 275 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 276 memset(env->pmsav7.drsr, 0, 277 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 278 memset(env->pmsav7.dracr, 0, 279 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 280 } 281 } 282 env->pmsav7.rnr[M_REG_NS] = 0; 283 env->pmsav7.rnr[M_REG_S] = 0; 284 env->pmsav8.mair0[M_REG_NS] = 0; 285 env->pmsav8.mair0[M_REG_S] = 0; 286 env->pmsav8.mair1[M_REG_NS] = 0; 287 env->pmsav8.mair1[M_REG_S] = 0; 288 } 289 290 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 291 if (cpu->sau_sregion > 0) { 292 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 293 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 294 } 295 env->sau.rnr = 0; 296 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 297 * the Cortex-M33 does. 298 */ 299 env->sau.ctrl = 0; 300 } 301 302 set_flush_to_zero(1, &env->vfp.standard_fp_status); 303 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 304 set_default_nan_mode(1, &env->vfp.standard_fp_status); 305 set_float_detect_tininess(float_tininess_before_rounding, 306 &env->vfp.fp_status); 307 set_float_detect_tininess(float_tininess_before_rounding, 308 &env->vfp.standard_fp_status); 309 #ifndef CONFIG_USER_ONLY 310 if (kvm_enabled()) { 311 kvm_arm_reset_vcpu(cpu); 312 } 313 #endif 314 315 hw_breakpoint_update_all(cpu); 316 hw_watchpoint_update_all(cpu); 317 } 318 319 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 320 { 321 CPUClass *cc = CPU_GET_CLASS(cs); 322 CPUARMState *env = cs->env_ptr; 323 uint32_t cur_el = arm_current_el(env); 324 bool secure = arm_is_secure(env); 325 uint32_t target_el; 326 uint32_t excp_idx; 327 bool ret = false; 328 329 if (interrupt_request & CPU_INTERRUPT_FIQ) { 330 excp_idx = EXCP_FIQ; 331 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 332 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 333 cs->exception_index = excp_idx; 334 env->exception.target_el = target_el; 335 cc->do_interrupt(cs); 336 ret = true; 337 } 338 } 339 if (interrupt_request & CPU_INTERRUPT_HARD) { 340 excp_idx = EXCP_IRQ; 341 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 342 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 343 cs->exception_index = excp_idx; 344 env->exception.target_el = target_el; 345 cc->do_interrupt(cs); 346 ret = true; 347 } 348 } 349 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 350 excp_idx = EXCP_VIRQ; 351 target_el = 1; 352 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 353 cs->exception_index = excp_idx; 354 env->exception.target_el = target_el; 355 cc->do_interrupt(cs); 356 ret = true; 357 } 358 } 359 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 360 excp_idx = EXCP_VFIQ; 361 target_el = 1; 362 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 363 cs->exception_index = excp_idx; 364 env->exception.target_el = target_el; 365 cc->do_interrupt(cs); 366 ret = true; 367 } 368 } 369 370 return ret; 371 } 372 373 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 374 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 375 { 376 CPUClass *cc = CPU_GET_CLASS(cs); 377 ARMCPU *cpu = ARM_CPU(cs); 378 CPUARMState *env = &cpu->env; 379 bool ret = false; 380 381 /* ARMv7-M interrupt masking works differently than -A or -R. 382 * There is no FIQ/IRQ distinction. Instead of I and F bits 383 * masking FIQ and IRQ interrupts, an exception is taken only 384 * if it is higher priority than the current execution priority 385 * (which depends on state like BASEPRI, FAULTMASK and the 386 * currently active exception). 387 */ 388 if (interrupt_request & CPU_INTERRUPT_HARD 389 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 390 cs->exception_index = EXCP_IRQ; 391 cc->do_interrupt(cs); 392 ret = true; 393 } 394 return ret; 395 } 396 #endif 397 398 #ifndef CONFIG_USER_ONLY 399 static void arm_cpu_set_irq(void *opaque, int irq, int level) 400 { 401 ARMCPU *cpu = opaque; 402 CPUARMState *env = &cpu->env; 403 CPUState *cs = CPU(cpu); 404 static const int mask[] = { 405 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 406 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 407 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 408 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 409 }; 410 411 switch (irq) { 412 case ARM_CPU_VIRQ: 413 case ARM_CPU_VFIQ: 414 assert(arm_feature(env, ARM_FEATURE_EL2)); 415 /* fall through */ 416 case ARM_CPU_IRQ: 417 case ARM_CPU_FIQ: 418 if (level) { 419 cpu_interrupt(cs, mask[irq]); 420 } else { 421 cpu_reset_interrupt(cs, mask[irq]); 422 } 423 break; 424 default: 425 g_assert_not_reached(); 426 } 427 } 428 429 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 430 { 431 #ifdef CONFIG_KVM 432 ARMCPU *cpu = opaque; 433 CPUState *cs = CPU(cpu); 434 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 435 436 switch (irq) { 437 case ARM_CPU_IRQ: 438 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 439 break; 440 case ARM_CPU_FIQ: 441 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 442 break; 443 default: 444 g_assert_not_reached(); 445 } 446 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 447 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 448 #endif 449 } 450 451 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 452 { 453 ARMCPU *cpu = ARM_CPU(cs); 454 CPUARMState *env = &cpu->env; 455 456 cpu_synchronize_state(cs); 457 return arm_cpu_data_is_big_endian(env); 458 } 459 460 #endif 461 462 static inline void set_feature(CPUARMState *env, int feature) 463 { 464 env->features |= 1ULL << feature; 465 } 466 467 static inline void unset_feature(CPUARMState *env, int feature) 468 { 469 env->features &= ~(1ULL << feature); 470 } 471 472 static int 473 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 474 { 475 return print_insn_arm(pc | 1, info); 476 } 477 478 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 479 { 480 ARMCPU *ac = ARM_CPU(cpu); 481 CPUARMState *env = &ac->env; 482 bool sctlr_b; 483 484 if (is_a64(env)) { 485 /* We might not be compiled with the A64 disassembler 486 * because it needs a C++ compiler. Leave print_insn 487 * unset in this case to use the caller default behaviour. 488 */ 489 #if defined(CONFIG_ARM_A64_DIS) 490 info->print_insn = print_insn_arm_a64; 491 #endif 492 info->cap_arch = CS_ARCH_ARM64; 493 info->cap_insn_unit = 4; 494 info->cap_insn_split = 4; 495 } else { 496 int cap_mode; 497 if (env->thumb) { 498 info->print_insn = print_insn_thumb1; 499 info->cap_insn_unit = 2; 500 info->cap_insn_split = 4; 501 cap_mode = CS_MODE_THUMB; 502 } else { 503 info->print_insn = print_insn_arm; 504 info->cap_insn_unit = 4; 505 info->cap_insn_split = 4; 506 cap_mode = CS_MODE_ARM; 507 } 508 if (arm_feature(env, ARM_FEATURE_V8)) { 509 cap_mode |= CS_MODE_V8; 510 } 511 if (arm_feature(env, ARM_FEATURE_M)) { 512 cap_mode |= CS_MODE_MCLASS; 513 } 514 info->cap_arch = CS_ARCH_ARM; 515 info->cap_mode = cap_mode; 516 } 517 518 sctlr_b = arm_sctlr_b(env); 519 if (bswap_code(sctlr_b)) { 520 #ifdef TARGET_WORDS_BIGENDIAN 521 info->endian = BFD_ENDIAN_LITTLE; 522 #else 523 info->endian = BFD_ENDIAN_BIG; 524 #endif 525 } 526 info->flags &= ~INSN_ARM_BE32; 527 #ifndef CONFIG_USER_ONLY 528 if (sctlr_b) { 529 info->flags |= INSN_ARM_BE32; 530 } 531 #endif 532 } 533 534 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 535 { 536 uint32_t Aff1 = idx / clustersz; 537 uint32_t Aff0 = idx % clustersz; 538 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 539 } 540 541 static void arm_cpu_initfn(Object *obj) 542 { 543 CPUState *cs = CPU(obj); 544 ARMCPU *cpu = ARM_CPU(obj); 545 546 cs->env_ptr = &cpu->env; 547 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 548 g_free, g_free); 549 550 #ifndef CONFIG_USER_ONLY 551 /* Our inbound IRQ and FIQ lines */ 552 if (kvm_enabled()) { 553 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 554 * the same interface as non-KVM CPUs. 555 */ 556 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 557 } else { 558 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 559 } 560 561 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 562 arm_gt_ptimer_cb, cpu); 563 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 564 arm_gt_vtimer_cb, cpu); 565 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 566 arm_gt_htimer_cb, cpu); 567 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 568 arm_gt_stimer_cb, cpu); 569 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 570 ARRAY_SIZE(cpu->gt_timer_outputs)); 571 572 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 573 "gicv3-maintenance-interrupt", 1); 574 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 575 "pmu-interrupt", 1); 576 #endif 577 578 /* DTB consumers generally don't in fact care what the 'compatible' 579 * string is, so always provide some string and trust that a hypothetical 580 * picky DTB consumer will also provide a helpful error message. 581 */ 582 cpu->dtb_compatible = "qemu,unknown"; 583 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 584 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 585 586 if (tcg_enabled()) { 587 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 588 } 589 } 590 591 static Property arm_cpu_reset_cbar_property = 592 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 593 594 static Property arm_cpu_reset_hivecs_property = 595 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 596 597 static Property arm_cpu_rvbar_property = 598 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 599 600 static Property arm_cpu_has_el2_property = 601 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 602 603 static Property arm_cpu_has_el3_property = 604 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 605 606 static Property arm_cpu_cfgend_property = 607 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 608 609 /* use property name "pmu" to match other archs and virt tools */ 610 static Property arm_cpu_has_pmu_property = 611 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 612 613 static Property arm_cpu_has_mpu_property = 614 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 615 616 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 617 * because the CPU initfn will have already set cpu->pmsav7_dregion to 618 * the right value for that particular CPU type, and we don't want 619 * to override that with an incorrect constant value. 620 */ 621 static Property arm_cpu_pmsav7_dregion_property = 622 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 623 pmsav7_dregion, 624 qdev_prop_uint32, uint32_t); 625 626 static void arm_cpu_post_init(Object *obj) 627 { 628 ARMCPU *cpu = ARM_CPU(obj); 629 630 /* M profile implies PMSA. We have to do this here rather than 631 * in realize with the other feature-implication checks because 632 * we look at the PMSA bit to see if we should add some properties. 633 */ 634 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 635 set_feature(&cpu->env, ARM_FEATURE_PMSA); 636 } 637 638 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 639 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 640 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 641 &error_abort); 642 } 643 644 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 645 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 646 &error_abort); 647 } 648 649 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 650 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 651 &error_abort); 652 } 653 654 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 655 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 656 * prevent "has_el3" from existing on CPUs which cannot support EL3. 657 */ 658 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 659 &error_abort); 660 661 #ifndef CONFIG_USER_ONLY 662 object_property_add_link(obj, "secure-memory", 663 TYPE_MEMORY_REGION, 664 (Object **)&cpu->secure_memory, 665 qdev_prop_allow_set_link_before_realize, 666 OBJ_PROP_LINK_UNREF_ON_RELEASE, 667 &error_abort); 668 #endif 669 } 670 671 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 672 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 673 &error_abort); 674 } 675 676 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 677 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 678 &error_abort); 679 } 680 681 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 682 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 683 &error_abort); 684 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 685 qdev_property_add_static(DEVICE(obj), 686 &arm_cpu_pmsav7_dregion_property, 687 &error_abort); 688 } 689 } 690 691 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 692 &error_abort); 693 } 694 695 static void arm_cpu_finalizefn(Object *obj) 696 { 697 ARMCPU *cpu = ARM_CPU(obj); 698 g_hash_table_destroy(cpu->cp_regs); 699 } 700 701 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 702 { 703 CPUState *cs = CPU(dev); 704 ARMCPU *cpu = ARM_CPU(dev); 705 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 706 CPUARMState *env = &cpu->env; 707 int pagebits; 708 Error *local_err = NULL; 709 710 cpu_exec_realizefn(cs, &local_err); 711 if (local_err != NULL) { 712 error_propagate(errp, local_err); 713 return; 714 } 715 716 /* Some features automatically imply others: */ 717 if (arm_feature(env, ARM_FEATURE_V8)) { 718 set_feature(env, ARM_FEATURE_V7); 719 set_feature(env, ARM_FEATURE_ARM_DIV); 720 set_feature(env, ARM_FEATURE_LPAE); 721 } 722 if (arm_feature(env, ARM_FEATURE_V7)) { 723 set_feature(env, ARM_FEATURE_VAPA); 724 set_feature(env, ARM_FEATURE_THUMB2); 725 set_feature(env, ARM_FEATURE_MPIDR); 726 if (!arm_feature(env, ARM_FEATURE_M)) { 727 set_feature(env, ARM_FEATURE_V6K); 728 } else { 729 set_feature(env, ARM_FEATURE_V6); 730 } 731 732 /* Always define VBAR for V7 CPUs even if it doesn't exist in 733 * non-EL3 configs. This is needed by some legacy boards. 734 */ 735 set_feature(env, ARM_FEATURE_VBAR); 736 } 737 if (arm_feature(env, ARM_FEATURE_V6K)) { 738 set_feature(env, ARM_FEATURE_V6); 739 set_feature(env, ARM_FEATURE_MVFR); 740 } 741 if (arm_feature(env, ARM_FEATURE_V6)) { 742 set_feature(env, ARM_FEATURE_V5); 743 set_feature(env, ARM_FEATURE_JAZELLE); 744 if (!arm_feature(env, ARM_FEATURE_M)) { 745 set_feature(env, ARM_FEATURE_AUXCR); 746 } 747 } 748 if (arm_feature(env, ARM_FEATURE_V5)) { 749 set_feature(env, ARM_FEATURE_V4T); 750 } 751 if (arm_feature(env, ARM_FEATURE_M)) { 752 set_feature(env, ARM_FEATURE_THUMB_DIV); 753 } 754 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { 755 set_feature(env, ARM_FEATURE_THUMB_DIV); 756 } 757 if (arm_feature(env, ARM_FEATURE_VFP4)) { 758 set_feature(env, ARM_FEATURE_VFP3); 759 set_feature(env, ARM_FEATURE_VFP_FP16); 760 } 761 if (arm_feature(env, ARM_FEATURE_VFP3)) { 762 set_feature(env, ARM_FEATURE_VFP); 763 } 764 if (arm_feature(env, ARM_FEATURE_LPAE)) { 765 set_feature(env, ARM_FEATURE_V7MP); 766 set_feature(env, ARM_FEATURE_PXN); 767 } 768 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 769 set_feature(env, ARM_FEATURE_CBAR); 770 } 771 if (arm_feature(env, ARM_FEATURE_THUMB2) && 772 !arm_feature(env, ARM_FEATURE_M)) { 773 set_feature(env, ARM_FEATURE_THUMB_DSP); 774 } 775 776 if (arm_feature(env, ARM_FEATURE_V7) && 777 !arm_feature(env, ARM_FEATURE_M) && 778 !arm_feature(env, ARM_FEATURE_PMSA)) { 779 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 780 * can use 4K pages. 781 */ 782 pagebits = 12; 783 } else { 784 /* For CPUs which might have tiny 1K pages, or which have an 785 * MPU and might have small region sizes, stick with 1K pages. 786 */ 787 pagebits = 10; 788 } 789 if (!set_preferred_target_page_bits(pagebits)) { 790 /* This can only ever happen for hotplugging a CPU, or if 791 * the board code incorrectly creates a CPU which it has 792 * promised via minimum_page_size that it will not. 793 */ 794 error_setg(errp, "This CPU requires a smaller page size than the " 795 "system is using"); 796 return; 797 } 798 799 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 800 * We don't support setting cluster ID ([16..23]) (known as Aff2 801 * in later ARM ARM versions), or any of the higher affinity level fields, 802 * so these bits always RAZ. 803 */ 804 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 805 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 806 ARM_DEFAULT_CPUS_PER_CLUSTER); 807 } 808 809 if (cpu->reset_hivecs) { 810 cpu->reset_sctlr |= (1 << 13); 811 } 812 813 if (cpu->cfgend) { 814 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 815 cpu->reset_sctlr |= SCTLR_EE; 816 } else { 817 cpu->reset_sctlr |= SCTLR_B; 818 } 819 } 820 821 if (!cpu->has_el3) { 822 /* If the has_el3 CPU property is disabled then we need to disable the 823 * feature. 824 */ 825 unset_feature(env, ARM_FEATURE_EL3); 826 827 /* Disable the security extension feature bits in the processor feature 828 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 829 */ 830 cpu->id_pfr1 &= ~0xf0; 831 cpu->id_aa64pfr0 &= ~0xf000; 832 } 833 834 if (!cpu->has_el2) { 835 unset_feature(env, ARM_FEATURE_EL2); 836 } 837 838 if (!cpu->has_pmu) { 839 unset_feature(env, ARM_FEATURE_PMU); 840 cpu->id_aa64dfr0 &= ~0xf00; 841 } 842 843 if (!arm_feature(env, ARM_FEATURE_EL2)) { 844 /* Disable the hypervisor feature bits in the processor feature 845 * registers if we don't have EL2. These are id_pfr1[15:12] and 846 * id_aa64pfr0_el1[11:8]. 847 */ 848 cpu->id_aa64pfr0 &= ~0xf00; 849 cpu->id_pfr1 &= ~0xf000; 850 } 851 852 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 853 * to false or by setting pmsav7-dregion to 0. 854 */ 855 if (!cpu->has_mpu) { 856 cpu->pmsav7_dregion = 0; 857 } 858 if (cpu->pmsav7_dregion == 0) { 859 cpu->has_mpu = false; 860 } 861 862 if (arm_feature(env, ARM_FEATURE_PMSA) && 863 arm_feature(env, ARM_FEATURE_V7)) { 864 uint32_t nr = cpu->pmsav7_dregion; 865 866 if (nr > 0xff) { 867 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 868 return; 869 } 870 871 if (nr) { 872 if (arm_feature(env, ARM_FEATURE_V8)) { 873 /* PMSAv8 */ 874 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 875 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 876 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 877 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 878 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 879 } 880 } else { 881 env->pmsav7.drbar = g_new0(uint32_t, nr); 882 env->pmsav7.drsr = g_new0(uint32_t, nr); 883 env->pmsav7.dracr = g_new0(uint32_t, nr); 884 } 885 } 886 } 887 888 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 889 uint32_t nr = cpu->sau_sregion; 890 891 if (nr > 0xff) { 892 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 893 return; 894 } 895 896 if (nr) { 897 env->sau.rbar = g_new0(uint32_t, nr); 898 env->sau.rlar = g_new0(uint32_t, nr); 899 } 900 } 901 902 if (arm_feature(env, ARM_FEATURE_EL3)) { 903 set_feature(env, ARM_FEATURE_VBAR); 904 } 905 906 register_cp_regs_for_features(cpu); 907 arm_cpu_register_gdb_regs_for_features(cpu); 908 909 init_cpreg_list(cpu); 910 911 #ifndef CONFIG_USER_ONLY 912 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 913 cs->num_ases = 2; 914 915 if (!cpu->secure_memory) { 916 cpu->secure_memory = cs->memory; 917 } 918 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 919 cpu->secure_memory); 920 } else { 921 cs->num_ases = 1; 922 } 923 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 924 #endif 925 926 qemu_init_vcpu(cs); 927 cpu_reset(cs); 928 929 acc->parent_realize(dev, errp); 930 } 931 932 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 933 { 934 ObjectClass *oc; 935 char *typename; 936 char **cpuname; 937 938 cpuname = g_strsplit(cpu_model, ",", 1); 939 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpuname[0]); 940 oc = object_class_by_name(typename); 941 g_strfreev(cpuname); 942 g_free(typename); 943 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 944 object_class_is_abstract(oc)) { 945 return NULL; 946 } 947 return oc; 948 } 949 950 /* CPU models. These are not needed for the AArch64 linux-user build. */ 951 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 952 953 static void arm926_initfn(Object *obj) 954 { 955 ARMCPU *cpu = ARM_CPU(obj); 956 957 cpu->dtb_compatible = "arm,arm926"; 958 set_feature(&cpu->env, ARM_FEATURE_V5); 959 set_feature(&cpu->env, ARM_FEATURE_VFP); 960 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 961 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 962 set_feature(&cpu->env, ARM_FEATURE_JAZELLE); 963 cpu->midr = 0x41069265; 964 cpu->reset_fpsid = 0x41011090; 965 cpu->ctr = 0x1dd20d2; 966 cpu->reset_sctlr = 0x00090078; 967 } 968 969 static void arm946_initfn(Object *obj) 970 { 971 ARMCPU *cpu = ARM_CPU(obj); 972 973 cpu->dtb_compatible = "arm,arm946"; 974 set_feature(&cpu->env, ARM_FEATURE_V5); 975 set_feature(&cpu->env, ARM_FEATURE_PMSA); 976 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 977 cpu->midr = 0x41059461; 978 cpu->ctr = 0x0f004006; 979 cpu->reset_sctlr = 0x00000078; 980 } 981 982 static void arm1026_initfn(Object *obj) 983 { 984 ARMCPU *cpu = ARM_CPU(obj); 985 986 cpu->dtb_compatible = "arm,arm1026"; 987 set_feature(&cpu->env, ARM_FEATURE_V5); 988 set_feature(&cpu->env, ARM_FEATURE_VFP); 989 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 990 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 991 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 992 set_feature(&cpu->env, ARM_FEATURE_JAZELLE); 993 cpu->midr = 0x4106a262; 994 cpu->reset_fpsid = 0x410110a0; 995 cpu->ctr = 0x1dd20d2; 996 cpu->reset_sctlr = 0x00090078; 997 cpu->reset_auxcr = 1; 998 { 999 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 1000 ARMCPRegInfo ifar = { 1001 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 1002 .access = PL1_RW, 1003 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 1004 .resetvalue = 0 1005 }; 1006 define_one_arm_cp_reg(cpu, &ifar); 1007 } 1008 } 1009 1010 static void arm1136_r2_initfn(Object *obj) 1011 { 1012 ARMCPU *cpu = ARM_CPU(obj); 1013 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 1014 * older core than plain "arm1136". In particular this does not 1015 * have the v6K features. 1016 * These ID register values are correct for 1136 but may be wrong 1017 * for 1136_r2 (in particular r0p2 does not actually implement most 1018 * of the ID registers). 1019 */ 1020 1021 cpu->dtb_compatible = "arm,arm1136"; 1022 set_feature(&cpu->env, ARM_FEATURE_V6); 1023 set_feature(&cpu->env, ARM_FEATURE_VFP); 1024 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1025 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1026 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1027 cpu->midr = 0x4107b362; 1028 cpu->reset_fpsid = 0x410120b4; 1029 cpu->mvfr0 = 0x11111111; 1030 cpu->mvfr1 = 0x00000000; 1031 cpu->ctr = 0x1dd20d2; 1032 cpu->reset_sctlr = 0x00050078; 1033 cpu->id_pfr0 = 0x111; 1034 cpu->id_pfr1 = 0x1; 1035 cpu->id_dfr0 = 0x2; 1036 cpu->id_afr0 = 0x3; 1037 cpu->id_mmfr0 = 0x01130003; 1038 cpu->id_mmfr1 = 0x10030302; 1039 cpu->id_mmfr2 = 0x01222110; 1040 cpu->id_isar0 = 0x00140011; 1041 cpu->id_isar1 = 0x12002111; 1042 cpu->id_isar2 = 0x11231111; 1043 cpu->id_isar3 = 0x01102131; 1044 cpu->id_isar4 = 0x141; 1045 cpu->reset_auxcr = 7; 1046 } 1047 1048 static void arm1136_initfn(Object *obj) 1049 { 1050 ARMCPU *cpu = ARM_CPU(obj); 1051 1052 cpu->dtb_compatible = "arm,arm1136"; 1053 set_feature(&cpu->env, ARM_FEATURE_V6K); 1054 set_feature(&cpu->env, ARM_FEATURE_V6); 1055 set_feature(&cpu->env, ARM_FEATURE_VFP); 1056 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1057 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1058 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1059 cpu->midr = 0x4117b363; 1060 cpu->reset_fpsid = 0x410120b4; 1061 cpu->mvfr0 = 0x11111111; 1062 cpu->mvfr1 = 0x00000000; 1063 cpu->ctr = 0x1dd20d2; 1064 cpu->reset_sctlr = 0x00050078; 1065 cpu->id_pfr0 = 0x111; 1066 cpu->id_pfr1 = 0x1; 1067 cpu->id_dfr0 = 0x2; 1068 cpu->id_afr0 = 0x3; 1069 cpu->id_mmfr0 = 0x01130003; 1070 cpu->id_mmfr1 = 0x10030302; 1071 cpu->id_mmfr2 = 0x01222110; 1072 cpu->id_isar0 = 0x00140011; 1073 cpu->id_isar1 = 0x12002111; 1074 cpu->id_isar2 = 0x11231111; 1075 cpu->id_isar3 = 0x01102131; 1076 cpu->id_isar4 = 0x141; 1077 cpu->reset_auxcr = 7; 1078 } 1079 1080 static void arm1176_initfn(Object *obj) 1081 { 1082 ARMCPU *cpu = ARM_CPU(obj); 1083 1084 cpu->dtb_compatible = "arm,arm1176"; 1085 set_feature(&cpu->env, ARM_FEATURE_V6K); 1086 set_feature(&cpu->env, ARM_FEATURE_VFP); 1087 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1088 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1089 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1090 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1091 set_feature(&cpu->env, ARM_FEATURE_EL3); 1092 cpu->midr = 0x410fb767; 1093 cpu->reset_fpsid = 0x410120b5; 1094 cpu->mvfr0 = 0x11111111; 1095 cpu->mvfr1 = 0x00000000; 1096 cpu->ctr = 0x1dd20d2; 1097 cpu->reset_sctlr = 0x00050078; 1098 cpu->id_pfr0 = 0x111; 1099 cpu->id_pfr1 = 0x11; 1100 cpu->id_dfr0 = 0x33; 1101 cpu->id_afr0 = 0; 1102 cpu->id_mmfr0 = 0x01130003; 1103 cpu->id_mmfr1 = 0x10030302; 1104 cpu->id_mmfr2 = 0x01222100; 1105 cpu->id_isar0 = 0x0140011; 1106 cpu->id_isar1 = 0x12002111; 1107 cpu->id_isar2 = 0x11231121; 1108 cpu->id_isar3 = 0x01102131; 1109 cpu->id_isar4 = 0x01141; 1110 cpu->reset_auxcr = 7; 1111 } 1112 1113 static void arm11mpcore_initfn(Object *obj) 1114 { 1115 ARMCPU *cpu = ARM_CPU(obj); 1116 1117 cpu->dtb_compatible = "arm,arm11mpcore"; 1118 set_feature(&cpu->env, ARM_FEATURE_V6K); 1119 set_feature(&cpu->env, ARM_FEATURE_VFP); 1120 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1121 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1122 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1123 cpu->midr = 0x410fb022; 1124 cpu->reset_fpsid = 0x410120b4; 1125 cpu->mvfr0 = 0x11111111; 1126 cpu->mvfr1 = 0x00000000; 1127 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1128 cpu->id_pfr0 = 0x111; 1129 cpu->id_pfr1 = 0x1; 1130 cpu->id_dfr0 = 0; 1131 cpu->id_afr0 = 0x2; 1132 cpu->id_mmfr0 = 0x01100103; 1133 cpu->id_mmfr1 = 0x10020302; 1134 cpu->id_mmfr2 = 0x01222000; 1135 cpu->id_isar0 = 0x00100011; 1136 cpu->id_isar1 = 0x12002111; 1137 cpu->id_isar2 = 0x11221011; 1138 cpu->id_isar3 = 0x01102131; 1139 cpu->id_isar4 = 0x141; 1140 cpu->reset_auxcr = 1; 1141 } 1142 1143 static void cortex_m3_initfn(Object *obj) 1144 { 1145 ARMCPU *cpu = ARM_CPU(obj); 1146 set_feature(&cpu->env, ARM_FEATURE_V7); 1147 set_feature(&cpu->env, ARM_FEATURE_M); 1148 cpu->midr = 0x410fc231; 1149 cpu->pmsav7_dregion = 8; 1150 cpu->id_pfr0 = 0x00000030; 1151 cpu->id_pfr1 = 0x00000200; 1152 cpu->id_dfr0 = 0x00100000; 1153 cpu->id_afr0 = 0x00000000; 1154 cpu->id_mmfr0 = 0x00000030; 1155 cpu->id_mmfr1 = 0x00000000; 1156 cpu->id_mmfr2 = 0x00000000; 1157 cpu->id_mmfr3 = 0x00000000; 1158 cpu->id_isar0 = 0x01141110; 1159 cpu->id_isar1 = 0x02111000; 1160 cpu->id_isar2 = 0x21112231; 1161 cpu->id_isar3 = 0x01111110; 1162 cpu->id_isar4 = 0x01310102; 1163 cpu->id_isar5 = 0x00000000; 1164 } 1165 1166 static void cortex_m4_initfn(Object *obj) 1167 { 1168 ARMCPU *cpu = ARM_CPU(obj); 1169 1170 set_feature(&cpu->env, ARM_FEATURE_V7); 1171 set_feature(&cpu->env, ARM_FEATURE_M); 1172 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1173 cpu->midr = 0x410fc240; /* r0p0 */ 1174 cpu->pmsav7_dregion = 8; 1175 cpu->id_pfr0 = 0x00000030; 1176 cpu->id_pfr1 = 0x00000200; 1177 cpu->id_dfr0 = 0x00100000; 1178 cpu->id_afr0 = 0x00000000; 1179 cpu->id_mmfr0 = 0x00000030; 1180 cpu->id_mmfr1 = 0x00000000; 1181 cpu->id_mmfr2 = 0x00000000; 1182 cpu->id_mmfr3 = 0x00000000; 1183 cpu->id_isar0 = 0x01141110; 1184 cpu->id_isar1 = 0x02111000; 1185 cpu->id_isar2 = 0x21112231; 1186 cpu->id_isar3 = 0x01111110; 1187 cpu->id_isar4 = 0x01310102; 1188 cpu->id_isar5 = 0x00000000; 1189 } 1190 1191 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1192 { 1193 CPUClass *cc = CPU_CLASS(oc); 1194 1195 #ifndef CONFIG_USER_ONLY 1196 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1197 #endif 1198 1199 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1200 } 1201 1202 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1203 /* Dummy the TCM region regs for the moment */ 1204 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1205 .access = PL1_RW, .type = ARM_CP_CONST }, 1206 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1207 .access = PL1_RW, .type = ARM_CP_CONST }, 1208 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 1209 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 1210 REGINFO_SENTINEL 1211 }; 1212 1213 static void cortex_r5_initfn(Object *obj) 1214 { 1215 ARMCPU *cpu = ARM_CPU(obj); 1216 1217 set_feature(&cpu->env, ARM_FEATURE_V7); 1218 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); 1219 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1220 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1221 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1222 cpu->midr = 0x411fc153; /* r1p3 */ 1223 cpu->id_pfr0 = 0x0131; 1224 cpu->id_pfr1 = 0x001; 1225 cpu->id_dfr0 = 0x010400; 1226 cpu->id_afr0 = 0x0; 1227 cpu->id_mmfr0 = 0x0210030; 1228 cpu->id_mmfr1 = 0x00000000; 1229 cpu->id_mmfr2 = 0x01200000; 1230 cpu->id_mmfr3 = 0x0211; 1231 cpu->id_isar0 = 0x2101111; 1232 cpu->id_isar1 = 0x13112111; 1233 cpu->id_isar2 = 0x21232141; 1234 cpu->id_isar3 = 0x01112131; 1235 cpu->id_isar4 = 0x0010142; 1236 cpu->id_isar5 = 0x0; 1237 cpu->mp_is_up = true; 1238 cpu->pmsav7_dregion = 16; 1239 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1240 } 1241 1242 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1243 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1244 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1245 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1246 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1247 REGINFO_SENTINEL 1248 }; 1249 1250 static void cortex_a8_initfn(Object *obj) 1251 { 1252 ARMCPU *cpu = ARM_CPU(obj); 1253 1254 cpu->dtb_compatible = "arm,cortex-a8"; 1255 set_feature(&cpu->env, ARM_FEATURE_V7); 1256 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1257 set_feature(&cpu->env, ARM_FEATURE_NEON); 1258 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1259 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1260 set_feature(&cpu->env, ARM_FEATURE_EL3); 1261 cpu->midr = 0x410fc080; 1262 cpu->reset_fpsid = 0x410330c0; 1263 cpu->mvfr0 = 0x11110222; 1264 cpu->mvfr1 = 0x00011111; 1265 cpu->ctr = 0x82048004; 1266 cpu->reset_sctlr = 0x00c50078; 1267 cpu->id_pfr0 = 0x1031; 1268 cpu->id_pfr1 = 0x11; 1269 cpu->id_dfr0 = 0x400; 1270 cpu->id_afr0 = 0; 1271 cpu->id_mmfr0 = 0x31100003; 1272 cpu->id_mmfr1 = 0x20000000; 1273 cpu->id_mmfr2 = 0x01202000; 1274 cpu->id_mmfr3 = 0x11; 1275 cpu->id_isar0 = 0x00101111; 1276 cpu->id_isar1 = 0x12112111; 1277 cpu->id_isar2 = 0x21232031; 1278 cpu->id_isar3 = 0x11112131; 1279 cpu->id_isar4 = 0x00111142; 1280 cpu->dbgdidr = 0x15141000; 1281 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1282 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1283 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1284 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1285 cpu->reset_auxcr = 2; 1286 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1287 } 1288 1289 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1290 /* power_control should be set to maximum latency. Again, 1291 * default to 0 and set by private hook 1292 */ 1293 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1294 .access = PL1_RW, .resetvalue = 0, 1295 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1296 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1297 .access = PL1_RW, .resetvalue = 0, 1298 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1299 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1300 .access = PL1_RW, .resetvalue = 0, 1301 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1302 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1303 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1304 /* TLB lockdown control */ 1305 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1306 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1307 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1308 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1309 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1310 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1311 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1312 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1313 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1314 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1315 REGINFO_SENTINEL 1316 }; 1317 1318 static void cortex_a9_initfn(Object *obj) 1319 { 1320 ARMCPU *cpu = ARM_CPU(obj); 1321 1322 cpu->dtb_compatible = "arm,cortex-a9"; 1323 set_feature(&cpu->env, ARM_FEATURE_V7); 1324 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1325 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); 1326 set_feature(&cpu->env, ARM_FEATURE_NEON); 1327 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1328 set_feature(&cpu->env, ARM_FEATURE_EL3); 1329 /* Note that A9 supports the MP extensions even for 1330 * A9UP and single-core A9MP (which are both different 1331 * and valid configurations; we don't model A9UP). 1332 */ 1333 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1334 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1335 cpu->midr = 0x410fc090; 1336 cpu->reset_fpsid = 0x41033090; 1337 cpu->mvfr0 = 0x11110222; 1338 cpu->mvfr1 = 0x01111111; 1339 cpu->ctr = 0x80038003; 1340 cpu->reset_sctlr = 0x00c50078; 1341 cpu->id_pfr0 = 0x1031; 1342 cpu->id_pfr1 = 0x11; 1343 cpu->id_dfr0 = 0x000; 1344 cpu->id_afr0 = 0; 1345 cpu->id_mmfr0 = 0x00100103; 1346 cpu->id_mmfr1 = 0x20000000; 1347 cpu->id_mmfr2 = 0x01230000; 1348 cpu->id_mmfr3 = 0x00002111; 1349 cpu->id_isar0 = 0x00101111; 1350 cpu->id_isar1 = 0x13112111; 1351 cpu->id_isar2 = 0x21232041; 1352 cpu->id_isar3 = 0x11112131; 1353 cpu->id_isar4 = 0x00111142; 1354 cpu->dbgdidr = 0x35141000; 1355 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1356 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1357 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1358 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1359 } 1360 1361 #ifndef CONFIG_USER_ONLY 1362 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1363 { 1364 /* Linux wants the number of processors from here. 1365 * Might as well set the interrupt-controller bit too. 1366 */ 1367 return ((smp_cpus - 1) << 24) | (1 << 23); 1368 } 1369 #endif 1370 1371 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1372 #ifndef CONFIG_USER_ONLY 1373 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1374 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1375 .writefn = arm_cp_write_ignore, }, 1376 #endif 1377 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1378 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1379 REGINFO_SENTINEL 1380 }; 1381 1382 static void cortex_a7_initfn(Object *obj) 1383 { 1384 ARMCPU *cpu = ARM_CPU(obj); 1385 1386 cpu->dtb_compatible = "arm,cortex-a7"; 1387 set_feature(&cpu->env, ARM_FEATURE_V7); 1388 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1389 set_feature(&cpu->env, ARM_FEATURE_NEON); 1390 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1391 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1392 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1393 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1394 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1395 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1396 set_feature(&cpu->env, ARM_FEATURE_EL3); 1397 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1398 cpu->midr = 0x410fc075; 1399 cpu->reset_fpsid = 0x41023075; 1400 cpu->mvfr0 = 0x10110222; 1401 cpu->mvfr1 = 0x11111111; 1402 cpu->ctr = 0x84448003; 1403 cpu->reset_sctlr = 0x00c50078; 1404 cpu->id_pfr0 = 0x00001131; 1405 cpu->id_pfr1 = 0x00011011; 1406 cpu->id_dfr0 = 0x02010555; 1407 cpu->pmceid0 = 0x00000000; 1408 cpu->pmceid1 = 0x00000000; 1409 cpu->id_afr0 = 0x00000000; 1410 cpu->id_mmfr0 = 0x10101105; 1411 cpu->id_mmfr1 = 0x40000000; 1412 cpu->id_mmfr2 = 0x01240000; 1413 cpu->id_mmfr3 = 0x02102211; 1414 cpu->id_isar0 = 0x01101110; 1415 cpu->id_isar1 = 0x13112111; 1416 cpu->id_isar2 = 0x21232041; 1417 cpu->id_isar3 = 0x11112131; 1418 cpu->id_isar4 = 0x10011142; 1419 cpu->dbgdidr = 0x3515f005; 1420 cpu->clidr = 0x0a200023; 1421 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1422 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1423 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1424 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1425 } 1426 1427 static void cortex_a15_initfn(Object *obj) 1428 { 1429 ARMCPU *cpu = ARM_CPU(obj); 1430 1431 cpu->dtb_compatible = "arm,cortex-a15"; 1432 set_feature(&cpu->env, ARM_FEATURE_V7); 1433 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1434 set_feature(&cpu->env, ARM_FEATURE_NEON); 1435 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1436 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1437 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1438 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1439 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1440 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1441 set_feature(&cpu->env, ARM_FEATURE_EL3); 1442 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1443 cpu->midr = 0x412fc0f1; 1444 cpu->reset_fpsid = 0x410430f0; 1445 cpu->mvfr0 = 0x10110222; 1446 cpu->mvfr1 = 0x11111111; 1447 cpu->ctr = 0x8444c004; 1448 cpu->reset_sctlr = 0x00c50078; 1449 cpu->id_pfr0 = 0x00001131; 1450 cpu->id_pfr1 = 0x00011011; 1451 cpu->id_dfr0 = 0x02010555; 1452 cpu->pmceid0 = 0x0000000; 1453 cpu->pmceid1 = 0x00000000; 1454 cpu->id_afr0 = 0x00000000; 1455 cpu->id_mmfr0 = 0x10201105; 1456 cpu->id_mmfr1 = 0x20000000; 1457 cpu->id_mmfr2 = 0x01240000; 1458 cpu->id_mmfr3 = 0x02102211; 1459 cpu->id_isar0 = 0x02101110; 1460 cpu->id_isar1 = 0x13112111; 1461 cpu->id_isar2 = 0x21232041; 1462 cpu->id_isar3 = 0x11112131; 1463 cpu->id_isar4 = 0x10011142; 1464 cpu->dbgdidr = 0x3515f021; 1465 cpu->clidr = 0x0a200023; 1466 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1467 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1468 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1469 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 1470 } 1471 1472 static void ti925t_initfn(Object *obj) 1473 { 1474 ARMCPU *cpu = ARM_CPU(obj); 1475 set_feature(&cpu->env, ARM_FEATURE_V4T); 1476 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 1477 cpu->midr = ARM_CPUID_TI925T; 1478 cpu->ctr = 0x5109149; 1479 cpu->reset_sctlr = 0x00000070; 1480 } 1481 1482 static void sa1100_initfn(Object *obj) 1483 { 1484 ARMCPU *cpu = ARM_CPU(obj); 1485 1486 cpu->dtb_compatible = "intel,sa1100"; 1487 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1488 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1489 cpu->midr = 0x4401A11B; 1490 cpu->reset_sctlr = 0x00000070; 1491 } 1492 1493 static void sa1110_initfn(Object *obj) 1494 { 1495 ARMCPU *cpu = ARM_CPU(obj); 1496 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1497 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1498 cpu->midr = 0x6901B119; 1499 cpu->reset_sctlr = 0x00000070; 1500 } 1501 1502 static void pxa250_initfn(Object *obj) 1503 { 1504 ARMCPU *cpu = ARM_CPU(obj); 1505 1506 cpu->dtb_compatible = "marvell,xscale"; 1507 set_feature(&cpu->env, ARM_FEATURE_V5); 1508 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1509 cpu->midr = 0x69052100; 1510 cpu->ctr = 0xd172172; 1511 cpu->reset_sctlr = 0x00000078; 1512 } 1513 1514 static void pxa255_initfn(Object *obj) 1515 { 1516 ARMCPU *cpu = ARM_CPU(obj); 1517 1518 cpu->dtb_compatible = "marvell,xscale"; 1519 set_feature(&cpu->env, ARM_FEATURE_V5); 1520 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1521 cpu->midr = 0x69052d00; 1522 cpu->ctr = 0xd172172; 1523 cpu->reset_sctlr = 0x00000078; 1524 } 1525 1526 static void pxa260_initfn(Object *obj) 1527 { 1528 ARMCPU *cpu = ARM_CPU(obj); 1529 1530 cpu->dtb_compatible = "marvell,xscale"; 1531 set_feature(&cpu->env, ARM_FEATURE_V5); 1532 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1533 cpu->midr = 0x69052903; 1534 cpu->ctr = 0xd172172; 1535 cpu->reset_sctlr = 0x00000078; 1536 } 1537 1538 static void pxa261_initfn(Object *obj) 1539 { 1540 ARMCPU *cpu = ARM_CPU(obj); 1541 1542 cpu->dtb_compatible = "marvell,xscale"; 1543 set_feature(&cpu->env, ARM_FEATURE_V5); 1544 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1545 cpu->midr = 0x69052d05; 1546 cpu->ctr = 0xd172172; 1547 cpu->reset_sctlr = 0x00000078; 1548 } 1549 1550 static void pxa262_initfn(Object *obj) 1551 { 1552 ARMCPU *cpu = ARM_CPU(obj); 1553 1554 cpu->dtb_compatible = "marvell,xscale"; 1555 set_feature(&cpu->env, ARM_FEATURE_V5); 1556 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1557 cpu->midr = 0x69052d06; 1558 cpu->ctr = 0xd172172; 1559 cpu->reset_sctlr = 0x00000078; 1560 } 1561 1562 static void pxa270a0_initfn(Object *obj) 1563 { 1564 ARMCPU *cpu = ARM_CPU(obj); 1565 1566 cpu->dtb_compatible = "marvell,xscale"; 1567 set_feature(&cpu->env, ARM_FEATURE_V5); 1568 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1569 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1570 cpu->midr = 0x69054110; 1571 cpu->ctr = 0xd172172; 1572 cpu->reset_sctlr = 0x00000078; 1573 } 1574 1575 static void pxa270a1_initfn(Object *obj) 1576 { 1577 ARMCPU *cpu = ARM_CPU(obj); 1578 1579 cpu->dtb_compatible = "marvell,xscale"; 1580 set_feature(&cpu->env, ARM_FEATURE_V5); 1581 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1582 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1583 cpu->midr = 0x69054111; 1584 cpu->ctr = 0xd172172; 1585 cpu->reset_sctlr = 0x00000078; 1586 } 1587 1588 static void pxa270b0_initfn(Object *obj) 1589 { 1590 ARMCPU *cpu = ARM_CPU(obj); 1591 1592 cpu->dtb_compatible = "marvell,xscale"; 1593 set_feature(&cpu->env, ARM_FEATURE_V5); 1594 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1595 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1596 cpu->midr = 0x69054112; 1597 cpu->ctr = 0xd172172; 1598 cpu->reset_sctlr = 0x00000078; 1599 } 1600 1601 static void pxa270b1_initfn(Object *obj) 1602 { 1603 ARMCPU *cpu = ARM_CPU(obj); 1604 1605 cpu->dtb_compatible = "marvell,xscale"; 1606 set_feature(&cpu->env, ARM_FEATURE_V5); 1607 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1608 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1609 cpu->midr = 0x69054113; 1610 cpu->ctr = 0xd172172; 1611 cpu->reset_sctlr = 0x00000078; 1612 } 1613 1614 static void pxa270c0_initfn(Object *obj) 1615 { 1616 ARMCPU *cpu = ARM_CPU(obj); 1617 1618 cpu->dtb_compatible = "marvell,xscale"; 1619 set_feature(&cpu->env, ARM_FEATURE_V5); 1620 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1621 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1622 cpu->midr = 0x69054114; 1623 cpu->ctr = 0xd172172; 1624 cpu->reset_sctlr = 0x00000078; 1625 } 1626 1627 static void pxa270c5_initfn(Object *obj) 1628 { 1629 ARMCPU *cpu = ARM_CPU(obj); 1630 1631 cpu->dtb_compatible = "marvell,xscale"; 1632 set_feature(&cpu->env, ARM_FEATURE_V5); 1633 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1634 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1635 cpu->midr = 0x69054117; 1636 cpu->ctr = 0xd172172; 1637 cpu->reset_sctlr = 0x00000078; 1638 } 1639 1640 #ifdef CONFIG_USER_ONLY 1641 static void arm_any_initfn(Object *obj) 1642 { 1643 ARMCPU *cpu = ARM_CPU(obj); 1644 set_feature(&cpu->env, ARM_FEATURE_V8); 1645 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1646 set_feature(&cpu->env, ARM_FEATURE_NEON); 1647 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1648 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 1649 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 1650 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 1651 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 1652 set_feature(&cpu->env, ARM_FEATURE_CRC); 1653 cpu->midr = 0xffffffff; 1654 } 1655 #endif 1656 1657 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 1658 1659 typedef struct ARMCPUInfo { 1660 const char *name; 1661 void (*initfn)(Object *obj); 1662 void (*class_init)(ObjectClass *oc, void *data); 1663 } ARMCPUInfo; 1664 1665 static const ARMCPUInfo arm_cpus[] = { 1666 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1667 { .name = "arm926", .initfn = arm926_initfn }, 1668 { .name = "arm946", .initfn = arm946_initfn }, 1669 { .name = "arm1026", .initfn = arm1026_initfn }, 1670 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1671 * older core than plain "arm1136". In particular this does not 1672 * have the v6K features. 1673 */ 1674 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1675 { .name = "arm1136", .initfn = arm1136_initfn }, 1676 { .name = "arm1176", .initfn = arm1176_initfn }, 1677 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1678 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 1679 .class_init = arm_v7m_class_init }, 1680 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 1681 .class_init = arm_v7m_class_init }, 1682 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1683 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1684 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1685 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1686 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1687 { .name = "ti925t", .initfn = ti925t_initfn }, 1688 { .name = "sa1100", .initfn = sa1100_initfn }, 1689 { .name = "sa1110", .initfn = sa1110_initfn }, 1690 { .name = "pxa250", .initfn = pxa250_initfn }, 1691 { .name = "pxa255", .initfn = pxa255_initfn }, 1692 { .name = "pxa260", .initfn = pxa260_initfn }, 1693 { .name = "pxa261", .initfn = pxa261_initfn }, 1694 { .name = "pxa262", .initfn = pxa262_initfn }, 1695 /* "pxa270" is an alias for "pxa270-a0" */ 1696 { .name = "pxa270", .initfn = pxa270a0_initfn }, 1697 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 1698 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 1699 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 1700 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 1701 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 1702 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 1703 #ifdef CONFIG_USER_ONLY 1704 { .name = "any", .initfn = arm_any_initfn }, 1705 #endif 1706 #endif 1707 { .name = NULL } 1708 }; 1709 1710 static Property arm_cpu_properties[] = { 1711 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 1712 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 1713 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 1714 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 1715 mp_affinity, ARM64_AFFINITY_INVALID), 1716 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 1717 DEFINE_PROP_END_OF_LIST() 1718 }; 1719 1720 #ifdef CONFIG_USER_ONLY 1721 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, 1722 int rw, int mmu_idx) 1723 { 1724 ARMCPU *cpu = ARM_CPU(cs); 1725 CPUARMState *env = &cpu->env; 1726 1727 env->exception.vaddress = address; 1728 if (rw == 2) { 1729 cs->exception_index = EXCP_PREFETCH_ABORT; 1730 } else { 1731 cs->exception_index = EXCP_DATA_ABORT; 1732 } 1733 return 1; 1734 } 1735 #endif 1736 1737 static gchar *arm_gdb_arch_name(CPUState *cs) 1738 { 1739 ARMCPU *cpu = ARM_CPU(cs); 1740 CPUARMState *env = &cpu->env; 1741 1742 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 1743 return g_strdup("iwmmxt"); 1744 } 1745 return g_strdup("arm"); 1746 } 1747 1748 static void arm_cpu_class_init(ObjectClass *oc, void *data) 1749 { 1750 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1751 CPUClass *cc = CPU_CLASS(acc); 1752 DeviceClass *dc = DEVICE_CLASS(oc); 1753 1754 device_class_set_parent_realize(dc, arm_cpu_realizefn, 1755 &acc->parent_realize); 1756 dc->props = arm_cpu_properties; 1757 1758 acc->parent_reset = cc->reset; 1759 cc->reset = arm_cpu_reset; 1760 1761 cc->class_by_name = arm_cpu_class_by_name; 1762 cc->has_work = arm_cpu_has_work; 1763 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 1764 cc->dump_state = arm_cpu_dump_state; 1765 cc->set_pc = arm_cpu_set_pc; 1766 cc->gdb_read_register = arm_cpu_gdb_read_register; 1767 cc->gdb_write_register = arm_cpu_gdb_write_register; 1768 #ifdef CONFIG_USER_ONLY 1769 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; 1770 #else 1771 cc->do_interrupt = arm_cpu_do_interrupt; 1772 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 1773 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 1774 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 1775 cc->asidx_from_attrs = arm_asidx_from_attrs; 1776 cc->vmsd = &vmstate_arm_cpu; 1777 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 1778 cc->write_elf64_note = arm_cpu_write_elf64_note; 1779 cc->write_elf32_note = arm_cpu_write_elf32_note; 1780 #endif 1781 cc->gdb_num_core_regs = 26; 1782 cc->gdb_core_xml_file = "arm-core.xml"; 1783 cc->gdb_arch_name = arm_gdb_arch_name; 1784 cc->gdb_stop_before_watchpoint = true; 1785 cc->debug_excp_handler = arm_debug_excp_handler; 1786 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 1787 #if !defined(CONFIG_USER_ONLY) 1788 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 1789 #endif 1790 1791 cc->disas_set_info = arm_disas_set_info; 1792 #ifdef CONFIG_TCG 1793 cc->tcg_initialize = arm_translate_init; 1794 #endif 1795 } 1796 1797 static void cpu_register(const ARMCPUInfo *info) 1798 { 1799 TypeInfo type_info = { 1800 .parent = TYPE_ARM_CPU, 1801 .instance_size = sizeof(ARMCPU), 1802 .instance_init = info->initfn, 1803 .class_size = sizeof(ARMCPUClass), 1804 .class_init = info->class_init, 1805 }; 1806 1807 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 1808 type_register(&type_info); 1809 g_free((void *)type_info.name); 1810 } 1811 1812 static const TypeInfo arm_cpu_type_info = { 1813 .name = TYPE_ARM_CPU, 1814 .parent = TYPE_CPU, 1815 .instance_size = sizeof(ARMCPU), 1816 .instance_init = arm_cpu_initfn, 1817 .instance_post_init = arm_cpu_post_init, 1818 .instance_finalize = arm_cpu_finalizefn, 1819 .abstract = true, 1820 .class_size = sizeof(ARMCPUClass), 1821 .class_init = arm_cpu_class_init, 1822 }; 1823 1824 static void arm_cpu_register_types(void) 1825 { 1826 const ARMCPUInfo *info = arm_cpus; 1827 1828 type_register_static(&arm_cpu_type_info); 1829 1830 while (info->name) { 1831 cpu_register(info); 1832 info++; 1833 } 1834 } 1835 1836 type_init(arm_cpu_register_types) 1837