1 /* 2 * ARM cpu parameters for qemu. 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * SPDX-License-Identifier: LGPL-2.0+ 6 */ 7 8 #ifndef ARM_CPU_PARAM_H 9 #define ARM_CPU_PARAM_H 10 11 #ifdef TARGET_AARCH64 12 # define TARGET_LONG_BITS 64 13 # define TARGET_PHYS_ADDR_SPACE_BITS 52 14 # define TARGET_VIRT_ADDR_SPACE_BITS 52 15 #else 16 # define TARGET_LONG_BITS 32 17 # define TARGET_PHYS_ADDR_SPACE_BITS 40 18 # define TARGET_VIRT_ADDR_SPACE_BITS 32 19 #endif 20 21 #ifdef CONFIG_USER_ONLY 22 #define TARGET_PAGE_BITS 12 23 # ifdef TARGET_AARCH64 24 # define TARGET_TAGGED_ADDRESSES 25 # endif 26 #else 27 /* 28 * ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 29 * have to support 1K tiny pages. 30 */ 31 # define TARGET_PAGE_BITS_VARY 32 # define TARGET_PAGE_BITS_MIN 10 33 34 # define TARGET_TB_PCREL 1 35 36 /* 37 * Cache the attrs and shareability fields from the page table entry. 38 * 39 * For ARMMMUIdx_Stage2*, pte_attrs is the S2 descriptor bits [5:2]. 40 * Otherwise, pte_attrs is the same as the MAIR_EL1 8-bit format. 41 * For shareability and guarded, as in the SH and GP fields respectively 42 * of the VMSAv8-64 PTEs. 43 */ 44 # define TARGET_PAGE_ENTRY_EXTRA \ 45 uint8_t pte_attrs; \ 46 uint8_t shareability; \ 47 bool guarded; 48 #endif 49 50 #define NB_MMU_MODES 12 51 52 #endif 53