1 /* 2 * QEMU ARM CP Register access and descriptions 3 * 4 * Copyright (c) 2022 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #ifndef TARGET_ARM_CPREGS_H 22 #define TARGET_ARM_CPREGS_H 23 24 /* 25 * ARMCPRegInfo type field bits: 26 */ 27 enum { 28 /* 29 * Register must be handled specially during translation. 30 * The method is one of the values below: 31 */ 32 ARM_CP_SPECIAL_MASK = 0x000f, 33 /* Special: no change to PE state: writes ignored, reads ignored. */ 34 ARM_CP_NOP = 0x0001, 35 /* Special: sysreg is WFI, for v5 and v6. */ 36 ARM_CP_WFI = 0x0002, 37 /* Special: sysreg is NZCV. */ 38 ARM_CP_NZCV = 0x0003, 39 /* Special: sysreg is CURRENTEL. */ 40 ARM_CP_CURRENTEL = 0x0004, 41 /* Special: sysreg is DC ZVA or similar. */ 42 ARM_CP_DC_ZVA = 0x0005, 43 ARM_CP_DC_GVA = 0x0006, 44 ARM_CP_DC_GZVA = 0x0007, 45 46 /* Flag: reads produce resetvalue; writes ignored. */ 47 ARM_CP_CONST = 1 << 4, 48 /* Flag: For ARM_CP_STATE_AA32, sysreg is 64-bit. */ 49 ARM_CP_64BIT = 1 << 5, 50 /* 51 * Flag: TB should not be ended after a write to this register 52 * (the default is that the TB ends after cp writes). 53 */ 54 ARM_CP_SUPPRESS_TB_END = 1 << 6, 55 /* 56 * Flag: Permit a register definition to override a previous definition 57 * for the same (cp, is64, crn, crm, opc1, opc2) tuple: either the new 58 * or the old must have the ARM_CP_OVERRIDE bit set. 59 */ 60 ARM_CP_OVERRIDE = 1 << 7, 61 /* 62 * Flag: Register is an alias view of some underlying state which is also 63 * visible via another register, and that the other register is handling 64 * migration and reset; registers marked ARM_CP_ALIAS will not be migrated 65 * but may have their state set by syncing of register state from KVM. 66 */ 67 ARM_CP_ALIAS = 1 << 8, 68 /* 69 * Flag: Register does I/O and therefore its accesses need to be marked 70 * with gen_io_start() and also end the TB. In particular, registers which 71 * implement clocks or timers require this. 72 */ 73 ARM_CP_IO = 1 << 9, 74 /* 75 * Flag: Register has no underlying state and does not support raw access 76 * for state saving/loading; it will not be used for either migration or 77 * KVM state synchronization. Typically this is for "registers" which are 78 * actually used as instructions for cache maintenance and so on. 79 */ 80 ARM_CP_NO_RAW = 1 << 10, 81 /* 82 * Flag: The read or write hook might raise an exception; the generated 83 * code will synchronize the CPU state before calling the hook so that it 84 * is safe for the hook to call raise_exception(). 85 */ 86 ARM_CP_RAISES_EXC = 1 << 11, 87 /* 88 * Flag: Writes to the sysreg might change the exception level - typically 89 * on older ARM chips. For those cases we need to re-read the new el when 90 * recomputing the translation flags. 91 */ 92 ARM_CP_NEWEL = 1 << 12, 93 /* 94 * Flag: Access check for this sysreg is identical to accessing FPU state 95 * from an instruction: use translation fp_access_check(). 96 */ 97 ARM_CP_FPU = 1 << 13, 98 /* 99 * Flag: Access check for this sysreg is identical to accessing SVE state 100 * from an instruction: use translation sve_access_check(). 101 */ 102 ARM_CP_SVE = 1 << 14, 103 /* Flag: Do not expose in gdb sysreg xml. */ 104 ARM_CP_NO_GDB = 1 << 15, 105 /* 106 * Flags: If EL3 but not EL2... 107 * - UNDEF: discard the cpreg, 108 * - KEEP: retain the cpreg as is, 109 * - C_NZ: set const on the cpreg, but retain resetvalue, 110 * - else: set const on the cpreg, zero resetvalue, aka RES0. 111 * See rule RJFFP in section D1.1.3 of DDI0487H.a. 112 */ 113 ARM_CP_EL3_NO_EL2_UNDEF = 1 << 16, 114 ARM_CP_EL3_NO_EL2_KEEP = 1 << 17, 115 ARM_CP_EL3_NO_EL2_C_NZ = 1 << 18, 116 /* 117 * Flag: Access check for this sysreg is constrained by the 118 * ARM pseudocode function CheckSMEAccess(). 119 */ 120 ARM_CP_SME = 1 << 19, 121 }; 122 123 /* 124 * Valid values for ARMCPRegInfo state field, indicating which of 125 * the AArch32 and AArch64 execution states this register is visible in. 126 * If the reginfo doesn't explicitly specify then it is AArch32 only. 127 * If the reginfo is declared to be visible in both states then a second 128 * reginfo is synthesised for the AArch32 view of the AArch64 register, 129 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 130 * Note that we rely on the values of these enums as we iterate through 131 * the various states in some places. 132 */ 133 typedef enum { 134 ARM_CP_STATE_AA32 = 0, 135 ARM_CP_STATE_AA64 = 1, 136 ARM_CP_STATE_BOTH = 2, 137 } CPState; 138 139 /* 140 * ARM CP register secure state flags. These flags identify security state 141 * attributes for a given CP register entry. 142 * The existence of both or neither secure and non-secure flags indicates that 143 * the register has both a secure and non-secure hash entry. A single one of 144 * these flags causes the register to only be hashed for the specified 145 * security state. 146 * Although definitions may have any combination of the S/NS bits, each 147 * registered entry will only have one to identify whether the entry is secure 148 * or non-secure. 149 */ 150 typedef enum { 151 ARM_CP_SECSTATE_BOTH = 0, /* define one cpreg for each secstate */ 152 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 153 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 154 } CPSecureState; 155 156 /* 157 * Access rights: 158 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 159 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 160 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 161 * (ie any of the privileged modes in Secure state, or Monitor mode). 162 * If a register is accessible in one privilege level it's always accessible 163 * in higher privilege levels too. Since "Secure PL1" also follows this rule 164 * (ie anything visible in PL2 is visible in S-PL1, some things are only 165 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 166 * terminology a little and call this PL3. 167 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 168 * with the ELx exception levels. 169 * 170 * If access permissions for a register are more complex than can be 171 * described with these bits, then use a laxer set of restrictions, and 172 * do the more restrictive/complex check inside a helper function. 173 */ 174 typedef enum { 175 PL3_R = 0x80, 176 PL3_W = 0x40, 177 PL2_R = 0x20 | PL3_R, 178 PL2_W = 0x10 | PL3_W, 179 PL1_R = 0x08 | PL2_R, 180 PL1_W = 0x04 | PL2_W, 181 PL0_R = 0x02 | PL1_R, 182 PL0_W = 0x01 | PL1_W, 183 184 /* 185 * For user-mode some registers are accessible to EL0 via a kernel 186 * trap-and-emulate ABI. In this case we define the read permissions 187 * as actually being PL0_R. However some bits of any given register 188 * may still be masked. 189 */ 190 #ifdef CONFIG_USER_ONLY 191 PL0U_R = PL0_R, 192 #else 193 PL0U_R = PL1_R, 194 #endif 195 196 PL3_RW = PL3_R | PL3_W, 197 PL2_RW = PL2_R | PL2_W, 198 PL1_RW = PL1_R | PL1_W, 199 PL0_RW = PL0_R | PL0_W, 200 } CPAccessRights; 201 202 typedef enum CPAccessResult { 203 /* Access is permitted */ 204 CP_ACCESS_OK = 0, 205 206 /* 207 * Combined with one of the following, the low 2 bits indicate the 208 * target exception level. If 0, the exception is taken to the usual 209 * target EL (EL1 or PL1 if in EL0, otherwise to the current EL). 210 */ 211 CP_ACCESS_EL_MASK = 3, 212 213 /* 214 * Access fails due to a configurable trap or enable which would 215 * result in a categorized exception syndrome giving information about 216 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 217 * 0xc or 0x18). 218 */ 219 CP_ACCESS_TRAP = (1 << 2), 220 CP_ACCESS_TRAP_EL2 = CP_ACCESS_TRAP | 2, 221 CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP | 3, 222 223 /* 224 * Access fails and results in an exception syndrome 0x0 ("uncategorized"). 225 * Note that this is not a catch-all case -- the set of cases which may 226 * result in this failure is specifically defined by the architecture. 227 * This trap is always to the usual target EL, never directly to a 228 * specified target EL. 229 */ 230 CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2), 231 } CPAccessResult; 232 233 /* Indexes into fgt_read[] */ 234 #define FGTREG_HFGRTR 0 235 #define FGTREG_HDFGRTR 1 236 /* Indexes into fgt_write[] */ 237 #define FGTREG_HFGWTR 0 238 #define FGTREG_HDFGWTR 1 239 /* Indexes into fgt_exec[] */ 240 #define FGTREG_HFGITR 0 241 242 FIELD(HFGRTR_EL2, AFSR0_EL1, 0, 1) 243 FIELD(HFGRTR_EL2, AFSR1_EL1, 1, 1) 244 FIELD(HFGRTR_EL2, AIDR_EL1, 2, 1) 245 FIELD(HFGRTR_EL2, AMAIR_EL1, 3, 1) 246 FIELD(HFGRTR_EL2, APDAKEY, 4, 1) 247 FIELD(HFGRTR_EL2, APDBKEY, 5, 1) 248 FIELD(HFGRTR_EL2, APGAKEY, 6, 1) 249 FIELD(HFGRTR_EL2, APIAKEY, 7, 1) 250 FIELD(HFGRTR_EL2, APIBKEY, 8, 1) 251 FIELD(HFGRTR_EL2, CCSIDR_EL1, 9, 1) 252 FIELD(HFGRTR_EL2, CLIDR_EL1, 10, 1) 253 FIELD(HFGRTR_EL2, CONTEXTIDR_EL1, 11, 1) 254 FIELD(HFGRTR_EL2, CPACR_EL1, 12, 1) 255 FIELD(HFGRTR_EL2, CSSELR_EL1, 13, 1) 256 FIELD(HFGRTR_EL2, CTR_EL0, 14, 1) 257 FIELD(HFGRTR_EL2, DCZID_EL0, 15, 1) 258 FIELD(HFGRTR_EL2, ESR_EL1, 16, 1) 259 FIELD(HFGRTR_EL2, FAR_EL1, 17, 1) 260 FIELD(HFGRTR_EL2, ISR_EL1, 18, 1) 261 FIELD(HFGRTR_EL2, LORC_EL1, 19, 1) 262 FIELD(HFGRTR_EL2, LOREA_EL1, 20, 1) 263 FIELD(HFGRTR_EL2, LORID_EL1, 21, 1) 264 FIELD(HFGRTR_EL2, LORN_EL1, 22, 1) 265 FIELD(HFGRTR_EL2, LORSA_EL1, 23, 1) 266 FIELD(HFGRTR_EL2, MAIR_EL1, 24, 1) 267 FIELD(HFGRTR_EL2, MIDR_EL1, 25, 1) 268 FIELD(HFGRTR_EL2, MPIDR_EL1, 26, 1) 269 FIELD(HFGRTR_EL2, PAR_EL1, 27, 1) 270 FIELD(HFGRTR_EL2, REVIDR_EL1, 28, 1) 271 FIELD(HFGRTR_EL2, SCTLR_EL1, 29, 1) 272 FIELD(HFGRTR_EL2, SCXTNUM_EL1, 30, 1) 273 FIELD(HFGRTR_EL2, SCXTNUM_EL0, 31, 1) 274 FIELD(HFGRTR_EL2, TCR_EL1, 32, 1) 275 FIELD(HFGRTR_EL2, TPIDR_EL1, 33, 1) 276 FIELD(HFGRTR_EL2, TPIDRRO_EL0, 34, 1) 277 FIELD(HFGRTR_EL2, TPIDR_EL0, 35, 1) 278 FIELD(HFGRTR_EL2, TTBR0_EL1, 36, 1) 279 FIELD(HFGRTR_EL2, TTBR1_EL1, 37, 1) 280 FIELD(HFGRTR_EL2, VBAR_EL1, 38, 1) 281 FIELD(HFGRTR_EL2, ICC_IGRPENN_EL1, 39, 1) 282 FIELD(HFGRTR_EL2, ERRIDR_EL1, 40, 1) 283 FIELD(HFGRTR_EL2, ERRSELR_EL1, 41, 1) 284 FIELD(HFGRTR_EL2, ERXFR_EL1, 42, 1) 285 FIELD(HFGRTR_EL2, ERXCTLR_EL1, 43, 1) 286 FIELD(HFGRTR_EL2, ERXSTATUS_EL1, 44, 1) 287 FIELD(HFGRTR_EL2, ERXMISCN_EL1, 45, 1) 288 FIELD(HFGRTR_EL2, ERXPFGF_EL1, 46, 1) 289 FIELD(HFGRTR_EL2, ERXPFGCTL_EL1, 47, 1) 290 FIELD(HFGRTR_EL2, ERXPFGCDN_EL1, 48, 1) 291 FIELD(HFGRTR_EL2, ERXADDR_EL1, 49, 1) 292 FIELD(HFGRTR_EL2, NACCDATA_EL1, 50, 1) 293 /* 51-53: RES0 */ 294 FIELD(HFGRTR_EL2, NSMPRI_EL1, 54, 1) 295 FIELD(HFGRTR_EL2, NTPIDR2_EL0, 55, 1) 296 /* 56-63: RES0 */ 297 298 /* These match HFGRTR but bits for RO registers are RES0 */ 299 FIELD(HFGWTR_EL2, AFSR0_EL1, 0, 1) 300 FIELD(HFGWTR_EL2, AFSR1_EL1, 1, 1) 301 FIELD(HFGWTR_EL2, AMAIR_EL1, 3, 1) 302 FIELD(HFGWTR_EL2, APDAKEY, 4, 1) 303 FIELD(HFGWTR_EL2, APDBKEY, 5, 1) 304 FIELD(HFGWTR_EL2, APGAKEY, 6, 1) 305 FIELD(HFGWTR_EL2, APIAKEY, 7, 1) 306 FIELD(HFGWTR_EL2, APIBKEY, 8, 1) 307 FIELD(HFGWTR_EL2, CONTEXTIDR_EL1, 11, 1) 308 FIELD(HFGWTR_EL2, CPACR_EL1, 12, 1) 309 FIELD(HFGWTR_EL2, CSSELR_EL1, 13, 1) 310 FIELD(HFGWTR_EL2, ESR_EL1, 16, 1) 311 FIELD(HFGWTR_EL2, FAR_EL1, 17, 1) 312 FIELD(HFGWTR_EL2, LORC_EL1, 19, 1) 313 FIELD(HFGWTR_EL2, LOREA_EL1, 20, 1) 314 FIELD(HFGWTR_EL2, LORN_EL1, 22, 1) 315 FIELD(HFGWTR_EL2, LORSA_EL1, 23, 1) 316 FIELD(HFGWTR_EL2, MAIR_EL1, 24, 1) 317 FIELD(HFGWTR_EL2, PAR_EL1, 27, 1) 318 FIELD(HFGWTR_EL2, SCTLR_EL1, 29, 1) 319 FIELD(HFGWTR_EL2, SCXTNUM_EL1, 30, 1) 320 FIELD(HFGWTR_EL2, SCXTNUM_EL0, 31, 1) 321 FIELD(HFGWTR_EL2, TCR_EL1, 32, 1) 322 FIELD(HFGWTR_EL2, TPIDR_EL1, 33, 1) 323 FIELD(HFGWTR_EL2, TPIDRRO_EL0, 34, 1) 324 FIELD(HFGWTR_EL2, TPIDR_EL0, 35, 1) 325 FIELD(HFGWTR_EL2, TTBR0_EL1, 36, 1) 326 FIELD(HFGWTR_EL2, TTBR1_EL1, 37, 1) 327 FIELD(HFGWTR_EL2, VBAR_EL1, 38, 1) 328 FIELD(HFGWTR_EL2, ICC_IGRPENN_EL1, 39, 1) 329 FIELD(HFGWTR_EL2, ERRSELR_EL1, 41, 1) 330 FIELD(HFGWTR_EL2, ERXCTLR_EL1, 43, 1) 331 FIELD(HFGWTR_EL2, ERXSTATUS_EL1, 44, 1) 332 FIELD(HFGWTR_EL2, ERXMISCN_EL1, 45, 1) 333 FIELD(HFGWTR_EL2, ERXPFGCTL_EL1, 47, 1) 334 FIELD(HFGWTR_EL2, ERXPFGCDN_EL1, 48, 1) 335 FIELD(HFGWTR_EL2, ERXADDR_EL1, 49, 1) 336 FIELD(HFGWTR_EL2, NACCDATA_EL1, 50, 1) 337 FIELD(HFGWTR_EL2, NSMPRI_EL1, 54, 1) 338 FIELD(HFGWTR_EL2, NTPIDR2_EL0, 55, 1) 339 340 FIELD(HFGITR_EL2, ICIALLUIS, 0, 1) 341 FIELD(HFGITR_EL2, ICIALLU, 1, 1) 342 FIELD(HFGITR_EL2, ICIVAU, 2, 1) 343 FIELD(HFGITR_EL2, DCIVAC, 3, 1) 344 FIELD(HFGITR_EL2, DCISW, 4, 1) 345 FIELD(HFGITR_EL2, DCCSW, 5, 1) 346 FIELD(HFGITR_EL2, DCCISW, 6, 1) 347 FIELD(HFGITR_EL2, DCCVAU, 7, 1) 348 FIELD(HFGITR_EL2, DCCVAP, 8, 1) 349 FIELD(HFGITR_EL2, DCCVADP, 9, 1) 350 FIELD(HFGITR_EL2, DCCIVAC, 10, 1) 351 FIELD(HFGITR_EL2, DCZVA, 11, 1) 352 FIELD(HFGITR_EL2, ATS1E1R, 12, 1) 353 FIELD(HFGITR_EL2, ATS1E1W, 13, 1) 354 FIELD(HFGITR_EL2, ATS1E0R, 14, 1) 355 FIELD(HFGITR_EL2, ATS1E0W, 15, 1) 356 FIELD(HFGITR_EL2, ATS1E1RP, 16, 1) 357 FIELD(HFGITR_EL2, ATS1E1WP, 17, 1) 358 FIELD(HFGITR_EL2, TLBIVMALLE1OS, 18, 1) 359 FIELD(HFGITR_EL2, TLBIVAE1OS, 19, 1) 360 FIELD(HFGITR_EL2, TLBIASIDE1OS, 20, 1) 361 FIELD(HFGITR_EL2, TLBIVAAE1OS, 21, 1) 362 FIELD(HFGITR_EL2, TLBIVALE1OS, 22, 1) 363 FIELD(HFGITR_EL2, TLBIVAALE1OS, 23, 1) 364 FIELD(HFGITR_EL2, TLBIRVAE1OS, 24, 1) 365 FIELD(HFGITR_EL2, TLBIRVAAE1OS, 25, 1) 366 FIELD(HFGITR_EL2, TLBIRVALE1OS, 26, 1) 367 FIELD(HFGITR_EL2, TLBIRVAALE1OS, 27, 1) 368 FIELD(HFGITR_EL2, TLBIVMALLE1IS, 28, 1) 369 FIELD(HFGITR_EL2, TLBIVAE1IS, 29, 1) 370 FIELD(HFGITR_EL2, TLBIASIDE1IS, 30, 1) 371 FIELD(HFGITR_EL2, TLBIVAAE1IS, 31, 1) 372 FIELD(HFGITR_EL2, TLBIVALE1IS, 32, 1) 373 FIELD(HFGITR_EL2, TLBIVAALE1IS, 33, 1) 374 FIELD(HFGITR_EL2, TLBIRVAE1IS, 34, 1) 375 FIELD(HFGITR_EL2, TLBIRVAAE1IS, 35, 1) 376 FIELD(HFGITR_EL2, TLBIRVALE1IS, 36, 1) 377 FIELD(HFGITR_EL2, TLBIRVAALE1IS, 37, 1) 378 FIELD(HFGITR_EL2, TLBIRVAE1, 38, 1) 379 FIELD(HFGITR_EL2, TLBIRVAAE1, 39, 1) 380 FIELD(HFGITR_EL2, TLBIRVALE1, 40, 1) 381 FIELD(HFGITR_EL2, TLBIRVAALE1, 41, 1) 382 FIELD(HFGITR_EL2, TLBIVMALLE1, 42, 1) 383 FIELD(HFGITR_EL2, TLBIVAE1, 43, 1) 384 FIELD(HFGITR_EL2, TLBIASIDE1, 44, 1) 385 FIELD(HFGITR_EL2, TLBIVAAE1, 45, 1) 386 FIELD(HFGITR_EL2, TLBIVALE1, 46, 1) 387 FIELD(HFGITR_EL2, TLBIVAALE1, 47, 1) 388 FIELD(HFGITR_EL2, CFPRCTX, 48, 1) 389 FIELD(HFGITR_EL2, DVPRCTX, 49, 1) 390 FIELD(HFGITR_EL2, CPPRCTX, 50, 1) 391 FIELD(HFGITR_EL2, ERET, 51, 1) 392 FIELD(HFGITR_EL2, SVC_EL0, 52, 1) 393 FIELD(HFGITR_EL2, SVC_EL1, 53, 1) 394 FIELD(HFGITR_EL2, DCCVAC, 54, 1) 395 FIELD(HFGITR_EL2, NBRBINJ, 55, 1) 396 FIELD(HFGITR_EL2, NBRBIALL, 56, 1) 397 398 FIELD(HDFGRTR_EL2, DBGBCRN_EL1, 0, 1) 399 FIELD(HDFGRTR_EL2, DBGBVRN_EL1, 1, 1) 400 FIELD(HDFGRTR_EL2, DBGWCRN_EL1, 2, 1) 401 FIELD(HDFGRTR_EL2, DBGWVRN_EL1, 3, 1) 402 FIELD(HDFGRTR_EL2, MDSCR_EL1, 4, 1) 403 FIELD(HDFGRTR_EL2, DBGCLAIM, 5, 1) 404 FIELD(HDFGRTR_EL2, DBGAUTHSTATUS_EL1, 6, 1) 405 FIELD(HDFGRTR_EL2, DBGPRCR_EL1, 7, 1) 406 /* 8: RES0: OSLAR_EL1 is WO */ 407 FIELD(HDFGRTR_EL2, OSLSR_EL1, 9, 1) 408 FIELD(HDFGRTR_EL2, OSECCR_EL1, 10, 1) 409 FIELD(HDFGRTR_EL2, OSDLR_EL1, 11, 1) 410 FIELD(HDFGRTR_EL2, PMEVCNTRN_EL0, 12, 1) 411 FIELD(HDFGRTR_EL2, PMEVTYPERN_EL0, 13, 1) 412 FIELD(HDFGRTR_EL2, PMCCFILTR_EL0, 14, 1) 413 FIELD(HDFGRTR_EL2, PMCCNTR_EL0, 15, 1) 414 FIELD(HDFGRTR_EL2, PMCNTEN, 16, 1) 415 FIELD(HDFGRTR_EL2, PMINTEN, 17, 1) 416 FIELD(HDFGRTR_EL2, PMOVS, 18, 1) 417 FIELD(HDFGRTR_EL2, PMSELR_EL0, 19, 1) 418 /* 20: RES0: PMSWINC_EL0 is WO */ 419 /* 21: RES0: PMCR_EL0 is WO */ 420 FIELD(HDFGRTR_EL2, PMMIR_EL1, 22, 1) 421 FIELD(HDFGRTR_EL2, PMBLIMITR_EL1, 23, 1) 422 FIELD(HDFGRTR_EL2, PMBPTR_EL1, 24, 1) 423 FIELD(HDFGRTR_EL2, PMBSR_EL1, 25, 1) 424 FIELD(HDFGRTR_EL2, PMSCR_EL1, 26, 1) 425 FIELD(HDFGRTR_EL2, PMSEVFR_EL1, 27, 1) 426 FIELD(HDFGRTR_EL2, PMSFCR_EL1, 28, 1) 427 FIELD(HDFGRTR_EL2, PMSICR_EL1, 29, 1) 428 FIELD(HDFGRTR_EL2, PMSIDR_EL1, 30, 1) 429 FIELD(HDFGRTR_EL2, PMSIRR_EL1, 31, 1) 430 FIELD(HDFGRTR_EL2, PMSLATFR_EL1, 32, 1) 431 FIELD(HDFGRTR_EL2, TRC, 33, 1) 432 FIELD(HDFGRTR_EL2, TRCAUTHSTATUS, 34, 1) 433 FIELD(HDFGRTR_EL2, TRCAUXCTLR, 35, 1) 434 FIELD(HDFGRTR_EL2, TRCCLAIM, 36, 1) 435 FIELD(HDFGRTR_EL2, TRCCNTVRn, 37, 1) 436 /* 38, 39: RES0 */ 437 FIELD(HDFGRTR_EL2, TRCID, 40, 1) 438 FIELD(HDFGRTR_EL2, TRCIMSPECN, 41, 1) 439 /* 42: RES0: TRCOSLAR is WO */ 440 FIELD(HDFGRTR_EL2, TRCOSLSR, 43, 1) 441 FIELD(HDFGRTR_EL2, TRCPRGCTLR, 44, 1) 442 FIELD(HDFGRTR_EL2, TRCSEQSTR, 45, 1) 443 FIELD(HDFGRTR_EL2, TRCSSCSRN, 46, 1) 444 FIELD(HDFGRTR_EL2, TRCSTATR, 47, 1) 445 FIELD(HDFGRTR_EL2, TRCVICTLR, 48, 1) 446 /* 49: RES0: TRFCR_EL1 is WO */ 447 FIELD(HDFGRTR_EL2, TRBBASER_EL1, 50, 1) 448 FIELD(HDFGRTR_EL2, TRBIDR_EL1, 51, 1) 449 FIELD(HDFGRTR_EL2, TRBLIMITR_EL1, 52, 1) 450 FIELD(HDFGRTR_EL2, TRBMAR_EL1, 53, 1) 451 FIELD(HDFGRTR_EL2, TRBPTR_EL1, 54, 1) 452 FIELD(HDFGRTR_EL2, TRBSR_EL1, 55, 1) 453 FIELD(HDFGRTR_EL2, TRBTRG_EL1, 56, 1) 454 FIELD(HDFGRTR_EL2, PMUSERENR_EL0, 57, 1) 455 FIELD(HDFGRTR_EL2, PMCEIDN_EL0, 58, 1) 456 FIELD(HDFGRTR_EL2, NBRBIDR, 59, 1) 457 FIELD(HDFGRTR_EL2, NBRBCTL, 60, 1) 458 FIELD(HDFGRTR_EL2, NBRBDATA, 61, 1) 459 FIELD(HDFGRTR_EL2, NPMSNEVFR_EL1, 62, 1) 460 FIELD(HDFGRTR_EL2, PMBIDR_EL1, 63, 1) 461 462 /* 463 * These match HDFGRTR_EL2, but bits for RO registers are RES0. 464 * A few bits are for WO registers, where the HDFGRTR_EL2 bit is RES0. 465 */ 466 FIELD(HDFGWTR_EL2, DBGBCRN_EL1, 0, 1) 467 FIELD(HDFGWTR_EL2, DBGBVRN_EL1, 1, 1) 468 FIELD(HDFGWTR_EL2, DBGWCRN_EL1, 2, 1) 469 FIELD(HDFGWTR_EL2, DBGWVRN_EL1, 3, 1) 470 FIELD(HDFGWTR_EL2, MDSCR_EL1, 4, 1) 471 FIELD(HDFGWTR_EL2, DBGCLAIM, 5, 1) 472 FIELD(HDFGWTR_EL2, DBGPRCR_EL1, 7, 1) 473 FIELD(HDFGWTR_EL2, OSLAR_EL1, 8, 1) 474 FIELD(HDFGWTR_EL2, OSLSR_EL1, 9, 1) 475 FIELD(HDFGWTR_EL2, OSECCR_EL1, 10, 1) 476 FIELD(HDFGWTR_EL2, OSDLR_EL1, 11, 1) 477 FIELD(HDFGWTR_EL2, PMEVCNTRN_EL0, 12, 1) 478 FIELD(HDFGWTR_EL2, PMEVTYPERN_EL0, 13, 1) 479 FIELD(HDFGWTR_EL2, PMCCFILTR_EL0, 14, 1) 480 FIELD(HDFGWTR_EL2, PMCCNTR_EL0, 15, 1) 481 FIELD(HDFGWTR_EL2, PMCNTEN, 16, 1) 482 FIELD(HDFGWTR_EL2, PMINTEN, 17, 1) 483 FIELD(HDFGWTR_EL2, PMOVS, 18, 1) 484 FIELD(HDFGWTR_EL2, PMSELR_EL0, 19, 1) 485 FIELD(HDFGWTR_EL2, PMSWINC_EL0, 20, 1) 486 FIELD(HDFGWTR_EL2, PMCR_EL0, 21, 1) 487 FIELD(HDFGWTR_EL2, PMBLIMITR_EL1, 23, 1) 488 FIELD(HDFGWTR_EL2, PMBPTR_EL1, 24, 1) 489 FIELD(HDFGWTR_EL2, PMBSR_EL1, 25, 1) 490 FIELD(HDFGWTR_EL2, PMSCR_EL1, 26, 1) 491 FIELD(HDFGWTR_EL2, PMSEVFR_EL1, 27, 1) 492 FIELD(HDFGWTR_EL2, PMSFCR_EL1, 28, 1) 493 FIELD(HDFGWTR_EL2, PMSICR_EL1, 29, 1) 494 FIELD(HDFGWTR_EL2, PMSIRR_EL1, 31, 1) 495 FIELD(HDFGWTR_EL2, PMSLATFR_EL1, 32, 1) 496 FIELD(HDFGWTR_EL2, TRC, 33, 1) 497 FIELD(HDFGWTR_EL2, TRCAUXCTLR, 35, 1) 498 FIELD(HDFGWTR_EL2, TRCCLAIM, 36, 1) 499 FIELD(HDFGWTR_EL2, TRCCNTVRn, 37, 1) 500 FIELD(HDFGWTR_EL2, TRCIMSPECN, 41, 1) 501 FIELD(HDFGWTR_EL2, TRCOSLAR, 42, 1) 502 FIELD(HDFGWTR_EL2, TRCPRGCTLR, 44, 1) 503 FIELD(HDFGWTR_EL2, TRCSEQSTR, 45, 1) 504 FIELD(HDFGWTR_EL2, TRCSSCSRN, 46, 1) 505 FIELD(HDFGWTR_EL2, TRCVICTLR, 48, 1) 506 FIELD(HDFGWTR_EL2, TRFCR_EL1, 49, 1) 507 FIELD(HDFGWTR_EL2, TRBBASER_EL1, 50, 1) 508 FIELD(HDFGWTR_EL2, TRBLIMITR_EL1, 52, 1) 509 FIELD(HDFGWTR_EL2, TRBMAR_EL1, 53, 1) 510 FIELD(HDFGWTR_EL2, TRBPTR_EL1, 54, 1) 511 FIELD(HDFGWTR_EL2, TRBSR_EL1, 55, 1) 512 FIELD(HDFGWTR_EL2, TRBTRG_EL1, 56, 1) 513 FIELD(HDFGWTR_EL2, PMUSERENR_EL0, 57, 1) 514 FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1) 515 FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1) 516 FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1) 517 518 /* Which fine-grained trap bit register to check, if any */ 519 FIELD(FGT, TYPE, 10, 3) 520 FIELD(FGT, REV, 9, 1) /* Is bit sense reversed? */ 521 FIELD(FGT, IDX, 6, 3) /* Index within a uint64_t[] array */ 522 FIELD(FGT, BITPOS, 0, 6) /* Bit position within the uint64_t */ 523 524 /* 525 * Macros to define FGT_##bitname enum constants to use in ARMCPRegInfo::fgt 526 * fields. We assume for brevity's sake that there are no duplicated 527 * bit names across the various FGT registers. 528 */ 529 #define DO_BIT(REG, BITNAME) \ 530 FGT_##BITNAME = FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT 531 532 /* Some bits have reversed sense, so 0 means trap and 1 means not */ 533 #define DO_REV_BIT(REG, BITNAME) \ 534 FGT_##BITNAME = FGT_##REG | FGT_REV | R_##REG##_EL2_##BITNAME##_SHIFT 535 536 typedef enum FGTBit { 537 /* 538 * These bits tell us which register arrays to use: 539 * if FGT_R is set then reads are checked against fgt_read[]; 540 * if FGT_W is set then writes are checked against fgt_write[]; 541 * if FGT_EXEC is set then all accesses are checked against fgt_exec[]. 542 * 543 * For almost all bits in the R/W register pairs, the bit exists in 544 * both registers for a RW register, in HFGRTR/HDFGRTR for a RO register 545 * with the corresponding HFGWTR/HDFGTWTR bit being RES0, and vice-versa 546 * for a WO register. There are unfortunately a couple of exceptions 547 * (PMCR_EL0, TRFCR_EL1) where the register being trapped is RW but 548 * the FGT system only allows trapping of writes, not reads. 549 * 550 * Note that we arrange these bits so that a 0 FGTBit means "no trap". 551 */ 552 FGT_R = 1 << R_FGT_TYPE_SHIFT, 553 FGT_W = 2 << R_FGT_TYPE_SHIFT, 554 FGT_EXEC = 4 << R_FGT_TYPE_SHIFT, 555 FGT_RW = FGT_R | FGT_W, 556 /* Bit to identify whether trap bit is reversed sense */ 557 FGT_REV = R_FGT_REV_MASK, 558 559 /* 560 * If a bit exists in HFGRTR/HDFGRTR then either the register being 561 * trapped is RO or the bit also exists in HFGWTR/HDFGWTR, so we either 562 * want to trap for both reads and writes or else it's harmless to mark 563 * it as trap-on-writes. 564 * If a bit exists only in HFGWTR/HDFGWTR then either the register being 565 * trapped is WO, or else it is one of the two oddball special cases 566 * which are RW but have only a write trap. We mark these as only 567 * FGT_W so we get the right behaviour for those special cases. 568 * (If a bit was added in future that provided only a read trap for an 569 * RW register we'd need to do something special to get the FGT_R bit 570 * only. But this seems unlikely to happen.) 571 * 572 * So for the DO_BIT/DO_REV_BIT macros: use FGT_HFGRTR/FGT_HDFGRTR if 573 * the bit exists in that register. Otherwise use FGT_HFGWTR/FGT_HDFGWTR. 574 */ 575 FGT_HFGRTR = FGT_RW | (FGTREG_HFGRTR << R_FGT_IDX_SHIFT), 576 FGT_HFGWTR = FGT_W | (FGTREG_HFGWTR << R_FGT_IDX_SHIFT), 577 FGT_HDFGRTR = FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT), 578 FGT_HDFGWTR = FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT), 579 FGT_HFGITR = FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT), 580 581 /* Trap bits in HFGRTR_EL2 / HFGWTR_EL2, starting from bit 0. */ 582 DO_BIT(HFGRTR, AFSR0_EL1), 583 DO_BIT(HFGRTR, AFSR1_EL1), 584 DO_BIT(HFGRTR, AIDR_EL1), 585 DO_BIT(HFGRTR, AMAIR_EL1), 586 DO_BIT(HFGRTR, APDAKEY), 587 DO_BIT(HFGRTR, APDBKEY), 588 DO_BIT(HFGRTR, APGAKEY), 589 DO_BIT(HFGRTR, APIAKEY), 590 DO_BIT(HFGRTR, APIBKEY), 591 DO_BIT(HFGRTR, CCSIDR_EL1), 592 DO_BIT(HFGRTR, CLIDR_EL1), 593 DO_BIT(HFGRTR, CONTEXTIDR_EL1), 594 DO_BIT(HFGRTR, CPACR_EL1), 595 DO_BIT(HFGRTR, CSSELR_EL1), 596 DO_BIT(HFGRTR, CTR_EL0), 597 DO_BIT(HFGRTR, DCZID_EL0), 598 DO_BIT(HFGRTR, ESR_EL1), 599 DO_BIT(HFGRTR, FAR_EL1), 600 DO_BIT(HFGRTR, ISR_EL1), 601 DO_BIT(HFGRTR, LORC_EL1), 602 DO_BIT(HFGRTR, LOREA_EL1), 603 DO_BIT(HFGRTR, LORID_EL1), 604 DO_BIT(HFGRTR, LORN_EL1), 605 DO_BIT(HFGRTR, LORSA_EL1), 606 DO_BIT(HFGRTR, MAIR_EL1), 607 DO_BIT(HFGRTR, MIDR_EL1), 608 DO_BIT(HFGRTR, MPIDR_EL1), 609 DO_BIT(HFGRTR, PAR_EL1), 610 DO_BIT(HFGRTR, REVIDR_EL1), 611 DO_BIT(HFGRTR, SCTLR_EL1), 612 DO_BIT(HFGRTR, SCXTNUM_EL1), 613 DO_BIT(HFGRTR, SCXTNUM_EL0), 614 DO_BIT(HFGRTR, TCR_EL1), 615 DO_BIT(HFGRTR, TPIDR_EL1), 616 DO_BIT(HFGRTR, TPIDRRO_EL0), 617 DO_BIT(HFGRTR, TPIDR_EL0), 618 DO_BIT(HFGRTR, TTBR0_EL1), 619 DO_BIT(HFGRTR, TTBR1_EL1), 620 DO_BIT(HFGRTR, VBAR_EL1), 621 DO_BIT(HFGRTR, ICC_IGRPENN_EL1), 622 DO_BIT(HFGRTR, ERRIDR_EL1), 623 DO_REV_BIT(HFGRTR, NSMPRI_EL1), 624 DO_REV_BIT(HFGRTR, NTPIDR2_EL0), 625 } FGTBit; 626 627 #undef DO_BIT 628 #undef DO_REV_BIT 629 630 typedef struct ARMCPRegInfo ARMCPRegInfo; 631 632 /* 633 * Access functions for coprocessor registers. These cannot fail and 634 * may not raise exceptions. 635 */ 636 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 637 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 638 uint64_t value); 639 /* Access permission check functions for coprocessor registers. */ 640 typedef CPAccessResult CPAccessFn(CPUARMState *env, 641 const ARMCPRegInfo *opaque, 642 bool isread); 643 /* Hook function for register reset */ 644 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 645 646 #define CP_ANY 0xff 647 648 /* Definition of an ARM coprocessor register */ 649 struct ARMCPRegInfo { 650 /* Name of register (useful mainly for debugging, need not be unique) */ 651 const char *name; 652 /* 653 * Location of register: coprocessor number and (crn,crm,opc1,opc2) 654 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 655 * 'wildcard' field -- any value of that field in the MRC/MCR insn 656 * will be decoded to this register. The register read and write 657 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 658 * used by the program, so it is possible to register a wildcard and 659 * then behave differently on read/write if necessary. 660 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 661 * must both be zero. 662 * For AArch64-visible registers, opc0 is also used. 663 * Since there are no "coprocessors" in AArch64, cp is purely used as a 664 * way to distinguish (for KVM's benefit) guest-visible system registers 665 * from demuxed ones provided to preserve the "no side effects on 666 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 667 * visible (to match KVM's encoding); cp==0 will be converted to 668 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 669 */ 670 uint8_t cp; 671 uint8_t crn; 672 uint8_t crm; 673 uint8_t opc0; 674 uint8_t opc1; 675 uint8_t opc2; 676 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 677 CPState state; 678 /* Register type: ARM_CP_* bits/values */ 679 int type; 680 /* Access rights: PL*_[RW] */ 681 CPAccessRights access; 682 /* Security state: ARM_CP_SECSTATE_* bits/values */ 683 CPSecureState secure; 684 /* 685 * Which fine-grained trap register bit to check, if any. This 686 * value encodes both the trap register and bit within it. 687 */ 688 FGTBit fgt; 689 /* 690 * The opaque pointer passed to define_arm_cp_regs_with_opaque() when 691 * this register was defined: can be used to hand data through to the 692 * register read/write functions, since they are passed the ARMCPRegInfo*. 693 */ 694 void *opaque; 695 /* 696 * Value of this register, if it is ARM_CP_CONST. Otherwise, if 697 * fieldoffset is non-zero, the reset value of the register. 698 */ 699 uint64_t resetvalue; 700 /* 701 * Offset of the field in CPUARMState for this register. 702 * This is not needed if either: 703 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 704 * 2. both readfn and writefn are specified 705 */ 706 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 707 708 /* 709 * Offsets of the secure and non-secure fields in CPUARMState for the 710 * register if it is banked. These fields are only used during the static 711 * registration of a register. During hashing the bank associated 712 * with a given security state is copied to fieldoffset which is used from 713 * there on out. 714 * 715 * It is expected that register definitions use either fieldoffset or 716 * bank_fieldoffsets in the definition but not both. It is also expected 717 * that both bank offsets are set when defining a banked register. This 718 * use indicates that a register is banked. 719 */ 720 ptrdiff_t bank_fieldoffsets[2]; 721 722 /* 723 * Function for making any access checks for this register in addition to 724 * those specified by the 'access' permissions bits. If NULL, no extra 725 * checks required. The access check is performed at runtime, not at 726 * translate time. 727 */ 728 CPAccessFn *accessfn; 729 /* 730 * Function for handling reads of this register. If NULL, then reads 731 * will be done by loading from the offset into CPUARMState specified 732 * by fieldoffset. 733 */ 734 CPReadFn *readfn; 735 /* 736 * Function for handling writes of this register. If NULL, then writes 737 * will be done by writing to the offset into CPUARMState specified 738 * by fieldoffset. 739 */ 740 CPWriteFn *writefn; 741 /* 742 * Function for doing a "raw" read; used when we need to copy 743 * coprocessor state to the kernel for KVM or out for 744 * migration. This only needs to be provided if there is also a 745 * readfn and it has side effects (for instance clear-on-read bits). 746 */ 747 CPReadFn *raw_readfn; 748 /* 749 * Function for doing a "raw" write; used when we need to copy KVM 750 * kernel coprocessor state into userspace, or for inbound 751 * migration. This only needs to be provided if there is also a 752 * writefn and it masks out "unwritable" bits or has write-one-to-clear 753 * or similar behaviour. 754 */ 755 CPWriteFn *raw_writefn; 756 /* 757 * Function for resetting the register. If NULL, then reset will be done 758 * by writing resetvalue to the field specified in fieldoffset. If 759 * fieldoffset is 0 then no reset will be done. 760 */ 761 CPResetFn *resetfn; 762 763 /* 764 * "Original" writefn and readfn. 765 * For ARMv8.1-VHE register aliases, we overwrite the read/write 766 * accessor functions of various EL1/EL0 to perform the runtime 767 * check for which sysreg should actually be modified, and then 768 * forwards the operation. Before overwriting the accessors, 769 * the original function is copied here, so that accesses that 770 * really do go to the EL1/EL0 version proceed normally. 771 * (The corresponding EL2 register is linked via opaque.) 772 */ 773 CPReadFn *orig_readfn; 774 CPWriteFn *orig_writefn; 775 }; 776 777 /* 778 * Macros which are lvalues for the field in CPUARMState for the 779 * ARMCPRegInfo *ri. 780 */ 781 #define CPREG_FIELD32(env, ri) \ 782 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 783 #define CPREG_FIELD64(env, ri) \ 784 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 785 786 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, const ARMCPRegInfo *reg, 787 void *opaque); 788 789 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 790 { 791 define_one_arm_cp_reg_with_opaque(cpu, regs, NULL); 792 } 793 794 void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs, 795 void *opaque, size_t len); 796 797 #define define_arm_cp_regs_with_opaque(CPU, REGS, OPAQUE) \ 798 do { \ 799 QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \ 800 define_arm_cp_regs_with_opaque_len(CPU, REGS, OPAQUE, \ 801 ARRAY_SIZE(REGS)); \ 802 } while (0) 803 804 #define define_arm_cp_regs(CPU, REGS) \ 805 define_arm_cp_regs_with_opaque(CPU, REGS, NULL) 806 807 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 808 809 /* 810 * Definition of an ARM co-processor register as viewed from 811 * userspace. This is used for presenting sanitised versions of 812 * registers to userspace when emulating the Linux AArch64 CPU 813 * ID/feature ABI (advertised as HWCAP_CPUID). 814 */ 815 typedef struct ARMCPRegUserSpaceInfo { 816 /* Name of register */ 817 const char *name; 818 819 /* Is the name actually a glob pattern */ 820 bool is_glob; 821 822 /* Only some bits are exported to user space */ 823 uint64_t exported_bits; 824 825 /* Fixed bits are applied after the mask */ 826 uint64_t fixed_bits; 827 } ARMCPRegUserSpaceInfo; 828 829 void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len, 830 const ARMCPRegUserSpaceInfo *mods, 831 size_t mods_len); 832 833 #define modify_arm_cp_regs(REGS, MODS) \ 834 do { \ 835 QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \ 836 QEMU_BUILD_BUG_ON(ARRAY_SIZE(MODS) == 0); \ 837 modify_arm_cp_regs_with_len(REGS, ARRAY_SIZE(REGS), \ 838 MODS, ARRAY_SIZE(MODS)); \ 839 } while (0) 840 841 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 842 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 843 uint64_t value); 844 /* CPReadFn that can be used for read-as-zero behaviour */ 845 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 846 847 /* CPWriteFn that just writes the value to ri->fieldoffset */ 848 void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value); 849 850 /* 851 * CPResetFn that does nothing, for use if no reset is required even 852 * if fieldoffset is non zero. 853 */ 854 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 855 856 /* 857 * Return true if this reginfo struct's field in the cpu state struct 858 * is 64 bits wide. 859 */ 860 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 861 { 862 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 863 } 864 865 static inline bool cp_access_ok(int current_el, 866 const ARMCPRegInfo *ri, int isread) 867 { 868 return (ri->access >> ((current_el * 2) + isread)) & 1; 869 } 870 871 /* Raw read of a coprocessor register (as needed for migration, etc) */ 872 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 873 874 /* 875 * Return true if the cp register encoding is in the "feature ID space" as 876 * defined by FEAT_IDST (and thus should be reported with ER_ELx.EC 877 * as EC_SYSTEMREGISTERTRAP rather than EC_UNCATEGORIZED). 878 */ 879 static inline bool arm_cpreg_encoding_in_idspace(uint8_t opc0, uint8_t opc1, 880 uint8_t opc2, 881 uint8_t crn, uint8_t crm) 882 { 883 return opc0 == 3 && (opc1 == 0 || opc1 == 1 || opc1 == 3) && 884 crn == 0 && crm < 8; 885 } 886 887 /* 888 * As arm_cpreg_encoding_in_idspace(), but take the encoding from an 889 * ARMCPRegInfo. 890 */ 891 static inline bool arm_cpreg_in_idspace(const ARMCPRegInfo *ri) 892 { 893 return ri->state == ARM_CP_STATE_AA64 && 894 arm_cpreg_encoding_in_idspace(ri->opc0, ri->opc1, ri->opc2, 895 ri->crn, ri->crm); 896 } 897 898 #endif /* TARGET_ARM_CPREGS_H */ 899