1 /* 2 * QEMU ARM CP Register access and descriptions 3 * 4 * Copyright (c) 2022 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #ifndef TARGET_ARM_CPREGS_H 22 #define TARGET_ARM_CPREGS_H 23 24 /* 25 * ARMCPRegInfo type field bits: 26 */ 27 enum { 28 /* 29 * Register must be handled specially during translation. 30 * The method is one of the values below: 31 */ 32 ARM_CP_SPECIAL_MASK = 0x000f, 33 /* Special: no change to PE state: writes ignored, reads ignored. */ 34 ARM_CP_NOP = 0x0001, 35 /* Special: sysreg is WFI, for v5 and v6. */ 36 ARM_CP_WFI = 0x0002, 37 /* Special: sysreg is NZCV. */ 38 ARM_CP_NZCV = 0x0003, 39 /* Special: sysreg is CURRENTEL. */ 40 ARM_CP_CURRENTEL = 0x0004, 41 /* Special: sysreg is DC ZVA or similar. */ 42 ARM_CP_DC_ZVA = 0x0005, 43 ARM_CP_DC_GVA = 0x0006, 44 ARM_CP_DC_GZVA = 0x0007, 45 46 /* Flag: reads produce resetvalue; writes ignored. */ 47 ARM_CP_CONST = 1 << 4, 48 /* Flag: For ARM_CP_STATE_AA32, sysreg is 64-bit. */ 49 ARM_CP_64BIT = 1 << 5, 50 /* 51 * Flag: TB should not be ended after a write to this register 52 * (the default is that the TB ends after cp writes). 53 */ 54 ARM_CP_SUPPRESS_TB_END = 1 << 6, 55 /* 56 * Flag: Permit a register definition to override a previous definition 57 * for the same (cp, is64, crn, crm, opc1, opc2) tuple: either the new 58 * or the old must have the ARM_CP_OVERRIDE bit set. 59 */ 60 ARM_CP_OVERRIDE = 1 << 7, 61 /* 62 * Flag: Register is an alias view of some underlying state which is also 63 * visible via another register, and that the other register is handling 64 * migration and reset; registers marked ARM_CP_ALIAS will not be migrated 65 * but may have their state set by syncing of register state from KVM. 66 */ 67 ARM_CP_ALIAS = 1 << 8, 68 /* 69 * Flag: Register does I/O and therefore its accesses need to be marked 70 * with gen_io_start() and also end the TB. In particular, registers which 71 * implement clocks or timers require this. 72 */ 73 ARM_CP_IO = 1 << 9, 74 /* 75 * Flag: Register has no underlying state and does not support raw access 76 * for state saving/loading; it will not be used for either migration or 77 * KVM state synchronization. Typically this is for "registers" which are 78 * actually used as instructions for cache maintenance and so on. 79 */ 80 ARM_CP_NO_RAW = 1 << 10, 81 /* 82 * Flag: The read or write hook might raise an exception; the generated 83 * code will synchronize the CPU state before calling the hook so that it 84 * is safe for the hook to call raise_exception(). 85 */ 86 ARM_CP_RAISES_EXC = 1 << 11, 87 /* 88 * Flag: Writes to the sysreg might change the exception level - typically 89 * on older ARM chips. For those cases we need to re-read the new el when 90 * recomputing the translation flags. 91 */ 92 ARM_CP_NEWEL = 1 << 12, 93 /* 94 * Flag: Access check for this sysreg is identical to accessing FPU state 95 * from an instruction: use translation fp_access_check(). 96 */ 97 ARM_CP_FPU = 1 << 13, 98 /* 99 * Flag: Access check for this sysreg is identical to accessing SVE state 100 * from an instruction: use translation sve_access_check(). 101 */ 102 ARM_CP_SVE = 1 << 14, 103 /* Flag: Do not expose in gdb sysreg xml. */ 104 ARM_CP_NO_GDB = 1 << 15, 105 /* 106 * Flags: If EL3 but not EL2... 107 * - UNDEF: discard the cpreg, 108 * - KEEP: retain the cpreg as is, 109 * - C_NZ: set const on the cpreg, but retain resetvalue, 110 * - else: set const on the cpreg, zero resetvalue, aka RES0. 111 * See rule RJFFP in section D1.1.3 of DDI0487H.a. 112 */ 113 ARM_CP_EL3_NO_EL2_UNDEF = 1 << 16, 114 ARM_CP_EL3_NO_EL2_KEEP = 1 << 17, 115 ARM_CP_EL3_NO_EL2_C_NZ = 1 << 18, 116 /* 117 * Flag: Access check for this sysreg is constrained by the 118 * ARM pseudocode function CheckSMEAccess(). 119 */ 120 ARM_CP_SME = 1 << 19, 121 }; 122 123 /* 124 * Interface for defining coprocessor registers. 125 * Registers are defined in tables of arm_cp_reginfo structs 126 * which are passed to define_arm_cp_regs(). 127 */ 128 129 /* 130 * When looking up a coprocessor register we look for it 131 * via an integer which encodes all of: 132 * coprocessor number 133 * Crn, Crm, opc1, opc2 fields 134 * 32 or 64 bit register (ie is it accessed via MRC/MCR 135 * or via MRRC/MCRR?) 136 * non-secure/secure bank (AArch32 only) 137 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 138 * (In this case crn and opc2 should be zero.) 139 * For AArch64, there is no 32/64 bit size distinction; 140 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 141 * and 4 bit CRn and CRm. The encoding patterns are chosen 142 * to be easy to convert to and from the KVM encodings, and also 143 * so that the hashtable can contain both AArch32 and AArch64 144 * registers (to allow for interprocessing where we might run 145 * 32 bit code on a 64 bit core). 146 */ 147 /* 148 * This bit is private to our hashtable cpreg; in KVM register 149 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 150 * in the upper bits of the 64 bit ID. 151 */ 152 #define CP_REG_AA64_SHIFT 28 153 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 154 155 /* 156 * To enable banking of coprocessor registers depending on ns-bit we 157 * add a bit to distinguish between secure and non-secure cpregs in the 158 * hashtable. 159 */ 160 #define CP_REG_NS_SHIFT 29 161 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 162 163 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 164 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 165 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 166 167 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 168 (CP_REG_AA64_MASK | \ 169 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 170 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 171 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 172 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 173 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 174 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 175 176 /* 177 * Convert a full 64 bit KVM register ID to the truncated 32 bit 178 * version used as a key for the coprocessor register hashtable 179 */ 180 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 181 { 182 uint32_t cpregid = kvmid; 183 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 184 cpregid |= CP_REG_AA64_MASK; 185 } else { 186 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 187 cpregid |= (1 << 15); 188 } 189 190 /* 191 * KVM is always non-secure so add the NS flag on AArch32 register 192 * entries. 193 */ 194 cpregid |= 1 << CP_REG_NS_SHIFT; 195 } 196 return cpregid; 197 } 198 199 /* 200 * Convert a truncated 32 bit hashtable key into the full 201 * 64 bit KVM register ID. 202 */ 203 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 204 { 205 uint64_t kvmid; 206 207 if (cpregid & CP_REG_AA64_MASK) { 208 kvmid = cpregid & ~CP_REG_AA64_MASK; 209 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 210 } else { 211 kvmid = cpregid & ~(1 << 15); 212 if (cpregid & (1 << 15)) { 213 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 214 } else { 215 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 216 } 217 } 218 return kvmid; 219 } 220 221 /* 222 * Valid values for ARMCPRegInfo state field, indicating which of 223 * the AArch32 and AArch64 execution states this register is visible in. 224 * If the reginfo doesn't explicitly specify then it is AArch32 only. 225 * If the reginfo is declared to be visible in both states then a second 226 * reginfo is synthesised for the AArch32 view of the AArch64 register, 227 * such that the AArch32 view is the lower 32 bits of the AArch64 one. 228 * Note that we rely on the values of these enums as we iterate through 229 * the various states in some places. 230 */ 231 typedef enum { 232 ARM_CP_STATE_AA32 = 0, 233 ARM_CP_STATE_AA64 = 1, 234 ARM_CP_STATE_BOTH = 2, 235 } CPState; 236 237 /* 238 * ARM CP register secure state flags. These flags identify security state 239 * attributes for a given CP register entry. 240 * The existence of both or neither secure and non-secure flags indicates that 241 * the register has both a secure and non-secure hash entry. A single one of 242 * these flags causes the register to only be hashed for the specified 243 * security state. 244 * Although definitions may have any combination of the S/NS bits, each 245 * registered entry will only have one to identify whether the entry is secure 246 * or non-secure. 247 */ 248 typedef enum { 249 ARM_CP_SECSTATE_BOTH = 0, /* define one cpreg for each secstate */ 250 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ 251 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ 252 } CPSecureState; 253 254 /* 255 * Access rights: 256 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM 257 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and 258 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 259 * (ie any of the privileged modes in Secure state, or Monitor mode). 260 * If a register is accessible in one privilege level it's always accessible 261 * in higher privilege levels too. Since "Secure PL1" also follows this rule 262 * (ie anything visible in PL2 is visible in S-PL1, some things are only 263 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the 264 * terminology a little and call this PL3. 265 * In AArch64 things are somewhat simpler as the PLx bits line up exactly 266 * with the ELx exception levels. 267 * 268 * If access permissions for a register are more complex than can be 269 * described with these bits, then use a laxer set of restrictions, and 270 * do the more restrictive/complex check inside a helper function. 271 */ 272 typedef enum { 273 PL3_R = 0x80, 274 PL3_W = 0x40, 275 PL2_R = 0x20 | PL3_R, 276 PL2_W = 0x10 | PL3_W, 277 PL1_R = 0x08 | PL2_R, 278 PL1_W = 0x04 | PL2_W, 279 PL0_R = 0x02 | PL1_R, 280 PL0_W = 0x01 | PL1_W, 281 282 /* 283 * For user-mode some registers are accessible to EL0 via a kernel 284 * trap-and-emulate ABI. In this case we define the read permissions 285 * as actually being PL0_R. However some bits of any given register 286 * may still be masked. 287 */ 288 #ifdef CONFIG_USER_ONLY 289 PL0U_R = PL0_R, 290 #else 291 PL0U_R = PL1_R, 292 #endif 293 294 PL3_RW = PL3_R | PL3_W, 295 PL2_RW = PL2_R | PL2_W, 296 PL1_RW = PL1_R | PL1_W, 297 PL0_RW = PL0_R | PL0_W, 298 } CPAccessRights; 299 300 typedef enum CPAccessResult { 301 /* Access is permitted */ 302 CP_ACCESS_OK = 0, 303 304 /* 305 * Combined with one of the following, the low 2 bits indicate the 306 * target exception level. If 0, the exception is taken to the usual 307 * target EL (EL1 or PL1 if in EL0, otherwise to the current EL). 308 */ 309 CP_ACCESS_EL_MASK = 3, 310 311 /* 312 * Access fails due to a configurable trap or enable which would 313 * result in a categorized exception syndrome giving information about 314 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, 315 * 0xc or 0x18). 316 */ 317 CP_ACCESS_TRAP = (1 << 2), 318 CP_ACCESS_TRAP_EL2 = CP_ACCESS_TRAP | 2, 319 CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP | 3, 320 321 /* 322 * Access fails and results in an exception syndrome 0x0 ("uncategorized"). 323 * Note that this is not a catch-all case -- the set of cases which may 324 * result in this failure is specifically defined by the architecture. 325 * This trap is always to the usual target EL, never directly to a 326 * specified target EL. 327 */ 328 CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2), 329 } CPAccessResult; 330 331 /* Indexes into fgt_read[] */ 332 #define FGTREG_HFGRTR 0 333 #define FGTREG_HDFGRTR 1 334 /* Indexes into fgt_write[] */ 335 #define FGTREG_HFGWTR 0 336 #define FGTREG_HDFGWTR 1 337 /* Indexes into fgt_exec[] */ 338 #define FGTREG_HFGITR 0 339 340 FIELD(HFGRTR_EL2, AFSR0_EL1, 0, 1) 341 FIELD(HFGRTR_EL2, AFSR1_EL1, 1, 1) 342 FIELD(HFGRTR_EL2, AIDR_EL1, 2, 1) 343 FIELD(HFGRTR_EL2, AMAIR_EL1, 3, 1) 344 FIELD(HFGRTR_EL2, APDAKEY, 4, 1) 345 FIELD(HFGRTR_EL2, APDBKEY, 5, 1) 346 FIELD(HFGRTR_EL2, APGAKEY, 6, 1) 347 FIELD(HFGRTR_EL2, APIAKEY, 7, 1) 348 FIELD(HFGRTR_EL2, APIBKEY, 8, 1) 349 FIELD(HFGRTR_EL2, CCSIDR_EL1, 9, 1) 350 FIELD(HFGRTR_EL2, CLIDR_EL1, 10, 1) 351 FIELD(HFGRTR_EL2, CONTEXTIDR_EL1, 11, 1) 352 FIELD(HFGRTR_EL2, CPACR_EL1, 12, 1) 353 FIELD(HFGRTR_EL2, CSSELR_EL1, 13, 1) 354 FIELD(HFGRTR_EL2, CTR_EL0, 14, 1) 355 FIELD(HFGRTR_EL2, DCZID_EL0, 15, 1) 356 FIELD(HFGRTR_EL2, ESR_EL1, 16, 1) 357 FIELD(HFGRTR_EL2, FAR_EL1, 17, 1) 358 FIELD(HFGRTR_EL2, ISR_EL1, 18, 1) 359 FIELD(HFGRTR_EL2, LORC_EL1, 19, 1) 360 FIELD(HFGRTR_EL2, LOREA_EL1, 20, 1) 361 FIELD(HFGRTR_EL2, LORID_EL1, 21, 1) 362 FIELD(HFGRTR_EL2, LORN_EL1, 22, 1) 363 FIELD(HFGRTR_EL2, LORSA_EL1, 23, 1) 364 FIELD(HFGRTR_EL2, MAIR_EL1, 24, 1) 365 FIELD(HFGRTR_EL2, MIDR_EL1, 25, 1) 366 FIELD(HFGRTR_EL2, MPIDR_EL1, 26, 1) 367 FIELD(HFGRTR_EL2, PAR_EL1, 27, 1) 368 FIELD(HFGRTR_EL2, REVIDR_EL1, 28, 1) 369 FIELD(HFGRTR_EL2, SCTLR_EL1, 29, 1) 370 FIELD(HFGRTR_EL2, SCXTNUM_EL1, 30, 1) 371 FIELD(HFGRTR_EL2, SCXTNUM_EL0, 31, 1) 372 FIELD(HFGRTR_EL2, TCR_EL1, 32, 1) 373 FIELD(HFGRTR_EL2, TPIDR_EL1, 33, 1) 374 FIELD(HFGRTR_EL2, TPIDRRO_EL0, 34, 1) 375 FIELD(HFGRTR_EL2, TPIDR_EL0, 35, 1) 376 FIELD(HFGRTR_EL2, TTBR0_EL1, 36, 1) 377 FIELD(HFGRTR_EL2, TTBR1_EL1, 37, 1) 378 FIELD(HFGRTR_EL2, VBAR_EL1, 38, 1) 379 FIELD(HFGRTR_EL2, ICC_IGRPENN_EL1, 39, 1) 380 FIELD(HFGRTR_EL2, ERRIDR_EL1, 40, 1) 381 FIELD(HFGRTR_EL2, ERRSELR_EL1, 41, 1) 382 FIELD(HFGRTR_EL2, ERXFR_EL1, 42, 1) 383 FIELD(HFGRTR_EL2, ERXCTLR_EL1, 43, 1) 384 FIELD(HFGRTR_EL2, ERXSTATUS_EL1, 44, 1) 385 FIELD(HFGRTR_EL2, ERXMISCN_EL1, 45, 1) 386 FIELD(HFGRTR_EL2, ERXPFGF_EL1, 46, 1) 387 FIELD(HFGRTR_EL2, ERXPFGCTL_EL1, 47, 1) 388 FIELD(HFGRTR_EL2, ERXPFGCDN_EL1, 48, 1) 389 FIELD(HFGRTR_EL2, ERXADDR_EL1, 49, 1) 390 FIELD(HFGRTR_EL2, NACCDATA_EL1, 50, 1) 391 /* 51-53: RES0 */ 392 FIELD(HFGRTR_EL2, NSMPRI_EL1, 54, 1) 393 FIELD(HFGRTR_EL2, NTPIDR2_EL0, 55, 1) 394 /* 56-63: RES0 */ 395 396 /* These match HFGRTR but bits for RO registers are RES0 */ 397 FIELD(HFGWTR_EL2, AFSR0_EL1, 0, 1) 398 FIELD(HFGWTR_EL2, AFSR1_EL1, 1, 1) 399 FIELD(HFGWTR_EL2, AMAIR_EL1, 3, 1) 400 FIELD(HFGWTR_EL2, APDAKEY, 4, 1) 401 FIELD(HFGWTR_EL2, APDBKEY, 5, 1) 402 FIELD(HFGWTR_EL2, APGAKEY, 6, 1) 403 FIELD(HFGWTR_EL2, APIAKEY, 7, 1) 404 FIELD(HFGWTR_EL2, APIBKEY, 8, 1) 405 FIELD(HFGWTR_EL2, CONTEXTIDR_EL1, 11, 1) 406 FIELD(HFGWTR_EL2, CPACR_EL1, 12, 1) 407 FIELD(HFGWTR_EL2, CSSELR_EL1, 13, 1) 408 FIELD(HFGWTR_EL2, ESR_EL1, 16, 1) 409 FIELD(HFGWTR_EL2, FAR_EL1, 17, 1) 410 FIELD(HFGWTR_EL2, LORC_EL1, 19, 1) 411 FIELD(HFGWTR_EL2, LOREA_EL1, 20, 1) 412 FIELD(HFGWTR_EL2, LORN_EL1, 22, 1) 413 FIELD(HFGWTR_EL2, LORSA_EL1, 23, 1) 414 FIELD(HFGWTR_EL2, MAIR_EL1, 24, 1) 415 FIELD(HFGWTR_EL2, PAR_EL1, 27, 1) 416 FIELD(HFGWTR_EL2, SCTLR_EL1, 29, 1) 417 FIELD(HFGWTR_EL2, SCXTNUM_EL1, 30, 1) 418 FIELD(HFGWTR_EL2, SCXTNUM_EL0, 31, 1) 419 FIELD(HFGWTR_EL2, TCR_EL1, 32, 1) 420 FIELD(HFGWTR_EL2, TPIDR_EL1, 33, 1) 421 FIELD(HFGWTR_EL2, TPIDRRO_EL0, 34, 1) 422 FIELD(HFGWTR_EL2, TPIDR_EL0, 35, 1) 423 FIELD(HFGWTR_EL2, TTBR0_EL1, 36, 1) 424 FIELD(HFGWTR_EL2, TTBR1_EL1, 37, 1) 425 FIELD(HFGWTR_EL2, VBAR_EL1, 38, 1) 426 FIELD(HFGWTR_EL2, ICC_IGRPENN_EL1, 39, 1) 427 FIELD(HFGWTR_EL2, ERRSELR_EL1, 41, 1) 428 FIELD(HFGWTR_EL2, ERXCTLR_EL1, 43, 1) 429 FIELD(HFGWTR_EL2, ERXSTATUS_EL1, 44, 1) 430 FIELD(HFGWTR_EL2, ERXMISCN_EL1, 45, 1) 431 FIELD(HFGWTR_EL2, ERXPFGCTL_EL1, 47, 1) 432 FIELD(HFGWTR_EL2, ERXPFGCDN_EL1, 48, 1) 433 FIELD(HFGWTR_EL2, ERXADDR_EL1, 49, 1) 434 FIELD(HFGWTR_EL2, NACCDATA_EL1, 50, 1) 435 FIELD(HFGWTR_EL2, NSMPRI_EL1, 54, 1) 436 FIELD(HFGWTR_EL2, NTPIDR2_EL0, 55, 1) 437 438 FIELD(HFGITR_EL2, ICIALLUIS, 0, 1) 439 FIELD(HFGITR_EL2, ICIALLU, 1, 1) 440 FIELD(HFGITR_EL2, ICIVAU, 2, 1) 441 FIELD(HFGITR_EL2, DCIVAC, 3, 1) 442 FIELD(HFGITR_EL2, DCISW, 4, 1) 443 FIELD(HFGITR_EL2, DCCSW, 5, 1) 444 FIELD(HFGITR_EL2, DCCISW, 6, 1) 445 FIELD(HFGITR_EL2, DCCVAU, 7, 1) 446 FIELD(HFGITR_EL2, DCCVAP, 8, 1) 447 FIELD(HFGITR_EL2, DCCVADP, 9, 1) 448 FIELD(HFGITR_EL2, DCCIVAC, 10, 1) 449 FIELD(HFGITR_EL2, DCZVA, 11, 1) 450 FIELD(HFGITR_EL2, ATS1E1R, 12, 1) 451 FIELD(HFGITR_EL2, ATS1E1W, 13, 1) 452 FIELD(HFGITR_EL2, ATS1E0R, 14, 1) 453 FIELD(HFGITR_EL2, ATS1E0W, 15, 1) 454 FIELD(HFGITR_EL2, ATS1E1RP, 16, 1) 455 FIELD(HFGITR_EL2, ATS1E1WP, 17, 1) 456 FIELD(HFGITR_EL2, TLBIVMALLE1OS, 18, 1) 457 FIELD(HFGITR_EL2, TLBIVAE1OS, 19, 1) 458 FIELD(HFGITR_EL2, TLBIASIDE1OS, 20, 1) 459 FIELD(HFGITR_EL2, TLBIVAAE1OS, 21, 1) 460 FIELD(HFGITR_EL2, TLBIVALE1OS, 22, 1) 461 FIELD(HFGITR_EL2, TLBIVAALE1OS, 23, 1) 462 FIELD(HFGITR_EL2, TLBIRVAE1OS, 24, 1) 463 FIELD(HFGITR_EL2, TLBIRVAAE1OS, 25, 1) 464 FIELD(HFGITR_EL2, TLBIRVALE1OS, 26, 1) 465 FIELD(HFGITR_EL2, TLBIRVAALE1OS, 27, 1) 466 FIELD(HFGITR_EL2, TLBIVMALLE1IS, 28, 1) 467 FIELD(HFGITR_EL2, TLBIVAE1IS, 29, 1) 468 FIELD(HFGITR_EL2, TLBIASIDE1IS, 30, 1) 469 FIELD(HFGITR_EL2, TLBIVAAE1IS, 31, 1) 470 FIELD(HFGITR_EL2, TLBIVALE1IS, 32, 1) 471 FIELD(HFGITR_EL2, TLBIVAALE1IS, 33, 1) 472 FIELD(HFGITR_EL2, TLBIRVAE1IS, 34, 1) 473 FIELD(HFGITR_EL2, TLBIRVAAE1IS, 35, 1) 474 FIELD(HFGITR_EL2, TLBIRVALE1IS, 36, 1) 475 FIELD(HFGITR_EL2, TLBIRVAALE1IS, 37, 1) 476 FIELD(HFGITR_EL2, TLBIRVAE1, 38, 1) 477 FIELD(HFGITR_EL2, TLBIRVAAE1, 39, 1) 478 FIELD(HFGITR_EL2, TLBIRVALE1, 40, 1) 479 FIELD(HFGITR_EL2, TLBIRVAALE1, 41, 1) 480 FIELD(HFGITR_EL2, TLBIVMALLE1, 42, 1) 481 FIELD(HFGITR_EL2, TLBIVAE1, 43, 1) 482 FIELD(HFGITR_EL2, TLBIASIDE1, 44, 1) 483 FIELD(HFGITR_EL2, TLBIVAAE1, 45, 1) 484 FIELD(HFGITR_EL2, TLBIVALE1, 46, 1) 485 FIELD(HFGITR_EL2, TLBIVAALE1, 47, 1) 486 FIELD(HFGITR_EL2, CFPRCTX, 48, 1) 487 FIELD(HFGITR_EL2, DVPRCTX, 49, 1) 488 FIELD(HFGITR_EL2, CPPRCTX, 50, 1) 489 FIELD(HFGITR_EL2, ERET, 51, 1) 490 FIELD(HFGITR_EL2, SVC_EL0, 52, 1) 491 FIELD(HFGITR_EL2, SVC_EL1, 53, 1) 492 FIELD(HFGITR_EL2, DCCVAC, 54, 1) 493 FIELD(HFGITR_EL2, NBRBINJ, 55, 1) 494 FIELD(HFGITR_EL2, NBRBIALL, 56, 1) 495 496 FIELD(HDFGRTR_EL2, DBGBCRN_EL1, 0, 1) 497 FIELD(HDFGRTR_EL2, DBGBVRN_EL1, 1, 1) 498 FIELD(HDFGRTR_EL2, DBGWCRN_EL1, 2, 1) 499 FIELD(HDFGRTR_EL2, DBGWVRN_EL1, 3, 1) 500 FIELD(HDFGRTR_EL2, MDSCR_EL1, 4, 1) 501 FIELD(HDFGRTR_EL2, DBGCLAIM, 5, 1) 502 FIELD(HDFGRTR_EL2, DBGAUTHSTATUS_EL1, 6, 1) 503 FIELD(HDFGRTR_EL2, DBGPRCR_EL1, 7, 1) 504 /* 8: RES0: OSLAR_EL1 is WO */ 505 FIELD(HDFGRTR_EL2, OSLSR_EL1, 9, 1) 506 FIELD(HDFGRTR_EL2, OSECCR_EL1, 10, 1) 507 FIELD(HDFGRTR_EL2, OSDLR_EL1, 11, 1) 508 FIELD(HDFGRTR_EL2, PMEVCNTRN_EL0, 12, 1) 509 FIELD(HDFGRTR_EL2, PMEVTYPERN_EL0, 13, 1) 510 FIELD(HDFGRTR_EL2, PMCCFILTR_EL0, 14, 1) 511 FIELD(HDFGRTR_EL2, PMCCNTR_EL0, 15, 1) 512 FIELD(HDFGRTR_EL2, PMCNTEN, 16, 1) 513 FIELD(HDFGRTR_EL2, PMINTEN, 17, 1) 514 FIELD(HDFGRTR_EL2, PMOVS, 18, 1) 515 FIELD(HDFGRTR_EL2, PMSELR_EL0, 19, 1) 516 /* 20: RES0: PMSWINC_EL0 is WO */ 517 /* 21: RES0: PMCR_EL0 is WO */ 518 FIELD(HDFGRTR_EL2, PMMIR_EL1, 22, 1) 519 FIELD(HDFGRTR_EL2, PMBLIMITR_EL1, 23, 1) 520 FIELD(HDFGRTR_EL2, PMBPTR_EL1, 24, 1) 521 FIELD(HDFGRTR_EL2, PMBSR_EL1, 25, 1) 522 FIELD(HDFGRTR_EL2, PMSCR_EL1, 26, 1) 523 FIELD(HDFGRTR_EL2, PMSEVFR_EL1, 27, 1) 524 FIELD(HDFGRTR_EL2, PMSFCR_EL1, 28, 1) 525 FIELD(HDFGRTR_EL2, PMSICR_EL1, 29, 1) 526 FIELD(HDFGRTR_EL2, PMSIDR_EL1, 30, 1) 527 FIELD(HDFGRTR_EL2, PMSIRR_EL1, 31, 1) 528 FIELD(HDFGRTR_EL2, PMSLATFR_EL1, 32, 1) 529 FIELD(HDFGRTR_EL2, TRC, 33, 1) 530 FIELD(HDFGRTR_EL2, TRCAUTHSTATUS, 34, 1) 531 FIELD(HDFGRTR_EL2, TRCAUXCTLR, 35, 1) 532 FIELD(HDFGRTR_EL2, TRCCLAIM, 36, 1) 533 FIELD(HDFGRTR_EL2, TRCCNTVRn, 37, 1) 534 /* 38, 39: RES0 */ 535 FIELD(HDFGRTR_EL2, TRCID, 40, 1) 536 FIELD(HDFGRTR_EL2, TRCIMSPECN, 41, 1) 537 /* 42: RES0: TRCOSLAR is WO */ 538 FIELD(HDFGRTR_EL2, TRCOSLSR, 43, 1) 539 FIELD(HDFGRTR_EL2, TRCPRGCTLR, 44, 1) 540 FIELD(HDFGRTR_EL2, TRCSEQSTR, 45, 1) 541 FIELD(HDFGRTR_EL2, TRCSSCSRN, 46, 1) 542 FIELD(HDFGRTR_EL2, TRCSTATR, 47, 1) 543 FIELD(HDFGRTR_EL2, TRCVICTLR, 48, 1) 544 /* 49: RES0: TRFCR_EL1 is WO */ 545 FIELD(HDFGRTR_EL2, TRBBASER_EL1, 50, 1) 546 FIELD(HDFGRTR_EL2, TRBIDR_EL1, 51, 1) 547 FIELD(HDFGRTR_EL2, TRBLIMITR_EL1, 52, 1) 548 FIELD(HDFGRTR_EL2, TRBMAR_EL1, 53, 1) 549 FIELD(HDFGRTR_EL2, TRBPTR_EL1, 54, 1) 550 FIELD(HDFGRTR_EL2, TRBSR_EL1, 55, 1) 551 FIELD(HDFGRTR_EL2, TRBTRG_EL1, 56, 1) 552 FIELD(HDFGRTR_EL2, PMUSERENR_EL0, 57, 1) 553 FIELD(HDFGRTR_EL2, PMCEIDN_EL0, 58, 1) 554 FIELD(HDFGRTR_EL2, NBRBIDR, 59, 1) 555 FIELD(HDFGRTR_EL2, NBRBCTL, 60, 1) 556 FIELD(HDFGRTR_EL2, NBRBDATA, 61, 1) 557 FIELD(HDFGRTR_EL2, NPMSNEVFR_EL1, 62, 1) 558 FIELD(HDFGRTR_EL2, PMBIDR_EL1, 63, 1) 559 560 /* 561 * These match HDFGRTR_EL2, but bits for RO registers are RES0. 562 * A few bits are for WO registers, where the HDFGRTR_EL2 bit is RES0. 563 */ 564 FIELD(HDFGWTR_EL2, DBGBCRN_EL1, 0, 1) 565 FIELD(HDFGWTR_EL2, DBGBVRN_EL1, 1, 1) 566 FIELD(HDFGWTR_EL2, DBGWCRN_EL1, 2, 1) 567 FIELD(HDFGWTR_EL2, DBGWVRN_EL1, 3, 1) 568 FIELD(HDFGWTR_EL2, MDSCR_EL1, 4, 1) 569 FIELD(HDFGWTR_EL2, DBGCLAIM, 5, 1) 570 FIELD(HDFGWTR_EL2, DBGPRCR_EL1, 7, 1) 571 FIELD(HDFGWTR_EL2, OSLAR_EL1, 8, 1) 572 FIELD(HDFGWTR_EL2, OSLSR_EL1, 9, 1) 573 FIELD(HDFGWTR_EL2, OSECCR_EL1, 10, 1) 574 FIELD(HDFGWTR_EL2, OSDLR_EL1, 11, 1) 575 FIELD(HDFGWTR_EL2, PMEVCNTRN_EL0, 12, 1) 576 FIELD(HDFGWTR_EL2, PMEVTYPERN_EL0, 13, 1) 577 FIELD(HDFGWTR_EL2, PMCCFILTR_EL0, 14, 1) 578 FIELD(HDFGWTR_EL2, PMCCNTR_EL0, 15, 1) 579 FIELD(HDFGWTR_EL2, PMCNTEN, 16, 1) 580 FIELD(HDFGWTR_EL2, PMINTEN, 17, 1) 581 FIELD(HDFGWTR_EL2, PMOVS, 18, 1) 582 FIELD(HDFGWTR_EL2, PMSELR_EL0, 19, 1) 583 FIELD(HDFGWTR_EL2, PMSWINC_EL0, 20, 1) 584 FIELD(HDFGWTR_EL2, PMCR_EL0, 21, 1) 585 FIELD(HDFGWTR_EL2, PMBLIMITR_EL1, 23, 1) 586 FIELD(HDFGWTR_EL2, PMBPTR_EL1, 24, 1) 587 FIELD(HDFGWTR_EL2, PMBSR_EL1, 25, 1) 588 FIELD(HDFGWTR_EL2, PMSCR_EL1, 26, 1) 589 FIELD(HDFGWTR_EL2, PMSEVFR_EL1, 27, 1) 590 FIELD(HDFGWTR_EL2, PMSFCR_EL1, 28, 1) 591 FIELD(HDFGWTR_EL2, PMSICR_EL1, 29, 1) 592 FIELD(HDFGWTR_EL2, PMSIRR_EL1, 31, 1) 593 FIELD(HDFGWTR_EL2, PMSLATFR_EL1, 32, 1) 594 FIELD(HDFGWTR_EL2, TRC, 33, 1) 595 FIELD(HDFGWTR_EL2, TRCAUXCTLR, 35, 1) 596 FIELD(HDFGWTR_EL2, TRCCLAIM, 36, 1) 597 FIELD(HDFGWTR_EL2, TRCCNTVRn, 37, 1) 598 FIELD(HDFGWTR_EL2, TRCIMSPECN, 41, 1) 599 FIELD(HDFGWTR_EL2, TRCOSLAR, 42, 1) 600 FIELD(HDFGWTR_EL2, TRCPRGCTLR, 44, 1) 601 FIELD(HDFGWTR_EL2, TRCSEQSTR, 45, 1) 602 FIELD(HDFGWTR_EL2, TRCSSCSRN, 46, 1) 603 FIELD(HDFGWTR_EL2, TRCVICTLR, 48, 1) 604 FIELD(HDFGWTR_EL2, TRFCR_EL1, 49, 1) 605 FIELD(HDFGWTR_EL2, TRBBASER_EL1, 50, 1) 606 FIELD(HDFGWTR_EL2, TRBLIMITR_EL1, 52, 1) 607 FIELD(HDFGWTR_EL2, TRBMAR_EL1, 53, 1) 608 FIELD(HDFGWTR_EL2, TRBPTR_EL1, 54, 1) 609 FIELD(HDFGWTR_EL2, TRBSR_EL1, 55, 1) 610 FIELD(HDFGWTR_EL2, TRBTRG_EL1, 56, 1) 611 FIELD(HDFGWTR_EL2, PMUSERENR_EL0, 57, 1) 612 FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1) 613 FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1) 614 FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1) 615 616 /* Which fine-grained trap bit register to check, if any */ 617 FIELD(FGT, TYPE, 10, 3) 618 FIELD(FGT, REV, 9, 1) /* Is bit sense reversed? */ 619 FIELD(FGT, IDX, 6, 3) /* Index within a uint64_t[] array */ 620 FIELD(FGT, BITPOS, 0, 6) /* Bit position within the uint64_t */ 621 622 /* 623 * Macros to define FGT_##bitname enum constants to use in ARMCPRegInfo::fgt 624 * fields. We assume for brevity's sake that there are no duplicated 625 * bit names across the various FGT registers. 626 */ 627 #define DO_BIT(REG, BITNAME) \ 628 FGT_##BITNAME = FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT 629 630 /* Some bits have reversed sense, so 0 means trap and 1 means not */ 631 #define DO_REV_BIT(REG, BITNAME) \ 632 FGT_##BITNAME = FGT_##REG | FGT_REV | R_##REG##_EL2_##BITNAME##_SHIFT 633 634 typedef enum FGTBit { 635 /* 636 * These bits tell us which register arrays to use: 637 * if FGT_R is set then reads are checked against fgt_read[]; 638 * if FGT_W is set then writes are checked against fgt_write[]; 639 * if FGT_EXEC is set then all accesses are checked against fgt_exec[]. 640 * 641 * For almost all bits in the R/W register pairs, the bit exists in 642 * both registers for a RW register, in HFGRTR/HDFGRTR for a RO register 643 * with the corresponding HFGWTR/HDFGTWTR bit being RES0, and vice-versa 644 * for a WO register. There are unfortunately a couple of exceptions 645 * (PMCR_EL0, TRFCR_EL1) where the register being trapped is RW but 646 * the FGT system only allows trapping of writes, not reads. 647 * 648 * Note that we arrange these bits so that a 0 FGTBit means "no trap". 649 */ 650 FGT_R = 1 << R_FGT_TYPE_SHIFT, 651 FGT_W = 2 << R_FGT_TYPE_SHIFT, 652 FGT_EXEC = 4 << R_FGT_TYPE_SHIFT, 653 FGT_RW = FGT_R | FGT_W, 654 /* Bit to identify whether trap bit is reversed sense */ 655 FGT_REV = R_FGT_REV_MASK, 656 657 /* 658 * If a bit exists in HFGRTR/HDFGRTR then either the register being 659 * trapped is RO or the bit also exists in HFGWTR/HDFGWTR, so we either 660 * want to trap for both reads and writes or else it's harmless to mark 661 * it as trap-on-writes. 662 * If a bit exists only in HFGWTR/HDFGWTR then either the register being 663 * trapped is WO, or else it is one of the two oddball special cases 664 * which are RW but have only a write trap. We mark these as only 665 * FGT_W so we get the right behaviour for those special cases. 666 * (If a bit was added in future that provided only a read trap for an 667 * RW register we'd need to do something special to get the FGT_R bit 668 * only. But this seems unlikely to happen.) 669 * 670 * So for the DO_BIT/DO_REV_BIT macros: use FGT_HFGRTR/FGT_HDFGRTR if 671 * the bit exists in that register. Otherwise use FGT_HFGWTR/FGT_HDFGWTR. 672 */ 673 FGT_HFGRTR = FGT_RW | (FGTREG_HFGRTR << R_FGT_IDX_SHIFT), 674 FGT_HFGWTR = FGT_W | (FGTREG_HFGWTR << R_FGT_IDX_SHIFT), 675 FGT_HDFGRTR = FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT), 676 FGT_HDFGWTR = FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT), 677 FGT_HFGITR = FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT), 678 679 /* Trap bits in HFGRTR_EL2 / HFGWTR_EL2, starting from bit 0. */ 680 DO_BIT(HFGRTR, AFSR0_EL1), 681 DO_BIT(HFGRTR, AFSR1_EL1), 682 DO_BIT(HFGRTR, AIDR_EL1), 683 DO_BIT(HFGRTR, AMAIR_EL1), 684 DO_BIT(HFGRTR, APDAKEY), 685 DO_BIT(HFGRTR, APDBKEY), 686 DO_BIT(HFGRTR, APGAKEY), 687 DO_BIT(HFGRTR, APIAKEY), 688 DO_BIT(HFGRTR, APIBKEY), 689 DO_BIT(HFGRTR, CCSIDR_EL1), 690 DO_BIT(HFGRTR, CLIDR_EL1), 691 DO_BIT(HFGRTR, CONTEXTIDR_EL1), 692 DO_BIT(HFGRTR, CPACR_EL1), 693 DO_BIT(HFGRTR, CSSELR_EL1), 694 DO_BIT(HFGRTR, CTR_EL0), 695 DO_BIT(HFGRTR, DCZID_EL0), 696 DO_BIT(HFGRTR, ESR_EL1), 697 DO_BIT(HFGRTR, FAR_EL1), 698 DO_BIT(HFGRTR, ISR_EL1), 699 DO_BIT(HFGRTR, LORC_EL1), 700 DO_BIT(HFGRTR, LOREA_EL1), 701 DO_BIT(HFGRTR, LORID_EL1), 702 DO_BIT(HFGRTR, LORN_EL1), 703 DO_BIT(HFGRTR, LORSA_EL1), 704 DO_BIT(HFGRTR, MAIR_EL1), 705 DO_BIT(HFGRTR, MIDR_EL1), 706 DO_BIT(HFGRTR, MPIDR_EL1), 707 DO_BIT(HFGRTR, PAR_EL1), 708 DO_BIT(HFGRTR, REVIDR_EL1), 709 DO_BIT(HFGRTR, SCTLR_EL1), 710 DO_BIT(HFGRTR, SCXTNUM_EL1), 711 DO_BIT(HFGRTR, SCXTNUM_EL0), 712 DO_BIT(HFGRTR, TCR_EL1), 713 DO_BIT(HFGRTR, TPIDR_EL1), 714 DO_BIT(HFGRTR, TPIDRRO_EL0), 715 DO_BIT(HFGRTR, TPIDR_EL0), 716 DO_BIT(HFGRTR, TTBR0_EL1), 717 DO_BIT(HFGRTR, TTBR1_EL1), 718 DO_BIT(HFGRTR, VBAR_EL1), 719 DO_BIT(HFGRTR, ICC_IGRPENN_EL1), 720 DO_BIT(HFGRTR, ERRIDR_EL1), 721 DO_REV_BIT(HFGRTR, NSMPRI_EL1), 722 DO_REV_BIT(HFGRTR, NTPIDR2_EL0), 723 724 /* Trap bits in HDFGRTR_EL2 / HDFGWTR_EL2, starting from bit 0. */ 725 DO_BIT(HDFGRTR, DBGBCRN_EL1), 726 DO_BIT(HDFGRTR, DBGBVRN_EL1), 727 DO_BIT(HDFGRTR, DBGWCRN_EL1), 728 DO_BIT(HDFGRTR, DBGWVRN_EL1), 729 DO_BIT(HDFGRTR, MDSCR_EL1), 730 DO_BIT(HDFGRTR, DBGCLAIM), 731 DO_BIT(HDFGWTR, OSLAR_EL1), 732 DO_BIT(HDFGRTR, OSLSR_EL1), 733 DO_BIT(HDFGRTR, OSECCR_EL1), 734 DO_BIT(HDFGRTR, OSDLR_EL1), 735 DO_BIT(HDFGRTR, PMEVCNTRN_EL0), 736 DO_BIT(HDFGRTR, PMEVTYPERN_EL0), 737 DO_BIT(HDFGRTR, PMCCFILTR_EL0), 738 DO_BIT(HDFGRTR, PMCCNTR_EL0), 739 DO_BIT(HDFGRTR, PMCNTEN), 740 DO_BIT(HDFGRTR, PMINTEN), 741 DO_BIT(HDFGRTR, PMOVS), 742 DO_BIT(HDFGRTR, PMSELR_EL0), 743 DO_BIT(HDFGWTR, PMSWINC_EL0), 744 DO_BIT(HDFGWTR, PMCR_EL0), 745 DO_BIT(HDFGRTR, PMMIR_EL1), 746 DO_BIT(HDFGRTR, PMCEIDN_EL0), 747 748 /* Trap bits in HFGITR_EL2, starting from bit 0 */ 749 DO_BIT(HFGITR, ICIALLUIS), 750 DO_BIT(HFGITR, ICIALLU), 751 DO_BIT(HFGITR, ICIVAU), 752 DO_BIT(HFGITR, DCIVAC), 753 DO_BIT(HFGITR, DCISW), 754 DO_BIT(HFGITR, DCCSW), 755 DO_BIT(HFGITR, DCCISW), 756 DO_BIT(HFGITR, DCCVAU), 757 DO_BIT(HFGITR, DCCVAP), 758 DO_BIT(HFGITR, DCCVADP), 759 DO_BIT(HFGITR, DCCIVAC), 760 DO_BIT(HFGITR, DCZVA), 761 DO_BIT(HFGITR, ATS1E1R), 762 DO_BIT(HFGITR, ATS1E1W), 763 DO_BIT(HFGITR, ATS1E0R), 764 DO_BIT(HFGITR, ATS1E0W), 765 DO_BIT(HFGITR, ATS1E1RP), 766 DO_BIT(HFGITR, ATS1E1WP), 767 DO_BIT(HFGITR, TLBIVMALLE1OS), 768 DO_BIT(HFGITR, TLBIVAE1OS), 769 DO_BIT(HFGITR, TLBIASIDE1OS), 770 DO_BIT(HFGITR, TLBIVAAE1OS), 771 DO_BIT(HFGITR, TLBIVALE1OS), 772 DO_BIT(HFGITR, TLBIVAALE1OS), 773 DO_BIT(HFGITR, TLBIRVAE1OS), 774 DO_BIT(HFGITR, TLBIRVAAE1OS), 775 DO_BIT(HFGITR, TLBIRVALE1OS), 776 DO_BIT(HFGITR, TLBIRVAALE1OS), 777 DO_BIT(HFGITR, TLBIVMALLE1IS), 778 DO_BIT(HFGITR, TLBIVAE1IS), 779 DO_BIT(HFGITR, TLBIASIDE1IS), 780 DO_BIT(HFGITR, TLBIVAAE1IS), 781 DO_BIT(HFGITR, TLBIVALE1IS), 782 DO_BIT(HFGITR, TLBIVAALE1IS), 783 DO_BIT(HFGITR, TLBIRVAE1IS), 784 DO_BIT(HFGITR, TLBIRVAAE1IS), 785 DO_BIT(HFGITR, TLBIRVALE1IS), 786 DO_BIT(HFGITR, TLBIRVAALE1IS), 787 DO_BIT(HFGITR, TLBIRVAE1), 788 DO_BIT(HFGITR, TLBIRVAAE1), 789 DO_BIT(HFGITR, TLBIRVALE1), 790 DO_BIT(HFGITR, TLBIRVAALE1), 791 DO_BIT(HFGITR, TLBIVMALLE1), 792 DO_BIT(HFGITR, TLBIVAE1), 793 DO_BIT(HFGITR, TLBIASIDE1), 794 DO_BIT(HFGITR, TLBIVAAE1), 795 DO_BIT(HFGITR, TLBIVALE1), 796 DO_BIT(HFGITR, TLBIVAALE1), 797 DO_BIT(HFGITR, CFPRCTX), 798 DO_BIT(HFGITR, DVPRCTX), 799 DO_BIT(HFGITR, CPPRCTX), 800 DO_BIT(HFGITR, DCCVAC), 801 } FGTBit; 802 803 #undef DO_BIT 804 #undef DO_REV_BIT 805 806 typedef struct ARMCPRegInfo ARMCPRegInfo; 807 808 /* 809 * Access functions for coprocessor registers. These cannot fail and 810 * may not raise exceptions. 811 */ 812 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); 813 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, 814 uint64_t value); 815 /* Access permission check functions for coprocessor registers. */ 816 typedef CPAccessResult CPAccessFn(CPUARMState *env, 817 const ARMCPRegInfo *opaque, 818 bool isread); 819 /* Hook function for register reset */ 820 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); 821 822 #define CP_ANY 0xff 823 824 /* Definition of an ARM coprocessor register */ 825 struct ARMCPRegInfo { 826 /* Name of register (useful mainly for debugging, need not be unique) */ 827 const char *name; 828 /* 829 * Location of register: coprocessor number and (crn,crm,opc1,opc2) 830 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a 831 * 'wildcard' field -- any value of that field in the MRC/MCR insn 832 * will be decoded to this register. The register read and write 833 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 834 * used by the program, so it is possible to register a wildcard and 835 * then behave differently on read/write if necessary. 836 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 837 * must both be zero. 838 * For AArch64-visible registers, opc0 is also used. 839 * Since there are no "coprocessors" in AArch64, cp is purely used as a 840 * way to distinguish (for KVM's benefit) guest-visible system registers 841 * from demuxed ones provided to preserve the "no side effects on 842 * KVM register read/write from QEMU" semantics. cp==0x13 is guest 843 * visible (to match KVM's encoding); cp==0 will be converted to 844 * cp==0x13 when the ARMCPRegInfo is registered, for convenience. 845 */ 846 uint8_t cp; 847 uint8_t crn; 848 uint8_t crm; 849 uint8_t opc0; 850 uint8_t opc1; 851 uint8_t opc2; 852 /* Execution state in which this register is visible: ARM_CP_STATE_* */ 853 CPState state; 854 /* Register type: ARM_CP_* bits/values */ 855 int type; 856 /* Access rights: PL*_[RW] */ 857 CPAccessRights access; 858 /* Security state: ARM_CP_SECSTATE_* bits/values */ 859 CPSecureState secure; 860 /* 861 * Which fine-grained trap register bit to check, if any. This 862 * value encodes both the trap register and bit within it. 863 */ 864 FGTBit fgt; 865 /* 866 * The opaque pointer passed to define_arm_cp_regs_with_opaque() when 867 * this register was defined: can be used to hand data through to the 868 * register read/write functions, since they are passed the ARMCPRegInfo*. 869 */ 870 void *opaque; 871 /* 872 * Value of this register, if it is ARM_CP_CONST. Otherwise, if 873 * fieldoffset is non-zero, the reset value of the register. 874 */ 875 uint64_t resetvalue; 876 /* 877 * Offset of the field in CPUARMState for this register. 878 * This is not needed if either: 879 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs 880 * 2. both readfn and writefn are specified 881 */ 882 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ 883 884 /* 885 * Offsets of the secure and non-secure fields in CPUARMState for the 886 * register if it is banked. These fields are only used during the static 887 * registration of a register. During hashing the bank associated 888 * with a given security state is copied to fieldoffset which is used from 889 * there on out. 890 * 891 * It is expected that register definitions use either fieldoffset or 892 * bank_fieldoffsets in the definition but not both. It is also expected 893 * that both bank offsets are set when defining a banked register. This 894 * use indicates that a register is banked. 895 */ 896 ptrdiff_t bank_fieldoffsets[2]; 897 898 /* 899 * Function for making any access checks for this register in addition to 900 * those specified by the 'access' permissions bits. If NULL, no extra 901 * checks required. The access check is performed at runtime, not at 902 * translate time. 903 */ 904 CPAccessFn *accessfn; 905 /* 906 * Function for handling reads of this register. If NULL, then reads 907 * will be done by loading from the offset into CPUARMState specified 908 * by fieldoffset. 909 */ 910 CPReadFn *readfn; 911 /* 912 * Function for handling writes of this register. If NULL, then writes 913 * will be done by writing to the offset into CPUARMState specified 914 * by fieldoffset. 915 */ 916 CPWriteFn *writefn; 917 /* 918 * Function for doing a "raw" read; used when we need to copy 919 * coprocessor state to the kernel for KVM or out for 920 * migration. This only needs to be provided if there is also a 921 * readfn and it has side effects (for instance clear-on-read bits). 922 */ 923 CPReadFn *raw_readfn; 924 /* 925 * Function for doing a "raw" write; used when we need to copy KVM 926 * kernel coprocessor state into userspace, or for inbound 927 * migration. This only needs to be provided if there is also a 928 * writefn and it masks out "unwritable" bits or has write-one-to-clear 929 * or similar behaviour. 930 */ 931 CPWriteFn *raw_writefn; 932 /* 933 * Function for resetting the register. If NULL, then reset will be done 934 * by writing resetvalue to the field specified in fieldoffset. If 935 * fieldoffset is 0 then no reset will be done. 936 */ 937 CPResetFn *resetfn; 938 939 /* 940 * "Original" writefn and readfn. 941 * For ARMv8.1-VHE register aliases, we overwrite the read/write 942 * accessor functions of various EL1/EL0 to perform the runtime 943 * check for which sysreg should actually be modified, and then 944 * forwards the operation. Before overwriting the accessors, 945 * the original function is copied here, so that accesses that 946 * really do go to the EL1/EL0 version proceed normally. 947 * (The corresponding EL2 register is linked via opaque.) 948 */ 949 CPReadFn *orig_readfn; 950 CPWriteFn *orig_writefn; 951 }; 952 953 /* 954 * Macros which are lvalues for the field in CPUARMState for the 955 * ARMCPRegInfo *ri. 956 */ 957 #define CPREG_FIELD32(env, ri) \ 958 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) 959 #define CPREG_FIELD64(env, ri) \ 960 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) 961 962 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, const ARMCPRegInfo *reg, 963 void *opaque); 964 965 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) 966 { 967 define_one_arm_cp_reg_with_opaque(cpu, regs, NULL); 968 } 969 970 void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs, 971 void *opaque, size_t len); 972 973 #define define_arm_cp_regs_with_opaque(CPU, REGS, OPAQUE) \ 974 do { \ 975 QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \ 976 define_arm_cp_regs_with_opaque_len(CPU, REGS, OPAQUE, \ 977 ARRAY_SIZE(REGS)); \ 978 } while (0) 979 980 #define define_arm_cp_regs(CPU, REGS) \ 981 define_arm_cp_regs_with_opaque(CPU, REGS, NULL) 982 983 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); 984 985 /* 986 * Definition of an ARM co-processor register as viewed from 987 * userspace. This is used for presenting sanitised versions of 988 * registers to userspace when emulating the Linux AArch64 CPU 989 * ID/feature ABI (advertised as HWCAP_CPUID). 990 */ 991 typedef struct ARMCPRegUserSpaceInfo { 992 /* Name of register */ 993 const char *name; 994 995 /* Is the name actually a glob pattern */ 996 bool is_glob; 997 998 /* Only some bits are exported to user space */ 999 uint64_t exported_bits; 1000 1001 /* Fixed bits are applied after the mask */ 1002 uint64_t fixed_bits; 1003 } ARMCPRegUserSpaceInfo; 1004 1005 void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len, 1006 const ARMCPRegUserSpaceInfo *mods, 1007 size_t mods_len); 1008 1009 #define modify_arm_cp_regs(REGS, MODS) \ 1010 do { \ 1011 QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \ 1012 QEMU_BUILD_BUG_ON(ARRAY_SIZE(MODS) == 0); \ 1013 modify_arm_cp_regs_with_len(REGS, ARRAY_SIZE(REGS), \ 1014 MODS, ARRAY_SIZE(MODS)); \ 1015 } while (0) 1016 1017 /* CPWriteFn that can be used to implement writes-ignored behaviour */ 1018 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, 1019 uint64_t value); 1020 /* CPReadFn that can be used for read-as-zero behaviour */ 1021 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); 1022 1023 /* CPWriteFn that just writes the value to ri->fieldoffset */ 1024 void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value); 1025 1026 /* 1027 * CPResetFn that does nothing, for use if no reset is required even 1028 * if fieldoffset is non zero. 1029 */ 1030 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); 1031 1032 /* 1033 * Return true if this reginfo struct's field in the cpu state struct 1034 * is 64 bits wide. 1035 */ 1036 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) 1037 { 1038 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); 1039 } 1040 1041 static inline bool cp_access_ok(int current_el, 1042 const ARMCPRegInfo *ri, int isread) 1043 { 1044 return (ri->access >> ((current_el * 2) + isread)) & 1; 1045 } 1046 1047 /* Raw read of a coprocessor register (as needed for migration, etc) */ 1048 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); 1049 1050 /* 1051 * Return true if the cp register encoding is in the "feature ID space" as 1052 * defined by FEAT_IDST (and thus should be reported with ER_ELx.EC 1053 * as EC_SYSTEMREGISTERTRAP rather than EC_UNCATEGORIZED). 1054 */ 1055 static inline bool arm_cpreg_encoding_in_idspace(uint8_t opc0, uint8_t opc1, 1056 uint8_t opc2, 1057 uint8_t crn, uint8_t crm) 1058 { 1059 return opc0 == 3 && (opc1 == 0 || opc1 == 1 || opc1 == 3) && 1060 crn == 0 && crm < 8; 1061 } 1062 1063 /* 1064 * As arm_cpreg_encoding_in_idspace(), but take the encoding from an 1065 * ARMCPRegInfo. 1066 */ 1067 static inline bool arm_cpreg_in_idspace(const ARMCPRegInfo *ri) 1068 { 1069 return ri->state == ARM_CP_STATE_AA64 && 1070 arm_cpreg_encoding_in_idspace(ri->opc0, ri->opc1, ri->opc2, 1071 ri->crn, ri->crm); 1072 } 1073 1074 #ifdef CONFIG_USER_ONLY 1075 static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } 1076 #else 1077 void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); 1078 #endif 1079 1080 #endif /* TARGET_ARM_CPREGS_H */ 1081