1 /* 2 * ARM Cortex-A registers 3 * 4 * This code is licensed under the GNU GPL v2 or later. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #include "qemu/osdep.h" 10 #include "cpu.h" 11 #include "cpregs.h" 12 13 14 static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 15 { 16 ARMCPU *cpu = env_archcpu(env); 17 18 /* Number of cores is in [25:24]; otherwise we RAZ */ 19 return (cpu->core_count - 1) << 24; 20 } 21 22 static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { 23 { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, 24 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, 25 .access = PL1_RW, .readfn = l2ctlr_read, 26 .writefn = arm_cp_write_ignore }, 27 { .name = "L2CTLR", 28 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2, 29 .access = PL1_RW, .readfn = l2ctlr_read, 30 .writefn = arm_cp_write_ignore }, 31 { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64, 32 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3, 33 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 34 { .name = "L2ECTLR", 35 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3, 36 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 37 { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH, 38 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0, 39 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 40 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, 41 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0, 42 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 43 { .name = "CPUACTLR", 44 .cp = 15, .opc1 = 0, .crm = 15, 45 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 46 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, 47 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1, 48 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 49 { .name = "CPUECTLR", 50 .cp = 15, .opc1 = 1, .crm = 15, 51 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 52 { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64, 53 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2, 54 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 55 { .name = "CPUMERRSR", 56 .cp = 15, .opc1 = 2, .crm = 15, 57 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 58 { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64, 59 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3, 60 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 61 { .name = "L2MERRSR", 62 .cp = 15, .opc1 = 3, .crm = 15, 63 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 64 }; 65 66 void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) 67 { 68 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); 69 } 70