1 /* 2 * Alpha emulation cpu definitions for qemu. 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ALPHA_CPU_H 21 #define ALPHA_CPU_H 22 23 #include "qemu-common.h" 24 #include "cpu-qom.h" 25 #include "exec/cpu-defs.h" 26 27 #define ALIGNED_ONLY 28 29 #define CPUArchState struct CPUAlphaState 30 31 /* Alpha processors have a weak memory model */ 32 #define TCG_GUEST_DEFAULT_MO (0) 33 34 #define ICACHE_LINE_SIZE 32 35 #define DCACHE_LINE_SIZE 32 36 37 /* Alpha major type */ 38 enum { 39 ALPHA_EV3 = 1, 40 ALPHA_EV4 = 2, 41 ALPHA_SIM = 3, 42 ALPHA_LCA = 4, 43 ALPHA_EV5 = 5, /* 21164 */ 44 ALPHA_EV45 = 6, /* 21064A */ 45 ALPHA_EV56 = 7, /* 21164A */ 46 }; 47 48 /* EV4 minor type */ 49 enum { 50 ALPHA_EV4_2 = 0, 51 ALPHA_EV4_3 = 1, 52 }; 53 54 /* LCA minor type */ 55 enum { 56 ALPHA_LCA_1 = 1, /* 21066 */ 57 ALPHA_LCA_2 = 2, /* 20166 */ 58 ALPHA_LCA_3 = 3, /* 21068 */ 59 ALPHA_LCA_4 = 4, /* 21068 */ 60 ALPHA_LCA_5 = 5, /* 21066A */ 61 ALPHA_LCA_6 = 6, /* 21068A */ 62 }; 63 64 /* EV5 minor type */ 65 enum { 66 ALPHA_EV5_1 = 1, /* Rev BA, CA */ 67 ALPHA_EV5_2 = 2, /* Rev DA, EA */ 68 ALPHA_EV5_3 = 3, /* Pass 3 */ 69 ALPHA_EV5_4 = 4, /* Pass 3.2 */ 70 ALPHA_EV5_5 = 5, /* Pass 4 */ 71 }; 72 73 /* EV45 minor type */ 74 enum { 75 ALPHA_EV45_1 = 1, /* Pass 1 */ 76 ALPHA_EV45_2 = 2, /* Pass 1.1 */ 77 ALPHA_EV45_3 = 3, /* Pass 2 */ 78 }; 79 80 /* EV56 minor type */ 81 enum { 82 ALPHA_EV56_1 = 1, /* Pass 1 */ 83 ALPHA_EV56_2 = 2, /* Pass 2 */ 84 }; 85 86 enum { 87 IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */ 88 IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */ 89 IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */ 90 IMPLVER_21364 = 3, /* EV7 & EV79 */ 91 }; 92 93 enum { 94 AMASK_BWX = 0x00000001, 95 AMASK_FIX = 0x00000002, 96 AMASK_CIX = 0x00000004, 97 AMASK_MVI = 0x00000100, 98 AMASK_TRAP = 0x00000200, 99 AMASK_PREFETCH = 0x00001000, 100 }; 101 102 enum { 103 VAX_ROUND_NORMAL = 0, 104 VAX_ROUND_CHOPPED, 105 }; 106 107 enum { 108 IEEE_ROUND_NORMAL = 0, 109 IEEE_ROUND_DYNAMIC, 110 IEEE_ROUND_PLUS, 111 IEEE_ROUND_MINUS, 112 IEEE_ROUND_CHOPPED, 113 }; 114 115 /* IEEE floating-point operations encoding */ 116 /* Trap mode */ 117 enum { 118 FP_TRAP_I = 0x0, 119 FP_TRAP_U = 0x1, 120 FP_TRAP_S = 0x4, 121 FP_TRAP_SU = 0x5, 122 FP_TRAP_SUI = 0x7, 123 }; 124 125 /* Rounding mode */ 126 enum { 127 FP_ROUND_CHOPPED = 0x0, 128 FP_ROUND_MINUS = 0x1, 129 FP_ROUND_NORMAL = 0x2, 130 FP_ROUND_DYNAMIC = 0x3, 131 }; 132 133 /* FPCR bits -- right-shifted 32 so we can use a uint32_t. */ 134 #define FPCR_SUM (1U << (63 - 32)) 135 #define FPCR_INED (1U << (62 - 32)) 136 #define FPCR_UNFD (1U << (61 - 32)) 137 #define FPCR_UNDZ (1U << (60 - 32)) 138 #define FPCR_DYN_SHIFT (58 - 32) 139 #define FPCR_DYN_CHOPPED (0U << FPCR_DYN_SHIFT) 140 #define FPCR_DYN_MINUS (1U << FPCR_DYN_SHIFT) 141 #define FPCR_DYN_NORMAL (2U << FPCR_DYN_SHIFT) 142 #define FPCR_DYN_PLUS (3U << FPCR_DYN_SHIFT) 143 #define FPCR_DYN_MASK (3U << FPCR_DYN_SHIFT) 144 #define FPCR_IOV (1U << (57 - 32)) 145 #define FPCR_INE (1U << (56 - 32)) 146 #define FPCR_UNF (1U << (55 - 32)) 147 #define FPCR_OVF (1U << (54 - 32)) 148 #define FPCR_DZE (1U << (53 - 32)) 149 #define FPCR_INV (1U << (52 - 32)) 150 #define FPCR_OVFD (1U << (51 - 32)) 151 #define FPCR_DZED (1U << (50 - 32)) 152 #define FPCR_INVD (1U << (49 - 32)) 153 #define FPCR_DNZ (1U << (48 - 32)) 154 #define FPCR_DNOD (1U << (47 - 32)) 155 #define FPCR_STATUS_MASK (FPCR_IOV | FPCR_INE | FPCR_UNF \ 156 | FPCR_OVF | FPCR_DZE | FPCR_INV) 157 158 /* The silly software trap enables implemented by the kernel emulation. 159 These are more or less architecturally required, since the real hardware 160 has read-as-zero bits in the FPCR when the features aren't implemented. 161 For the purposes of QEMU, we pretend the FPCR can hold everything. */ 162 #define SWCR_TRAP_ENABLE_INV (1U << 1) 163 #define SWCR_TRAP_ENABLE_DZE (1U << 2) 164 #define SWCR_TRAP_ENABLE_OVF (1U << 3) 165 #define SWCR_TRAP_ENABLE_UNF (1U << 4) 166 #define SWCR_TRAP_ENABLE_INE (1U << 5) 167 #define SWCR_TRAP_ENABLE_DNO (1U << 6) 168 #define SWCR_TRAP_ENABLE_MASK ((1U << 7) - (1U << 1)) 169 170 #define SWCR_MAP_DMZ (1U << 12) 171 #define SWCR_MAP_UMZ (1U << 13) 172 #define SWCR_MAP_MASK (SWCR_MAP_DMZ | SWCR_MAP_UMZ) 173 174 #define SWCR_STATUS_INV (1U << 17) 175 #define SWCR_STATUS_DZE (1U << 18) 176 #define SWCR_STATUS_OVF (1U << 19) 177 #define SWCR_STATUS_UNF (1U << 20) 178 #define SWCR_STATUS_INE (1U << 21) 179 #define SWCR_STATUS_DNO (1U << 22) 180 #define SWCR_STATUS_MASK ((1U << 23) - (1U << 17)) 181 182 #define SWCR_STATUS_TO_EXCSUM_SHIFT 16 183 184 #define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK) 185 186 /* MMU modes definitions */ 187 188 /* Alpha has 5 MMU modes: PALcode, Kernel, Executive, Supervisor, and User. 189 The Unix PALcode only exposes the kernel and user modes; presumably 190 executive and supervisor are used by VMS. 191 192 PALcode itself uses physical mode for code and kernel mode for data; 193 there are PALmode instructions that can access data via physical mode 194 or via an os-installed "alternate mode", which is one of the 4 above. 195 196 That said, we're only emulating Unix PALcode, and not attempting VMS, 197 so we don't need to implement Executive and Supervisor. QEMU's own 198 PALcode cheats and usees the KSEG mapping for its code+data rather than 199 physical addresses. */ 200 201 #define MMU_MODE0_SUFFIX _kernel 202 #define MMU_MODE1_SUFFIX _user 203 #define MMU_KERNEL_IDX 0 204 #define MMU_USER_IDX 1 205 #define MMU_PHYS_IDX 2 206 207 typedef struct CPUAlphaState CPUAlphaState; 208 209 struct CPUAlphaState { 210 uint64_t ir[31]; 211 float64 fir[31]; 212 uint64_t pc; 213 uint64_t unique; 214 uint64_t lock_addr; 215 uint64_t lock_value; 216 217 /* The FPCR, and disassembled portions thereof. */ 218 uint32_t fpcr; 219 #ifdef CONFIG_USER_ONLY 220 uint32_t swcr; 221 #endif 222 uint32_t fpcr_exc_enable; 223 float_status fp_status; 224 uint8_t fpcr_dyn_round; 225 uint8_t fpcr_flush_to_zero; 226 227 /* Mask of PALmode, Processor State et al. Most of this gets copied 228 into the TranslatorBlock flags and controls code generation. */ 229 uint32_t flags; 230 231 /* The high 32-bits of the processor cycle counter. */ 232 uint32_t pcc_ofs; 233 234 /* These pass data from the exception logic in the translator and 235 helpers to the OS entry point. This is used for both system 236 emulation and user-mode. */ 237 uint64_t trap_arg0; 238 uint64_t trap_arg1; 239 uint64_t trap_arg2; 240 241 #if !defined(CONFIG_USER_ONLY) 242 /* The internal data required by our emulation of the Unix PALcode. */ 243 uint64_t exc_addr; 244 uint64_t palbr; 245 uint64_t ptbr; 246 uint64_t vptptr; 247 uint64_t sysval; 248 uint64_t usp; 249 uint64_t shadow[8]; 250 uint64_t scratch[24]; 251 #endif 252 253 /* This alarm doesn't exist in real hardware; we wish it did. */ 254 uint64_t alarm_expire; 255 256 /* Those resources are used only in QEMU core */ 257 CPU_COMMON 258 259 int error_code; 260 261 uint32_t features; 262 uint32_t amask; 263 int implver; 264 }; 265 266 /** 267 * AlphaCPU: 268 * @env: #CPUAlphaState 269 * 270 * An Alpha CPU. 271 */ 272 struct AlphaCPU { 273 /*< private >*/ 274 CPUState parent_obj; 275 /*< public >*/ 276 277 CPUAlphaState env; 278 279 /* This alarm doesn't exist in real hardware; we wish it did. */ 280 QEMUTimer *alarm_timer; 281 }; 282 283 static inline AlphaCPU *alpha_env_get_cpu(CPUAlphaState *env) 284 { 285 return container_of(env, AlphaCPU, env); 286 } 287 288 #define ENV_GET_CPU(e) CPU(alpha_env_get_cpu(e)) 289 290 #define ENV_OFFSET offsetof(AlphaCPU, env) 291 292 #ifndef CONFIG_USER_ONLY 293 extern const struct VMStateDescription vmstate_alpha_cpu; 294 #endif 295 296 void alpha_cpu_do_interrupt(CPUState *cpu); 297 bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req); 298 void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags); 299 hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 300 int alpha_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 301 int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 302 void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 303 MMUAccessType access_type, 304 int mmu_idx, uintptr_t retaddr); 305 306 #define cpu_list alpha_cpu_list 307 #define cpu_signal_handler cpu_alpha_signal_handler 308 309 #include "exec/cpu-all.h" 310 311 enum { 312 FEATURE_ASN = 0x00000001, 313 FEATURE_SPS = 0x00000002, 314 FEATURE_VIRBND = 0x00000004, 315 FEATURE_TBCHK = 0x00000008, 316 }; 317 318 enum { 319 EXCP_RESET, 320 EXCP_MCHK, 321 EXCP_SMP_INTERRUPT, 322 EXCP_CLK_INTERRUPT, 323 EXCP_DEV_INTERRUPT, 324 EXCP_MMFAULT, 325 EXCP_UNALIGN, 326 EXCP_OPCDEC, 327 EXCP_ARITH, 328 EXCP_FEN, 329 EXCP_CALL_PAL, 330 }; 331 332 /* Alpha-specific interrupt pending bits. */ 333 #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_EXT_0 334 #define CPU_INTERRUPT_SMP CPU_INTERRUPT_TGT_EXT_1 335 #define CPU_INTERRUPT_MCHK CPU_INTERRUPT_TGT_EXT_2 336 337 /* OSF/1 Page table bits. */ 338 enum { 339 PTE_VALID = 0x0001, 340 PTE_FOR = 0x0002, /* used for page protection (fault on read) */ 341 PTE_FOW = 0x0004, /* used for page protection (fault on write) */ 342 PTE_FOE = 0x0008, /* used for page protection (fault on exec) */ 343 PTE_ASM = 0x0010, 344 PTE_KRE = 0x0100, 345 PTE_URE = 0x0200, 346 PTE_KWE = 0x1000, 347 PTE_UWE = 0x2000 348 }; 349 350 /* Hardware interrupt (entInt) constants. */ 351 enum { 352 INT_K_IP, 353 INT_K_CLK, 354 INT_K_MCHK, 355 INT_K_DEV, 356 INT_K_PERF, 357 }; 358 359 /* Memory management (entMM) constants. */ 360 enum { 361 MM_K_TNV, 362 MM_K_ACV, 363 MM_K_FOR, 364 MM_K_FOE, 365 MM_K_FOW 366 }; 367 368 /* Arithmetic exception (entArith) constants. */ 369 enum { 370 EXC_M_SWC = 1, /* Software completion */ 371 EXC_M_INV = 2, /* Invalid operation */ 372 EXC_M_DZE = 4, /* Division by zero */ 373 EXC_M_FOV = 8, /* Overflow */ 374 EXC_M_UNF = 16, /* Underflow */ 375 EXC_M_INE = 32, /* Inexact result */ 376 EXC_M_IOV = 64 /* Integer Overflow */ 377 }; 378 379 /* Processor status constants. */ 380 /* Low 3 bits are interrupt mask level. */ 381 #define PS_INT_MASK 7u 382 383 /* Bits 4 and 5 are the mmu mode. The VMS PALcode uses all 4 modes; 384 The Unix PALcode only uses bit 4. */ 385 #define PS_USER_MODE 8u 386 387 /* CPUAlphaState->flags constants. These are layed out so that we 388 can set or reset the pieces individually by assigning to the byte, 389 or manipulated as a whole. */ 390 391 #define ENV_FLAG_PAL_SHIFT 0 392 #define ENV_FLAG_PS_SHIFT 8 393 #define ENV_FLAG_RX_SHIFT 16 394 #define ENV_FLAG_FEN_SHIFT 24 395 396 #define ENV_FLAG_PAL_MODE (1u << ENV_FLAG_PAL_SHIFT) 397 #define ENV_FLAG_PS_USER (PS_USER_MODE << ENV_FLAG_PS_SHIFT) 398 #define ENV_FLAG_RX_FLAG (1u << ENV_FLAG_RX_SHIFT) 399 #define ENV_FLAG_FEN (1u << ENV_FLAG_FEN_SHIFT) 400 401 #define ENV_FLAG_TB_MASK \ 402 (ENV_FLAG_PAL_MODE | ENV_FLAG_PS_USER | ENV_FLAG_FEN) 403 404 static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) 405 { 406 int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX; 407 if (env->flags & ENV_FLAG_PAL_MODE) { 408 ret = MMU_KERNEL_IDX; 409 } 410 return ret; 411 } 412 413 enum { 414 IR_V0 = 0, 415 IR_T0 = 1, 416 IR_T1 = 2, 417 IR_T2 = 3, 418 IR_T3 = 4, 419 IR_T4 = 5, 420 IR_T5 = 6, 421 IR_T6 = 7, 422 IR_T7 = 8, 423 IR_S0 = 9, 424 IR_S1 = 10, 425 IR_S2 = 11, 426 IR_S3 = 12, 427 IR_S4 = 13, 428 IR_S5 = 14, 429 IR_S6 = 15, 430 IR_FP = IR_S6, 431 IR_A0 = 16, 432 IR_A1 = 17, 433 IR_A2 = 18, 434 IR_A3 = 19, 435 IR_A4 = 20, 436 IR_A5 = 21, 437 IR_T8 = 22, 438 IR_T9 = 23, 439 IR_T10 = 24, 440 IR_T11 = 25, 441 IR_RA = 26, 442 IR_T12 = 27, 443 IR_PV = IR_T12, 444 IR_AT = 28, 445 IR_GP = 29, 446 IR_SP = 30, 447 IR_ZERO = 31, 448 }; 449 450 void alpha_translate_init(void); 451 452 #define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU 453 #define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX 454 #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU 455 456 void alpha_cpu_list(void); 457 /* you can call this signal handler from your SIGBUS and SIGSEGV 458 signal handlers to inform the virtual CPU of exceptions. non zero 459 is returned if the signal was handled by the virtual CPU. */ 460 int cpu_alpha_signal_handler(int host_signum, void *pinfo, 461 void *puc); 462 bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 463 MMUAccessType access_type, int mmu_idx, 464 bool probe, uintptr_t retaddr); 465 void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int); 466 void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t); 467 468 uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env); 469 void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val); 470 uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg); 471 void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val); 472 #ifndef CONFIG_USER_ONLY 473 void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 474 vaddr addr, unsigned size, 475 MMUAccessType access_type, 476 int mmu_idx, MemTxAttrs attrs, 477 MemTxResult response, uintptr_t retaddr); 478 #endif 479 480 static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc, 481 target_ulong *cs_base, uint32_t *pflags) 482 { 483 *pc = env->pc; 484 *cs_base = 0; 485 *pflags = env->flags & ENV_FLAG_TB_MASK; 486 } 487 488 #ifdef CONFIG_USER_ONLY 489 /* Copied from linux ieee_swcr_to_fpcr. */ 490 static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr) 491 { 492 uint64_t fpcr = 0; 493 494 fpcr |= (swcr & SWCR_STATUS_MASK) << 35; 495 fpcr |= (swcr & SWCR_MAP_DMZ) << 36; 496 fpcr |= (~swcr & (SWCR_TRAP_ENABLE_INV 497 | SWCR_TRAP_ENABLE_DZE 498 | SWCR_TRAP_ENABLE_OVF)) << 48; 499 fpcr |= (~swcr & (SWCR_TRAP_ENABLE_UNF 500 | SWCR_TRAP_ENABLE_INE)) << 57; 501 fpcr |= (swcr & SWCR_MAP_UMZ ? FPCR_UNDZ | FPCR_UNFD : 0); 502 fpcr |= (~swcr & SWCR_TRAP_ENABLE_DNO) << 41; 503 504 return fpcr; 505 } 506 507 /* Copied from linux ieee_fpcr_to_swcr. */ 508 static inline uint64_t alpha_ieee_fpcr_to_swcr(uint64_t fpcr) 509 { 510 uint64_t swcr = 0; 511 512 swcr |= (fpcr >> 35) & SWCR_STATUS_MASK; 513 swcr |= (fpcr >> 36) & SWCR_MAP_DMZ; 514 swcr |= (~fpcr >> 48) & (SWCR_TRAP_ENABLE_INV 515 | SWCR_TRAP_ENABLE_DZE 516 | SWCR_TRAP_ENABLE_OVF); 517 swcr |= (~fpcr >> 57) & (SWCR_TRAP_ENABLE_UNF | SWCR_TRAP_ENABLE_INE); 518 swcr |= (fpcr >> 47) & SWCR_MAP_UMZ; 519 swcr |= (~fpcr >> 41) & SWCR_TRAP_ENABLE_DNO; 520 521 return swcr; 522 } 523 #endif /* CONFIG_USER_ONLY */ 524 525 #endif /* ALPHA_CPU_H */ 526