1 /* 2 * Alpha emulation cpu definitions for qemu. 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ALPHA_CPU_H 21 #define ALPHA_CPU_H 22 23 #include "qemu-common.h" 24 #include "cpu-qom.h" 25 #include "exec/cpu-defs.h" 26 27 #define ALIGNED_ONLY 28 29 /* Alpha processors have a weak memory model */ 30 #define TCG_GUEST_DEFAULT_MO (0) 31 32 #define ICACHE_LINE_SIZE 32 33 #define DCACHE_LINE_SIZE 32 34 35 /* Alpha major type */ 36 enum { 37 ALPHA_EV3 = 1, 38 ALPHA_EV4 = 2, 39 ALPHA_SIM = 3, 40 ALPHA_LCA = 4, 41 ALPHA_EV5 = 5, /* 21164 */ 42 ALPHA_EV45 = 6, /* 21064A */ 43 ALPHA_EV56 = 7, /* 21164A */ 44 }; 45 46 /* EV4 minor type */ 47 enum { 48 ALPHA_EV4_2 = 0, 49 ALPHA_EV4_3 = 1, 50 }; 51 52 /* LCA minor type */ 53 enum { 54 ALPHA_LCA_1 = 1, /* 21066 */ 55 ALPHA_LCA_2 = 2, /* 20166 */ 56 ALPHA_LCA_3 = 3, /* 21068 */ 57 ALPHA_LCA_4 = 4, /* 21068 */ 58 ALPHA_LCA_5 = 5, /* 21066A */ 59 ALPHA_LCA_6 = 6, /* 21068A */ 60 }; 61 62 /* EV5 minor type */ 63 enum { 64 ALPHA_EV5_1 = 1, /* Rev BA, CA */ 65 ALPHA_EV5_2 = 2, /* Rev DA, EA */ 66 ALPHA_EV5_3 = 3, /* Pass 3 */ 67 ALPHA_EV5_4 = 4, /* Pass 3.2 */ 68 ALPHA_EV5_5 = 5, /* Pass 4 */ 69 }; 70 71 /* EV45 minor type */ 72 enum { 73 ALPHA_EV45_1 = 1, /* Pass 1 */ 74 ALPHA_EV45_2 = 2, /* Pass 1.1 */ 75 ALPHA_EV45_3 = 3, /* Pass 2 */ 76 }; 77 78 /* EV56 minor type */ 79 enum { 80 ALPHA_EV56_1 = 1, /* Pass 1 */ 81 ALPHA_EV56_2 = 2, /* Pass 2 */ 82 }; 83 84 enum { 85 IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */ 86 IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */ 87 IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */ 88 IMPLVER_21364 = 3, /* EV7 & EV79 */ 89 }; 90 91 enum { 92 AMASK_BWX = 0x00000001, 93 AMASK_FIX = 0x00000002, 94 AMASK_CIX = 0x00000004, 95 AMASK_MVI = 0x00000100, 96 AMASK_TRAP = 0x00000200, 97 AMASK_PREFETCH = 0x00001000, 98 }; 99 100 enum { 101 VAX_ROUND_NORMAL = 0, 102 VAX_ROUND_CHOPPED, 103 }; 104 105 enum { 106 IEEE_ROUND_NORMAL = 0, 107 IEEE_ROUND_DYNAMIC, 108 IEEE_ROUND_PLUS, 109 IEEE_ROUND_MINUS, 110 IEEE_ROUND_CHOPPED, 111 }; 112 113 /* IEEE floating-point operations encoding */ 114 /* Trap mode */ 115 enum { 116 FP_TRAP_I = 0x0, 117 FP_TRAP_U = 0x1, 118 FP_TRAP_S = 0x4, 119 FP_TRAP_SU = 0x5, 120 FP_TRAP_SUI = 0x7, 121 }; 122 123 /* Rounding mode */ 124 enum { 125 FP_ROUND_CHOPPED = 0x0, 126 FP_ROUND_MINUS = 0x1, 127 FP_ROUND_NORMAL = 0x2, 128 FP_ROUND_DYNAMIC = 0x3, 129 }; 130 131 /* FPCR bits -- right-shifted 32 so we can use a uint32_t. */ 132 #define FPCR_SUM (1U << (63 - 32)) 133 #define FPCR_INED (1U << (62 - 32)) 134 #define FPCR_UNFD (1U << (61 - 32)) 135 #define FPCR_UNDZ (1U << (60 - 32)) 136 #define FPCR_DYN_SHIFT (58 - 32) 137 #define FPCR_DYN_CHOPPED (0U << FPCR_DYN_SHIFT) 138 #define FPCR_DYN_MINUS (1U << FPCR_DYN_SHIFT) 139 #define FPCR_DYN_NORMAL (2U << FPCR_DYN_SHIFT) 140 #define FPCR_DYN_PLUS (3U << FPCR_DYN_SHIFT) 141 #define FPCR_DYN_MASK (3U << FPCR_DYN_SHIFT) 142 #define FPCR_IOV (1U << (57 - 32)) 143 #define FPCR_INE (1U << (56 - 32)) 144 #define FPCR_UNF (1U << (55 - 32)) 145 #define FPCR_OVF (1U << (54 - 32)) 146 #define FPCR_DZE (1U << (53 - 32)) 147 #define FPCR_INV (1U << (52 - 32)) 148 #define FPCR_OVFD (1U << (51 - 32)) 149 #define FPCR_DZED (1U << (50 - 32)) 150 #define FPCR_INVD (1U << (49 - 32)) 151 #define FPCR_DNZ (1U << (48 - 32)) 152 #define FPCR_DNOD (1U << (47 - 32)) 153 #define FPCR_STATUS_MASK (FPCR_IOV | FPCR_INE | FPCR_UNF \ 154 | FPCR_OVF | FPCR_DZE | FPCR_INV) 155 156 /* The silly software trap enables implemented by the kernel emulation. 157 These are more or less architecturally required, since the real hardware 158 has read-as-zero bits in the FPCR when the features aren't implemented. 159 For the purposes of QEMU, we pretend the FPCR can hold everything. */ 160 #define SWCR_TRAP_ENABLE_INV (1U << 1) 161 #define SWCR_TRAP_ENABLE_DZE (1U << 2) 162 #define SWCR_TRAP_ENABLE_OVF (1U << 3) 163 #define SWCR_TRAP_ENABLE_UNF (1U << 4) 164 #define SWCR_TRAP_ENABLE_INE (1U << 5) 165 #define SWCR_TRAP_ENABLE_DNO (1U << 6) 166 #define SWCR_TRAP_ENABLE_MASK ((1U << 7) - (1U << 1)) 167 168 #define SWCR_MAP_DMZ (1U << 12) 169 #define SWCR_MAP_UMZ (1U << 13) 170 #define SWCR_MAP_MASK (SWCR_MAP_DMZ | SWCR_MAP_UMZ) 171 172 #define SWCR_STATUS_INV (1U << 17) 173 #define SWCR_STATUS_DZE (1U << 18) 174 #define SWCR_STATUS_OVF (1U << 19) 175 #define SWCR_STATUS_UNF (1U << 20) 176 #define SWCR_STATUS_INE (1U << 21) 177 #define SWCR_STATUS_DNO (1U << 22) 178 #define SWCR_STATUS_MASK ((1U << 23) - (1U << 17)) 179 180 #define SWCR_STATUS_TO_EXCSUM_SHIFT 16 181 182 #define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK) 183 184 /* MMU modes definitions */ 185 186 /* Alpha has 5 MMU modes: PALcode, Kernel, Executive, Supervisor, and User. 187 The Unix PALcode only exposes the kernel and user modes; presumably 188 executive and supervisor are used by VMS. 189 190 PALcode itself uses physical mode for code and kernel mode for data; 191 there are PALmode instructions that can access data via physical mode 192 or via an os-installed "alternate mode", which is one of the 4 above. 193 194 That said, we're only emulating Unix PALcode, and not attempting VMS, 195 so we don't need to implement Executive and Supervisor. QEMU's own 196 PALcode cheats and usees the KSEG mapping for its code+data rather than 197 physical addresses. */ 198 199 #define MMU_MODE0_SUFFIX _kernel 200 #define MMU_MODE1_SUFFIX _user 201 #define MMU_KERNEL_IDX 0 202 #define MMU_USER_IDX 1 203 #define MMU_PHYS_IDX 2 204 205 typedef struct CPUAlphaState CPUAlphaState; 206 207 struct CPUAlphaState { 208 uint64_t ir[31]; 209 float64 fir[31]; 210 uint64_t pc; 211 uint64_t unique; 212 uint64_t lock_addr; 213 uint64_t lock_value; 214 215 /* The FPCR, and disassembled portions thereof. */ 216 uint32_t fpcr; 217 #ifdef CONFIG_USER_ONLY 218 uint32_t swcr; 219 #endif 220 uint32_t fpcr_exc_enable; 221 float_status fp_status; 222 uint8_t fpcr_dyn_round; 223 uint8_t fpcr_flush_to_zero; 224 225 /* Mask of PALmode, Processor State et al. Most of this gets copied 226 into the TranslatorBlock flags and controls code generation. */ 227 uint32_t flags; 228 229 /* The high 32-bits of the processor cycle counter. */ 230 uint32_t pcc_ofs; 231 232 /* These pass data from the exception logic in the translator and 233 helpers to the OS entry point. This is used for both system 234 emulation and user-mode. */ 235 uint64_t trap_arg0; 236 uint64_t trap_arg1; 237 uint64_t trap_arg2; 238 239 #if !defined(CONFIG_USER_ONLY) 240 /* The internal data required by our emulation of the Unix PALcode. */ 241 uint64_t exc_addr; 242 uint64_t palbr; 243 uint64_t ptbr; 244 uint64_t vptptr; 245 uint64_t sysval; 246 uint64_t usp; 247 uint64_t shadow[8]; 248 uint64_t scratch[24]; 249 #endif 250 251 /* This alarm doesn't exist in real hardware; we wish it did. */ 252 uint64_t alarm_expire; 253 254 /* Those resources are used only in QEMU core */ 255 CPU_COMMON 256 257 int error_code; 258 259 uint32_t features; 260 uint32_t amask; 261 int implver; 262 }; 263 264 /** 265 * AlphaCPU: 266 * @env: #CPUAlphaState 267 * 268 * An Alpha CPU. 269 */ 270 struct AlphaCPU { 271 /*< private >*/ 272 CPUState parent_obj; 273 /*< public >*/ 274 275 CPUAlphaState env; 276 277 /* This alarm doesn't exist in real hardware; we wish it did. */ 278 QEMUTimer *alarm_timer; 279 }; 280 281 282 #ifndef CONFIG_USER_ONLY 283 extern const struct VMStateDescription vmstate_alpha_cpu; 284 #endif 285 286 void alpha_cpu_do_interrupt(CPUState *cpu); 287 bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req); 288 void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags); 289 hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 290 int alpha_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 291 int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 292 void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 293 MMUAccessType access_type, 294 int mmu_idx, uintptr_t retaddr); 295 296 #define cpu_list alpha_cpu_list 297 #define cpu_signal_handler cpu_alpha_signal_handler 298 299 typedef CPUAlphaState CPUArchState; 300 typedef AlphaCPU ArchCPU; 301 302 #include "exec/cpu-all.h" 303 304 enum { 305 FEATURE_ASN = 0x00000001, 306 FEATURE_SPS = 0x00000002, 307 FEATURE_VIRBND = 0x00000004, 308 FEATURE_TBCHK = 0x00000008, 309 }; 310 311 enum { 312 EXCP_RESET, 313 EXCP_MCHK, 314 EXCP_SMP_INTERRUPT, 315 EXCP_CLK_INTERRUPT, 316 EXCP_DEV_INTERRUPT, 317 EXCP_MMFAULT, 318 EXCP_UNALIGN, 319 EXCP_OPCDEC, 320 EXCP_ARITH, 321 EXCP_FEN, 322 EXCP_CALL_PAL, 323 }; 324 325 /* Alpha-specific interrupt pending bits. */ 326 #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_EXT_0 327 #define CPU_INTERRUPT_SMP CPU_INTERRUPT_TGT_EXT_1 328 #define CPU_INTERRUPT_MCHK CPU_INTERRUPT_TGT_EXT_2 329 330 /* OSF/1 Page table bits. */ 331 enum { 332 PTE_VALID = 0x0001, 333 PTE_FOR = 0x0002, /* used for page protection (fault on read) */ 334 PTE_FOW = 0x0004, /* used for page protection (fault on write) */ 335 PTE_FOE = 0x0008, /* used for page protection (fault on exec) */ 336 PTE_ASM = 0x0010, 337 PTE_KRE = 0x0100, 338 PTE_URE = 0x0200, 339 PTE_KWE = 0x1000, 340 PTE_UWE = 0x2000 341 }; 342 343 /* Hardware interrupt (entInt) constants. */ 344 enum { 345 INT_K_IP, 346 INT_K_CLK, 347 INT_K_MCHK, 348 INT_K_DEV, 349 INT_K_PERF, 350 }; 351 352 /* Memory management (entMM) constants. */ 353 enum { 354 MM_K_TNV, 355 MM_K_ACV, 356 MM_K_FOR, 357 MM_K_FOE, 358 MM_K_FOW 359 }; 360 361 /* Arithmetic exception (entArith) constants. */ 362 enum { 363 EXC_M_SWC = 1, /* Software completion */ 364 EXC_M_INV = 2, /* Invalid operation */ 365 EXC_M_DZE = 4, /* Division by zero */ 366 EXC_M_FOV = 8, /* Overflow */ 367 EXC_M_UNF = 16, /* Underflow */ 368 EXC_M_INE = 32, /* Inexact result */ 369 EXC_M_IOV = 64 /* Integer Overflow */ 370 }; 371 372 /* Processor status constants. */ 373 /* Low 3 bits are interrupt mask level. */ 374 #define PS_INT_MASK 7u 375 376 /* Bits 4 and 5 are the mmu mode. The VMS PALcode uses all 4 modes; 377 The Unix PALcode only uses bit 4. */ 378 #define PS_USER_MODE 8u 379 380 /* CPUAlphaState->flags constants. These are layed out so that we 381 can set or reset the pieces individually by assigning to the byte, 382 or manipulated as a whole. */ 383 384 #define ENV_FLAG_PAL_SHIFT 0 385 #define ENV_FLAG_PS_SHIFT 8 386 #define ENV_FLAG_RX_SHIFT 16 387 #define ENV_FLAG_FEN_SHIFT 24 388 389 #define ENV_FLAG_PAL_MODE (1u << ENV_FLAG_PAL_SHIFT) 390 #define ENV_FLAG_PS_USER (PS_USER_MODE << ENV_FLAG_PS_SHIFT) 391 #define ENV_FLAG_RX_FLAG (1u << ENV_FLAG_RX_SHIFT) 392 #define ENV_FLAG_FEN (1u << ENV_FLAG_FEN_SHIFT) 393 394 #define ENV_FLAG_TB_MASK \ 395 (ENV_FLAG_PAL_MODE | ENV_FLAG_PS_USER | ENV_FLAG_FEN) 396 397 static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) 398 { 399 int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX; 400 if (env->flags & ENV_FLAG_PAL_MODE) { 401 ret = MMU_KERNEL_IDX; 402 } 403 return ret; 404 } 405 406 enum { 407 IR_V0 = 0, 408 IR_T0 = 1, 409 IR_T1 = 2, 410 IR_T2 = 3, 411 IR_T3 = 4, 412 IR_T4 = 5, 413 IR_T5 = 6, 414 IR_T6 = 7, 415 IR_T7 = 8, 416 IR_S0 = 9, 417 IR_S1 = 10, 418 IR_S2 = 11, 419 IR_S3 = 12, 420 IR_S4 = 13, 421 IR_S5 = 14, 422 IR_S6 = 15, 423 IR_FP = IR_S6, 424 IR_A0 = 16, 425 IR_A1 = 17, 426 IR_A2 = 18, 427 IR_A3 = 19, 428 IR_A4 = 20, 429 IR_A5 = 21, 430 IR_T8 = 22, 431 IR_T9 = 23, 432 IR_T10 = 24, 433 IR_T11 = 25, 434 IR_RA = 26, 435 IR_T12 = 27, 436 IR_PV = IR_T12, 437 IR_AT = 28, 438 IR_GP = 29, 439 IR_SP = 30, 440 IR_ZERO = 31, 441 }; 442 443 void alpha_translate_init(void); 444 445 #define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU 446 #define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX 447 #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU 448 449 void alpha_cpu_list(void); 450 /* you can call this signal handler from your SIGBUS and SIGSEGV 451 signal handlers to inform the virtual CPU of exceptions. non zero 452 is returned if the signal was handled by the virtual CPU. */ 453 int cpu_alpha_signal_handler(int host_signum, void *pinfo, 454 void *puc); 455 bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 456 MMUAccessType access_type, int mmu_idx, 457 bool probe, uintptr_t retaddr); 458 void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int); 459 void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t); 460 461 uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env); 462 void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val); 463 uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg); 464 void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val); 465 #ifndef CONFIG_USER_ONLY 466 void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 467 vaddr addr, unsigned size, 468 MMUAccessType access_type, 469 int mmu_idx, MemTxAttrs attrs, 470 MemTxResult response, uintptr_t retaddr); 471 #endif 472 473 static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc, 474 target_ulong *cs_base, uint32_t *pflags) 475 { 476 *pc = env->pc; 477 *cs_base = 0; 478 *pflags = env->flags & ENV_FLAG_TB_MASK; 479 } 480 481 #ifdef CONFIG_USER_ONLY 482 /* Copied from linux ieee_swcr_to_fpcr. */ 483 static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr) 484 { 485 uint64_t fpcr = 0; 486 487 fpcr |= (swcr & SWCR_STATUS_MASK) << 35; 488 fpcr |= (swcr & SWCR_MAP_DMZ) << 36; 489 fpcr |= (~swcr & (SWCR_TRAP_ENABLE_INV 490 | SWCR_TRAP_ENABLE_DZE 491 | SWCR_TRAP_ENABLE_OVF)) << 48; 492 fpcr |= (~swcr & (SWCR_TRAP_ENABLE_UNF 493 | SWCR_TRAP_ENABLE_INE)) << 57; 494 fpcr |= (swcr & SWCR_MAP_UMZ ? FPCR_UNDZ | FPCR_UNFD : 0); 495 fpcr |= (~swcr & SWCR_TRAP_ENABLE_DNO) << 41; 496 497 return fpcr; 498 } 499 500 /* Copied from linux ieee_fpcr_to_swcr. */ 501 static inline uint64_t alpha_ieee_fpcr_to_swcr(uint64_t fpcr) 502 { 503 uint64_t swcr = 0; 504 505 swcr |= (fpcr >> 35) & SWCR_STATUS_MASK; 506 swcr |= (fpcr >> 36) & SWCR_MAP_DMZ; 507 swcr |= (~fpcr >> 48) & (SWCR_TRAP_ENABLE_INV 508 | SWCR_TRAP_ENABLE_DZE 509 | SWCR_TRAP_ENABLE_OVF); 510 swcr |= (~fpcr >> 57) & (SWCR_TRAP_ENABLE_UNF | SWCR_TRAP_ENABLE_INE); 511 swcr |= (fpcr >> 47) & SWCR_MAP_UMZ; 512 swcr |= (~fpcr >> 41) & SWCR_TRAP_ENABLE_DNO; 513 514 return swcr; 515 } 516 #endif /* CONFIG_USER_ONLY */ 517 518 #endif /* ALPHA_CPU_H */ 519