1 /* 2 * QEMU Alpha CPU 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * Copyright (c) 2012 SUSE LINUX Products GmbH 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see 19 * <http://www.gnu.org/licenses/lgpl-2.1.html> 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "qemu/qemu-print.h" 25 #include "cpu.h" 26 #include "exec/exec-all.h" 27 28 29 static void alpha_cpu_set_pc(CPUState *cs, vaddr value) 30 { 31 AlphaCPU *cpu = ALPHA_CPU(cs); 32 33 cpu->env.pc = value; 34 } 35 36 static vaddr alpha_cpu_get_pc(CPUState *cs) 37 { 38 AlphaCPU *cpu = ALPHA_CPU(cs); 39 40 return cpu->env.pc; 41 } 42 43 static void alpha_restore_state_to_opc(CPUState *cs, 44 const TranslationBlock *tb, 45 const uint64_t *data) 46 { 47 AlphaCPU *cpu = ALPHA_CPU(cs); 48 49 cpu->env.pc = data[0]; 50 } 51 52 static bool alpha_cpu_has_work(CPUState *cs) 53 { 54 /* Here we are checking to see if the CPU should wake up from HALT. 55 We will have gotten into this state only for WTINT from PALmode. */ 56 /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU 57 asleep even if (some) interrupts have been asserted. For now, 58 assume that if a CPU really wants to stay asleep, it will mask 59 interrupts at the chipset level, which will prevent these bits 60 from being set in the first place. */ 61 return cs->interrupt_request & (CPU_INTERRUPT_HARD 62 | CPU_INTERRUPT_TIMER 63 | CPU_INTERRUPT_SMP 64 | CPU_INTERRUPT_MCHK); 65 } 66 67 static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) 68 { 69 info->mach = bfd_mach_alpha_ev6; 70 info->print_insn = print_insn_alpha; 71 } 72 73 static void alpha_cpu_realizefn(DeviceState *dev, Error **errp) 74 { 75 CPUState *cs = CPU(dev); 76 AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev); 77 Error *local_err = NULL; 78 79 cpu_exec_realizefn(cs, &local_err); 80 if (local_err != NULL) { 81 error_propagate(errp, local_err); 82 return; 83 } 84 85 qemu_init_vcpu(cs); 86 87 acc->parent_realize(dev, errp); 88 } 89 90 /* Models */ 91 typedef struct AlphaCPUAlias { 92 const char *alias; 93 const char *typename; 94 } AlphaCPUAlias; 95 96 static const AlphaCPUAlias alpha_cpu_aliases[] = { 97 { "21064", ALPHA_CPU_TYPE_NAME("ev4") }, 98 { "21164", ALPHA_CPU_TYPE_NAME("ev5") }, 99 { "21164a", ALPHA_CPU_TYPE_NAME("ev56") }, 100 { "21164pc", ALPHA_CPU_TYPE_NAME("pca56") }, 101 { "21264", ALPHA_CPU_TYPE_NAME("ev6") }, 102 { "21264a", ALPHA_CPU_TYPE_NAME("ev67") }, 103 }; 104 105 static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model) 106 { 107 ObjectClass *oc; 108 char *typename; 109 int i; 110 111 oc = object_class_by_name(cpu_model); 112 if (oc != NULL && object_class_dynamic_cast(oc, TYPE_ALPHA_CPU) != NULL) { 113 return oc; 114 } 115 116 for (i = 0; i < ARRAY_SIZE(alpha_cpu_aliases); i++) { 117 if (strcmp(cpu_model, alpha_cpu_aliases[i].alias) == 0) { 118 oc = object_class_by_name(alpha_cpu_aliases[i].typename); 119 assert(oc != NULL && !object_class_is_abstract(oc)); 120 return oc; 121 } 122 } 123 124 typename = g_strdup_printf(ALPHA_CPU_TYPE_NAME("%s"), cpu_model); 125 oc = object_class_by_name(typename); 126 g_free(typename); 127 128 return oc; 129 } 130 131 static void ev4_cpu_initfn(Object *obj) 132 { 133 AlphaCPU *cpu = ALPHA_CPU(obj); 134 CPUAlphaState *env = &cpu->env; 135 136 env->implver = IMPLVER_2106x; 137 } 138 139 static void ev5_cpu_initfn(Object *obj) 140 { 141 AlphaCPU *cpu = ALPHA_CPU(obj); 142 CPUAlphaState *env = &cpu->env; 143 144 env->implver = IMPLVER_21164; 145 } 146 147 static void ev56_cpu_initfn(Object *obj) 148 { 149 AlphaCPU *cpu = ALPHA_CPU(obj); 150 CPUAlphaState *env = &cpu->env; 151 152 env->amask |= AMASK_BWX; 153 } 154 155 static void pca56_cpu_initfn(Object *obj) 156 { 157 AlphaCPU *cpu = ALPHA_CPU(obj); 158 CPUAlphaState *env = &cpu->env; 159 160 env->amask |= AMASK_MVI; 161 } 162 163 static void ev6_cpu_initfn(Object *obj) 164 { 165 AlphaCPU *cpu = ALPHA_CPU(obj); 166 CPUAlphaState *env = &cpu->env; 167 168 env->implver = IMPLVER_21264; 169 env->amask = AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP; 170 } 171 172 static void ev67_cpu_initfn(Object *obj) 173 { 174 AlphaCPU *cpu = ALPHA_CPU(obj); 175 CPUAlphaState *env = &cpu->env; 176 177 env->amask |= AMASK_CIX | AMASK_PREFETCH; 178 } 179 180 static void alpha_cpu_initfn(Object *obj) 181 { 182 AlphaCPU *cpu = ALPHA_CPU(obj); 183 CPUAlphaState *env = &cpu->env; 184 185 env->lock_addr = -1; 186 #if defined(CONFIG_USER_ONLY) 187 env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN; 188 cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD 189 | FPCR_UNFD | FPCR_INED | FPCR_DNOD 190 | FPCR_DYN_NORMAL) << 32); 191 #else 192 env->flags = ENV_FLAG_PAL_MODE | ENV_FLAG_FEN; 193 #endif 194 } 195 196 #ifndef CONFIG_USER_ONLY 197 #include "hw/core/sysemu-cpu-ops.h" 198 199 static const struct SysemuCPUOps alpha_sysemu_ops = { 200 .get_phys_page_debug = alpha_cpu_get_phys_page_debug, 201 }; 202 #endif 203 204 #include "hw/core/tcg-cpu-ops.h" 205 206 static const struct TCGCPUOps alpha_tcg_ops = { 207 .initialize = alpha_translate_init, 208 .restore_state_to_opc = alpha_restore_state_to_opc, 209 210 #ifdef CONFIG_USER_ONLY 211 .record_sigsegv = alpha_cpu_record_sigsegv, 212 .record_sigbus = alpha_cpu_record_sigbus, 213 #else 214 .tlb_fill = alpha_cpu_tlb_fill, 215 .cpu_exec_interrupt = alpha_cpu_exec_interrupt, 216 .do_interrupt = alpha_cpu_do_interrupt, 217 .do_transaction_failed = alpha_cpu_do_transaction_failed, 218 .do_unaligned_access = alpha_cpu_do_unaligned_access, 219 #endif /* !CONFIG_USER_ONLY */ 220 }; 221 222 static void alpha_cpu_class_init(ObjectClass *oc, void *data) 223 { 224 DeviceClass *dc = DEVICE_CLASS(oc); 225 CPUClass *cc = CPU_CLASS(oc); 226 AlphaCPUClass *acc = ALPHA_CPU_CLASS(oc); 227 228 device_class_set_parent_realize(dc, alpha_cpu_realizefn, 229 &acc->parent_realize); 230 231 cc->class_by_name = alpha_cpu_class_by_name; 232 cc->has_work = alpha_cpu_has_work; 233 cc->dump_state = alpha_cpu_dump_state; 234 cc->set_pc = alpha_cpu_set_pc; 235 cc->get_pc = alpha_cpu_get_pc; 236 cc->gdb_read_register = alpha_cpu_gdb_read_register; 237 cc->gdb_write_register = alpha_cpu_gdb_write_register; 238 #ifndef CONFIG_USER_ONLY 239 dc->vmsd = &vmstate_alpha_cpu; 240 cc->sysemu_ops = &alpha_sysemu_ops; 241 #endif 242 cc->disas_set_info = alpha_cpu_disas_set_info; 243 244 cc->tcg_ops = &alpha_tcg_ops; 245 cc->gdb_num_core_regs = 67; 246 } 247 248 #define DEFINE_ALPHA_CPU_TYPE(base_type, cpu_model, initfn) \ 249 { \ 250 .parent = base_type, \ 251 .instance_init = initfn, \ 252 .name = ALPHA_CPU_TYPE_NAME(cpu_model), \ 253 } 254 255 static const TypeInfo alpha_cpu_type_infos[] = { 256 { 257 .name = TYPE_ALPHA_CPU, 258 .parent = TYPE_CPU, 259 .instance_size = sizeof(AlphaCPU), 260 .instance_align = __alignof(AlphaCPU), 261 .instance_init = alpha_cpu_initfn, 262 .abstract = true, 263 .class_size = sizeof(AlphaCPUClass), 264 .class_init = alpha_cpu_class_init, 265 }, 266 DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev4", ev4_cpu_initfn), 267 DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev5", ev5_cpu_initfn), 268 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev5"), "ev56", ev56_cpu_initfn), 269 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev56"), "pca56", 270 pca56_cpu_initfn), 271 DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev6", ev6_cpu_initfn), 272 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev6"), "ev67", ev67_cpu_initfn), 273 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev67"), "ev68", NULL), 274 }; 275 276 DEFINE_TYPES(alpha_cpu_type_infos) 277