1 /* 2 * QEMU Alpha CPU 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * Copyright (c) 2012 SUSE LINUX Products GmbH 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see 19 * <http://www.gnu.org/licenses/lgpl-2.1.html> 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "qemu/qemu-print.h" 25 #include "cpu.h" 26 #include "exec/exec-all.h" 27 28 29 static void alpha_cpu_set_pc(CPUState *cs, vaddr value) 30 { 31 AlphaCPU *cpu = ALPHA_CPU(cs); 32 33 cpu->env.pc = value; 34 } 35 36 static vaddr alpha_cpu_get_pc(CPUState *cs) 37 { 38 AlphaCPU *cpu = ALPHA_CPU(cs); 39 40 return cpu->env.pc; 41 } 42 43 static void alpha_restore_state_to_opc(CPUState *cs, 44 const TranslationBlock *tb, 45 const uint64_t *data) 46 { 47 AlphaCPU *cpu = ALPHA_CPU(cs); 48 49 cpu->env.pc = data[0]; 50 } 51 52 static bool alpha_cpu_has_work(CPUState *cs) 53 { 54 /* Here we are checking to see if the CPU should wake up from HALT. 55 We will have gotten into this state only for WTINT from PALmode. */ 56 /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU 57 asleep even if (some) interrupts have been asserted. For now, 58 assume that if a CPU really wants to stay asleep, it will mask 59 interrupts at the chipset level, which will prevent these bits 60 from being set in the first place. */ 61 return cs->interrupt_request & (CPU_INTERRUPT_HARD 62 | CPU_INTERRUPT_TIMER 63 | CPU_INTERRUPT_SMP 64 | CPU_INTERRUPT_MCHK); 65 } 66 67 static int alpha_cpu_mmu_index(CPUState *cs, bool ifetch) 68 { 69 return alpha_env_mmu_index(cpu_env(cs)); 70 } 71 72 static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) 73 { 74 info->mach = bfd_mach_alpha_ev6; 75 info->print_insn = print_insn_alpha; 76 } 77 78 static void alpha_cpu_realizefn(DeviceState *dev, Error **errp) 79 { 80 CPUState *cs = CPU(dev); 81 AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev); 82 Error *local_err = NULL; 83 84 cpu_exec_realizefn(cs, &local_err); 85 if (local_err != NULL) { 86 error_propagate(errp, local_err); 87 return; 88 } 89 90 qemu_init_vcpu(cs); 91 92 acc->parent_realize(dev, errp); 93 } 94 95 /* Models */ 96 typedef struct AlphaCPUAlias { 97 const char *alias; 98 const char *typename; 99 } AlphaCPUAlias; 100 101 static const AlphaCPUAlias alpha_cpu_aliases[] = { 102 { "21064", ALPHA_CPU_TYPE_NAME("ev4") }, 103 { "21164", ALPHA_CPU_TYPE_NAME("ev5") }, 104 { "21164a", ALPHA_CPU_TYPE_NAME("ev56") }, 105 { "21164pc", ALPHA_CPU_TYPE_NAME("pca56") }, 106 { "21264", ALPHA_CPU_TYPE_NAME("ev6") }, 107 { "21264a", ALPHA_CPU_TYPE_NAME("ev67") }, 108 }; 109 110 static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model) 111 { 112 ObjectClass *oc; 113 char *typename; 114 int i; 115 116 oc = object_class_by_name(cpu_model); 117 if (oc != NULL && object_class_dynamic_cast(oc, TYPE_ALPHA_CPU) != NULL) { 118 return oc; 119 } 120 121 for (i = 0; i < ARRAY_SIZE(alpha_cpu_aliases); i++) { 122 if (strcmp(cpu_model, alpha_cpu_aliases[i].alias) == 0) { 123 oc = object_class_by_name(alpha_cpu_aliases[i].typename); 124 assert(oc != NULL && !object_class_is_abstract(oc)); 125 return oc; 126 } 127 } 128 129 typename = g_strdup_printf(ALPHA_CPU_TYPE_NAME("%s"), cpu_model); 130 oc = object_class_by_name(typename); 131 g_free(typename); 132 133 return oc; 134 } 135 136 static void ev4_cpu_initfn(Object *obj) 137 { 138 cpu_env(CPU(obj))->implver = IMPLVER_2106x; 139 } 140 141 static void ev5_cpu_initfn(Object *obj) 142 { 143 cpu_env(CPU(obj))->implver = IMPLVER_21164; 144 } 145 146 static void ev56_cpu_initfn(Object *obj) 147 { 148 cpu_env(CPU(obj))->amask |= AMASK_BWX; 149 } 150 151 static void pca56_cpu_initfn(Object *obj) 152 { 153 cpu_env(CPU(obj))->amask |= AMASK_MVI; 154 } 155 156 static void ev6_cpu_initfn(Object *obj) 157 { 158 CPUAlphaState *env = cpu_env(CPU(obj)); 159 160 env->implver = IMPLVER_21264; 161 env->amask = AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP; 162 } 163 164 static void ev67_cpu_initfn(Object *obj) 165 { 166 cpu_env(CPU(obj))->amask |= AMASK_CIX | AMASK_PREFETCH; 167 } 168 169 static void alpha_cpu_initfn(Object *obj) 170 { 171 CPUAlphaState *env = cpu_env(CPU(obj)); 172 173 env->lock_addr = -1; 174 #if defined(CONFIG_USER_ONLY) 175 env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN; 176 cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD 177 | FPCR_UNFD | FPCR_INED | FPCR_DNOD 178 | FPCR_DYN_NORMAL) << 32); 179 #else 180 env->flags = ENV_FLAG_PAL_MODE | ENV_FLAG_FEN; 181 #endif 182 } 183 184 #ifndef CONFIG_USER_ONLY 185 #include "hw/core/sysemu-cpu-ops.h" 186 187 static const struct SysemuCPUOps alpha_sysemu_ops = { 188 .get_phys_page_debug = alpha_cpu_get_phys_page_debug, 189 }; 190 #endif 191 192 #include "hw/core/tcg-cpu-ops.h" 193 194 static const TCGCPUOps alpha_tcg_ops = { 195 .initialize = alpha_translate_init, 196 .restore_state_to_opc = alpha_restore_state_to_opc, 197 198 #ifdef CONFIG_USER_ONLY 199 .record_sigsegv = alpha_cpu_record_sigsegv, 200 .record_sigbus = alpha_cpu_record_sigbus, 201 #else 202 .tlb_fill = alpha_cpu_tlb_fill, 203 .cpu_exec_interrupt = alpha_cpu_exec_interrupt, 204 .do_interrupt = alpha_cpu_do_interrupt, 205 .do_transaction_failed = alpha_cpu_do_transaction_failed, 206 .do_unaligned_access = alpha_cpu_do_unaligned_access, 207 #endif /* !CONFIG_USER_ONLY */ 208 }; 209 210 static void alpha_cpu_class_init(ObjectClass *oc, void *data) 211 { 212 DeviceClass *dc = DEVICE_CLASS(oc); 213 CPUClass *cc = CPU_CLASS(oc); 214 AlphaCPUClass *acc = ALPHA_CPU_CLASS(oc); 215 216 device_class_set_parent_realize(dc, alpha_cpu_realizefn, 217 &acc->parent_realize); 218 219 cc->class_by_name = alpha_cpu_class_by_name; 220 cc->has_work = alpha_cpu_has_work; 221 cc->mmu_index = alpha_cpu_mmu_index; 222 cc->dump_state = alpha_cpu_dump_state; 223 cc->set_pc = alpha_cpu_set_pc; 224 cc->get_pc = alpha_cpu_get_pc; 225 cc->gdb_read_register = alpha_cpu_gdb_read_register; 226 cc->gdb_write_register = alpha_cpu_gdb_write_register; 227 #ifndef CONFIG_USER_ONLY 228 dc->vmsd = &vmstate_alpha_cpu; 229 cc->sysemu_ops = &alpha_sysemu_ops; 230 #endif 231 cc->disas_set_info = alpha_cpu_disas_set_info; 232 233 cc->tcg_ops = &alpha_tcg_ops; 234 cc->gdb_num_core_regs = 67; 235 } 236 237 #define DEFINE_ALPHA_CPU_TYPE(base_type, cpu_model, initfn) \ 238 { \ 239 .parent = base_type, \ 240 .instance_init = initfn, \ 241 .name = ALPHA_CPU_TYPE_NAME(cpu_model), \ 242 } 243 244 static const TypeInfo alpha_cpu_type_infos[] = { 245 { 246 .name = TYPE_ALPHA_CPU, 247 .parent = TYPE_CPU, 248 .instance_size = sizeof(AlphaCPU), 249 .instance_align = __alignof(AlphaCPU), 250 .instance_init = alpha_cpu_initfn, 251 .abstract = true, 252 .class_size = sizeof(AlphaCPUClass), 253 .class_init = alpha_cpu_class_init, 254 }, 255 DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev4", ev4_cpu_initfn), 256 DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev5", ev5_cpu_initfn), 257 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev5"), "ev56", ev56_cpu_initfn), 258 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev56"), "pca56", 259 pca56_cpu_initfn), 260 DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev6", ev6_cpu_initfn), 261 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev6"), "ev67", ev67_cpu_initfn), 262 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev67"), "ev68", NULL), 263 }; 264 265 DEFINE_TYPES(alpha_cpu_type_infos) 266