1 /* 2 * QEMU Alpha CPU 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * Copyright (c) 2012 SUSE LINUX Products GmbH 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see 19 * <http://www.gnu.org/licenses/lgpl-2.1.html> 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "qemu/qemu-print.h" 25 #include "cpu.h" 26 #include "qemu-common.h" 27 #include "exec/exec-all.h" 28 29 30 static void alpha_cpu_set_pc(CPUState *cs, vaddr value) 31 { 32 AlphaCPU *cpu = ALPHA_CPU(cs); 33 34 cpu->env.pc = value; 35 } 36 37 static bool alpha_cpu_has_work(CPUState *cs) 38 { 39 /* Here we are checking to see if the CPU should wake up from HALT. 40 We will have gotten into this state only for WTINT from PALmode. */ 41 /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU 42 asleep even if (some) interrupts have been asserted. For now, 43 assume that if a CPU really wants to stay asleep, it will mask 44 interrupts at the chipset level, which will prevent these bits 45 from being set in the first place. */ 46 return cs->interrupt_request & (CPU_INTERRUPT_HARD 47 | CPU_INTERRUPT_TIMER 48 | CPU_INTERRUPT_SMP 49 | CPU_INTERRUPT_MCHK); 50 } 51 52 static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) 53 { 54 info->mach = bfd_mach_alpha_ev6; 55 info->print_insn = print_insn_alpha; 56 } 57 58 static void alpha_cpu_realizefn(DeviceState *dev, Error **errp) 59 { 60 CPUState *cs = CPU(dev); 61 AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev); 62 Error *local_err = NULL; 63 64 cpu_exec_realizefn(cs, &local_err); 65 if (local_err != NULL) { 66 error_propagate(errp, local_err); 67 return; 68 } 69 70 qemu_init_vcpu(cs); 71 72 acc->parent_realize(dev, errp); 73 } 74 75 static void alpha_cpu_list_entry(gpointer data, gpointer user_data) 76 { 77 ObjectClass *oc = data; 78 79 qemu_printf(" %s\n", object_class_get_name(oc)); 80 } 81 82 void alpha_cpu_list(void) 83 { 84 GSList *list; 85 86 list = object_class_get_list_sorted(TYPE_ALPHA_CPU, false); 87 qemu_printf("Available CPUs:\n"); 88 g_slist_foreach(list, alpha_cpu_list_entry, NULL); 89 g_slist_free(list); 90 } 91 92 /* Models */ 93 typedef struct AlphaCPUAlias { 94 const char *alias; 95 const char *typename; 96 } AlphaCPUAlias; 97 98 static const AlphaCPUAlias alpha_cpu_aliases[] = { 99 { "21064", ALPHA_CPU_TYPE_NAME("ev4") }, 100 { "21164", ALPHA_CPU_TYPE_NAME("ev5") }, 101 { "21164a", ALPHA_CPU_TYPE_NAME("ev56") }, 102 { "21164pc", ALPHA_CPU_TYPE_NAME("pca56") }, 103 { "21264", ALPHA_CPU_TYPE_NAME("ev6") }, 104 { "21264a", ALPHA_CPU_TYPE_NAME("ev67") }, 105 }; 106 107 static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model) 108 { 109 ObjectClass *oc; 110 char *typename; 111 int i; 112 113 oc = object_class_by_name(cpu_model); 114 if (oc != NULL && object_class_dynamic_cast(oc, TYPE_ALPHA_CPU) != NULL && 115 !object_class_is_abstract(oc)) { 116 return oc; 117 } 118 119 for (i = 0; i < ARRAY_SIZE(alpha_cpu_aliases); i++) { 120 if (strcmp(cpu_model, alpha_cpu_aliases[i].alias) == 0) { 121 oc = object_class_by_name(alpha_cpu_aliases[i].typename); 122 assert(oc != NULL && !object_class_is_abstract(oc)); 123 return oc; 124 } 125 } 126 127 typename = g_strdup_printf(ALPHA_CPU_TYPE_NAME("%s"), cpu_model); 128 oc = object_class_by_name(typename); 129 g_free(typename); 130 if (oc != NULL && object_class_is_abstract(oc)) { 131 oc = NULL; 132 } 133 134 /* TODO: remove match everything nonsense */ 135 /* Default to ev67; no reason not to emulate insns by default. */ 136 if (!oc) { 137 oc = object_class_by_name(ALPHA_CPU_TYPE_NAME("ev67")); 138 } 139 140 return oc; 141 } 142 143 static void ev4_cpu_initfn(Object *obj) 144 { 145 AlphaCPU *cpu = ALPHA_CPU(obj); 146 CPUAlphaState *env = &cpu->env; 147 148 env->implver = IMPLVER_2106x; 149 } 150 151 static void ev5_cpu_initfn(Object *obj) 152 { 153 AlphaCPU *cpu = ALPHA_CPU(obj); 154 CPUAlphaState *env = &cpu->env; 155 156 env->implver = IMPLVER_21164; 157 } 158 159 static void ev56_cpu_initfn(Object *obj) 160 { 161 AlphaCPU *cpu = ALPHA_CPU(obj); 162 CPUAlphaState *env = &cpu->env; 163 164 env->amask |= AMASK_BWX; 165 } 166 167 static void pca56_cpu_initfn(Object *obj) 168 { 169 AlphaCPU *cpu = ALPHA_CPU(obj); 170 CPUAlphaState *env = &cpu->env; 171 172 env->amask |= AMASK_MVI; 173 } 174 175 static void ev6_cpu_initfn(Object *obj) 176 { 177 AlphaCPU *cpu = ALPHA_CPU(obj); 178 CPUAlphaState *env = &cpu->env; 179 180 env->implver = IMPLVER_21264; 181 env->amask = AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP; 182 } 183 184 static void ev67_cpu_initfn(Object *obj) 185 { 186 AlphaCPU *cpu = ALPHA_CPU(obj); 187 CPUAlphaState *env = &cpu->env; 188 189 env->amask |= AMASK_CIX | AMASK_PREFETCH; 190 } 191 192 static void alpha_cpu_initfn(Object *obj) 193 { 194 CPUState *cs = CPU(obj); 195 AlphaCPU *cpu = ALPHA_CPU(obj); 196 CPUAlphaState *env = &cpu->env; 197 198 cs->env_ptr = env; 199 200 env->lock_addr = -1; 201 #if defined(CONFIG_USER_ONLY) 202 env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN; 203 cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD 204 | FPCR_UNFD | FPCR_INED | FPCR_DNOD 205 | FPCR_DYN_NORMAL) << 32); 206 #else 207 env->flags = ENV_FLAG_PAL_MODE | ENV_FLAG_FEN; 208 #endif 209 } 210 211 static void alpha_cpu_class_init(ObjectClass *oc, void *data) 212 { 213 DeviceClass *dc = DEVICE_CLASS(oc); 214 CPUClass *cc = CPU_CLASS(oc); 215 AlphaCPUClass *acc = ALPHA_CPU_CLASS(oc); 216 217 device_class_set_parent_realize(dc, alpha_cpu_realizefn, 218 &acc->parent_realize); 219 220 cc->class_by_name = alpha_cpu_class_by_name; 221 cc->has_work = alpha_cpu_has_work; 222 cc->do_interrupt = alpha_cpu_do_interrupt; 223 cc->cpu_exec_interrupt = alpha_cpu_exec_interrupt; 224 cc->dump_state = alpha_cpu_dump_state; 225 cc->set_pc = alpha_cpu_set_pc; 226 cc->gdb_read_register = alpha_cpu_gdb_read_register; 227 cc->gdb_write_register = alpha_cpu_gdb_write_register; 228 cc->tlb_fill = alpha_cpu_tlb_fill; 229 #ifndef CONFIG_USER_ONLY 230 cc->do_transaction_failed = alpha_cpu_do_transaction_failed; 231 cc->do_unaligned_access = alpha_cpu_do_unaligned_access; 232 cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug; 233 dc->vmsd = &vmstate_alpha_cpu; 234 #endif 235 cc->disas_set_info = alpha_cpu_disas_set_info; 236 cc->tcg_initialize = alpha_translate_init; 237 238 cc->gdb_num_core_regs = 67; 239 } 240 241 #define DEFINE_ALPHA_CPU_TYPE(base_type, cpu_model, initfn) \ 242 { \ 243 .parent = base_type, \ 244 .instance_init = initfn, \ 245 .name = ALPHA_CPU_TYPE_NAME(cpu_model), \ 246 } 247 248 static const TypeInfo alpha_cpu_type_infos[] = { 249 { 250 .name = TYPE_ALPHA_CPU, 251 .parent = TYPE_CPU, 252 .instance_size = sizeof(AlphaCPU), 253 .instance_init = alpha_cpu_initfn, 254 .abstract = true, 255 .class_size = sizeof(AlphaCPUClass), 256 .class_init = alpha_cpu_class_init, 257 }, 258 DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev4", ev4_cpu_initfn), 259 DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev5", ev5_cpu_initfn), 260 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev5"), "ev56", ev56_cpu_initfn), 261 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev56"), "pca56", 262 pca56_cpu_initfn), 263 DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev6", ev6_cpu_initfn), 264 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev6"), "ev67", ev67_cpu_initfn), 265 DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev67"), "ev68", NULL), 266 }; 267 268 DEFINE_TYPES(alpha_cpu_type_infos) 269