1 /*
2  * Virtio GPU Device
3  *
4  * Copyright Red Hat, Inc. 2013-2014
5  *
6  * Authors:
7  *     Dave Airlie <airlied@redhat.com>
8  *     Gerd Hoffmann <kraxel@redhat.com>
9  *
10  * This header is BSD licensed so anyone can use the definitions
11  * to implement compatible drivers/servers:
12  *
13  * Redistribution and use in source and binary forms, with or without
14  * modification, are permitted provided that the following conditions
15  * are met:
16  * 1. Redistributions of source code must retain the above copyright
17  *    notice, this list of conditions and the following disclaimer.
18  * 2. Redistributions in binary form must reproduce the above copyright
19  *    notice, this list of conditions and the following disclaimer in the
20  *    documentation and/or other materials provided with the distribution.
21  * 3. Neither the name of IBM nor the names of its contributors
22  *    may be used to endorse or promote products derived from this software
23  *    without specific prior written permission.
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
27  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL IBM OR
28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
31  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
32  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
33  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
34  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35  * SUCH DAMAGE.
36  */
37 
38 #ifndef VIRTIO_GPU_HW_H
39 #define VIRTIO_GPU_HW_H
40 
41 #include "standard-headers/linux/types.h"
42 
43 #define VIRTIO_GPU_FEATURE_VIRGL 0
44 
45 enum virtio_gpu_ctrl_type {
46 	VIRTIO_GPU_UNDEFINED = 0,
47 
48 	/* 2d commands */
49 	VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100,
50 	VIRTIO_GPU_CMD_RESOURCE_CREATE_2D,
51 	VIRTIO_GPU_CMD_RESOURCE_UNREF,
52 	VIRTIO_GPU_CMD_SET_SCANOUT,
53 	VIRTIO_GPU_CMD_RESOURCE_FLUSH,
54 	VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D,
55 	VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING,
56 	VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING,
57 	VIRTIO_GPU_CMD_GET_CAPSET_INFO,
58 	VIRTIO_GPU_CMD_GET_CAPSET,
59 
60 	/* 3d commands */
61 	VIRTIO_GPU_CMD_CTX_CREATE = 0x0200,
62 	VIRTIO_GPU_CMD_CTX_DESTROY,
63 	VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE,
64 	VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE,
65 	VIRTIO_GPU_CMD_RESOURCE_CREATE_3D,
66 	VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D,
67 	VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D,
68 	VIRTIO_GPU_CMD_SUBMIT_3D,
69 
70 	/* cursor commands */
71 	VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300,
72 	VIRTIO_GPU_CMD_MOVE_CURSOR,
73 
74 	/* success responses */
75 	VIRTIO_GPU_RESP_OK_NODATA = 0x1100,
76 	VIRTIO_GPU_RESP_OK_DISPLAY_INFO,
77 	VIRTIO_GPU_RESP_OK_CAPSET_INFO,
78 	VIRTIO_GPU_RESP_OK_CAPSET,
79 
80 	/* error responses */
81 	VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,
82 	VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY,
83 	VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID,
84 	VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID,
85 	VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID,
86 	VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER,
87 };
88 
89 #define VIRTIO_GPU_FLAG_FENCE (1 << 0)
90 
91 struct virtio_gpu_ctrl_hdr {
92 	uint32_t type;
93 	uint32_t flags;
94 	uint64_t fence_id;
95 	uint32_t ctx_id;
96 	uint32_t padding;
97 };
98 
99 /* data passed in the cursor vq */
100 
101 struct virtio_gpu_cursor_pos {
102 	uint32_t scanout_id;
103 	uint32_t x;
104 	uint32_t y;
105 	uint32_t padding;
106 };
107 
108 /* VIRTIO_GPU_CMD_UPDATE_CURSOR, VIRTIO_GPU_CMD_MOVE_CURSOR */
109 struct virtio_gpu_update_cursor {
110 	struct virtio_gpu_ctrl_hdr hdr;
111 	struct virtio_gpu_cursor_pos pos;  /* update & move */
112 	uint32_t resource_id;           /* update only */
113 	uint32_t hot_x;                 /* update only */
114 	uint32_t hot_y;                 /* update only */
115 	uint32_t padding;
116 };
117 
118 /* data passed in the control vq, 2d related */
119 
120 struct virtio_gpu_rect {
121 	uint32_t x;
122 	uint32_t y;
123 	uint32_t width;
124 	uint32_t height;
125 };
126 
127 /* VIRTIO_GPU_CMD_RESOURCE_UNREF */
128 struct virtio_gpu_resource_unref {
129 	struct virtio_gpu_ctrl_hdr hdr;
130 	uint32_t resource_id;
131 	uint32_t padding;
132 };
133 
134 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: create a 2d resource with a format */
135 struct virtio_gpu_resource_create_2d {
136 	struct virtio_gpu_ctrl_hdr hdr;
137 	uint32_t resource_id;
138 	uint32_t format;
139 	uint32_t width;
140 	uint32_t height;
141 };
142 
143 /* VIRTIO_GPU_CMD_SET_SCANOUT */
144 struct virtio_gpu_set_scanout {
145 	struct virtio_gpu_ctrl_hdr hdr;
146 	struct virtio_gpu_rect r;
147 	uint32_t scanout_id;
148 	uint32_t resource_id;
149 };
150 
151 /* VIRTIO_GPU_CMD_RESOURCE_FLUSH */
152 struct virtio_gpu_resource_flush {
153 	struct virtio_gpu_ctrl_hdr hdr;
154 	struct virtio_gpu_rect r;
155 	uint32_t resource_id;
156 	uint32_t padding;
157 };
158 
159 /* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: simple transfer to_host */
160 struct virtio_gpu_transfer_to_host_2d {
161 	struct virtio_gpu_ctrl_hdr hdr;
162 	struct virtio_gpu_rect r;
163 	uint64_t offset;
164 	uint32_t resource_id;
165 	uint32_t padding;
166 };
167 
168 struct virtio_gpu_mem_entry {
169 	uint64_t addr;
170 	uint32_t length;
171 	uint32_t padding;
172 };
173 
174 /* VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING */
175 struct virtio_gpu_resource_attach_backing {
176 	struct virtio_gpu_ctrl_hdr hdr;
177 	uint32_t resource_id;
178 	uint32_t nr_entries;
179 };
180 
181 /* VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING */
182 struct virtio_gpu_resource_detach_backing {
183 	struct virtio_gpu_ctrl_hdr hdr;
184 	uint32_t resource_id;
185 	uint32_t padding;
186 };
187 
188 /* VIRTIO_GPU_RESP_OK_DISPLAY_INFO */
189 #define VIRTIO_GPU_MAX_SCANOUTS 16
190 struct virtio_gpu_resp_display_info {
191 	struct virtio_gpu_ctrl_hdr hdr;
192 	struct virtio_gpu_display_one {
193 		struct virtio_gpu_rect r;
194 		uint32_t enabled;
195 		uint32_t flags;
196 	} pmodes[VIRTIO_GPU_MAX_SCANOUTS];
197 };
198 
199 /* data passed in the control vq, 3d related */
200 
201 struct virtio_gpu_box {
202 	uint32_t x, y, z;
203 	uint32_t w, h, d;
204 };
205 
206 /* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D */
207 struct virtio_gpu_transfer_host_3d {
208 	struct virtio_gpu_ctrl_hdr hdr;
209 	struct virtio_gpu_box box;
210 	uint64_t offset;
211 	uint32_t resource_id;
212 	uint32_t level;
213 	uint32_t stride;
214 	uint32_t layer_stride;
215 };
216 
217 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_3D */
218 #define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0)
219 struct virtio_gpu_resource_create_3d {
220 	struct virtio_gpu_ctrl_hdr hdr;
221 	uint32_t resource_id;
222 	uint32_t target;
223 	uint32_t format;
224 	uint32_t bind;
225 	uint32_t width;
226 	uint32_t height;
227 	uint32_t depth;
228 	uint32_t array_size;
229 	uint32_t last_level;
230 	uint32_t nr_samples;
231 	uint32_t flags;
232 	uint32_t padding;
233 };
234 
235 /* VIRTIO_GPU_CMD_CTX_CREATE */
236 struct virtio_gpu_ctx_create {
237 	struct virtio_gpu_ctrl_hdr hdr;
238 	uint32_t nlen;
239 	uint32_t padding;
240 	char debug_name[64];
241 };
242 
243 /* VIRTIO_GPU_CMD_CTX_DESTROY */
244 struct virtio_gpu_ctx_destroy {
245 	struct virtio_gpu_ctrl_hdr hdr;
246 };
247 
248 /* VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE */
249 struct virtio_gpu_ctx_resource {
250 	struct virtio_gpu_ctrl_hdr hdr;
251 	uint32_t resource_id;
252 	uint32_t padding;
253 };
254 
255 /* VIRTIO_GPU_CMD_SUBMIT_3D */
256 struct virtio_gpu_cmd_submit {
257 	struct virtio_gpu_ctrl_hdr hdr;
258 	uint32_t size;
259 	uint32_t padding;
260 };
261 
262 #define VIRTIO_GPU_CAPSET_VIRGL 1
263 
264 /* VIRTIO_GPU_CMD_GET_CAPSET_INFO */
265 struct virtio_gpu_get_capset_info {
266 	struct virtio_gpu_ctrl_hdr hdr;
267 	uint32_t capset_index;
268 	uint32_t padding;
269 };
270 
271 /* VIRTIO_GPU_RESP_OK_CAPSET_INFO */
272 struct virtio_gpu_resp_capset_info {
273 	struct virtio_gpu_ctrl_hdr hdr;
274 	uint32_t capset_id;
275 	uint32_t capset_max_version;
276 	uint32_t capset_max_size;
277 	uint32_t padding;
278 };
279 
280 /* VIRTIO_GPU_CMD_GET_CAPSET */
281 struct virtio_gpu_get_capset {
282 	struct virtio_gpu_ctrl_hdr hdr;
283 	uint32_t capset_id;
284 	uint32_t capset_version;
285 };
286 
287 /* VIRTIO_GPU_RESP_OK_CAPSET */
288 struct virtio_gpu_resp_capset {
289 	struct virtio_gpu_ctrl_hdr hdr;
290 	uint8_t capset_data[];
291 };
292 
293 #define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)
294 
295 struct virtio_gpu_config {
296 	uint32_t events_read;
297 	uint32_t events_clear;
298 	uint32_t num_scanouts;
299 	uint32_t num_capsets;
300 };
301 
302 /* simple formats for fbcon/X use */
303 enum virtio_gpu_formats {
304 	VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM  = 1,
305 	VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM  = 2,
306 	VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM  = 3,
307 	VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM  = 4,
308 
309 	VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM  = 67,
310 	VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM  = 68,
311 
312 	VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM  = 121,
313 	VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM  = 134,
314 };
315 
316 #endif
317