1412a8245SMichael S. Tsirkin /*
2412a8245SMichael S. Tsirkin  *	pci_regs.h
3412a8245SMichael S. Tsirkin  *
4412a8245SMichael S. Tsirkin  *	PCI standard defines
5412a8245SMichael S. Tsirkin  *	Copyright 1994, Drew Eckhardt
6412a8245SMichael S. Tsirkin  *	Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7412a8245SMichael S. Tsirkin  *
8412a8245SMichael S. Tsirkin  *	For more information, please consult the following manuals (look at
9412a8245SMichael S. Tsirkin  *	http://www.pcisig.com/ for how to get them):
10412a8245SMichael S. Tsirkin  *
11412a8245SMichael S. Tsirkin  *	PCI BIOS Specification
12412a8245SMichael S. Tsirkin  *	PCI Local Bus Specification
13412a8245SMichael S. Tsirkin  *	PCI to PCI Bridge Specification
14412a8245SMichael S. Tsirkin  *	PCI System Design Guide
15412a8245SMichael S. Tsirkin  *
16120758fbSPaolo Bonzini  *	For HyperTransport information, please consult the following manuals
17412a8245SMichael S. Tsirkin  *	from http://www.hypertransport.org
18412a8245SMichael S. Tsirkin  *
19120758fbSPaolo Bonzini  *	The HyperTransport I/O Link Specification
20412a8245SMichael S. Tsirkin  */
21412a8245SMichael S. Tsirkin 
22412a8245SMichael S. Tsirkin #ifndef LINUX_PCI_REGS_H
23412a8245SMichael S. Tsirkin #define LINUX_PCI_REGS_H
24412a8245SMichael S. Tsirkin 
25412a8245SMichael S. Tsirkin /*
263a5eb5b4SPaolo Bonzini  * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
273a5eb5b4SPaolo Bonzini  * configuration space.  PCI-X Mode 2 and PCIe devices have 4096 bytes of
283a5eb5b4SPaolo Bonzini  * configuration space.
293a5eb5b4SPaolo Bonzini  */
303a5eb5b4SPaolo Bonzini #define PCI_CFG_SPACE_SIZE	256
313a5eb5b4SPaolo Bonzini #define PCI_CFG_SPACE_EXP_SIZE	4096
323a5eb5b4SPaolo Bonzini 
333a5eb5b4SPaolo Bonzini /*
34412a8245SMichael S. Tsirkin  * Under PCI, each device has 256 bytes of configuration address space,
35412a8245SMichael S. Tsirkin  * of which the first 64 bytes are standardized as follows:
36412a8245SMichael S. Tsirkin  */
37120758fbSPaolo Bonzini #define PCI_STD_HEADER_SIZEOF	64
38412a8245SMichael S. Tsirkin #define PCI_VENDOR_ID		0x00	/* 16 bits */
39412a8245SMichael S. Tsirkin #define PCI_DEVICE_ID		0x02	/* 16 bits */
40412a8245SMichael S. Tsirkin #define PCI_COMMAND		0x04	/* 16 bits */
41412a8245SMichael S. Tsirkin #define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
42412a8245SMichael S. Tsirkin #define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
43412a8245SMichael S. Tsirkin #define  PCI_COMMAND_MASTER	0x4	/* Enable bus mastering */
44412a8245SMichael S. Tsirkin #define  PCI_COMMAND_SPECIAL	0x8	/* Enable response to special cycles */
45412a8245SMichael S. Tsirkin #define  PCI_COMMAND_INVALIDATE	0x10	/* Use memory write and invalidate */
46412a8245SMichael S. Tsirkin #define  PCI_COMMAND_VGA_PALETTE 0x20	/* Enable palette snooping */
47412a8245SMichael S. Tsirkin #define  PCI_COMMAND_PARITY	0x40	/* Enable parity checking */
48412a8245SMichael S. Tsirkin #define  PCI_COMMAND_WAIT	0x80	/* Enable address/data stepping */
49412a8245SMichael S. Tsirkin #define  PCI_COMMAND_SERR	0x100	/* Enable SERR */
50412a8245SMichael S. Tsirkin #define  PCI_COMMAND_FAST_BACK	0x200	/* Enable back-to-back writes */
51412a8245SMichael S. Tsirkin #define  PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
52412a8245SMichael S. Tsirkin 
53412a8245SMichael S. Tsirkin #define PCI_STATUS		0x06	/* 16 bits */
54412a8245SMichael S. Tsirkin #define  PCI_STATUS_INTERRUPT	0x08	/* Interrupt status */
55412a8245SMichael S. Tsirkin #define  PCI_STATUS_CAP_LIST	0x10	/* Support Capability List */
56120758fbSPaolo Bonzini #define  PCI_STATUS_66MHZ	0x20	/* Support 66 MHz PCI 2.1 bus */
57412a8245SMichael S. Tsirkin #define  PCI_STATUS_UDF		0x40	/* Support User Definable Features [obsolete] */
58412a8245SMichael S. Tsirkin #define  PCI_STATUS_FAST_BACK	0x80	/* Accept fast-back to back */
59412a8245SMichael S. Tsirkin #define  PCI_STATUS_PARITY	0x100	/* Detected parity error */
60412a8245SMichael S. Tsirkin #define  PCI_STATUS_DEVSEL_MASK	0x600	/* DEVSEL timing */
61412a8245SMichael S. Tsirkin #define  PCI_STATUS_DEVSEL_FAST		0x000
62412a8245SMichael S. Tsirkin #define  PCI_STATUS_DEVSEL_MEDIUM	0x200
63412a8245SMichael S. Tsirkin #define  PCI_STATUS_DEVSEL_SLOW		0x400
64412a8245SMichael S. Tsirkin #define  PCI_STATUS_SIG_TARGET_ABORT	0x800 /* Set on target abort */
65412a8245SMichael S. Tsirkin #define  PCI_STATUS_REC_TARGET_ABORT	0x1000 /* Master ack of " */
66412a8245SMichael S. Tsirkin #define  PCI_STATUS_REC_MASTER_ABORT	0x2000 /* Set on master abort */
67412a8245SMichael S. Tsirkin #define  PCI_STATUS_SIG_SYSTEM_ERROR	0x4000 /* Set when we drive SERR */
68412a8245SMichael S. Tsirkin #define  PCI_STATUS_DETECTED_PARITY	0x8000 /* Set on parity error */
69412a8245SMichael S. Tsirkin 
70412a8245SMichael S. Tsirkin #define PCI_CLASS_REVISION	0x08	/* High 24 bits are class, low 8 revision */
71412a8245SMichael S. Tsirkin #define PCI_REVISION_ID		0x08	/* Revision ID */
72412a8245SMichael S. Tsirkin #define PCI_CLASS_PROG		0x09	/* Reg. Level Programming Interface */
73412a8245SMichael S. Tsirkin #define PCI_CLASS_DEVICE	0x0a	/* Device class */
74412a8245SMichael S. Tsirkin 
75412a8245SMichael S. Tsirkin #define PCI_CACHE_LINE_SIZE	0x0c	/* 8 bits */
76412a8245SMichael S. Tsirkin #define PCI_LATENCY_TIMER	0x0d	/* 8 bits */
77412a8245SMichael S. Tsirkin #define PCI_HEADER_TYPE		0x0e	/* 8 bits */
78412a8245SMichael S. Tsirkin #define  PCI_HEADER_TYPE_NORMAL		0
79412a8245SMichael S. Tsirkin #define  PCI_HEADER_TYPE_BRIDGE		1
80412a8245SMichael S. Tsirkin #define  PCI_HEADER_TYPE_CARDBUS	2
81412a8245SMichael S. Tsirkin 
82412a8245SMichael S. Tsirkin #define PCI_BIST		0x0f	/* 8 bits */
83412a8245SMichael S. Tsirkin #define  PCI_BIST_CODE_MASK	0x0f	/* Return result */
84412a8245SMichael S. Tsirkin #define  PCI_BIST_START		0x40	/* 1 to start BIST, 2 secs or less */
85412a8245SMichael S. Tsirkin #define  PCI_BIST_CAPABLE	0x80	/* 1 if BIST capable */
86412a8245SMichael S. Tsirkin 
87412a8245SMichael S. Tsirkin /*
88412a8245SMichael S. Tsirkin  * Base addresses specify locations in memory or I/O space.
89412a8245SMichael S. Tsirkin  * Decoded size can be determined by writing a value of
90412a8245SMichael S. Tsirkin  * 0xffffffff to the register, and reading it back.  Only
91412a8245SMichael S. Tsirkin  * 1 bits are decoded.
92412a8245SMichael S. Tsirkin  */
93412a8245SMichael S. Tsirkin #define PCI_BASE_ADDRESS_0	0x10	/* 32 bits */
94412a8245SMichael S. Tsirkin #define PCI_BASE_ADDRESS_1	0x14	/* 32 bits [htype 0,1 only] */
95412a8245SMichael S. Tsirkin #define PCI_BASE_ADDRESS_2	0x18	/* 32 bits [htype 0 only] */
96412a8245SMichael S. Tsirkin #define PCI_BASE_ADDRESS_3	0x1c	/* 32 bits */
97412a8245SMichael S. Tsirkin #define PCI_BASE_ADDRESS_4	0x20	/* 32 bits */
98412a8245SMichael S. Tsirkin #define PCI_BASE_ADDRESS_5	0x24	/* 32 bits */
99412a8245SMichael S. Tsirkin #define  PCI_BASE_ADDRESS_SPACE		0x01	/* 0 = memory, 1 = I/O */
100412a8245SMichael S. Tsirkin #define  PCI_BASE_ADDRESS_SPACE_IO	0x01
101412a8245SMichael S. Tsirkin #define  PCI_BASE_ADDRESS_SPACE_MEMORY	0x00
102412a8245SMichael S. Tsirkin #define  PCI_BASE_ADDRESS_MEM_TYPE_MASK	0x06
103412a8245SMichael S. Tsirkin #define  PCI_BASE_ADDRESS_MEM_TYPE_32	0x00	/* 32 bit address */
104412a8245SMichael S. Tsirkin #define  PCI_BASE_ADDRESS_MEM_TYPE_1M	0x02	/* Below 1M [obsolete] */
105412a8245SMichael S. Tsirkin #define  PCI_BASE_ADDRESS_MEM_TYPE_64	0x04	/* 64 bit address */
106412a8245SMichael S. Tsirkin #define  PCI_BASE_ADDRESS_MEM_PREFETCH	0x08	/* prefetchable? */
107412a8245SMichael S. Tsirkin #define  PCI_BASE_ADDRESS_MEM_MASK	(~0x0fUL)
108412a8245SMichael S. Tsirkin #define  PCI_BASE_ADDRESS_IO_MASK	(~0x03UL)
109412a8245SMichael S. Tsirkin /* bit 1 is reserved if address_space = 1 */
110412a8245SMichael S. Tsirkin 
111412a8245SMichael S. Tsirkin /* Header type 0 (normal devices) */
112412a8245SMichael S. Tsirkin #define PCI_CARDBUS_CIS		0x28
113412a8245SMichael S. Tsirkin #define PCI_SUBSYSTEM_VENDOR_ID	0x2c
114412a8245SMichael S. Tsirkin #define PCI_SUBSYSTEM_ID	0x2e
115412a8245SMichael S. Tsirkin #define PCI_ROM_ADDRESS		0x30	/* Bits 31..11 are address, 10..1 reserved */
116412a8245SMichael S. Tsirkin #define  PCI_ROM_ADDRESS_ENABLE	0x01
11774c98e20SCornelia Huck #define PCI_ROM_ADDRESS_MASK	(~0x7ffU)
118412a8245SMichael S. Tsirkin 
119412a8245SMichael S. Tsirkin #define PCI_CAPABILITY_LIST	0x34	/* Offset of first capability list entry */
120412a8245SMichael S. Tsirkin 
121412a8245SMichael S. Tsirkin /* 0x35-0x3b are reserved */
122412a8245SMichael S. Tsirkin #define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */
123412a8245SMichael S. Tsirkin #define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */
124412a8245SMichael S. Tsirkin #define PCI_MIN_GNT		0x3e	/* 8 bits */
125412a8245SMichael S. Tsirkin #define PCI_MAX_LAT		0x3f	/* 8 bits */
126412a8245SMichael S. Tsirkin 
127412a8245SMichael S. Tsirkin /* Header type 1 (PCI-to-PCI bridges) */
128412a8245SMichael S. Tsirkin #define PCI_PRIMARY_BUS		0x18	/* Primary bus number */
129412a8245SMichael S. Tsirkin #define PCI_SECONDARY_BUS	0x19	/* Secondary bus number */
130412a8245SMichael S. Tsirkin #define PCI_SUBORDINATE_BUS	0x1a	/* Highest bus number behind the bridge */
131412a8245SMichael S. Tsirkin #define PCI_SEC_LATENCY_TIMER	0x1b	/* Latency timer for secondary interface */
132412a8245SMichael S. Tsirkin #define PCI_IO_BASE		0x1c	/* I/O range behind the bridge */
133412a8245SMichael S. Tsirkin #define PCI_IO_LIMIT		0x1d
134412a8245SMichael S. Tsirkin #define  PCI_IO_RANGE_TYPE_MASK	0x0fUL	/* I/O bridging type */
135412a8245SMichael S. Tsirkin #define  PCI_IO_RANGE_TYPE_16	0x00
136412a8245SMichael S. Tsirkin #define  PCI_IO_RANGE_TYPE_32	0x01
137120758fbSPaolo Bonzini #define  PCI_IO_RANGE_MASK	(~0x0fUL) /* Standard 4K I/O windows */
138120758fbSPaolo Bonzini #define  PCI_IO_1K_RANGE_MASK	(~0x03UL) /* Intel 1K I/O windows */
139412a8245SMichael S. Tsirkin #define PCI_SEC_STATUS		0x1e	/* Secondary status register, only bit 14 used */
140412a8245SMichael S. Tsirkin #define PCI_MEMORY_BASE		0x20	/* Memory range behind */
141412a8245SMichael S. Tsirkin #define PCI_MEMORY_LIMIT	0x22
142412a8245SMichael S. Tsirkin #define  PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
143412a8245SMichael S. Tsirkin #define  PCI_MEMORY_RANGE_MASK	(~0x0fUL)
144412a8245SMichael S. Tsirkin #define PCI_PREF_MEMORY_BASE	0x24	/* Prefetchable memory range behind */
145412a8245SMichael S. Tsirkin #define PCI_PREF_MEMORY_LIMIT	0x26
146412a8245SMichael S. Tsirkin #define  PCI_PREF_RANGE_TYPE_MASK 0x0fUL
147412a8245SMichael S. Tsirkin #define  PCI_PREF_RANGE_TYPE_32	0x00
148412a8245SMichael S. Tsirkin #define  PCI_PREF_RANGE_TYPE_64	0x01
149412a8245SMichael S. Tsirkin #define  PCI_PREF_RANGE_MASK	(~0x0fUL)
150412a8245SMichael S. Tsirkin #define PCI_PREF_BASE_UPPER32	0x28	/* Upper half of prefetchable memory range */
151412a8245SMichael S. Tsirkin #define PCI_PREF_LIMIT_UPPER32	0x2c
152412a8245SMichael S. Tsirkin #define PCI_IO_BASE_UPPER16	0x30	/* Upper half of I/O addresses */
153412a8245SMichael S. Tsirkin #define PCI_IO_LIMIT_UPPER16	0x32
154412a8245SMichael S. Tsirkin /* 0x34 same as for htype 0 */
155412a8245SMichael S. Tsirkin /* 0x35-0x3b is reserved */
156412a8245SMichael S. Tsirkin #define PCI_ROM_ADDRESS1	0x38	/* Same as PCI_ROM_ADDRESS, but for htype 1 */
157412a8245SMichael S. Tsirkin /* 0x3c-0x3d are same as for htype 0 */
158412a8245SMichael S. Tsirkin #define PCI_BRIDGE_CONTROL	0x3e
159412a8245SMichael S. Tsirkin #define  PCI_BRIDGE_CTL_PARITY	0x01	/* Enable parity detection on secondary interface */
160412a8245SMichael S. Tsirkin #define  PCI_BRIDGE_CTL_SERR	0x02	/* The same for SERR forwarding */
161412a8245SMichael S. Tsirkin #define  PCI_BRIDGE_CTL_ISA	0x04	/* Enable ISA mode */
162412a8245SMichael S. Tsirkin #define  PCI_BRIDGE_CTL_VGA	0x08	/* Forward VGA addresses */
163412a8245SMichael S. Tsirkin #define  PCI_BRIDGE_CTL_MASTER_ABORT	0x20  /* Report master aborts */
164412a8245SMichael S. Tsirkin #define  PCI_BRIDGE_CTL_BUS_RESET	0x40	/* Secondary bus reset */
165412a8245SMichael S. Tsirkin #define  PCI_BRIDGE_CTL_FAST_BACK	0x80	/* Fast Back2Back enabled on secondary interface */
166412a8245SMichael S. Tsirkin 
167412a8245SMichael S. Tsirkin /* Header type 2 (CardBus bridges) */
168412a8245SMichael S. Tsirkin #define PCI_CB_CAPABILITY_LIST	0x14
169412a8245SMichael S. Tsirkin /* 0x15 reserved */
170412a8245SMichael S. Tsirkin #define PCI_CB_SEC_STATUS	0x16	/* Secondary status */
171412a8245SMichael S. Tsirkin #define PCI_CB_PRIMARY_BUS	0x18	/* PCI bus number */
172412a8245SMichael S. Tsirkin #define PCI_CB_CARD_BUS		0x19	/* CardBus bus number */
173412a8245SMichael S. Tsirkin #define PCI_CB_SUBORDINATE_BUS	0x1a	/* Subordinate bus number */
174412a8245SMichael S. Tsirkin #define PCI_CB_LATENCY_TIMER	0x1b	/* CardBus latency timer */
175412a8245SMichael S. Tsirkin #define PCI_CB_MEMORY_BASE_0	0x1c
176412a8245SMichael S. Tsirkin #define PCI_CB_MEMORY_LIMIT_0	0x20
177412a8245SMichael S. Tsirkin #define PCI_CB_MEMORY_BASE_1	0x24
178412a8245SMichael S. Tsirkin #define PCI_CB_MEMORY_LIMIT_1	0x28
179412a8245SMichael S. Tsirkin #define PCI_CB_IO_BASE_0	0x2c
180412a8245SMichael S. Tsirkin #define PCI_CB_IO_BASE_0_HI	0x2e
181412a8245SMichael S. Tsirkin #define PCI_CB_IO_LIMIT_0	0x30
182412a8245SMichael S. Tsirkin #define PCI_CB_IO_LIMIT_0_HI	0x32
183412a8245SMichael S. Tsirkin #define PCI_CB_IO_BASE_1	0x34
184412a8245SMichael S. Tsirkin #define PCI_CB_IO_BASE_1_HI	0x36
185412a8245SMichael S. Tsirkin #define PCI_CB_IO_LIMIT_1	0x38
186412a8245SMichael S. Tsirkin #define PCI_CB_IO_LIMIT_1_HI	0x3a
187412a8245SMichael S. Tsirkin #define  PCI_CB_IO_RANGE_MASK	(~0x03UL)
188412a8245SMichael S. Tsirkin /* 0x3c-0x3d are same as for htype 0 */
189412a8245SMichael S. Tsirkin #define PCI_CB_BRIDGE_CONTROL	0x3e
190412a8245SMichael S. Tsirkin #define  PCI_CB_BRIDGE_CTL_PARITY	0x01	/* Similar to standard bridge control register */
191412a8245SMichael S. Tsirkin #define  PCI_CB_BRIDGE_CTL_SERR		0x02
192412a8245SMichael S. Tsirkin #define  PCI_CB_BRIDGE_CTL_ISA		0x04
193412a8245SMichael S. Tsirkin #define  PCI_CB_BRIDGE_CTL_VGA		0x08
194412a8245SMichael S. Tsirkin #define  PCI_CB_BRIDGE_CTL_MASTER_ABORT	0x20
195412a8245SMichael S. Tsirkin #define  PCI_CB_BRIDGE_CTL_CB_RESET	0x40	/* CardBus reset */
196412a8245SMichael S. Tsirkin #define  PCI_CB_BRIDGE_CTL_16BIT_INT	0x80	/* Enable interrupt for 16-bit cards */
197412a8245SMichael S. Tsirkin #define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100	/* Prefetch enable for both memory regions */
198412a8245SMichael S. Tsirkin #define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
199412a8245SMichael S. Tsirkin #define  PCI_CB_BRIDGE_CTL_POST_WRITES	0x400
200412a8245SMichael S. Tsirkin #define PCI_CB_SUBSYSTEM_VENDOR_ID	0x40
201412a8245SMichael S. Tsirkin #define PCI_CB_SUBSYSTEM_ID		0x42
202412a8245SMichael S. Tsirkin #define PCI_CB_LEGACY_MODE_BASE		0x44	/* 16-bit PC Card legacy mode base address (ExCa) */
203412a8245SMichael S. Tsirkin /* 0x48-0x7f reserved */
204412a8245SMichael S. Tsirkin 
205412a8245SMichael S. Tsirkin /* Capability lists */
206412a8245SMichael S. Tsirkin 
207412a8245SMichael S. Tsirkin #define PCI_CAP_LIST_ID		0	/* Capability ID */
208412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_PM		0x01	/* Power Management */
209412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_AGP		0x02	/* Accelerated Graphics Port */
210412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_VPD		0x03	/* Vital Product Data */
211412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_SLOTID	0x04	/* Slot Identification */
212412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_MSI		0x05	/* Message Signalled Interrupts */
213412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_CHSWP	0x06	/* CompactPCI HotSwap */
214412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_PCIX	0x07	/* PCI-X */
215412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_HT		0x08	/* HyperTransport */
216120758fbSPaolo Bonzini #define  PCI_CAP_ID_VNDR	0x09	/* Vendor-Specific */
217412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_DBG		0x0A	/* Debug port */
218412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_CCRC	0x0B	/* CompactPCI Central Resource Control */
219412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_SHPC	0x0C	/* PCI Standard Hot-Plug Controller */
220412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_SSVID	0x0D	/* Bridge subsystem vendor/device ID */
221412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_AGP3	0x0E	/* AGP Target PCI-PCI bridge */
222120758fbSPaolo Bonzini #define  PCI_CAP_ID_SECDEV	0x0F	/* Secure Device */
223412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_EXP		0x10	/* PCI Express */
224412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_MSIX	0x11	/* MSI-X */
225120758fbSPaolo Bonzini #define  PCI_CAP_ID_SATA	0x12	/* SATA Data/Index Conf. */
226412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_AF		0x13	/* PCI Advanced Features */
227fff02bc0SPaolo Bonzini #define  PCI_CAP_ID_EA		0x14	/* PCI Enhanced Allocation */
228fff02bc0SPaolo Bonzini #define  PCI_CAP_ID_MAX		PCI_CAP_ID_EA
229412a8245SMichael S. Tsirkin #define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
230412a8245SMichael S. Tsirkin #define PCI_CAP_FLAGS		2	/* Capability defined flags (16 bits) */
231412a8245SMichael S. Tsirkin #define PCI_CAP_SIZEOF		4
232412a8245SMichael S. Tsirkin 
233412a8245SMichael S. Tsirkin /* Power Management Registers */
234412a8245SMichael S. Tsirkin 
235412a8245SMichael S. Tsirkin #define PCI_PM_PMC		2	/* PM Capabilities Register */
236412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_VER_MASK	0x0007	/* Version */
237412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_PME_CLOCK	0x0008	/* PME clock required */
238412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_RESERVED    0x0010  /* Reserved field */
239412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_DSI		0x0020	/* Device specific initialization */
240412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_AUX_POWER	0x01C0	/* Auxiliary power support mask */
241412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_D1		0x0200	/* D1 power state support */
242412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_D2		0x0400	/* D2 power state support */
243412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_PME		0x0800	/* PME pin supported */
244412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_PME_MASK	0xF800	/* PME Mask of all supported states */
245412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_PME_D0	0x0800	/* PME# from D0 */
246412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_PME_D1	0x1000	/* PME# from D1 */
247412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_PME_D2	0x2000	/* PME# from D2 */
248412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_PME_D3	0x4000	/* PME# from D3 (hot) */
249412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_PME_D3cold	0x8000	/* PME# from D3 (cold) */
250412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_PME_SHIFT	11	/* Start of the PME Mask in PMC */
251412a8245SMichael S. Tsirkin #define PCI_PM_CTRL		4	/* PM control and status register */
252412a8245SMichael S. Tsirkin #define  PCI_PM_CTRL_STATE_MASK	0x0003	/* Current power state (D0 to D3) */
253412a8245SMichael S. Tsirkin #define  PCI_PM_CTRL_NO_SOFT_RESET	0x0008	/* No reset for D3hot->D0 */
254412a8245SMichael S. Tsirkin #define  PCI_PM_CTRL_PME_ENABLE	0x0100	/* PME pin enable */
255412a8245SMichael S. Tsirkin #define  PCI_PM_CTRL_DATA_SEL_MASK	0x1e00	/* Data select (??) */
256412a8245SMichael S. Tsirkin #define  PCI_PM_CTRL_DATA_SCALE_MASK	0x6000	/* Data scale (??) */
257412a8245SMichael S. Tsirkin #define  PCI_PM_CTRL_PME_STATUS	0x8000	/* PME pin status */
258412a8245SMichael S. Tsirkin #define PCI_PM_PPB_EXTENSIONS	6	/* PPB support extensions (??) */
259412a8245SMichael S. Tsirkin #define  PCI_PM_PPB_B2_B3	0x40	/* Stop clock when in D3hot (??) */
260412a8245SMichael S. Tsirkin #define  PCI_PM_BPCC_ENABLE	0x80	/* Bus power/clock control enable (??) */
261412a8245SMichael S. Tsirkin #define PCI_PM_DATA_REGISTER	7	/* (??) */
262412a8245SMichael S. Tsirkin #define PCI_PM_SIZEOF		8
263412a8245SMichael S. Tsirkin 
264412a8245SMichael S. Tsirkin /* AGP registers */
265412a8245SMichael S. Tsirkin 
266412a8245SMichael S. Tsirkin #define PCI_AGP_VERSION		2	/* BCD version number */
267412a8245SMichael S. Tsirkin #define PCI_AGP_RFU		3	/* Rest of capability flags */
268412a8245SMichael S. Tsirkin #define PCI_AGP_STATUS		4	/* Status register */
269412a8245SMichael S. Tsirkin #define  PCI_AGP_STATUS_RQ_MASK	0xff000000	/* Maximum number of requests - 1 */
270412a8245SMichael S. Tsirkin #define  PCI_AGP_STATUS_SBA	0x0200	/* Sideband addressing supported */
271412a8245SMichael S. Tsirkin #define  PCI_AGP_STATUS_64BIT	0x0020	/* 64-bit addressing supported */
272412a8245SMichael S. Tsirkin #define  PCI_AGP_STATUS_FW	0x0010	/* FW transfers supported */
273412a8245SMichael S. Tsirkin #define  PCI_AGP_STATUS_RATE4	0x0004	/* 4x transfer rate supported */
274412a8245SMichael S. Tsirkin #define  PCI_AGP_STATUS_RATE2	0x0002	/* 2x transfer rate supported */
275412a8245SMichael S. Tsirkin #define  PCI_AGP_STATUS_RATE1	0x0001	/* 1x transfer rate supported */
276412a8245SMichael S. Tsirkin #define PCI_AGP_COMMAND		8	/* Control register */
277412a8245SMichael S. Tsirkin #define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
278412a8245SMichael S. Tsirkin #define  PCI_AGP_COMMAND_SBA	0x0200	/* Sideband addressing enabled */
279412a8245SMichael S. Tsirkin #define  PCI_AGP_COMMAND_AGP	0x0100	/* Allow processing of AGP transactions */
280412a8245SMichael S. Tsirkin #define  PCI_AGP_COMMAND_64BIT	0x0020	/* Allow processing of 64-bit addresses */
281412a8245SMichael S. Tsirkin #define  PCI_AGP_COMMAND_FW	0x0010	/* Force FW transfers */
282412a8245SMichael S. Tsirkin #define  PCI_AGP_COMMAND_RATE4	0x0004	/* Use 4x rate */
283412a8245SMichael S. Tsirkin #define  PCI_AGP_COMMAND_RATE2	0x0002	/* Use 2x rate */
284412a8245SMichael S. Tsirkin #define  PCI_AGP_COMMAND_RATE1	0x0001	/* Use 1x rate */
285412a8245SMichael S. Tsirkin #define PCI_AGP_SIZEOF		12
286412a8245SMichael S. Tsirkin 
287412a8245SMichael S. Tsirkin /* Vital Product Data */
288412a8245SMichael S. Tsirkin 
289412a8245SMichael S. Tsirkin #define PCI_VPD_ADDR		2	/* Address to access (15 bits!) */
290412a8245SMichael S. Tsirkin #define  PCI_VPD_ADDR_MASK	0x7fff	/* Address mask */
291412a8245SMichael S. Tsirkin #define  PCI_VPD_ADDR_F		0x8000	/* Write 0, 1 indicates completion */
292412a8245SMichael S. Tsirkin #define PCI_VPD_DATA		4	/* 32-bits of data returned here */
293120758fbSPaolo Bonzini #define PCI_CAP_VPD_SIZEOF	8
294412a8245SMichael S. Tsirkin 
295412a8245SMichael S. Tsirkin /* Slot Identification */
296412a8245SMichael S. Tsirkin 
297412a8245SMichael S. Tsirkin #define PCI_SID_ESR		2	/* Expansion Slot Register */
298412a8245SMichael S. Tsirkin #define  PCI_SID_ESR_NSLOTS	0x1f	/* Number of expansion slots available */
299412a8245SMichael S. Tsirkin #define  PCI_SID_ESR_FIC	0x20	/* First In Chassis Flag */
300412a8245SMichael S. Tsirkin #define PCI_SID_CHASSIS_NR	3	/* Chassis Number */
301412a8245SMichael S. Tsirkin 
302412a8245SMichael S. Tsirkin /* Message Signalled Interrupts registers */
303412a8245SMichael S. Tsirkin 
304120758fbSPaolo Bonzini #define PCI_MSI_FLAGS		2	/* Message Control */
305120758fbSPaolo Bonzini #define  PCI_MSI_FLAGS_ENABLE	0x0001	/* MSI feature enabled */
306120758fbSPaolo Bonzini #define  PCI_MSI_FLAGS_QMASK	0x000e	/* Maximum queue size available */
307120758fbSPaolo Bonzini #define  PCI_MSI_FLAGS_QSIZE	0x0070	/* Message queue size configured */
308120758fbSPaolo Bonzini #define  PCI_MSI_FLAGS_64BIT	0x0080	/* 64-bit addresses allowed */
309120758fbSPaolo Bonzini #define  PCI_MSI_FLAGS_MASKBIT	0x0100	/* Per-vector masking capable */
310412a8245SMichael S. Tsirkin #define PCI_MSI_RFU		3	/* Rest of capability flags */
311412a8245SMichael S. Tsirkin #define PCI_MSI_ADDRESS_LO	4	/* Lower 32 bits */
312412a8245SMichael S. Tsirkin #define PCI_MSI_ADDRESS_HI	8	/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
313412a8245SMichael S. Tsirkin #define PCI_MSI_DATA_32		8	/* 16 bits of data for 32-bit devices */
314412a8245SMichael S. Tsirkin #define PCI_MSI_MASK_32		12	/* Mask bits register for 32-bit devices */
315120758fbSPaolo Bonzini #define PCI_MSI_PENDING_32	16	/* Pending intrs for 32-bit devices */
316412a8245SMichael S. Tsirkin #define PCI_MSI_DATA_64		12	/* 16 bits of data for 64-bit devices */
317412a8245SMichael S. Tsirkin #define PCI_MSI_MASK_64		16	/* Mask bits register for 64-bit devices */
318120758fbSPaolo Bonzini #define PCI_MSI_PENDING_64	20	/* Pending intrs for 64-bit devices */
319412a8245SMichael S. Tsirkin 
320412a8245SMichael S. Tsirkin /* MSI-X registers */
321120758fbSPaolo Bonzini #define PCI_MSIX_FLAGS		2	/* Message Control */
322120758fbSPaolo Bonzini #define  PCI_MSIX_FLAGS_QSIZE	0x07FF	/* Table size */
323120758fbSPaolo Bonzini #define  PCI_MSIX_FLAGS_MASKALL	0x4000	/* Mask all vectors for this function */
324120758fbSPaolo Bonzini #define  PCI_MSIX_FLAGS_ENABLE	0x8000	/* MSI-X enable */
325120758fbSPaolo Bonzini #define PCI_MSIX_TABLE		4	/* Table offset */
326120758fbSPaolo Bonzini #define  PCI_MSIX_TABLE_BIR	0x00000007 /* BAR index */
327120758fbSPaolo Bonzini #define  PCI_MSIX_TABLE_OFFSET	0xfffffff8 /* Offset into specified BAR */
328120758fbSPaolo Bonzini #define PCI_MSIX_PBA		8	/* Pending Bit Array offset */
329120758fbSPaolo Bonzini #define  PCI_MSIX_PBA_BIR	0x00000007 /* BAR index */
330120758fbSPaolo Bonzini #define  PCI_MSIX_PBA_OFFSET	0xfffffff8 /* Offset into specified BAR */
331120758fbSPaolo Bonzini #define PCI_MSIX_FLAGS_BIRMASK	PCI_MSIX_PBA_BIR /* deprecated */
332120758fbSPaolo Bonzini #define PCI_CAP_MSIX_SIZEOF	12	/* size of MSIX registers */
333412a8245SMichael S. Tsirkin 
334120758fbSPaolo Bonzini /* MSI-X Table entry format */
335412a8245SMichael S. Tsirkin #define PCI_MSIX_ENTRY_SIZE		16
336412a8245SMichael S. Tsirkin #define  PCI_MSIX_ENTRY_LOWER_ADDR	0
337412a8245SMichael S. Tsirkin #define  PCI_MSIX_ENTRY_UPPER_ADDR	4
338412a8245SMichael S. Tsirkin #define  PCI_MSIX_ENTRY_DATA		8
339412a8245SMichael S. Tsirkin #define  PCI_MSIX_ENTRY_VECTOR_CTRL	12
340412a8245SMichael S. Tsirkin #define   PCI_MSIX_ENTRY_CTRL_MASKBIT	1
341412a8245SMichael S. Tsirkin 
342412a8245SMichael S. Tsirkin /* CompactPCI Hotswap Register */
343412a8245SMichael S. Tsirkin 
344412a8245SMichael S. Tsirkin #define PCI_CHSWP_CSR		2	/* Control and Status Register */
345412a8245SMichael S. Tsirkin #define  PCI_CHSWP_DHA		0x01	/* Device Hiding Arm */
346412a8245SMichael S. Tsirkin #define  PCI_CHSWP_EIM		0x02	/* ENUM# Signal Mask */
347412a8245SMichael S. Tsirkin #define  PCI_CHSWP_PIE		0x04	/* Pending Insert or Extract */
348412a8245SMichael S. Tsirkin #define  PCI_CHSWP_LOO		0x08	/* LED On / Off */
349412a8245SMichael S. Tsirkin #define  PCI_CHSWP_PI		0x30	/* Programming Interface */
350412a8245SMichael S. Tsirkin #define  PCI_CHSWP_EXT		0x40	/* ENUM# status - extraction */
351412a8245SMichael S. Tsirkin #define  PCI_CHSWP_INS		0x80	/* ENUM# status - insertion */
352412a8245SMichael S. Tsirkin 
353412a8245SMichael S. Tsirkin /* PCI Advanced Feature registers */
354412a8245SMichael S. Tsirkin 
355412a8245SMichael S. Tsirkin #define PCI_AF_LENGTH		2
356412a8245SMichael S. Tsirkin #define PCI_AF_CAP		3
357412a8245SMichael S. Tsirkin #define  PCI_AF_CAP_TP		0x01
358412a8245SMichael S. Tsirkin #define  PCI_AF_CAP_FLR		0x02
359412a8245SMichael S. Tsirkin #define PCI_AF_CTRL		4
360412a8245SMichael S. Tsirkin #define  PCI_AF_CTRL_FLR	0x01
361412a8245SMichael S. Tsirkin #define PCI_AF_STATUS		5
362412a8245SMichael S. Tsirkin #define  PCI_AF_STATUS_TP	0x01
363120758fbSPaolo Bonzini #define PCI_CAP_AF_SIZEOF	6	/* size of AF registers */
364412a8245SMichael S. Tsirkin 
365fff02bc0SPaolo Bonzini /* PCI Enhanced Allocation registers */
366fff02bc0SPaolo Bonzini 
367fff02bc0SPaolo Bonzini #define PCI_EA_NUM_ENT		2	/* Number of Capability Entries */
368fff02bc0SPaolo Bonzini #define  PCI_EA_NUM_ENT_MASK	0x3f	/* Num Entries Mask */
369fff02bc0SPaolo Bonzini #define PCI_EA_FIRST_ENT	4	/* First EA Entry in List */
370fff02bc0SPaolo Bonzini #define PCI_EA_FIRST_ENT_BRIDGE	8	/* First EA Entry for Bridges */
371fff02bc0SPaolo Bonzini #define  PCI_EA_ES		0x00000007 /* Entry Size */
372fff02bc0SPaolo Bonzini #define  PCI_EA_BEI		0x000000f0 /* BAR Equivalent Indicator */
373fff02bc0SPaolo Bonzini /* 0-5 map to BARs 0-5 respectively */
374fff02bc0SPaolo Bonzini #define   PCI_EA_BEI_BAR0		0
375fff02bc0SPaolo Bonzini #define   PCI_EA_BEI_BAR5		5
376fff02bc0SPaolo Bonzini #define   PCI_EA_BEI_BRIDGE		6	/* Resource behind bridge */
377fff02bc0SPaolo Bonzini #define   PCI_EA_BEI_ENI		7	/* Equivalent Not Indicated */
378fff02bc0SPaolo Bonzini #define   PCI_EA_BEI_ROM		8	/* Expansion ROM */
379fff02bc0SPaolo Bonzini /* 9-14 map to VF BARs 0-5 respectively */
380fff02bc0SPaolo Bonzini #define   PCI_EA_BEI_VF_BAR0		9
381fff02bc0SPaolo Bonzini #define   PCI_EA_BEI_VF_BAR5		14
382fff02bc0SPaolo Bonzini #define   PCI_EA_BEI_RESERVED		15	/* Reserved - Treat like ENI */
383fff02bc0SPaolo Bonzini #define  PCI_EA_PP		0x0000ff00	/* Primary Properties */
384fff02bc0SPaolo Bonzini #define  PCI_EA_SP		0x00ff0000	/* Secondary Properties */
385fff02bc0SPaolo Bonzini #define   PCI_EA_P_MEM			0x00	/* Non-Prefetch Memory */
386fff02bc0SPaolo Bonzini #define   PCI_EA_P_MEM_PREFETCH		0x01	/* Prefetchable Memory */
387fff02bc0SPaolo Bonzini #define   PCI_EA_P_IO			0x02	/* I/O Space */
388fff02bc0SPaolo Bonzini #define   PCI_EA_P_VF_MEM_PREFETCH	0x03	/* VF Prefetchable Memory */
389fff02bc0SPaolo Bonzini #define   PCI_EA_P_VF_MEM		0x04	/* VF Non-Prefetch Memory */
390fff02bc0SPaolo Bonzini #define   PCI_EA_P_BRIDGE_MEM		0x05	/* Bridge Non-Prefetch Memory */
391fff02bc0SPaolo Bonzini #define   PCI_EA_P_BRIDGE_MEM_PREFETCH	0x06	/* Bridge Prefetchable Memory */
392fff02bc0SPaolo Bonzini #define   PCI_EA_P_BRIDGE_IO		0x07	/* Bridge I/O Space */
393fff02bc0SPaolo Bonzini /* 0x08-0xfc reserved */
394fff02bc0SPaolo Bonzini #define   PCI_EA_P_MEM_RESERVED		0xfd	/* Reserved Memory */
395fff02bc0SPaolo Bonzini #define   PCI_EA_P_IO_RESERVED		0xfe	/* Reserved I/O Space */
396fff02bc0SPaolo Bonzini #define   PCI_EA_P_UNAVAILABLE		0xff	/* Entry Unavailable */
397fff02bc0SPaolo Bonzini #define  PCI_EA_WRITABLE	0x40000000	/* Writable: 1 = RW, 0 = HwInit */
398fff02bc0SPaolo Bonzini #define  PCI_EA_ENABLE		0x80000000	/* Enable for this entry */
399fff02bc0SPaolo Bonzini #define PCI_EA_BASE		4		/* Base Address Offset */
400fff02bc0SPaolo Bonzini #define PCI_EA_MAX_OFFSET	8		/* MaxOffset (resource length) */
401fff02bc0SPaolo Bonzini /* bit 0 is reserved */
402fff02bc0SPaolo Bonzini #define  PCI_EA_IS_64		0x00000002	/* 64-bit field flag */
403fff02bc0SPaolo Bonzini #define  PCI_EA_FIELD_MASK	0xfffffffc	/* For Base & Max Offset */
404fff02bc0SPaolo Bonzini 
405120758fbSPaolo Bonzini /* PCI-X registers (Type 0 (non-bridge) devices) */
406412a8245SMichael S. Tsirkin 
407412a8245SMichael S. Tsirkin #define PCI_X_CMD		2	/* Modes & Features */
408412a8245SMichael S. Tsirkin #define  PCI_X_CMD_DPERR_E	0x0001	/* Data Parity Error Recovery Enable */
409412a8245SMichael S. Tsirkin #define  PCI_X_CMD_ERO		0x0002	/* Enable Relaxed Ordering */
410412a8245SMichael S. Tsirkin #define  PCI_X_CMD_READ_512	0x0000	/* 512 byte maximum read byte count */
411412a8245SMichael S. Tsirkin #define  PCI_X_CMD_READ_1K	0x0004	/* 1Kbyte maximum read byte count */
412412a8245SMichael S. Tsirkin #define  PCI_X_CMD_READ_2K	0x0008	/* 2Kbyte maximum read byte count */
413412a8245SMichael S. Tsirkin #define  PCI_X_CMD_READ_4K	0x000c	/* 4Kbyte maximum read byte count */
414412a8245SMichael S. Tsirkin #define  PCI_X_CMD_MAX_READ	0x000c	/* Max Memory Read Byte Count */
415412a8245SMichael S. Tsirkin 				/* Max # of outstanding split transactions */
416412a8245SMichael S. Tsirkin #define  PCI_X_CMD_SPLIT_1	0x0000	/* Max 1 */
417412a8245SMichael S. Tsirkin #define  PCI_X_CMD_SPLIT_2	0x0010	/* Max 2 */
418412a8245SMichael S. Tsirkin #define  PCI_X_CMD_SPLIT_3	0x0020	/* Max 3 */
419412a8245SMichael S. Tsirkin #define  PCI_X_CMD_SPLIT_4	0x0030	/* Max 4 */
420412a8245SMichael S. Tsirkin #define  PCI_X_CMD_SPLIT_8	0x0040	/* Max 8 */
421412a8245SMichael S. Tsirkin #define  PCI_X_CMD_SPLIT_12	0x0050	/* Max 12 */
422412a8245SMichael S. Tsirkin #define  PCI_X_CMD_SPLIT_16	0x0060	/* Max 16 */
423412a8245SMichael S. Tsirkin #define  PCI_X_CMD_SPLIT_32	0x0070	/* Max 32 */
424412a8245SMichael S. Tsirkin #define  PCI_X_CMD_MAX_SPLIT	0x0070	/* Max Outstanding Split Transactions */
425412a8245SMichael S. Tsirkin #define  PCI_X_CMD_VERSION(x)	(((x) >> 12) & 3) /* Version */
426412a8245SMichael S. Tsirkin #define PCI_X_STATUS		4	/* PCI-X capabilities */
427412a8245SMichael S. Tsirkin #define  PCI_X_STATUS_DEVFN	0x000000ff	/* A copy of devfn */
428412a8245SMichael S. Tsirkin #define  PCI_X_STATUS_BUS	0x0000ff00	/* A copy of bus nr */
429412a8245SMichael S. Tsirkin #define  PCI_X_STATUS_64BIT	0x00010000	/* 64-bit device */
430412a8245SMichael S. Tsirkin #define  PCI_X_STATUS_133MHZ	0x00020000	/* 133 MHz capable */
431412a8245SMichael S. Tsirkin #define  PCI_X_STATUS_SPL_DISC	0x00040000	/* Split Completion Discarded */
432412a8245SMichael S. Tsirkin #define  PCI_X_STATUS_UNX_SPL	0x00080000	/* Unexpected Split Completion */
433412a8245SMichael S. Tsirkin #define  PCI_X_STATUS_COMPLEX	0x00100000	/* Device Complexity */
434412a8245SMichael S. Tsirkin #define  PCI_X_STATUS_MAX_READ	0x00600000	/* Designed Max Memory Read Count */
435412a8245SMichael S. Tsirkin #define  PCI_X_STATUS_MAX_SPLIT	0x03800000	/* Designed Max Outstanding Split Transactions */
436412a8245SMichael S. Tsirkin #define  PCI_X_STATUS_MAX_CUM	0x1c000000	/* Designed Max Cumulative Read Size */
437412a8245SMichael S. Tsirkin #define  PCI_X_STATUS_SPL_ERR	0x20000000	/* Rcvd Split Completion Error Msg */
438412a8245SMichael S. Tsirkin #define  PCI_X_STATUS_266MHZ	0x40000000	/* 266 MHz capable */
439412a8245SMichael S. Tsirkin #define  PCI_X_STATUS_533MHZ	0x80000000	/* 533 MHz capable */
440120758fbSPaolo Bonzini #define PCI_X_ECC_CSR		8	/* ECC control and status */
441120758fbSPaolo Bonzini #define PCI_CAP_PCIX_SIZEOF_V0	8	/* size of registers for Version 0 */
442120758fbSPaolo Bonzini #define PCI_CAP_PCIX_SIZEOF_V1	24	/* size for Version 1 */
443120758fbSPaolo Bonzini #define PCI_CAP_PCIX_SIZEOF_V2	PCI_CAP_PCIX_SIZEOF_V1	/* Same for v2 */
444120758fbSPaolo Bonzini 
445120758fbSPaolo Bonzini /* PCI-X registers (Type 1 (bridge) devices) */
446120758fbSPaolo Bonzini 
447120758fbSPaolo Bonzini #define PCI_X_BRIDGE_SSTATUS	2	/* Secondary Status */
448120758fbSPaolo Bonzini #define  PCI_X_SSTATUS_64BIT	0x0001	/* Secondary AD interface is 64 bits */
449120758fbSPaolo Bonzini #define  PCI_X_SSTATUS_133MHZ	0x0002	/* 133 MHz capable */
450120758fbSPaolo Bonzini #define  PCI_X_SSTATUS_FREQ	0x03c0	/* Secondary Bus Mode and Frequency */
451120758fbSPaolo Bonzini #define  PCI_X_SSTATUS_VERS	0x3000	/* PCI-X Capability Version */
452120758fbSPaolo Bonzini #define  PCI_X_SSTATUS_V1	0x1000	/* Mode 2, not Mode 1 */
453120758fbSPaolo Bonzini #define  PCI_X_SSTATUS_V2	0x2000	/* Mode 1 or Modes 1 and 2 */
454120758fbSPaolo Bonzini #define  PCI_X_SSTATUS_266MHZ	0x4000	/* 266 MHz capable */
455120758fbSPaolo Bonzini #define  PCI_X_SSTATUS_533MHZ	0x8000	/* 533 MHz capable */
456120758fbSPaolo Bonzini #define PCI_X_BRIDGE_STATUS	4	/* Bridge Status */
457412a8245SMichael S. Tsirkin 
458412a8245SMichael S. Tsirkin /* PCI Bridge Subsystem ID registers */
459412a8245SMichael S. Tsirkin 
460120758fbSPaolo Bonzini #define PCI_SSVID_VENDOR_ID     4	/* PCI Bridge subsystem vendor ID */
461120758fbSPaolo Bonzini #define PCI_SSVID_DEVICE_ID     6	/* PCI Bridge subsystem device ID */
462412a8245SMichael S. Tsirkin 
463412a8245SMichael S. Tsirkin /* PCI Express capability registers */
464412a8245SMichael S. Tsirkin 
465412a8245SMichael S. Tsirkin #define PCI_EXP_FLAGS		2	/* Capabilities register */
466412a8245SMichael S. Tsirkin #define PCI_EXP_FLAGS_VERS	0x000f	/* Capability version */
467412a8245SMichael S. Tsirkin #define PCI_EXP_FLAGS_TYPE	0x00f0	/* Device/Port type */
468412a8245SMichael S. Tsirkin #define  PCI_EXP_TYPE_ENDPOINT	0x0	/* Express Endpoint */
469412a8245SMichael S. Tsirkin #define  PCI_EXP_TYPE_LEG_END	0x1	/* Legacy Endpoint */
470412a8245SMichael S. Tsirkin #define  PCI_EXP_TYPE_ROOT_PORT 0x4	/* Root Port */
471412a8245SMichael S. Tsirkin #define  PCI_EXP_TYPE_UPSTREAM	0x5	/* Upstream Port */
472412a8245SMichael S. Tsirkin #define  PCI_EXP_TYPE_DOWNSTREAM 0x6	/* Downstream Port */
473120758fbSPaolo Bonzini #define  PCI_EXP_TYPE_PCI_BRIDGE 0x7	/* PCIe to PCI/PCI-X Bridge */
474120758fbSPaolo Bonzini #define  PCI_EXP_TYPE_PCIE_BRIDGE 0x8	/* PCI/PCI-X to PCIe Bridge */
475412a8245SMichael S. Tsirkin #define  PCI_EXP_TYPE_RC_END	0x9	/* Root Complex Integrated Endpoint */
476412a8245SMichael S. Tsirkin #define  PCI_EXP_TYPE_RC_EC	0xa	/* Root Complex Event Collector */
477412a8245SMichael S. Tsirkin #define PCI_EXP_FLAGS_SLOT	0x0100	/* Slot implemented */
478412a8245SMichael S. Tsirkin #define PCI_EXP_FLAGS_IRQ	0x3e00	/* Interrupt message number */
479412a8245SMichael S. Tsirkin #define PCI_EXP_DEVCAP		4	/* Device capabilities */
480120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP_PAYLOAD	0x00000007 /* Max_Payload_Size */
481120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP_PHANTOM	0x00000018 /* Phantom functions */
482120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP_EXT_TAG	0x00000020 /* Extended tags */
483120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP_L0S	0x000001c0 /* L0s Acceptable Latency */
484120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP_L1	0x00000e00 /* L1 Acceptable Latency */
485120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP_ATN_BUT	0x00001000 /* Attention Button Present */
486120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP_ATN_IND	0x00002000 /* Attention Indicator Present */
487120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP_PWR_IND	0x00004000 /* Power Indicator Present */
488120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP_RBER	0x00008000 /* Role-Based Error Reporting */
489120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP_PWR_VAL	0x03fc0000 /* Slot Power Limit Value */
490120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP_PWR_SCL	0x0c000000 /* Slot Power Limit Scale */
491412a8245SMichael S. Tsirkin #define  PCI_EXP_DEVCAP_FLR     0x10000000 /* Function Level Reset */
492412a8245SMichael S. Tsirkin #define PCI_EXP_DEVCTL		8	/* Device Control */
493412a8245SMichael S. Tsirkin #define  PCI_EXP_DEVCTL_CERE	0x0001	/* Correctable Error Reporting En. */
494412a8245SMichael S. Tsirkin #define  PCI_EXP_DEVCTL_NFERE	0x0002	/* Non-Fatal Error Reporting Enable */
495412a8245SMichael S. Tsirkin #define  PCI_EXP_DEVCTL_FERE	0x0004	/* Fatal Error Reporting Enable */
496412a8245SMichael S. Tsirkin #define  PCI_EXP_DEVCTL_URRE	0x0008	/* Unsupported Request Reporting En. */
497412a8245SMichael S. Tsirkin #define  PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
498412a8245SMichael S. Tsirkin #define  PCI_EXP_DEVCTL_PAYLOAD	0x00e0	/* Max_Payload_Size */
499412a8245SMichael S. Tsirkin #define  PCI_EXP_DEVCTL_EXT_TAG	0x0100	/* Extended Tag Field Enable */
500412a8245SMichael S. Tsirkin #define  PCI_EXP_DEVCTL_PHANTOM	0x0200	/* Phantom Functions Enable */
501412a8245SMichael S. Tsirkin #define  PCI_EXP_DEVCTL_AUX_PME	0x0400	/* Auxiliary Power PM Enable */
502412a8245SMichael S. Tsirkin #define  PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800  /* Enable No Snoop */
503412a8245SMichael S. Tsirkin #define  PCI_EXP_DEVCTL_READRQ	0x7000	/* Max_Read_Request_Size */
504120758fbSPaolo Bonzini #define  PCI_EXP_DEVCTL_READRQ_128B  0x0000 /* 128 Bytes */
505120758fbSPaolo Bonzini #define  PCI_EXP_DEVCTL_READRQ_256B  0x1000 /* 256 Bytes */
506120758fbSPaolo Bonzini #define  PCI_EXP_DEVCTL_READRQ_512B  0x2000 /* 512 Bytes */
507120758fbSPaolo Bonzini #define  PCI_EXP_DEVCTL_READRQ_1024B 0x3000 /* 1024 Bytes */
508412a8245SMichael S. Tsirkin #define  PCI_EXP_DEVCTL_BCR_FLR 0x8000  /* Bridge Configuration Retry / FLR */
509412a8245SMichael S. Tsirkin #define PCI_EXP_DEVSTA		10	/* Device Status */
510120758fbSPaolo Bonzini #define  PCI_EXP_DEVSTA_CED	0x0001	/* Correctable Error Detected */
511120758fbSPaolo Bonzini #define  PCI_EXP_DEVSTA_NFED	0x0002	/* Non-Fatal Error Detected */
512120758fbSPaolo Bonzini #define  PCI_EXP_DEVSTA_FED	0x0004	/* Fatal Error Detected */
513120758fbSPaolo Bonzini #define  PCI_EXP_DEVSTA_URD	0x0008	/* Unsupported Request Detected */
514120758fbSPaolo Bonzini #define  PCI_EXP_DEVSTA_AUXPD	0x0010	/* AUX Power Detected */
515120758fbSPaolo Bonzini #define  PCI_EXP_DEVSTA_TRPND	0x0020	/* Transactions Pending */
516*d4083f50SAlexey Perevalov #define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V1	12	/* v1 endpoints without link end here */
517412a8245SMichael S. Tsirkin #define PCI_EXP_LNKCAP		12	/* Link Capabilities */
518412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCAP_SLS	0x0000000f /* Supported Link Speeds */
519120758fbSPaolo Bonzini #define  PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */
520120758fbSPaolo Bonzini #define  PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
5213272f0e2SChristian Borntraeger #define  PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
522412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCAP_MLW	0x000003f0 /* Maximum Link Width */
523412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCAP_ASPMS	0x00000c00 /* ASPM Support */
524412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCAP_L0SEL	0x00007000 /* L0s Exit Latency */
525412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCAP_L1EL	0x00038000 /* L1 Exit Latency */
526120758fbSPaolo Bonzini #define  PCI_EXP_LNKCAP_CLKPM	0x00040000 /* Clock Power Management */
527412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCAP_SDERC	0x00080000 /* Surprise Down Error Reporting Capable */
528412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCAP_DLLLARC	0x00100000 /* Data Link Layer Link Active Reporting Capable */
529412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCAP_LBNC	0x00200000 /* Link Bandwidth Notification Capability */
530412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCAP_PN	0xff000000 /* Port Number */
531412a8245SMichael S. Tsirkin #define PCI_EXP_LNKCTL		16	/* Link Control */
532412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCTL_ASPMC	0x0003	/* ASPM Control */
533120758fbSPaolo Bonzini #define  PCI_EXP_LNKCTL_ASPM_L0S 0x0001	/* L0s Enable */
534120758fbSPaolo Bonzini #define  PCI_EXP_LNKCTL_ASPM_L1  0x0002	/* L1 Enable */
535412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCTL_RCB	0x0008	/* Read Completion Boundary */
536412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCTL_LD	0x0010	/* Link Disable */
537412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCTL_RL	0x0020	/* Retrain Link */
538412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCTL_CCC	0x0040	/* Common Clock Configuration */
539412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCTL_ES	0x0080	/* Extended Synch */
540120758fbSPaolo Bonzini #define  PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 /* Enable clkreq */
541412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCTL_HAWD	0x0200	/* Hardware Autonomous Width Disable */
542412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCTL_LBMIE	0x0400	/* Link Bandwidth Management Interrupt Enable */
543120758fbSPaolo Bonzini #define  PCI_EXP_LNKCTL_LABIE	0x0800	/* Link Autonomous Bandwidth Interrupt Enable */
544412a8245SMichael S. Tsirkin #define PCI_EXP_LNKSTA		18	/* Link Status */
545412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKSTA_CLS	0x000f	/* Current Link Speed */
546120758fbSPaolo Bonzini #define  PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
547120758fbSPaolo Bonzini #define  PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
548120758fbSPaolo Bonzini #define  PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
549120758fbSPaolo Bonzini #define  PCI_EXP_LNKSTA_NLW	0x03f0	/* Negotiated Link Width */
550120758fbSPaolo Bonzini #define  PCI_EXP_LNKSTA_NLW_X1	0x0010	/* Current Link Width x1 */
551120758fbSPaolo Bonzini #define  PCI_EXP_LNKSTA_NLW_X2	0x0020	/* Current Link Width x2 */
552120758fbSPaolo Bonzini #define  PCI_EXP_LNKSTA_NLW_X4	0x0040	/* Current Link Width x4 */
553120758fbSPaolo Bonzini #define  PCI_EXP_LNKSTA_NLW_X8	0x0080	/* Current Link Width x8 */
554412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKSTA_NLW_SHIFT 4	/* start of NLW mask in link status */
555412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKSTA_LT	0x0800	/* Link Training */
556412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKSTA_SLC	0x1000	/* Slot Clock Configuration */
557412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKSTA_DLLLA	0x2000	/* Data Link Layer Link Active */
558412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKSTA_LBMS	0x4000	/* Link Bandwidth Management Status */
559412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKSTA_LABS	0x8000	/* Link Autonomous Bandwidth Status */
560*d4083f50SAlexey Perevalov #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1	20	/* v1 endpoints with link end here */
561412a8245SMichael S. Tsirkin #define PCI_EXP_SLTCAP		20	/* Slot Capabilities */
562412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCAP_ABP	0x00000001 /* Attention Button Present */
563412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCAP_PCP	0x00000002 /* Power Controller Present */
564412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCAP_MRLSP	0x00000004 /* MRL Sensor Present */
565412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCAP_AIP	0x00000008 /* Attention Indicator Present */
566412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCAP_PIP	0x00000010 /* Power Indicator Present */
567412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCAP_HPS	0x00000020 /* Hot-Plug Surprise */
568412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCAP_HPC	0x00000040 /* Hot-Plug Capable */
569412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCAP_SPLV	0x00007f80 /* Slot Power Limit Value */
570412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCAP_SPLS	0x00018000 /* Slot Power Limit Scale */
571412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCAP_EIP	0x00020000 /* Electromechanical Interlock Present */
572412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCAP_NCCS	0x00040000 /* No Command Completed Support */
573412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCAP_PSN	0xfff80000 /* Physical Slot Number */
574412a8245SMichael S. Tsirkin #define PCI_EXP_SLTCTL		24	/* Slot Control */
575412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCTL_ABPE	0x0001	/* Attention Button Pressed Enable */
576412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCTL_PFDE	0x0002	/* Power Fault Detected Enable */
577412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCTL_MRLSCE	0x0004	/* MRL Sensor Changed Enable */
578412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCTL_PDCE	0x0008	/* Presence Detect Changed Enable */
579412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCTL_CCIE	0x0010	/* Command Completed Interrupt Enable */
580412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCTL_HPIE	0x0020	/* Hot-Plug Interrupt Enable */
581412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCTL_AIC	0x00c0	/* Attention Indicator Control */
582120758fbSPaolo Bonzini #define  PCI_EXP_SLTCTL_ATTN_IND_ON    0x0040 /* Attention Indicator on */
583120758fbSPaolo Bonzini #define  PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 /* Attention Indicator blinking */
584120758fbSPaolo Bonzini #define  PCI_EXP_SLTCTL_ATTN_IND_OFF   0x00c0 /* Attention Indicator off */
585412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCTL_PIC	0x0300	/* Power Indicator Control */
586120758fbSPaolo Bonzini #define  PCI_EXP_SLTCTL_PWR_IND_ON     0x0100 /* Power Indicator on */
587120758fbSPaolo Bonzini #define  PCI_EXP_SLTCTL_PWR_IND_BLINK  0x0200 /* Power Indicator blinking */
588120758fbSPaolo Bonzini #define  PCI_EXP_SLTCTL_PWR_IND_OFF    0x0300 /* Power Indicator off */
589412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCTL_PCC	0x0400	/* Power Controller Control */
590120758fbSPaolo Bonzini #define  PCI_EXP_SLTCTL_PWR_ON         0x0000 /* Power On */
591120758fbSPaolo Bonzini #define  PCI_EXP_SLTCTL_PWR_OFF        0x0400 /* Power Off */
592412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCTL_EIC	0x0800	/* Electromechanical Interlock Control */
593412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCTL_DLLSCE	0x1000	/* Data Link Layer State Changed Enable */
594412a8245SMichael S. Tsirkin #define PCI_EXP_SLTSTA		26	/* Slot Status */
595412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTSTA_ABP	0x0001	/* Attention Button Pressed */
596412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTSTA_PFD	0x0002	/* Power Fault Detected */
597412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTSTA_MRLSC	0x0004	/* MRL Sensor Changed */
598412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTSTA_PDC	0x0008	/* Presence Detect Changed */
599412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTSTA_CC	0x0010	/* Command Completed */
600412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTSTA_MRLSS	0x0020	/* MRL Sensor State */
601412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTSTA_PDS	0x0040	/* Presence Detect State */
602412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTSTA_EIS	0x0080	/* Electromechanical Interlock Status */
603412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTSTA_DLLSC	0x0100	/* Data Link Layer State Changed */
604412a8245SMichael S. Tsirkin #define PCI_EXP_RTCTL		28	/* Root Control */
605120758fbSPaolo Bonzini #define  PCI_EXP_RTCTL_SECEE	0x0001	/* System Error on Correctable Error */
606120758fbSPaolo Bonzini #define  PCI_EXP_RTCTL_SENFEE	0x0002	/* System Error on Non-Fatal Error */
607120758fbSPaolo Bonzini #define  PCI_EXP_RTCTL_SEFEE	0x0004	/* System Error on Fatal Error */
608120758fbSPaolo Bonzini #define  PCI_EXP_RTCTL_PMEIE	0x0008	/* PME Interrupt Enable */
609120758fbSPaolo Bonzini #define  PCI_EXP_RTCTL_CRSSVE	0x0010	/* CRS Software Visibility Enable */
610412a8245SMichael S. Tsirkin #define PCI_EXP_RTCAP		30	/* Root Capabilities */
611120758fbSPaolo Bonzini #define  PCI_EXP_RTCAP_CRSVIS	0x0001	/* CRS Software Visibility capability */
612412a8245SMichael S. Tsirkin #define PCI_EXP_RTSTA		32	/* Root Status */
613120758fbSPaolo Bonzini #define PCI_EXP_RTSTA_PME	0x00010000 /* PME status */
614120758fbSPaolo Bonzini #define PCI_EXP_RTSTA_PENDING	0x00020000 /* PME pending */
615120758fbSPaolo Bonzini /*
616120758fbSPaolo Bonzini  * The Device Capabilities 2, Device Status 2, Device Control 2,
617120758fbSPaolo Bonzini  * Link Capabilities 2, Link Status 2, Link Control 2,
618120758fbSPaolo Bonzini  * Slot Capabilities 2, Slot Status 2, and Slot Control 2 registers
619120758fbSPaolo Bonzini  * are only present on devices with PCIe Capability version 2.
620120758fbSPaolo Bonzini  * Use pcie_capability_read_word() and similar interfaces to use them
621120758fbSPaolo Bonzini  * safely.
622120758fbSPaolo Bonzini  */
623412a8245SMichael S. Tsirkin #define PCI_EXP_DEVCAP2		36	/* Device Capabilities 2 */
624120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP2_ARI		0x00000020 /* Alternative Routing-ID */
625bc204035SMarcelo Tosatti #define  PCI_EXP_DEVCAP2_ATOMIC_ROUTE	0x00000040 /* Atomic Op routing */
626bc204035SMarcelo Tosatti #define PCI_EXP_DEVCAP2_ATOMIC_COMP64	0x00000100 /* Atomic 64-bit compare */
627120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP2_LTR		0x00000800 /* Latency tolerance reporting */
628120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP2_OBFF_MASK	0x000c0000 /* OBFF support mechanism */
629120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP2_OBFF_MSG	0x00040000 /* New message signaling */
630120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP2_OBFF_WAKE	0x00080000 /* Re-use WAKE# for OBFF */
631412a8245SMichael S. Tsirkin #define PCI_EXP_DEVCTL2		40	/* Device Control 2 */
632120758fbSPaolo Bonzini #define  PCI_EXP_DEVCTL2_COMP_TIMEOUT	0x000f	/* Completion Timeout Value */
633120758fbSPaolo Bonzini #define  PCI_EXP_DEVCTL2_ARI		0x0020	/* Alternative Routing-ID */
634bc204035SMarcelo Tosatti #define PCI_EXP_DEVCTL2_ATOMIC_REQ	0x0040	/* Set Atomic requests */
63574c98e20SCornelia Huck #define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */
636120758fbSPaolo Bonzini #define  PCI_EXP_DEVCTL2_IDO_REQ_EN	0x0100	/* Allow IDO for requests */
637120758fbSPaolo Bonzini #define  PCI_EXP_DEVCTL2_IDO_CMP_EN	0x0200	/* Allow IDO for completions */
638120758fbSPaolo Bonzini #define  PCI_EXP_DEVCTL2_LTR_EN		0x0400	/* Enable LTR mechanism */
639120758fbSPaolo Bonzini #define  PCI_EXP_DEVCTL2_OBFF_MSGA_EN	0x2000	/* Enable OBFF Message type A */
640120758fbSPaolo Bonzini #define  PCI_EXP_DEVCTL2_OBFF_MSGB_EN	0x4000	/* Enable OBFF Message type B */
641120758fbSPaolo Bonzini #define  PCI_EXP_DEVCTL2_OBFF_WAKE_EN	0x6000	/* OBFF using WAKE# signaling */
642120758fbSPaolo Bonzini #define PCI_EXP_DEVSTA2		42	/* Device Status 2 */
643*d4083f50SAlexey Perevalov #define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2	44	/* v2 endpoints without link end here */
644120758fbSPaolo Bonzini #define PCI_EXP_LNKCAP2		44	/* Link Capabilities 2 */
645120758fbSPaolo Bonzini #define  PCI_EXP_LNKCAP2_SLS_2_5GB	0x00000002 /* Supported Speed 2.5GT/s */
646120758fbSPaolo Bonzini #define  PCI_EXP_LNKCAP2_SLS_5_0GB	0x00000004 /* Supported Speed 5.0GT/s */
647120758fbSPaolo Bonzini #define  PCI_EXP_LNKCAP2_SLS_8_0GB	0x00000008 /* Supported Speed 8.0GT/s */
648120758fbSPaolo Bonzini #define  PCI_EXP_LNKCAP2_CROSSLINK	0x00000100 /* Crosslink supported */
649412a8245SMichael S. Tsirkin #define PCI_EXP_LNKCTL2		48	/* Link Control 2 */
650120758fbSPaolo Bonzini #define PCI_EXP_LNKSTA2		50	/* Link Status 2 */
651*d4083f50SAlexey Perevalov #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2	52	/* v2 endpoints with link end here */
652120758fbSPaolo Bonzini #define PCI_EXP_SLTCAP2		52	/* Slot Capabilities 2 */
653412a8245SMichael S. Tsirkin #define PCI_EXP_SLTCTL2		56	/* Slot Control 2 */
654120758fbSPaolo Bonzini #define PCI_EXP_SLTSTA2		58	/* Slot Status 2 */
655412a8245SMichael S. Tsirkin 
656412a8245SMichael S. Tsirkin /* Extended Capabilities (PCI-X 2.0 and Express) */
657412a8245SMichael S. Tsirkin #define PCI_EXT_CAP_ID(header)		(header & 0x0000ffff)
658412a8245SMichael S. Tsirkin #define PCI_EXT_CAP_VER(header)		((header >> 16) & 0xf)
659412a8245SMichael S. Tsirkin #define PCI_EXT_CAP_NEXT(header)	((header >> 20) & 0xffc)
660412a8245SMichael S. Tsirkin 
661120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_ERR	0x01	/* Advanced Error Reporting */
662120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_VC	0x02	/* Virtual Channel Capability */
663120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_DSN	0x03	/* Device Serial Number */
664120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_PWR	0x04	/* Power Budgeting */
665120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_RCLD	0x05	/* Root Complex Link Declaration */
666120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_RCILC	0x06	/* Root Complex Internal Link Control */
667120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_RCEC	0x07	/* Root Complex Event Collector */
668120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_MFVC	0x08	/* Multi-Function VC Capability */
669120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_VC9	0x09	/* same as _VC */
670120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_RCRB	0x0A	/* Root Complex RB? */
671120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_VNDR	0x0B	/* Vendor-Specific */
672120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_CAC	0x0C	/* Config Access - obsolete */
673120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_ACS	0x0D	/* Access Control Services */
674120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_ARI	0x0E	/* Alternate Routing ID */
675120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_ATS	0x0F	/* Address Translation Services */
676120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_SRIOV	0x10	/* Single Root I/O Virtualization */
677120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_MRIOV	0x11	/* Multi Root I/O Virtualization */
678120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_MCAST	0x12	/* Multicast */
679120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_PRI	0x13	/* Page Request Interface */
680120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_AMD_XXX	0x14	/* Reserved for AMD */
681120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_REBAR	0x15	/* Resizable BAR */
682120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_DPA	0x16	/* Dynamic Power Allocation */
683120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_TPH	0x17	/* TPH Requester */
684120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_LTR	0x18	/* Latency Tolerance Reporting */
685120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_SECPCI	0x19	/* Secondary PCIe Capability */
686120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_PMUX	0x1A	/* Protocol Multiplexing */
687120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_PASID	0x1B	/* Process Address Space ID */
688ff804f15SCornelia Huck #define PCI_EXT_CAP_ID_DPC	0x1D	/* Downstream Port Containment */
6893a5eb5b4SPaolo Bonzini #define PCI_EXT_CAP_ID_L1SS	0x1E	/* L1 PM Substates */
690bc204035SMarcelo Tosatti #define PCI_EXT_CAP_ID_PTM	0x1F	/* Precision Time Measurement */
691bc204035SMarcelo Tosatti #define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_PTM
692120758fbSPaolo Bonzini 
693120758fbSPaolo Bonzini #define PCI_EXT_CAP_DSN_SIZEOF	12
694120758fbSPaolo Bonzini #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
695412a8245SMichael S. Tsirkin 
696412a8245SMichael S. Tsirkin /* Advanced Error Reporting */
697412a8245SMichael S. Tsirkin #define PCI_ERR_UNCOR_STATUS	4	/* Uncorrectable Error Status */
698120758fbSPaolo Bonzini #define  PCI_ERR_UNC_UND	0x00000001	/* Undefined */
699412a8245SMichael S. Tsirkin #define  PCI_ERR_UNC_DLP	0x00000010	/* Data Link Protocol */
700120758fbSPaolo Bonzini #define  PCI_ERR_UNC_SURPDN	0x00000020	/* Surprise Down */
701412a8245SMichael S. Tsirkin #define  PCI_ERR_UNC_POISON_TLP	0x00001000	/* Poisoned TLP */
702412a8245SMichael S. Tsirkin #define  PCI_ERR_UNC_FCP	0x00002000	/* Flow Control Protocol */
703412a8245SMichael S. Tsirkin #define  PCI_ERR_UNC_COMP_TIME	0x00004000	/* Completion Timeout */
704412a8245SMichael S. Tsirkin #define  PCI_ERR_UNC_COMP_ABORT	0x00008000	/* Completer Abort */
705412a8245SMichael S. Tsirkin #define  PCI_ERR_UNC_UNX_COMP	0x00010000	/* Unexpected Completion */
706412a8245SMichael S. Tsirkin #define  PCI_ERR_UNC_RX_OVER	0x00020000	/* Receiver Overflow */
707412a8245SMichael S. Tsirkin #define  PCI_ERR_UNC_MALF_TLP	0x00040000	/* Malformed TLP */
708412a8245SMichael S. Tsirkin #define  PCI_ERR_UNC_ECRC	0x00080000	/* ECRC Error Status */
709412a8245SMichael S. Tsirkin #define  PCI_ERR_UNC_UNSUP	0x00100000	/* Unsupported Request */
710120758fbSPaolo Bonzini #define  PCI_ERR_UNC_ACSV	0x00200000	/* ACS Violation */
711120758fbSPaolo Bonzini #define  PCI_ERR_UNC_INTN	0x00400000	/* internal error */
712120758fbSPaolo Bonzini #define  PCI_ERR_UNC_MCBTLP	0x00800000	/* MC blocked TLP */
713120758fbSPaolo Bonzini #define  PCI_ERR_UNC_ATOMEG	0x01000000	/* Atomic egress blocked */
714120758fbSPaolo Bonzini #define  PCI_ERR_UNC_TLPPRE	0x02000000	/* TLP prefix blocked */
715412a8245SMichael S. Tsirkin #define PCI_ERR_UNCOR_MASK	8	/* Uncorrectable Error Mask */
716412a8245SMichael S. Tsirkin 	/* Same bits as above */
717412a8245SMichael S. Tsirkin #define PCI_ERR_UNCOR_SEVER	12	/* Uncorrectable Error Severity */
718412a8245SMichael S. Tsirkin 	/* Same bits as above */
719412a8245SMichael S. Tsirkin #define PCI_ERR_COR_STATUS	16	/* Correctable Error Status */
720412a8245SMichael S. Tsirkin #define  PCI_ERR_COR_RCVR	0x00000001	/* Receiver Error Status */
721412a8245SMichael S. Tsirkin #define  PCI_ERR_COR_BAD_TLP	0x00000040	/* Bad TLP Status */
722412a8245SMichael S. Tsirkin #define  PCI_ERR_COR_BAD_DLLP	0x00000080	/* Bad DLLP Status */
723412a8245SMichael S. Tsirkin #define  PCI_ERR_COR_REP_ROLL	0x00000100	/* REPLAY_NUM Rollover */
724412a8245SMichael S. Tsirkin #define  PCI_ERR_COR_REP_TIMER	0x00001000	/* Replay Timer Timeout */
725120758fbSPaolo Bonzini #define  PCI_ERR_COR_ADV_NFAT	0x00002000	/* Advisory Non-Fatal */
726120758fbSPaolo Bonzini #define  PCI_ERR_COR_INTERNAL	0x00004000	/* Corrected Internal */
727120758fbSPaolo Bonzini #define  PCI_ERR_COR_LOG_OVER	0x00008000	/* Header Log Overflow */
728412a8245SMichael S. Tsirkin #define PCI_ERR_COR_MASK	20	/* Correctable Error Mask */
729412a8245SMichael S. Tsirkin 	/* Same bits as above */
730412a8245SMichael S. Tsirkin #define PCI_ERR_CAP		24	/* Advanced Error Capabilities */
731412a8245SMichael S. Tsirkin #define  PCI_ERR_CAP_FEP(x)	((x) & 31)	/* First Error Pointer */
732412a8245SMichael S. Tsirkin #define  PCI_ERR_CAP_ECRC_GENC	0x00000020	/* ECRC Generation Capable */
733412a8245SMichael S. Tsirkin #define  PCI_ERR_CAP_ECRC_GENE	0x00000040	/* ECRC Generation Enable */
734412a8245SMichael S. Tsirkin #define  PCI_ERR_CAP_ECRC_CHKC	0x00000080	/* ECRC Check Capable */
735412a8245SMichael S. Tsirkin #define  PCI_ERR_CAP_ECRC_CHKE	0x00000100	/* ECRC Check Enable */
736412a8245SMichael S. Tsirkin #define PCI_ERR_HEADER_LOG	28	/* Header Log Register (16 bytes) */
737412a8245SMichael S. Tsirkin #define PCI_ERR_ROOT_COMMAND	44	/* Root Error Command */
738*d4083f50SAlexey Perevalov #define PCI_ERR_ROOT_CMD_COR_EN		0x00000001 /* Correctable Err Reporting Enable */
739*d4083f50SAlexey Perevalov #define PCI_ERR_ROOT_CMD_NONFATAL_EN	0x00000002 /* Non-Fatal Err Reporting Enable */
740*d4083f50SAlexey Perevalov #define PCI_ERR_ROOT_CMD_FATAL_EN	0x00000004 /* Fatal Err Reporting Enable */
741412a8245SMichael S. Tsirkin #define PCI_ERR_ROOT_STATUS	48
742412a8245SMichael S. Tsirkin #define PCI_ERR_ROOT_COR_RCV		0x00000001 /* ERR_COR Received */
743*d4083f50SAlexey Perevalov #define PCI_ERR_ROOT_MULTI_COR_RCV	0x00000002 /* Multiple ERR_COR */
744*d4083f50SAlexey Perevalov #define PCI_ERR_ROOT_UNCOR_RCV		0x00000004 /* ERR_FATAL/NONFATAL */
745*d4083f50SAlexey Perevalov #define PCI_ERR_ROOT_MULTI_UNCOR_RCV	0x00000008 /* Multiple FATAL/NONFATAL */
746*d4083f50SAlexey Perevalov #define PCI_ERR_ROOT_FIRST_FATAL	0x00000010 /* First UNC is Fatal */
747412a8245SMichael S. Tsirkin #define PCI_ERR_ROOT_NONFATAL_RCV	0x00000020 /* Non-Fatal Received */
748412a8245SMichael S. Tsirkin #define PCI_ERR_ROOT_FATAL_RCV		0x00000040 /* Fatal Received */
749412a8245SMichael S. Tsirkin #define PCI_ERR_ROOT_ERR_SRC	52	/* Error Source Identification */
750412a8245SMichael S. Tsirkin 
751412a8245SMichael S. Tsirkin /* Virtual Channel */
752120758fbSPaolo Bonzini #define PCI_VC_PORT_CAP1	4
753120758fbSPaolo Bonzini #define  PCI_VC_CAP1_EVCC	0x00000007	/* extended VC count */
754120758fbSPaolo Bonzini #define  PCI_VC_CAP1_LPEVCC	0x00000070	/* low prio extended VC count */
755120758fbSPaolo Bonzini #define  PCI_VC_CAP1_ARB_SIZE	0x00000c00
756120758fbSPaolo Bonzini #define PCI_VC_PORT_CAP2	8
757120758fbSPaolo Bonzini #define  PCI_VC_CAP2_32_PHASE		0x00000002
758120758fbSPaolo Bonzini #define  PCI_VC_CAP2_64_PHASE		0x00000004
759120758fbSPaolo Bonzini #define  PCI_VC_CAP2_128_PHASE		0x00000008
760120758fbSPaolo Bonzini #define  PCI_VC_CAP2_ARB_OFF		0xff000000
761412a8245SMichael S. Tsirkin #define PCI_VC_PORT_CTRL	12
762120758fbSPaolo Bonzini #define  PCI_VC_PORT_CTRL_LOAD_TABLE	0x00000001
763412a8245SMichael S. Tsirkin #define PCI_VC_PORT_STATUS	14
764120758fbSPaolo Bonzini #define  PCI_VC_PORT_STATUS_TABLE	0x00000001
765412a8245SMichael S. Tsirkin #define PCI_VC_RES_CAP		16
766120758fbSPaolo Bonzini #define  PCI_VC_RES_CAP_32_PHASE	0x00000002
767120758fbSPaolo Bonzini #define  PCI_VC_RES_CAP_64_PHASE	0x00000004
768120758fbSPaolo Bonzini #define  PCI_VC_RES_CAP_128_PHASE	0x00000008
769120758fbSPaolo Bonzini #define  PCI_VC_RES_CAP_128_PHASE_TB	0x00000010
770120758fbSPaolo Bonzini #define  PCI_VC_RES_CAP_256_PHASE	0x00000020
771120758fbSPaolo Bonzini #define  PCI_VC_RES_CAP_ARB_OFF		0xff000000
772412a8245SMichael S. Tsirkin #define PCI_VC_RES_CTRL		20
773120758fbSPaolo Bonzini #define  PCI_VC_RES_CTRL_LOAD_TABLE	0x00010000
774120758fbSPaolo Bonzini #define  PCI_VC_RES_CTRL_ARB_SELECT	0x000e0000
775120758fbSPaolo Bonzini #define  PCI_VC_RES_CTRL_ID		0x07000000
776120758fbSPaolo Bonzini #define  PCI_VC_RES_CTRL_ENABLE		0x80000000
777412a8245SMichael S. Tsirkin #define PCI_VC_RES_STATUS	26
778120758fbSPaolo Bonzini #define  PCI_VC_RES_STATUS_TABLE	0x00000001
779120758fbSPaolo Bonzini #define  PCI_VC_RES_STATUS_NEGO		0x00000002
780120758fbSPaolo Bonzini #define PCI_CAP_VC_BASE_SIZEOF		0x10
781120758fbSPaolo Bonzini #define PCI_CAP_VC_PER_VC_SIZEOF	0x0C
782412a8245SMichael S. Tsirkin 
783412a8245SMichael S. Tsirkin /* Power Budgeting */
784412a8245SMichael S. Tsirkin #define PCI_PWR_DSR		4	/* Data Select Register */
785412a8245SMichael S. Tsirkin #define PCI_PWR_DATA		8	/* Data Register */
786412a8245SMichael S. Tsirkin #define  PCI_PWR_DATA_BASE(x)	((x) & 0xff)	    /* Base Power */
787412a8245SMichael S. Tsirkin #define  PCI_PWR_DATA_SCALE(x)	(((x) >> 8) & 3)    /* Data Scale */
788412a8245SMichael S. Tsirkin #define  PCI_PWR_DATA_PM_SUB(x)	(((x) >> 10) & 7)   /* PM Sub State */
789412a8245SMichael S. Tsirkin #define  PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
790412a8245SMichael S. Tsirkin #define  PCI_PWR_DATA_TYPE(x)	(((x) >> 15) & 7)   /* Type */
791412a8245SMichael S. Tsirkin #define  PCI_PWR_DATA_RAIL(x)	(((x) >> 18) & 7)   /* Power Rail */
792412a8245SMichael S. Tsirkin #define PCI_PWR_CAP		12	/* Capability */
793412a8245SMichael S. Tsirkin #define  PCI_PWR_CAP_BUDGET(x)	((x) & 1)	/* Included in system budget */
794120758fbSPaolo Bonzini #define PCI_EXT_CAP_PWR_SIZEOF	16
795120758fbSPaolo Bonzini 
796120758fbSPaolo Bonzini /* Vendor-Specific (VSEC, PCI_EXT_CAP_ID_VNDR) */
797120758fbSPaolo Bonzini #define PCI_VNDR_HEADER		4	/* Vendor-Specific Header */
798120758fbSPaolo Bonzini #define  PCI_VNDR_HEADER_ID(x)	((x) & 0xffff)
799120758fbSPaolo Bonzini #define  PCI_VNDR_HEADER_REV(x)	(((x) >> 16) & 0xf)
800120758fbSPaolo Bonzini #define  PCI_VNDR_HEADER_LEN(x)	(((x) >> 20) & 0xfff)
801412a8245SMichael S. Tsirkin 
802412a8245SMichael S. Tsirkin /*
803120758fbSPaolo Bonzini  * HyperTransport sub capability types
804412a8245SMichael S. Tsirkin  *
805412a8245SMichael S. Tsirkin  * Unfortunately there are both 3 bit and 5 bit capability types defined
806412a8245SMichael S. Tsirkin  * in the HT spec, catering for that is a little messy. You probably don't
807412a8245SMichael S. Tsirkin  * want to use these directly, just use pci_find_ht_capability() and it
808412a8245SMichael S. Tsirkin  * will do the right thing for you.
809412a8245SMichael S. Tsirkin  */
810412a8245SMichael S. Tsirkin #define HT_3BIT_CAP_MASK	0xE0
811412a8245SMichael S. Tsirkin #define HT_CAPTYPE_SLAVE	0x00	/* Slave/Primary link configuration */
812412a8245SMichael S. Tsirkin #define HT_CAPTYPE_HOST		0x20	/* Host/Secondary link configuration */
813412a8245SMichael S. Tsirkin 
814412a8245SMichael S. Tsirkin #define HT_5BIT_CAP_MASK	0xF8
815412a8245SMichael S. Tsirkin #define HT_CAPTYPE_IRQ		0x80	/* IRQ Configuration */
816412a8245SMichael S. Tsirkin #define HT_CAPTYPE_REMAPPING_40	0xA0	/* 40 bit address remapping */
817412a8245SMichael S. Tsirkin #define HT_CAPTYPE_REMAPPING_64 0xA2	/* 64 bit address remapping */
818412a8245SMichael S. Tsirkin #define HT_CAPTYPE_UNITID_CLUMP	0x90	/* Unit ID clumping */
819412a8245SMichael S. Tsirkin #define HT_CAPTYPE_EXTCONF	0x98	/* Extended Configuration Space Access */
820412a8245SMichael S. Tsirkin #define HT_CAPTYPE_MSI_MAPPING	0xA8	/* MSI Mapping Capability */
821412a8245SMichael S. Tsirkin #define  HT_MSI_FLAGS		0x02		/* Offset to flags */
822412a8245SMichael S. Tsirkin #define  HT_MSI_FLAGS_ENABLE	0x1		/* Mapping enable */
823412a8245SMichael S. Tsirkin #define  HT_MSI_FLAGS_FIXED	0x2		/* Fixed mapping only */
824412a8245SMichael S. Tsirkin #define  HT_MSI_FIXED_ADDR	0x00000000FEE00000ULL	/* Fixed addr */
825412a8245SMichael S. Tsirkin #define  HT_MSI_ADDR_LO		0x04		/* Offset to low addr bits */
826412a8245SMichael S. Tsirkin #define  HT_MSI_ADDR_LO_MASK	0xFFF00000	/* Low address bit mask */
827412a8245SMichael S. Tsirkin #define  HT_MSI_ADDR_HI		0x08		/* Offset to high addr bits */
828412a8245SMichael S. Tsirkin #define HT_CAPTYPE_DIRECT_ROUTE	0xB0	/* Direct routing configuration */
829412a8245SMichael S. Tsirkin #define HT_CAPTYPE_VCSET	0xB8	/* Virtual Channel configuration */
830412a8245SMichael S. Tsirkin #define HT_CAPTYPE_ERROR_RETRY	0xC0	/* Retry on error configuration */
831120758fbSPaolo Bonzini #define HT_CAPTYPE_GEN3		0xD0	/* Generation 3 HyperTransport configuration */
832120758fbSPaolo Bonzini #define HT_CAPTYPE_PM		0xE0	/* HyperTransport power management configuration */
833120758fbSPaolo Bonzini #define HT_CAP_SIZEOF_LONG	28	/* slave & primary */
834120758fbSPaolo Bonzini #define HT_CAP_SIZEOF_SHORT	24	/* host & secondary */
835412a8245SMichael S. Tsirkin 
836412a8245SMichael S. Tsirkin /* Alternative Routing-ID Interpretation */
837412a8245SMichael S. Tsirkin #define PCI_ARI_CAP		0x04	/* ARI Capability Register */
838412a8245SMichael S. Tsirkin #define  PCI_ARI_CAP_MFVC	0x0001	/* MFVC Function Groups Capability */
839412a8245SMichael S. Tsirkin #define  PCI_ARI_CAP_ACS	0x0002	/* ACS Function Groups Capability */
840412a8245SMichael S. Tsirkin #define  PCI_ARI_CAP_NFN(x)	(((x) >> 8) & 0xff) /* Next Function Number */
841412a8245SMichael S. Tsirkin #define PCI_ARI_CTRL		0x06	/* ARI Control Register */
842412a8245SMichael S. Tsirkin #define  PCI_ARI_CTRL_MFVC	0x0001	/* MFVC Function Groups Enable */
843412a8245SMichael S. Tsirkin #define  PCI_ARI_CTRL_ACS	0x0002	/* ACS Function Groups Enable */
844412a8245SMichael S. Tsirkin #define  PCI_ARI_CTRL_FG(x)	(((x) >> 4) & 7) /* Function Group */
845120758fbSPaolo Bonzini #define PCI_EXT_CAP_ARI_SIZEOF	8
846412a8245SMichael S. Tsirkin 
847412a8245SMichael S. Tsirkin /* Address Translation Service */
848412a8245SMichael S. Tsirkin #define PCI_ATS_CAP		0x04	/* ATS Capability Register */
849412a8245SMichael S. Tsirkin #define  PCI_ATS_CAP_QDEP(x)	((x) & 0x1f)	/* Invalidate Queue Depth */
850412a8245SMichael S. Tsirkin #define  PCI_ATS_MAX_QDEP	32	/* Max Invalidate Queue Depth */
851412a8245SMichael S. Tsirkin #define PCI_ATS_CTRL		0x06	/* ATS Control Register */
852412a8245SMichael S. Tsirkin #define  PCI_ATS_CTRL_ENABLE	0x8000	/* ATS Enable */
853412a8245SMichael S. Tsirkin #define  PCI_ATS_CTRL_STU(x)	((x) & 0x1f)	/* Smallest Translation Unit */
854412a8245SMichael S. Tsirkin #define  PCI_ATS_MIN_STU	12	/* shift of minimum STU block */
855120758fbSPaolo Bonzini #define PCI_EXT_CAP_ATS_SIZEOF	8
856120758fbSPaolo Bonzini 
857120758fbSPaolo Bonzini /* Page Request Interface */
858120758fbSPaolo Bonzini #define PCI_PRI_CTRL		0x04	/* PRI control register */
859120758fbSPaolo Bonzini #define  PCI_PRI_CTRL_ENABLE	0x01	/* Enable */
860120758fbSPaolo Bonzini #define  PCI_PRI_CTRL_RESET	0x02	/* Reset */
861120758fbSPaolo Bonzini #define PCI_PRI_STATUS		0x06	/* PRI status register */
862120758fbSPaolo Bonzini #define  PCI_PRI_STATUS_RF	0x001	/* Response Failure */
863120758fbSPaolo Bonzini #define  PCI_PRI_STATUS_UPRGI	0x002	/* Unexpected PRG index */
864120758fbSPaolo Bonzini #define  PCI_PRI_STATUS_STOPPED	0x100	/* PRI Stopped */
865120758fbSPaolo Bonzini #define PCI_PRI_MAX_REQ		0x08	/* PRI max reqs supported */
866120758fbSPaolo Bonzini #define PCI_PRI_ALLOC_REQ	0x0c	/* PRI max reqs allowed */
867120758fbSPaolo Bonzini #define PCI_EXT_CAP_PRI_SIZEOF	16
868120758fbSPaolo Bonzini 
869120758fbSPaolo Bonzini /* Process Address Space ID */
870120758fbSPaolo Bonzini #define PCI_PASID_CAP		0x04    /* PASID feature register */
871120758fbSPaolo Bonzini #define  PCI_PASID_CAP_EXEC	0x02	/* Exec permissions Supported */
872120758fbSPaolo Bonzini #define  PCI_PASID_CAP_PRIV	0x04	/* Privilege Mode Supported */
873120758fbSPaolo Bonzini #define PCI_PASID_CTRL		0x06    /* PASID control register */
874120758fbSPaolo Bonzini #define  PCI_PASID_CTRL_ENABLE	0x01	/* Enable bit */
875120758fbSPaolo Bonzini #define  PCI_PASID_CTRL_EXEC	0x02	/* Exec permissions Enable */
876120758fbSPaolo Bonzini #define  PCI_PASID_CTRL_PRIV	0x04	/* Privilege Mode Enable */
877120758fbSPaolo Bonzini #define PCI_EXT_CAP_PASID_SIZEOF	8
878412a8245SMichael S. Tsirkin 
879412a8245SMichael S. Tsirkin /* Single Root I/O Virtualization */
880412a8245SMichael S. Tsirkin #define PCI_SRIOV_CAP		0x04	/* SR-IOV Capabilities */
881412a8245SMichael S. Tsirkin #define  PCI_SRIOV_CAP_VFM	0x01	/* VF Migration Capable */
882412a8245SMichael S. Tsirkin #define  PCI_SRIOV_CAP_INTR(x)	((x) >> 21) /* Interrupt Message Number */
883412a8245SMichael S. Tsirkin #define PCI_SRIOV_CTRL		0x08	/* SR-IOV Control */
884412a8245SMichael S. Tsirkin #define  PCI_SRIOV_CTRL_VFE	0x01	/* VF Enable */
885412a8245SMichael S. Tsirkin #define  PCI_SRIOV_CTRL_VFM	0x02	/* VF Migration Enable */
886412a8245SMichael S. Tsirkin #define  PCI_SRIOV_CTRL_INTR	0x04	/* VF Migration Interrupt Enable */
887412a8245SMichael S. Tsirkin #define  PCI_SRIOV_CTRL_MSE	0x08	/* VF Memory Space Enable */
888412a8245SMichael S. Tsirkin #define  PCI_SRIOV_CTRL_ARI	0x10	/* ARI Capable Hierarchy */
889412a8245SMichael S. Tsirkin #define PCI_SRIOV_STATUS	0x0a	/* SR-IOV Status */
890412a8245SMichael S. Tsirkin #define  PCI_SRIOV_STATUS_VFM	0x01	/* VF Migration Status */
891412a8245SMichael S. Tsirkin #define PCI_SRIOV_INITIAL_VF	0x0c	/* Initial VFs */
892412a8245SMichael S. Tsirkin #define PCI_SRIOV_TOTAL_VF	0x0e	/* Total VFs */
893412a8245SMichael S. Tsirkin #define PCI_SRIOV_NUM_VF	0x10	/* Number of VFs */
894412a8245SMichael S. Tsirkin #define PCI_SRIOV_FUNC_LINK	0x12	/* Function Dependency Link */
895412a8245SMichael S. Tsirkin #define PCI_SRIOV_VF_OFFSET	0x14	/* First VF Offset */
896412a8245SMichael S. Tsirkin #define PCI_SRIOV_VF_STRIDE	0x16	/* Following VF Stride */
897412a8245SMichael S. Tsirkin #define PCI_SRIOV_VF_DID	0x1a	/* VF Device ID */
898412a8245SMichael S. Tsirkin #define PCI_SRIOV_SUP_PGSIZE	0x1c	/* Supported Page Sizes */
899412a8245SMichael S. Tsirkin #define PCI_SRIOV_SYS_PGSIZE	0x20	/* System Page Size */
900412a8245SMichael S. Tsirkin #define PCI_SRIOV_BAR		0x24	/* VF BAR0 */
901412a8245SMichael S. Tsirkin #define  PCI_SRIOV_NUM_BARS	6	/* Number of VF BARs */
902412a8245SMichael S. Tsirkin #define PCI_SRIOV_VFM		0x3c	/* VF Migration State Array Offset*/
903412a8245SMichael S. Tsirkin #define  PCI_SRIOV_VFM_BIR(x)	((x) & 7)	/* State BIR */
904412a8245SMichael S. Tsirkin #define  PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7)	/* State Offset */
905412a8245SMichael S. Tsirkin #define  PCI_SRIOV_VFM_UA	0x0	/* Inactive.Unavailable */
906412a8245SMichael S. Tsirkin #define  PCI_SRIOV_VFM_MI	0x1	/* Dormant.MigrateIn */
907412a8245SMichael S. Tsirkin #define  PCI_SRIOV_VFM_MO	0x2	/* Active.MigrateOut */
908412a8245SMichael S. Tsirkin #define  PCI_SRIOV_VFM_AV	0x3	/* Active.Available */
909120758fbSPaolo Bonzini #define PCI_EXT_CAP_SRIOV_SIZEOF 64
910412a8245SMichael S. Tsirkin 
911412a8245SMichael S. Tsirkin #define PCI_LTR_MAX_SNOOP_LAT	0x4
912412a8245SMichael S. Tsirkin #define PCI_LTR_MAX_NOSNOOP_LAT	0x6
913412a8245SMichael S. Tsirkin #define  PCI_LTR_VALUE_MASK	0x000003ff
914412a8245SMichael S. Tsirkin #define  PCI_LTR_SCALE_MASK	0x00001c00
915412a8245SMichael S. Tsirkin #define  PCI_LTR_SCALE_SHIFT	10
916120758fbSPaolo Bonzini #define PCI_EXT_CAP_LTR_SIZEOF	8
917412a8245SMichael S. Tsirkin 
918412a8245SMichael S. Tsirkin /* Access Control Service */
919412a8245SMichael S. Tsirkin #define PCI_ACS_CAP		0x04	/* ACS Capability Register */
920412a8245SMichael S. Tsirkin #define  PCI_ACS_SV		0x01	/* Source Validation */
921412a8245SMichael S. Tsirkin #define  PCI_ACS_TB		0x02	/* Translation Blocking */
922412a8245SMichael S. Tsirkin #define  PCI_ACS_RR		0x04	/* P2P Request Redirect */
923412a8245SMichael S. Tsirkin #define  PCI_ACS_CR		0x08	/* P2P Completion Redirect */
924412a8245SMichael S. Tsirkin #define  PCI_ACS_UF		0x10	/* Upstream Forwarding */
925412a8245SMichael S. Tsirkin #define  PCI_ACS_EC		0x20	/* P2P Egress Control */
926412a8245SMichael S. Tsirkin #define  PCI_ACS_DT		0x40	/* Direct Translated P2P */
927120758fbSPaolo Bonzini #define PCI_ACS_EGRESS_BITS	0x05	/* ACS Egress Control Vector Size */
928412a8245SMichael S. Tsirkin #define PCI_ACS_CTRL		0x06	/* ACS Control Register */
929412a8245SMichael S. Tsirkin #define PCI_ACS_EGRESS_CTL_V	0x08	/* ACS Egress Control Vector */
930412a8245SMichael S. Tsirkin 
931120758fbSPaolo Bonzini #define PCI_VSEC_HDR		4	/* extended cap - vendor-specific */
932120758fbSPaolo Bonzini #define  PCI_VSEC_HDR_LEN_SHIFT	20	/* shift for length field */
933120758fbSPaolo Bonzini 
934120758fbSPaolo Bonzini /* SATA capability */
935120758fbSPaolo Bonzini #define PCI_SATA_REGS		4	/* SATA REGs specifier */
936120758fbSPaolo Bonzini #define  PCI_SATA_REGS_MASK	0xF	/* location - BAR#/inline */
937120758fbSPaolo Bonzini #define  PCI_SATA_REGS_INLINE	0xF	/* REGS in config space */
938120758fbSPaolo Bonzini #define PCI_SATA_SIZEOF_SHORT	8
939120758fbSPaolo Bonzini #define PCI_SATA_SIZEOF_LONG	16
940120758fbSPaolo Bonzini 
941120758fbSPaolo Bonzini /* Resizable BARs */
942120758fbSPaolo Bonzini #define PCI_REBAR_CTRL		8	/* control register */
943120758fbSPaolo Bonzini #define  PCI_REBAR_CTRL_NBAR_MASK	(7 << 5)	/* mask for # bars */
944120758fbSPaolo Bonzini #define  PCI_REBAR_CTRL_NBAR_SHIFT	5	/* shift for # bars */
945120758fbSPaolo Bonzini 
946120758fbSPaolo Bonzini /* Dynamic Power Allocation */
947120758fbSPaolo Bonzini #define PCI_DPA_CAP		4	/* capability register */
948120758fbSPaolo Bonzini #define  PCI_DPA_CAP_SUBSTATE_MASK	0x1F	/* # substates - 1 */
949120758fbSPaolo Bonzini #define PCI_DPA_BASE_SIZEOF	16	/* size with 0 substates */
950120758fbSPaolo Bonzini 
951120758fbSPaolo Bonzini /* TPH Requester */
952120758fbSPaolo Bonzini #define PCI_TPH_CAP		4	/* capability register */
953120758fbSPaolo Bonzini #define  PCI_TPH_CAP_LOC_MASK	0x600	/* location mask */
954120758fbSPaolo Bonzini #define   PCI_TPH_LOC_NONE	0x000	/* no location */
955120758fbSPaolo Bonzini #define   PCI_TPH_LOC_CAP	0x200	/* in capability */
956120758fbSPaolo Bonzini #define   PCI_TPH_LOC_MSIX	0x400	/* in MSI-X */
957120758fbSPaolo Bonzini #define PCI_TPH_CAP_ST_MASK	0x07FF0000	/* st table mask */
958120758fbSPaolo Bonzini #define PCI_TPH_CAP_ST_SHIFT	16	/* st table shift */
959120758fbSPaolo Bonzini #define PCI_TPH_BASE_SIZEOF	12	/* size with no st table */
960120758fbSPaolo Bonzini 
961ff804f15SCornelia Huck /* Downstream Port Containment */
962ff804f15SCornelia Huck #define PCI_EXP_DPC_CAP			4	/* DPC Capability */
963ff804f15SCornelia Huck #define  PCI_EXP_DPC_CAP_RP_EXT		0x20	/* Root Port Extensions for DPC */
964ff804f15SCornelia Huck #define  PCI_EXP_DPC_CAP_POISONED_TLP	0x40	/* Poisoned TLP Egress Blocking Supported */
965ff804f15SCornelia Huck #define  PCI_EXP_DPC_CAP_SW_TRIGGER	0x80	/* Software Triggering Supported */
966*d4083f50SAlexey Perevalov #define  PCI_EXP_DPC_RP_PIO_LOG_SIZE	0xF00	/* RP PIO log size */
967ff804f15SCornelia Huck #define  PCI_EXP_DPC_CAP_DL_ACTIVE	0x1000	/* ERR_COR signal on DL_Active supported */
968ff804f15SCornelia Huck 
969ff804f15SCornelia Huck #define PCI_EXP_DPC_CTL			6	/* DPC control */
970ff804f15SCornelia Huck #define  PCI_EXP_DPC_CTL_EN_NONFATAL 	0x02	/* Enable trigger on ERR_NONFATAL message */
971ff804f15SCornelia Huck #define  PCI_EXP_DPC_CTL_INT_EN 	0x08	/* DPC Interrupt Enable */
972ff804f15SCornelia Huck 
973ff804f15SCornelia Huck #define PCI_EXP_DPC_STATUS		8	/* DPC Status */
974ff804f15SCornelia Huck #define  PCI_EXP_DPC_STATUS_TRIGGER	0x01	/* Trigger Status */
975ff804f15SCornelia Huck #define  PCI_EXP_DPC_STATUS_INTERRUPT	0x08	/* Interrupt Status */
9763a5eb5b4SPaolo Bonzini #define  PCI_EXP_DPC_RP_BUSY		0x10	/* Root Port Busy */
977ff804f15SCornelia Huck 
978ff804f15SCornelia Huck #define PCI_EXP_DPC_SOURCE_ID		10	/* DPC Source Identifier */
979ff804f15SCornelia Huck 
980*d4083f50SAlexey Perevalov #define PCI_EXP_DPC_RP_PIO_STATUS	 0x0C	/* RP PIO Status */
981*d4083f50SAlexey Perevalov #define PCI_EXP_DPC_RP_PIO_MASK		 0x10	/* RP PIO MASK */
982*d4083f50SAlexey Perevalov #define PCI_EXP_DPC_RP_PIO_SEVERITY	 0x14	/* RP PIO Severity */
983*d4083f50SAlexey Perevalov #define PCI_EXP_DPC_RP_PIO_SYSERROR	 0x18	/* RP PIO SysError */
984*d4083f50SAlexey Perevalov #define PCI_EXP_DPC_RP_PIO_EXCEPTION	 0x1C	/* RP PIO Exception */
985*d4083f50SAlexey Perevalov #define PCI_EXP_DPC_RP_PIO_HEADER_LOG	 0x20	/* RP PIO Header Log */
986*d4083f50SAlexey Perevalov #define PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG	 0x30	/* RP PIO ImpSpec Log */
987*d4083f50SAlexey Perevalov #define PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG 0x34	/* RP PIO TLP Prefix Log */
988*d4083f50SAlexey Perevalov 
989bc204035SMarcelo Tosatti /* Precision Time Measurement */
990bc204035SMarcelo Tosatti #define PCI_PTM_CAP			0x04	    /* PTM Capability */
991bc204035SMarcelo Tosatti #define  PCI_PTM_CAP_REQ		0x00000001  /* Requester capable */
992bc204035SMarcelo Tosatti #define  PCI_PTM_CAP_ROOT		0x00000004  /* Root capable */
993bc204035SMarcelo Tosatti #define  PCI_PTM_GRANULARITY_MASK	0x0000FF00  /* Clock granularity */
994bc204035SMarcelo Tosatti #define PCI_PTM_CTRL			0x08	    /* PTM Control */
995bc204035SMarcelo Tosatti #define  PCI_PTM_CTRL_ENABLE		0x00000001  /* PTM enable */
996bc204035SMarcelo Tosatti #define  PCI_PTM_CTRL_ROOT		0x00000002  /* Root select */
997bc204035SMarcelo Tosatti 
9983a5eb5b4SPaolo Bonzini /* L1 PM Substates */
9993a5eb5b4SPaolo Bonzini #define PCI_L1SS_CAP		    4	/* capability register */
10003a5eb5b4SPaolo Bonzini #define  PCI_L1SS_CAP_PCIPM_L1_2	 1	/* PCI PM L1.2 Support */
10013a5eb5b4SPaolo Bonzini #define  PCI_L1SS_CAP_PCIPM_L1_1	 2	/* PCI PM L1.1 Support */
10023a5eb5b4SPaolo Bonzini #define  PCI_L1SS_CAP_ASPM_L1_2		 4	/* ASPM L1.2 Support */
10033a5eb5b4SPaolo Bonzini #define  PCI_L1SS_CAP_ASPM_L1_1		 8	/* ASPM L1.1 Support */
10043a5eb5b4SPaolo Bonzini #define  PCI_L1SS_CAP_L1_PM_SS		16	/* L1 PM Substates Support */
10053a5eb5b4SPaolo Bonzini #define PCI_L1SS_CTL1		    8	/* Control Register 1 */
10063a5eb5b4SPaolo Bonzini #define  PCI_L1SS_CTL1_PCIPM_L1_2	1	/* PCI PM L1.2 Enable */
10073a5eb5b4SPaolo Bonzini #define  PCI_L1SS_CTL1_PCIPM_L1_1	2	/* PCI PM L1.1 Support */
10083a5eb5b4SPaolo Bonzini #define  PCI_L1SS_CTL1_ASPM_L1_2	4	/* ASPM L1.2 Support */
10093a5eb5b4SPaolo Bonzini #define  PCI_L1SS_CTL1_ASPM_L1_1	8	/* ASPM L1.1 Support */
10103a5eb5b4SPaolo Bonzini #define  PCI_L1SS_CTL1_L1SS_MASK	0x0000000F
10113a5eb5b4SPaolo Bonzini #define PCI_L1SS_CTL2		    0xC	/* Control Register 2 */
10123a5eb5b4SPaolo Bonzini 
1013412a8245SMichael S. Tsirkin #endif /* LINUX_PCI_REGS_H */
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