1dd873966SEric Auger /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2412a8245SMichael S. Tsirkin /*
3412a8245SMichael S. Tsirkin  *	PCI standard defines
4412a8245SMichael S. Tsirkin  *	Copyright 1994, Drew Eckhardt
5412a8245SMichael S. Tsirkin  *	Copyright 1997--1999 Martin Mares <mj@ucw.cz>
6412a8245SMichael S. Tsirkin  *
7412a8245SMichael S. Tsirkin  *	For more information, please consult the following manuals (look at
8412a8245SMichael S. Tsirkin  *	http://www.pcisig.com/ for how to get them):
9412a8245SMichael S. Tsirkin  *
10412a8245SMichael S. Tsirkin  *	PCI BIOS Specification
11412a8245SMichael S. Tsirkin  *	PCI Local Bus Specification
12412a8245SMichael S. Tsirkin  *	PCI to PCI Bridge Specification
13412a8245SMichael S. Tsirkin  *	PCI System Design Guide
14412a8245SMichael S. Tsirkin  *
15120758fbSPaolo Bonzini  *	For HyperTransport information, please consult the following manuals
16d9cb4336SCornelia Huck  *	from http://www.hypertransport.org :
17412a8245SMichael S. Tsirkin  *
18120758fbSPaolo Bonzini  *	The HyperTransport I/O Link Specification
19412a8245SMichael S. Tsirkin  */
20412a8245SMichael S. Tsirkin 
21412a8245SMichael S. Tsirkin #ifndef LINUX_PCI_REGS_H
22412a8245SMichael S. Tsirkin #define LINUX_PCI_REGS_H
23412a8245SMichael S. Tsirkin 
24412a8245SMichael S. Tsirkin /*
253a5eb5b4SPaolo Bonzini  * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
263a5eb5b4SPaolo Bonzini  * configuration space.  PCI-X Mode 2 and PCIe devices have 4096 bytes of
273a5eb5b4SPaolo Bonzini  * configuration space.
283a5eb5b4SPaolo Bonzini  */
293a5eb5b4SPaolo Bonzini #define PCI_CFG_SPACE_SIZE	256
303a5eb5b4SPaolo Bonzini #define PCI_CFG_SPACE_EXP_SIZE	4096
313a5eb5b4SPaolo Bonzini 
323a5eb5b4SPaolo Bonzini /*
33412a8245SMichael S. Tsirkin  * Under PCI, each device has 256 bytes of configuration address space,
34412a8245SMichael S. Tsirkin  * of which the first 64 bytes are standardized as follows:
35412a8245SMichael S. Tsirkin  */
36120758fbSPaolo Bonzini #define PCI_STD_HEADER_SIZEOF	64
3750fd0c37SBharata B Rao #define PCI_STD_NUM_BARS	6	/* Number of standard BARs */
38412a8245SMichael S. Tsirkin #define PCI_VENDOR_ID		0x00	/* 16 bits */
39412a8245SMichael S. Tsirkin #define PCI_DEVICE_ID		0x02	/* 16 bits */
40412a8245SMichael S. Tsirkin #define PCI_COMMAND		0x04	/* 16 bits */
41412a8245SMichael S. Tsirkin #define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
42412a8245SMichael S. Tsirkin #define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
43412a8245SMichael S. Tsirkin #define  PCI_COMMAND_MASTER	0x4	/* Enable bus mastering */
44412a8245SMichael S. Tsirkin #define  PCI_COMMAND_SPECIAL	0x8	/* Enable response to special cycles */
45412a8245SMichael S. Tsirkin #define  PCI_COMMAND_INVALIDATE	0x10	/* Use memory write and invalidate */
46412a8245SMichael S. Tsirkin #define  PCI_COMMAND_VGA_PALETTE 0x20	/* Enable palette snooping */
47412a8245SMichael S. Tsirkin #define  PCI_COMMAND_PARITY	0x40	/* Enable parity checking */
48412a8245SMichael S. Tsirkin #define  PCI_COMMAND_WAIT	0x80	/* Enable address/data stepping */
49412a8245SMichael S. Tsirkin #define  PCI_COMMAND_SERR	0x100	/* Enable SERR */
50412a8245SMichael S. Tsirkin #define  PCI_COMMAND_FAST_BACK	0x200	/* Enable back-to-back writes */
51412a8245SMichael S. Tsirkin #define  PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
52412a8245SMichael S. Tsirkin 
53412a8245SMichael S. Tsirkin #define PCI_STATUS		0x06	/* 16 bits */
54da054c64SPaolo Bonzini #define  PCI_STATUS_IMM_READY	0x01	/* Immediate Readiness */
55412a8245SMichael S. Tsirkin #define  PCI_STATUS_INTERRUPT	0x08	/* Interrupt status */
56412a8245SMichael S. Tsirkin #define  PCI_STATUS_CAP_LIST	0x10	/* Support Capability List */
57120758fbSPaolo Bonzini #define  PCI_STATUS_66MHZ	0x20	/* Support 66 MHz PCI 2.1 bus */
58412a8245SMichael S. Tsirkin #define  PCI_STATUS_UDF		0x40	/* Support User Definable Features [obsolete] */
59412a8245SMichael S. Tsirkin #define  PCI_STATUS_FAST_BACK	0x80	/* Accept fast-back to back */
60412a8245SMichael S. Tsirkin #define  PCI_STATUS_PARITY	0x100	/* Detected parity error */
61412a8245SMichael S. Tsirkin #define  PCI_STATUS_DEVSEL_MASK	0x600	/* DEVSEL timing */
62412a8245SMichael S. Tsirkin #define  PCI_STATUS_DEVSEL_FAST		0x000
63412a8245SMichael S. Tsirkin #define  PCI_STATUS_DEVSEL_MEDIUM	0x200
64412a8245SMichael S. Tsirkin #define  PCI_STATUS_DEVSEL_SLOW		0x400
65412a8245SMichael S. Tsirkin #define  PCI_STATUS_SIG_TARGET_ABORT	0x800 /* Set on target abort */
66412a8245SMichael S. Tsirkin #define  PCI_STATUS_REC_TARGET_ABORT	0x1000 /* Master ack of " */
67412a8245SMichael S. Tsirkin #define  PCI_STATUS_REC_MASTER_ABORT	0x2000 /* Set on master abort */
68412a8245SMichael S. Tsirkin #define  PCI_STATUS_SIG_SYSTEM_ERROR	0x4000 /* Set when we drive SERR */
69412a8245SMichael S. Tsirkin #define  PCI_STATUS_DETECTED_PARITY	0x8000 /* Set on parity error */
70412a8245SMichael S. Tsirkin 
71412a8245SMichael S. Tsirkin #define PCI_CLASS_REVISION	0x08	/* High 24 bits are class, low 8 revision */
72412a8245SMichael S. Tsirkin #define PCI_REVISION_ID		0x08	/* Revision ID */
73412a8245SMichael S. Tsirkin #define PCI_CLASS_PROG		0x09	/* Reg. Level Programming Interface */
74412a8245SMichael S. Tsirkin #define PCI_CLASS_DEVICE	0x0a	/* Device class */
75412a8245SMichael S. Tsirkin 
76412a8245SMichael S. Tsirkin #define PCI_CACHE_LINE_SIZE	0x0c	/* 8 bits */
77412a8245SMichael S. Tsirkin #define PCI_LATENCY_TIMER	0x0d	/* 8 bits */
78412a8245SMichael S. Tsirkin #define PCI_HEADER_TYPE		0x0e	/* 8 bits */
7953ba2eeeSMatthew Rosato #define  PCI_HEADER_TYPE_MASK		0x7f
80412a8245SMichael S. Tsirkin #define  PCI_HEADER_TYPE_NORMAL		0
81412a8245SMichael S. Tsirkin #define  PCI_HEADER_TYPE_BRIDGE		1
82412a8245SMichael S. Tsirkin #define  PCI_HEADER_TYPE_CARDBUS	2
83412a8245SMichael S. Tsirkin 
84412a8245SMichael S. Tsirkin #define PCI_BIST		0x0f	/* 8 bits */
85412a8245SMichael S. Tsirkin #define  PCI_BIST_CODE_MASK	0x0f	/* Return result */
86412a8245SMichael S. Tsirkin #define  PCI_BIST_START		0x40	/* 1 to start BIST, 2 secs or less */
87412a8245SMichael S. Tsirkin #define  PCI_BIST_CAPABLE	0x80	/* 1 if BIST capable */
88412a8245SMichael S. Tsirkin 
89412a8245SMichael S. Tsirkin /*
90412a8245SMichael S. Tsirkin  * Base addresses specify locations in memory or I/O space.
91412a8245SMichael S. Tsirkin  * Decoded size can be determined by writing a value of
92412a8245SMichael S. Tsirkin  * 0xffffffff to the register, and reading it back.  Only
93412a8245SMichael S. Tsirkin  * 1 bits are decoded.
94412a8245SMichael S. Tsirkin  */
95412a8245SMichael S. Tsirkin #define PCI_BASE_ADDRESS_0	0x10	/* 32 bits */
96412a8245SMichael S. Tsirkin #define PCI_BASE_ADDRESS_1	0x14	/* 32 bits [htype 0,1 only] */
97412a8245SMichael S. Tsirkin #define PCI_BASE_ADDRESS_2	0x18	/* 32 bits [htype 0 only] */
98412a8245SMichael S. Tsirkin #define PCI_BASE_ADDRESS_3	0x1c	/* 32 bits */
99412a8245SMichael S. Tsirkin #define PCI_BASE_ADDRESS_4	0x20	/* 32 bits */
100412a8245SMichael S. Tsirkin #define PCI_BASE_ADDRESS_5	0x24	/* 32 bits */
101412a8245SMichael S. Tsirkin #define  PCI_BASE_ADDRESS_SPACE		0x01	/* 0 = memory, 1 = I/O */
102412a8245SMichael S. Tsirkin #define  PCI_BASE_ADDRESS_SPACE_IO	0x01
103412a8245SMichael S. Tsirkin #define  PCI_BASE_ADDRESS_SPACE_MEMORY	0x00
104412a8245SMichael S. Tsirkin #define  PCI_BASE_ADDRESS_MEM_TYPE_MASK	0x06
105412a8245SMichael S. Tsirkin #define  PCI_BASE_ADDRESS_MEM_TYPE_32	0x00	/* 32 bit address */
106412a8245SMichael S. Tsirkin #define  PCI_BASE_ADDRESS_MEM_TYPE_1M	0x02	/* Below 1M [obsolete] */
107412a8245SMichael S. Tsirkin #define  PCI_BASE_ADDRESS_MEM_TYPE_64	0x04	/* 64 bit address */
108412a8245SMichael S. Tsirkin #define  PCI_BASE_ADDRESS_MEM_PREFETCH	0x08	/* prefetchable? */
109412a8245SMichael S. Tsirkin #define  PCI_BASE_ADDRESS_MEM_MASK	(~0x0fUL)
110412a8245SMichael S. Tsirkin #define  PCI_BASE_ADDRESS_IO_MASK	(~0x03UL)
111412a8245SMichael S. Tsirkin /* bit 1 is reserved if address_space = 1 */
112412a8245SMichael S. Tsirkin 
113412a8245SMichael S. Tsirkin /* Header type 0 (normal devices) */
114412a8245SMichael S. Tsirkin #define PCI_CARDBUS_CIS		0x28
115412a8245SMichael S. Tsirkin #define PCI_SUBSYSTEM_VENDOR_ID	0x2c
116412a8245SMichael S. Tsirkin #define PCI_SUBSYSTEM_ID	0x2e
117412a8245SMichael S. Tsirkin #define PCI_ROM_ADDRESS		0x30	/* Bits 31..11 are address, 10..1 reserved */
118412a8245SMichael S. Tsirkin #define  PCI_ROM_ADDRESS_ENABLE	0x01
11974c98e20SCornelia Huck #define PCI_ROM_ADDRESS_MASK	(~0x7ffU)
120412a8245SMichael S. Tsirkin 
121412a8245SMichael S. Tsirkin #define PCI_CAPABILITY_LIST	0x34	/* Offset of first capability list entry */
122412a8245SMichael S. Tsirkin 
123412a8245SMichael S. Tsirkin /* 0x35-0x3b are reserved */
124412a8245SMichael S. Tsirkin #define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */
125412a8245SMichael S. Tsirkin #define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */
126412a8245SMichael S. Tsirkin #define PCI_MIN_GNT		0x3e	/* 8 bits */
127412a8245SMichael S. Tsirkin #define PCI_MAX_LAT		0x3f	/* 8 bits */
128412a8245SMichael S. Tsirkin 
129412a8245SMichael S. Tsirkin /* Header type 1 (PCI-to-PCI bridges) */
130412a8245SMichael S. Tsirkin #define PCI_PRIMARY_BUS		0x18	/* Primary bus number */
131412a8245SMichael S. Tsirkin #define PCI_SECONDARY_BUS	0x19	/* Secondary bus number */
132412a8245SMichael S. Tsirkin #define PCI_SUBORDINATE_BUS	0x1a	/* Highest bus number behind the bridge */
133412a8245SMichael S. Tsirkin #define PCI_SEC_LATENCY_TIMER	0x1b	/* Latency timer for secondary interface */
134412a8245SMichael S. Tsirkin #define PCI_IO_BASE		0x1c	/* I/O range behind the bridge */
135412a8245SMichael S. Tsirkin #define PCI_IO_LIMIT		0x1d
136412a8245SMichael S. Tsirkin #define  PCI_IO_RANGE_TYPE_MASK	0x0fUL	/* I/O bridging type */
137412a8245SMichael S. Tsirkin #define  PCI_IO_RANGE_TYPE_16	0x00
138412a8245SMichael S. Tsirkin #define  PCI_IO_RANGE_TYPE_32	0x01
139120758fbSPaolo Bonzini #define  PCI_IO_RANGE_MASK	(~0x0fUL) /* Standard 4K I/O windows */
140120758fbSPaolo Bonzini #define  PCI_IO_1K_RANGE_MASK	(~0x03UL) /* Intel 1K I/O windows */
141412a8245SMichael S. Tsirkin #define PCI_SEC_STATUS		0x1e	/* Secondary status register, only bit 14 used */
142412a8245SMichael S. Tsirkin #define PCI_MEMORY_BASE		0x20	/* Memory range behind */
143412a8245SMichael S. Tsirkin #define PCI_MEMORY_LIMIT	0x22
144412a8245SMichael S. Tsirkin #define  PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
145412a8245SMichael S. Tsirkin #define  PCI_MEMORY_RANGE_MASK	(~0x0fUL)
146412a8245SMichael S. Tsirkin #define PCI_PREF_MEMORY_BASE	0x24	/* Prefetchable memory range behind */
147412a8245SMichael S. Tsirkin #define PCI_PREF_MEMORY_LIMIT	0x26
148412a8245SMichael S. Tsirkin #define  PCI_PREF_RANGE_TYPE_MASK 0x0fUL
149412a8245SMichael S. Tsirkin #define  PCI_PREF_RANGE_TYPE_32	0x00
150412a8245SMichael S. Tsirkin #define  PCI_PREF_RANGE_TYPE_64	0x01
151412a8245SMichael S. Tsirkin #define  PCI_PREF_RANGE_MASK	(~0x0fUL)
152412a8245SMichael S. Tsirkin #define PCI_PREF_BASE_UPPER32	0x28	/* Upper half of prefetchable memory range */
153412a8245SMichael S. Tsirkin #define PCI_PREF_LIMIT_UPPER32	0x2c
154412a8245SMichael S. Tsirkin #define PCI_IO_BASE_UPPER16	0x30	/* Upper half of I/O addresses */
155412a8245SMichael S. Tsirkin #define PCI_IO_LIMIT_UPPER16	0x32
156412a8245SMichael S. Tsirkin /* 0x34 same as for htype 0 */
157412a8245SMichael S. Tsirkin /* 0x35-0x3b is reserved */
158412a8245SMichael S. Tsirkin #define PCI_ROM_ADDRESS1	0x38	/* Same as PCI_ROM_ADDRESS, but for htype 1 */
159412a8245SMichael S. Tsirkin /* 0x3c-0x3d are same as for htype 0 */
160412a8245SMichael S. Tsirkin #define PCI_BRIDGE_CONTROL	0x3e
161412a8245SMichael S. Tsirkin #define  PCI_BRIDGE_CTL_PARITY	0x01	/* Enable parity detection on secondary interface */
162412a8245SMichael S. Tsirkin #define  PCI_BRIDGE_CTL_SERR	0x02	/* The same for SERR forwarding */
163412a8245SMichael S. Tsirkin #define  PCI_BRIDGE_CTL_ISA	0x04	/* Enable ISA mode */
164412a8245SMichael S. Tsirkin #define  PCI_BRIDGE_CTL_VGA	0x08	/* Forward VGA addresses */
165412a8245SMichael S. Tsirkin #define  PCI_BRIDGE_CTL_MASTER_ABORT	0x20  /* Report master aborts */
166412a8245SMichael S. Tsirkin #define  PCI_BRIDGE_CTL_BUS_RESET	0x40	/* Secondary bus reset */
167412a8245SMichael S. Tsirkin #define  PCI_BRIDGE_CTL_FAST_BACK	0x80	/* Fast Back2Back enabled on secondary interface */
168412a8245SMichael S. Tsirkin 
169412a8245SMichael S. Tsirkin /* Header type 2 (CardBus bridges) */
170412a8245SMichael S. Tsirkin #define PCI_CB_CAPABILITY_LIST	0x14
171412a8245SMichael S. Tsirkin /* 0x15 reserved */
172412a8245SMichael S. Tsirkin #define PCI_CB_SEC_STATUS	0x16	/* Secondary status */
173412a8245SMichael S. Tsirkin #define PCI_CB_PRIMARY_BUS	0x18	/* PCI bus number */
174412a8245SMichael S. Tsirkin #define PCI_CB_CARD_BUS		0x19	/* CardBus bus number */
175412a8245SMichael S. Tsirkin #define PCI_CB_SUBORDINATE_BUS	0x1a	/* Subordinate bus number */
176412a8245SMichael S. Tsirkin #define PCI_CB_LATENCY_TIMER	0x1b	/* CardBus latency timer */
177412a8245SMichael S. Tsirkin #define PCI_CB_MEMORY_BASE_0	0x1c
178412a8245SMichael S. Tsirkin #define PCI_CB_MEMORY_LIMIT_0	0x20
179412a8245SMichael S. Tsirkin #define PCI_CB_MEMORY_BASE_1	0x24
180412a8245SMichael S. Tsirkin #define PCI_CB_MEMORY_LIMIT_1	0x28
181412a8245SMichael S. Tsirkin #define PCI_CB_IO_BASE_0	0x2c
182412a8245SMichael S. Tsirkin #define PCI_CB_IO_BASE_0_HI	0x2e
183412a8245SMichael S. Tsirkin #define PCI_CB_IO_LIMIT_0	0x30
184412a8245SMichael S. Tsirkin #define PCI_CB_IO_LIMIT_0_HI	0x32
185412a8245SMichael S. Tsirkin #define PCI_CB_IO_BASE_1	0x34
186412a8245SMichael S. Tsirkin #define PCI_CB_IO_BASE_1_HI	0x36
187412a8245SMichael S. Tsirkin #define PCI_CB_IO_LIMIT_1	0x38
188412a8245SMichael S. Tsirkin #define PCI_CB_IO_LIMIT_1_HI	0x3a
189412a8245SMichael S. Tsirkin #define  PCI_CB_IO_RANGE_MASK	(~0x03UL)
190412a8245SMichael S. Tsirkin /* 0x3c-0x3d are same as for htype 0 */
191412a8245SMichael S. Tsirkin #define PCI_CB_BRIDGE_CONTROL	0x3e
192412a8245SMichael S. Tsirkin #define  PCI_CB_BRIDGE_CTL_PARITY	0x01	/* Similar to standard bridge control register */
193412a8245SMichael S. Tsirkin #define  PCI_CB_BRIDGE_CTL_SERR		0x02
194412a8245SMichael S. Tsirkin #define  PCI_CB_BRIDGE_CTL_ISA		0x04
195412a8245SMichael S. Tsirkin #define  PCI_CB_BRIDGE_CTL_VGA		0x08
196412a8245SMichael S. Tsirkin #define  PCI_CB_BRIDGE_CTL_MASTER_ABORT	0x20
197412a8245SMichael S. Tsirkin #define  PCI_CB_BRIDGE_CTL_CB_RESET	0x40	/* CardBus reset */
198412a8245SMichael S. Tsirkin #define  PCI_CB_BRIDGE_CTL_16BIT_INT	0x80	/* Enable interrupt for 16-bit cards */
199412a8245SMichael S. Tsirkin #define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100	/* Prefetch enable for both memory regions */
200412a8245SMichael S. Tsirkin #define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
201412a8245SMichael S. Tsirkin #define  PCI_CB_BRIDGE_CTL_POST_WRITES	0x400
202412a8245SMichael S. Tsirkin #define PCI_CB_SUBSYSTEM_VENDOR_ID	0x40
203412a8245SMichael S. Tsirkin #define PCI_CB_SUBSYSTEM_ID		0x42
204412a8245SMichael S. Tsirkin #define PCI_CB_LEGACY_MODE_BASE		0x44	/* 16-bit PC Card legacy mode base address (ExCa) */
205412a8245SMichael S. Tsirkin /* 0x48-0x7f reserved */
206412a8245SMichael S. Tsirkin 
207412a8245SMichael S. Tsirkin /* Capability lists */
208412a8245SMichael S. Tsirkin 
209412a8245SMichael S. Tsirkin #define PCI_CAP_LIST_ID		0	/* Capability ID */
210412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_PM		0x01	/* Power Management */
211412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_AGP		0x02	/* Accelerated Graphics Port */
212412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_VPD		0x03	/* Vital Product Data */
213412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_SLOTID	0x04	/* Slot Identification */
214412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_MSI		0x05	/* Message Signalled Interrupts */
215412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_CHSWP	0x06	/* CompactPCI HotSwap */
216412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_PCIX	0x07	/* PCI-X */
217412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_HT		0x08	/* HyperTransport */
218120758fbSPaolo Bonzini #define  PCI_CAP_ID_VNDR	0x09	/* Vendor-Specific */
219412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_DBG		0x0A	/* Debug port */
220412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_CCRC	0x0B	/* CompactPCI Central Resource Control */
221412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_SHPC	0x0C	/* PCI Standard Hot-Plug Controller */
222412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_SSVID	0x0D	/* Bridge subsystem vendor/device ID */
223412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_AGP3	0x0E	/* AGP Target PCI-PCI bridge */
224120758fbSPaolo Bonzini #define  PCI_CAP_ID_SECDEV	0x0F	/* Secure Device */
225412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_EXP		0x10	/* PCI Express */
226412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_MSIX	0x11	/* MSI-X */
227120758fbSPaolo Bonzini #define  PCI_CAP_ID_SATA	0x12	/* SATA Data/Index Conf. */
228412a8245SMichael S. Tsirkin #define  PCI_CAP_ID_AF		0x13	/* PCI Advanced Features */
229fff02bc0SPaolo Bonzini #define  PCI_CAP_ID_EA		0x14	/* PCI Enhanced Allocation */
230fff02bc0SPaolo Bonzini #define  PCI_CAP_ID_MAX		PCI_CAP_ID_EA
231412a8245SMichael S. Tsirkin #define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
232412a8245SMichael S. Tsirkin #define PCI_CAP_FLAGS		2	/* Capability defined flags (16 bits) */
233412a8245SMichael S. Tsirkin #define PCI_CAP_SIZEOF		4
234412a8245SMichael S. Tsirkin 
235412a8245SMichael S. Tsirkin /* Power Management Registers */
236412a8245SMichael S. Tsirkin 
237412a8245SMichael S. Tsirkin #define PCI_PM_PMC		2	/* PM Capabilities Register */
238412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_VER_MASK	0x0007	/* Version */
239412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_PME_CLOCK	0x0008	/* PME clock required */
240412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_RESERVED    0x0010  /* Reserved field */
241412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_DSI		0x0020	/* Device specific initialization */
242412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_AUX_POWER	0x01C0	/* Auxiliary power support mask */
243412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_D1		0x0200	/* D1 power state support */
244412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_D2		0x0400	/* D2 power state support */
245412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_PME		0x0800	/* PME pin supported */
246412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_PME_MASK	0xF800	/* PME Mask of all supported states */
247412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_PME_D0	0x0800	/* PME# from D0 */
248412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_PME_D1	0x1000	/* PME# from D1 */
249412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_PME_D2	0x2000	/* PME# from D2 */
25053ba2eeeSMatthew Rosato #define  PCI_PM_CAP_PME_D3hot	0x4000	/* PME# from D3 (hot) */
251412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_PME_D3cold	0x8000	/* PME# from D3 (cold) */
252412a8245SMichael S. Tsirkin #define  PCI_PM_CAP_PME_SHIFT	11	/* Start of the PME Mask in PMC */
253412a8245SMichael S. Tsirkin #define PCI_PM_CTRL		4	/* PM control and status register */
254412a8245SMichael S. Tsirkin #define  PCI_PM_CTRL_STATE_MASK	0x0003	/* Current power state (D0 to D3) */
255412a8245SMichael S. Tsirkin #define  PCI_PM_CTRL_NO_SOFT_RESET	0x0008	/* No reset for D3hot->D0 */
256412a8245SMichael S. Tsirkin #define  PCI_PM_CTRL_PME_ENABLE	0x0100	/* PME pin enable */
257412a8245SMichael S. Tsirkin #define  PCI_PM_CTRL_DATA_SEL_MASK	0x1e00	/* Data select (??) */
258412a8245SMichael S. Tsirkin #define  PCI_PM_CTRL_DATA_SCALE_MASK	0x6000	/* Data scale (??) */
259412a8245SMichael S. Tsirkin #define  PCI_PM_CTRL_PME_STATUS	0x8000	/* PME pin status */
260412a8245SMichael S. Tsirkin #define PCI_PM_PPB_EXTENSIONS	6	/* PPB support extensions (??) */
261412a8245SMichael S. Tsirkin #define  PCI_PM_PPB_B2_B3	0x40	/* Stop clock when in D3hot (??) */
262412a8245SMichael S. Tsirkin #define  PCI_PM_BPCC_ENABLE	0x80	/* Bus power/clock control enable (??) */
263412a8245SMichael S. Tsirkin #define PCI_PM_DATA_REGISTER	7	/* (??) */
264412a8245SMichael S. Tsirkin #define PCI_PM_SIZEOF		8
265412a8245SMichael S. Tsirkin 
266412a8245SMichael S. Tsirkin /* AGP registers */
267412a8245SMichael S. Tsirkin 
268412a8245SMichael S. Tsirkin #define PCI_AGP_VERSION		2	/* BCD version number */
269412a8245SMichael S. Tsirkin #define PCI_AGP_RFU		3	/* Rest of capability flags */
270412a8245SMichael S. Tsirkin #define PCI_AGP_STATUS		4	/* Status register */
271412a8245SMichael S. Tsirkin #define  PCI_AGP_STATUS_RQ_MASK	0xff000000	/* Maximum number of requests - 1 */
272412a8245SMichael S. Tsirkin #define  PCI_AGP_STATUS_SBA	0x0200	/* Sideband addressing supported */
273412a8245SMichael S. Tsirkin #define  PCI_AGP_STATUS_64BIT	0x0020	/* 64-bit addressing supported */
274412a8245SMichael S. Tsirkin #define  PCI_AGP_STATUS_FW	0x0010	/* FW transfers supported */
275412a8245SMichael S. Tsirkin #define  PCI_AGP_STATUS_RATE4	0x0004	/* 4x transfer rate supported */
276412a8245SMichael S. Tsirkin #define  PCI_AGP_STATUS_RATE2	0x0002	/* 2x transfer rate supported */
277412a8245SMichael S. Tsirkin #define  PCI_AGP_STATUS_RATE1	0x0001	/* 1x transfer rate supported */
278412a8245SMichael S. Tsirkin #define PCI_AGP_COMMAND		8	/* Control register */
279412a8245SMichael S. Tsirkin #define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
280412a8245SMichael S. Tsirkin #define  PCI_AGP_COMMAND_SBA	0x0200	/* Sideband addressing enabled */
281412a8245SMichael S. Tsirkin #define  PCI_AGP_COMMAND_AGP	0x0100	/* Allow processing of AGP transactions */
282412a8245SMichael S. Tsirkin #define  PCI_AGP_COMMAND_64BIT	0x0020	/* Allow processing of 64-bit addresses */
283412a8245SMichael S. Tsirkin #define  PCI_AGP_COMMAND_FW	0x0010	/* Force FW transfers */
284412a8245SMichael S. Tsirkin #define  PCI_AGP_COMMAND_RATE4	0x0004	/* Use 4x rate */
285412a8245SMichael S. Tsirkin #define  PCI_AGP_COMMAND_RATE2	0x0002	/* Use 2x rate */
286412a8245SMichael S. Tsirkin #define  PCI_AGP_COMMAND_RATE1	0x0001	/* Use 1x rate */
287412a8245SMichael S. Tsirkin #define PCI_AGP_SIZEOF		12
288412a8245SMichael S. Tsirkin 
289412a8245SMichael S. Tsirkin /* Vital Product Data */
290412a8245SMichael S. Tsirkin 
291412a8245SMichael S. Tsirkin #define PCI_VPD_ADDR		2	/* Address to access (15 bits!) */
292412a8245SMichael S. Tsirkin #define  PCI_VPD_ADDR_MASK	0x7fff	/* Address mask */
293412a8245SMichael S. Tsirkin #define  PCI_VPD_ADDR_F		0x8000	/* Write 0, 1 indicates completion */
294412a8245SMichael S. Tsirkin #define PCI_VPD_DATA		4	/* 32-bits of data returned here */
295120758fbSPaolo Bonzini #define PCI_CAP_VPD_SIZEOF	8
296412a8245SMichael S. Tsirkin 
297412a8245SMichael S. Tsirkin /* Slot Identification */
298412a8245SMichael S. Tsirkin 
299412a8245SMichael S. Tsirkin #define PCI_SID_ESR		2	/* Expansion Slot Register */
300412a8245SMichael S. Tsirkin #define  PCI_SID_ESR_NSLOTS	0x1f	/* Number of expansion slots available */
301412a8245SMichael S. Tsirkin #define  PCI_SID_ESR_FIC	0x20	/* First In Chassis Flag */
302412a8245SMichael S. Tsirkin #define PCI_SID_CHASSIS_NR	3	/* Chassis Number */
303412a8245SMichael S. Tsirkin 
304ef17dd6aSVivek Goyal /* Message Signaled Interrupt registers */
305412a8245SMichael S. Tsirkin 
306ef17dd6aSVivek Goyal #define PCI_MSI_FLAGS		0x02	/* Message Control */
307120758fbSPaolo Bonzini #define  PCI_MSI_FLAGS_ENABLE	0x0001	/* MSI feature enabled */
308120758fbSPaolo Bonzini #define  PCI_MSI_FLAGS_QMASK	0x000e	/* Maximum queue size available */
309120758fbSPaolo Bonzini #define  PCI_MSI_FLAGS_QSIZE	0x0070	/* Message queue size configured */
310120758fbSPaolo Bonzini #define  PCI_MSI_FLAGS_64BIT	0x0080	/* 64-bit addresses allowed */
311120758fbSPaolo Bonzini #define  PCI_MSI_FLAGS_MASKBIT	0x0100	/* Per-vector masking capable */
312412a8245SMichael S. Tsirkin #define PCI_MSI_RFU		3	/* Rest of capability flags */
313ef17dd6aSVivek Goyal #define PCI_MSI_ADDRESS_LO	0x04	/* Lower 32 bits */
314ef17dd6aSVivek Goyal #define PCI_MSI_ADDRESS_HI	0x08	/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
315ef17dd6aSVivek Goyal #define PCI_MSI_DATA_32		0x08	/* 16 bits of data for 32-bit devices */
316ef17dd6aSVivek Goyal #define PCI_MSI_MASK_32		0x0c	/* Mask bits register for 32-bit devices */
317ef17dd6aSVivek Goyal #define PCI_MSI_PENDING_32	0x10	/* Pending intrs for 32-bit devices */
318ef17dd6aSVivek Goyal #define PCI_MSI_DATA_64		0x0c	/* 16 bits of data for 64-bit devices */
319ef17dd6aSVivek Goyal #define PCI_MSI_MASK_64		0x10	/* Mask bits register for 64-bit devices */
320ef17dd6aSVivek Goyal #define PCI_MSI_PENDING_64	0x14	/* Pending intrs for 64-bit devices */
321412a8245SMichael S. Tsirkin 
322d9cb4336SCornelia Huck /* MSI-X registers (in MSI-X capability) */
323120758fbSPaolo Bonzini #define PCI_MSIX_FLAGS		2	/* Message Control */
324120758fbSPaolo Bonzini #define  PCI_MSIX_FLAGS_QSIZE	0x07FF	/* Table size */
325120758fbSPaolo Bonzini #define  PCI_MSIX_FLAGS_MASKALL	0x4000	/* Mask all vectors for this function */
326120758fbSPaolo Bonzini #define  PCI_MSIX_FLAGS_ENABLE	0x8000	/* MSI-X enable */
327120758fbSPaolo Bonzini #define PCI_MSIX_TABLE		4	/* Table offset */
328120758fbSPaolo Bonzini #define  PCI_MSIX_TABLE_BIR	0x00000007 /* BAR index */
329120758fbSPaolo Bonzini #define  PCI_MSIX_TABLE_OFFSET	0xfffffff8 /* Offset into specified BAR */
330120758fbSPaolo Bonzini #define PCI_MSIX_PBA		8	/* Pending Bit Array offset */
331120758fbSPaolo Bonzini #define  PCI_MSIX_PBA_BIR	0x00000007 /* BAR index */
332120758fbSPaolo Bonzini #define  PCI_MSIX_PBA_OFFSET	0xfffffff8 /* Offset into specified BAR */
333120758fbSPaolo Bonzini #define PCI_MSIX_FLAGS_BIRMASK	PCI_MSIX_PBA_BIR /* deprecated */
334120758fbSPaolo Bonzini #define PCI_CAP_MSIX_SIZEOF	12	/* size of MSIX registers */
335412a8245SMichael S. Tsirkin 
336d9cb4336SCornelia Huck /* MSI-X Table entry format (in memory mapped by a BAR) */
337412a8245SMichael S. Tsirkin #define PCI_MSIX_ENTRY_SIZE		16
338ef17dd6aSVivek Goyal #define PCI_MSIX_ENTRY_LOWER_ADDR	0x0  /* Message Address */
339ef17dd6aSVivek Goyal #define PCI_MSIX_ENTRY_UPPER_ADDR	0x4  /* Message Upper Address */
340ef17dd6aSVivek Goyal #define PCI_MSIX_ENTRY_DATA		0x8  /* Message Data */
341ef17dd6aSVivek Goyal #define PCI_MSIX_ENTRY_VECTOR_CTRL	0xc  /* Vector Control */
342d9cb4336SCornelia Huck #define  PCI_MSIX_ENTRY_CTRL_MASKBIT	0x00000001
343412a8245SMichael S. Tsirkin 
344412a8245SMichael S. Tsirkin /* CompactPCI Hotswap Register */
345412a8245SMichael S. Tsirkin 
346412a8245SMichael S. Tsirkin #define PCI_CHSWP_CSR		2	/* Control and Status Register */
347412a8245SMichael S. Tsirkin #define  PCI_CHSWP_DHA		0x01	/* Device Hiding Arm */
348412a8245SMichael S. Tsirkin #define  PCI_CHSWP_EIM		0x02	/* ENUM# Signal Mask */
349412a8245SMichael S. Tsirkin #define  PCI_CHSWP_PIE		0x04	/* Pending Insert or Extract */
350412a8245SMichael S. Tsirkin #define  PCI_CHSWP_LOO		0x08	/* LED On / Off */
351412a8245SMichael S. Tsirkin #define  PCI_CHSWP_PI		0x30	/* Programming Interface */
352412a8245SMichael S. Tsirkin #define  PCI_CHSWP_EXT		0x40	/* ENUM# status - extraction */
353412a8245SMichael S. Tsirkin #define  PCI_CHSWP_INS		0x80	/* ENUM# status - insertion */
354412a8245SMichael S. Tsirkin 
355412a8245SMichael S. Tsirkin /* PCI Advanced Feature registers */
356412a8245SMichael S. Tsirkin 
357412a8245SMichael S. Tsirkin #define PCI_AF_LENGTH		2
358412a8245SMichael S. Tsirkin #define PCI_AF_CAP		3
359412a8245SMichael S. Tsirkin #define  PCI_AF_CAP_TP		0x01
360412a8245SMichael S. Tsirkin #define  PCI_AF_CAP_FLR		0x02
361412a8245SMichael S. Tsirkin #define PCI_AF_CTRL		4
362412a8245SMichael S. Tsirkin #define  PCI_AF_CTRL_FLR	0x01
363412a8245SMichael S. Tsirkin #define PCI_AF_STATUS		5
364412a8245SMichael S. Tsirkin #define  PCI_AF_STATUS_TP	0x01
365120758fbSPaolo Bonzini #define PCI_CAP_AF_SIZEOF	6	/* size of AF registers */
366412a8245SMichael S. Tsirkin 
367fff02bc0SPaolo Bonzini /* PCI Enhanced Allocation registers */
368fff02bc0SPaolo Bonzini 
369fff02bc0SPaolo Bonzini #define PCI_EA_NUM_ENT		2	/* Number of Capability Entries */
370fff02bc0SPaolo Bonzini #define  PCI_EA_NUM_ENT_MASK	0x3f	/* Num Entries Mask */
371fff02bc0SPaolo Bonzini #define PCI_EA_FIRST_ENT	4	/* First EA Entry in List */
372fff02bc0SPaolo Bonzini #define PCI_EA_FIRST_ENT_BRIDGE	8	/* First EA Entry for Bridges */
373fff02bc0SPaolo Bonzini #define  PCI_EA_ES		0x00000007 /* Entry Size */
374fff02bc0SPaolo Bonzini #define  PCI_EA_BEI		0x000000f0 /* BAR Equivalent Indicator */
375d9cb4336SCornelia Huck 
376d9cb4336SCornelia Huck /* EA fixed Secondary and Subordinate bus numbers for Bridge */
377d9cb4336SCornelia Huck #define PCI_EA_SEC_BUS_MASK	0xff
378d9cb4336SCornelia Huck #define PCI_EA_SUB_BUS_MASK	0xff00
379d9cb4336SCornelia Huck #define PCI_EA_SUB_BUS_SHIFT	8
380d9cb4336SCornelia Huck 
381fff02bc0SPaolo Bonzini /* 0-5 map to BARs 0-5 respectively */
382fff02bc0SPaolo Bonzini #define   PCI_EA_BEI_BAR0		0
383fff02bc0SPaolo Bonzini #define   PCI_EA_BEI_BAR5		5
384fff02bc0SPaolo Bonzini #define   PCI_EA_BEI_BRIDGE		6	/* Resource behind bridge */
385fff02bc0SPaolo Bonzini #define   PCI_EA_BEI_ENI		7	/* Equivalent Not Indicated */
386fff02bc0SPaolo Bonzini #define   PCI_EA_BEI_ROM		8	/* Expansion ROM */
387fff02bc0SPaolo Bonzini /* 9-14 map to VF BARs 0-5 respectively */
388fff02bc0SPaolo Bonzini #define   PCI_EA_BEI_VF_BAR0		9
389fff02bc0SPaolo Bonzini #define   PCI_EA_BEI_VF_BAR5		14
390fff02bc0SPaolo Bonzini #define   PCI_EA_BEI_RESERVED		15	/* Reserved - Treat like ENI */
391fff02bc0SPaolo Bonzini #define  PCI_EA_PP		0x0000ff00	/* Primary Properties */
392fff02bc0SPaolo Bonzini #define  PCI_EA_SP		0x00ff0000	/* Secondary Properties */
393fff02bc0SPaolo Bonzini #define   PCI_EA_P_MEM			0x00	/* Non-Prefetch Memory */
394fff02bc0SPaolo Bonzini #define   PCI_EA_P_MEM_PREFETCH		0x01	/* Prefetchable Memory */
395fff02bc0SPaolo Bonzini #define   PCI_EA_P_IO			0x02	/* I/O Space */
396fff02bc0SPaolo Bonzini #define   PCI_EA_P_VF_MEM_PREFETCH	0x03	/* VF Prefetchable Memory */
397fff02bc0SPaolo Bonzini #define   PCI_EA_P_VF_MEM		0x04	/* VF Non-Prefetch Memory */
398fff02bc0SPaolo Bonzini #define   PCI_EA_P_BRIDGE_MEM		0x05	/* Bridge Non-Prefetch Memory */
399fff02bc0SPaolo Bonzini #define   PCI_EA_P_BRIDGE_MEM_PREFETCH	0x06	/* Bridge Prefetchable Memory */
400fff02bc0SPaolo Bonzini #define   PCI_EA_P_BRIDGE_IO		0x07	/* Bridge I/O Space */
401fff02bc0SPaolo Bonzini /* 0x08-0xfc reserved */
402fff02bc0SPaolo Bonzini #define   PCI_EA_P_MEM_RESERVED		0xfd	/* Reserved Memory */
403fff02bc0SPaolo Bonzini #define   PCI_EA_P_IO_RESERVED		0xfe	/* Reserved I/O Space */
404fff02bc0SPaolo Bonzini #define   PCI_EA_P_UNAVAILABLE		0xff	/* Entry Unavailable */
405fff02bc0SPaolo Bonzini #define  PCI_EA_WRITABLE	0x40000000	/* Writable: 1 = RW, 0 = HwInit */
406fff02bc0SPaolo Bonzini #define  PCI_EA_ENABLE		0x80000000	/* Enable for this entry */
407fff02bc0SPaolo Bonzini #define PCI_EA_BASE		4		/* Base Address Offset */
408fff02bc0SPaolo Bonzini #define PCI_EA_MAX_OFFSET	8		/* MaxOffset (resource length) */
409fff02bc0SPaolo Bonzini /* bit 0 is reserved */
410fff02bc0SPaolo Bonzini #define  PCI_EA_IS_64		0x00000002	/* 64-bit field flag */
411fff02bc0SPaolo Bonzini #define  PCI_EA_FIELD_MASK	0xfffffffc	/* For Base & Max Offset */
412fff02bc0SPaolo Bonzini 
413120758fbSPaolo Bonzini /* PCI-X registers (Type 0 (non-bridge) devices) */
414412a8245SMichael S. Tsirkin 
415412a8245SMichael S. Tsirkin #define PCI_X_CMD		2	/* Modes & Features */
416412a8245SMichael S. Tsirkin #define  PCI_X_CMD_DPERR_E	0x0001	/* Data Parity Error Recovery Enable */
417412a8245SMichael S. Tsirkin #define  PCI_X_CMD_ERO		0x0002	/* Enable Relaxed Ordering */
418412a8245SMichael S. Tsirkin #define  PCI_X_CMD_READ_512	0x0000	/* 512 byte maximum read byte count */
419412a8245SMichael S. Tsirkin #define  PCI_X_CMD_READ_1K	0x0004	/* 1Kbyte maximum read byte count */
420412a8245SMichael S. Tsirkin #define  PCI_X_CMD_READ_2K	0x0008	/* 2Kbyte maximum read byte count */
421412a8245SMichael S. Tsirkin #define  PCI_X_CMD_READ_4K	0x000c	/* 4Kbyte maximum read byte count */
422412a8245SMichael S. Tsirkin #define  PCI_X_CMD_MAX_READ	0x000c	/* Max Memory Read Byte Count */
423412a8245SMichael S. Tsirkin 				/* Max # of outstanding split transactions */
424412a8245SMichael S. Tsirkin #define  PCI_X_CMD_SPLIT_1	0x0000	/* Max 1 */
425412a8245SMichael S. Tsirkin #define  PCI_X_CMD_SPLIT_2	0x0010	/* Max 2 */
426412a8245SMichael S. Tsirkin #define  PCI_X_CMD_SPLIT_3	0x0020	/* Max 3 */
427412a8245SMichael S. Tsirkin #define  PCI_X_CMD_SPLIT_4	0x0030	/* Max 4 */
428412a8245SMichael S. Tsirkin #define  PCI_X_CMD_SPLIT_8	0x0040	/* Max 8 */
429412a8245SMichael S. Tsirkin #define  PCI_X_CMD_SPLIT_12	0x0050	/* Max 12 */
430412a8245SMichael S. Tsirkin #define  PCI_X_CMD_SPLIT_16	0x0060	/* Max 16 */
431412a8245SMichael S. Tsirkin #define  PCI_X_CMD_SPLIT_32	0x0070	/* Max 32 */
432412a8245SMichael S. Tsirkin #define  PCI_X_CMD_MAX_SPLIT	0x0070	/* Max Outstanding Split Transactions */
433412a8245SMichael S. Tsirkin #define  PCI_X_CMD_VERSION(x)	(((x) >> 12) & 3) /* Version */
434412a8245SMichael S. Tsirkin #define PCI_X_STATUS		4	/* PCI-X capabilities */
435412a8245SMichael S. Tsirkin #define  PCI_X_STATUS_DEVFN	0x000000ff	/* A copy of devfn */
436412a8245SMichael S. Tsirkin #define  PCI_X_STATUS_BUS	0x0000ff00	/* A copy of bus nr */
437412a8245SMichael S. Tsirkin #define  PCI_X_STATUS_64BIT	0x00010000	/* 64-bit device */
438412a8245SMichael S. Tsirkin #define  PCI_X_STATUS_133MHZ	0x00020000	/* 133 MHz capable */
439412a8245SMichael S. Tsirkin #define  PCI_X_STATUS_SPL_DISC	0x00040000	/* Split Completion Discarded */
440412a8245SMichael S. Tsirkin #define  PCI_X_STATUS_UNX_SPL	0x00080000	/* Unexpected Split Completion */
441412a8245SMichael S. Tsirkin #define  PCI_X_STATUS_COMPLEX	0x00100000	/* Device Complexity */
442412a8245SMichael S. Tsirkin #define  PCI_X_STATUS_MAX_READ	0x00600000	/* Designed Max Memory Read Count */
443412a8245SMichael S. Tsirkin #define  PCI_X_STATUS_MAX_SPLIT	0x03800000	/* Designed Max Outstanding Split Transactions */
444412a8245SMichael S. Tsirkin #define  PCI_X_STATUS_MAX_CUM	0x1c000000	/* Designed Max Cumulative Read Size */
445412a8245SMichael S. Tsirkin #define  PCI_X_STATUS_SPL_ERR	0x20000000	/* Rcvd Split Completion Error Msg */
446412a8245SMichael S. Tsirkin #define  PCI_X_STATUS_266MHZ	0x40000000	/* 266 MHz capable */
447412a8245SMichael S. Tsirkin #define  PCI_X_STATUS_533MHZ	0x80000000	/* 533 MHz capable */
448120758fbSPaolo Bonzini #define PCI_X_ECC_CSR		8	/* ECC control and status */
449120758fbSPaolo Bonzini #define PCI_CAP_PCIX_SIZEOF_V0	8	/* size of registers for Version 0 */
450120758fbSPaolo Bonzini #define PCI_CAP_PCIX_SIZEOF_V1	24	/* size for Version 1 */
451120758fbSPaolo Bonzini #define PCI_CAP_PCIX_SIZEOF_V2	PCI_CAP_PCIX_SIZEOF_V1	/* Same for v2 */
452120758fbSPaolo Bonzini 
453120758fbSPaolo Bonzini /* PCI-X registers (Type 1 (bridge) devices) */
454120758fbSPaolo Bonzini 
455120758fbSPaolo Bonzini #define PCI_X_BRIDGE_SSTATUS	2	/* Secondary Status */
456120758fbSPaolo Bonzini #define  PCI_X_SSTATUS_64BIT	0x0001	/* Secondary AD interface is 64 bits */
457120758fbSPaolo Bonzini #define  PCI_X_SSTATUS_133MHZ	0x0002	/* 133 MHz capable */
458120758fbSPaolo Bonzini #define  PCI_X_SSTATUS_FREQ	0x03c0	/* Secondary Bus Mode and Frequency */
459120758fbSPaolo Bonzini #define  PCI_X_SSTATUS_VERS	0x3000	/* PCI-X Capability Version */
460120758fbSPaolo Bonzini #define  PCI_X_SSTATUS_V1	0x1000	/* Mode 2, not Mode 1 */
461120758fbSPaolo Bonzini #define  PCI_X_SSTATUS_V2	0x2000	/* Mode 1 or Modes 1 and 2 */
462120758fbSPaolo Bonzini #define  PCI_X_SSTATUS_266MHZ	0x4000	/* 266 MHz capable */
463120758fbSPaolo Bonzini #define  PCI_X_SSTATUS_533MHZ	0x8000	/* 533 MHz capable */
464120758fbSPaolo Bonzini #define PCI_X_BRIDGE_STATUS	4	/* Bridge Status */
465412a8245SMichael S. Tsirkin 
466412a8245SMichael S. Tsirkin /* PCI Bridge Subsystem ID registers */
467412a8245SMichael S. Tsirkin 
468120758fbSPaolo Bonzini #define PCI_SSVID_VENDOR_ID     4	/* PCI Bridge subsystem vendor ID */
469120758fbSPaolo Bonzini #define PCI_SSVID_DEVICE_ID     6	/* PCI Bridge subsystem device ID */
470412a8245SMichael S. Tsirkin 
471412a8245SMichael S. Tsirkin /* PCI Express capability registers */
472412a8245SMichael S. Tsirkin 
473ef17dd6aSVivek Goyal #define PCI_EXP_FLAGS		0x02	/* Capabilities register */
474412a8245SMichael S. Tsirkin #define  PCI_EXP_FLAGS_VERS	0x000f	/* Capability version */
475412a8245SMichael S. Tsirkin #define  PCI_EXP_FLAGS_TYPE	0x00f0	/* Device/Port type */
476412a8245SMichael S. Tsirkin #define   PCI_EXP_TYPE_ENDPOINT	   0x0	/* Express Endpoint */
477412a8245SMichael S. Tsirkin #define   PCI_EXP_TYPE_LEG_END	   0x1	/* Legacy Endpoint */
478412a8245SMichael S. Tsirkin #define   PCI_EXP_TYPE_ROOT_PORT   0x4	/* Root Port */
479412a8245SMichael S. Tsirkin #define   PCI_EXP_TYPE_UPSTREAM	   0x5	/* Upstream Port */
480412a8245SMichael S. Tsirkin #define   PCI_EXP_TYPE_DOWNSTREAM  0x6	/* Downstream Port */
481120758fbSPaolo Bonzini #define   PCI_EXP_TYPE_PCI_BRIDGE  0x7	/* PCIe to PCI/PCI-X Bridge */
482120758fbSPaolo Bonzini #define   PCI_EXP_TYPE_PCIE_BRIDGE 0x8	/* PCI/PCI-X to PCIe Bridge */
483412a8245SMichael S. Tsirkin #define   PCI_EXP_TYPE_RC_END	   0x9	/* Root Complex Integrated Endpoint */
484412a8245SMichael S. Tsirkin #define   PCI_EXP_TYPE_RC_EC	   0xa	/* Root Complex Event Collector */
485412a8245SMichael S. Tsirkin #define  PCI_EXP_FLAGS_SLOT	0x0100	/* Slot implemented */
486412a8245SMichael S. Tsirkin #define  PCI_EXP_FLAGS_IRQ	0x3e00	/* Interrupt message number */
487ef17dd6aSVivek Goyal #define PCI_EXP_DEVCAP		0x04	/* Device capabilities */
488120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP_PAYLOAD	0x00000007 /* Max_Payload_Size */
489120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP_PHANTOM	0x00000018 /* Phantom functions */
490120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP_EXT_TAG	0x00000020 /* Extended tags */
491120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP_L0S	0x000001c0 /* L0s Acceptable Latency */
492120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP_L1	0x00000e00 /* L1 Acceptable Latency */
493120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP_ATN_BUT	0x00001000 /* Attention Button Present */
494120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP_ATN_IND	0x00002000 /* Attention Indicator Present */
495120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP_PWR_IND	0x00004000 /* Power Indicator Present */
496120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP_RBER	0x00008000 /* Role-Based Error Reporting */
497120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP_PWR_VAL	0x03fc0000 /* Slot Power Limit Value */
498120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP_PWR_SCL	0x0c000000 /* Slot Power Limit Scale */
499412a8245SMichael S. Tsirkin #define  PCI_EXP_DEVCAP_FLR     0x10000000 /* Function Level Reset */
500ef17dd6aSVivek Goyal #define PCI_EXP_DEVCTL		0x08	/* Device Control */
501412a8245SMichael S. Tsirkin #define  PCI_EXP_DEVCTL_CERE	0x0001	/* Correctable Error Reporting En. */
502412a8245SMichael S. Tsirkin #define  PCI_EXP_DEVCTL_NFERE	0x0002	/* Non-Fatal Error Reporting Enable */
503412a8245SMichael S. Tsirkin #define  PCI_EXP_DEVCTL_FERE	0x0004	/* Fatal Error Reporting Enable */
504412a8245SMichael S. Tsirkin #define  PCI_EXP_DEVCTL_URRE	0x0008	/* Unsupported Request Reporting En. */
505412a8245SMichael S. Tsirkin #define  PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
506412a8245SMichael S. Tsirkin #define  PCI_EXP_DEVCTL_PAYLOAD	0x00e0	/* Max_Payload_Size */
50743709a0cSPaolo Bonzini #define  PCI_EXP_DEVCTL_PAYLOAD_128B 0x0000 /* 128 Bytes */
50843709a0cSPaolo Bonzini #define  PCI_EXP_DEVCTL_PAYLOAD_256B 0x0020 /* 256 Bytes */
50943709a0cSPaolo Bonzini #define  PCI_EXP_DEVCTL_PAYLOAD_512B 0x0040 /* 512 Bytes */
51043709a0cSPaolo Bonzini #define  PCI_EXP_DEVCTL_PAYLOAD_1024B 0x0060 /* 1024 Bytes */
51143709a0cSPaolo Bonzini #define  PCI_EXP_DEVCTL_PAYLOAD_2048B 0x0080 /* 2048 Bytes */
51243709a0cSPaolo Bonzini #define  PCI_EXP_DEVCTL_PAYLOAD_4096B 0x00a0 /* 4096 Bytes */
513412a8245SMichael S. Tsirkin #define  PCI_EXP_DEVCTL_EXT_TAG	0x0100	/* Extended Tag Field Enable */
514412a8245SMichael S. Tsirkin #define  PCI_EXP_DEVCTL_PHANTOM	0x0200	/* Phantom Functions Enable */
515412a8245SMichael S. Tsirkin #define  PCI_EXP_DEVCTL_AUX_PME	0x0400	/* Auxiliary Power PM Enable */
516412a8245SMichael S. Tsirkin #define  PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800  /* Enable No Snoop */
517412a8245SMichael S. Tsirkin #define  PCI_EXP_DEVCTL_READRQ	0x7000	/* Max_Read_Request_Size */
518120758fbSPaolo Bonzini #define  PCI_EXP_DEVCTL_READRQ_128B  0x0000 /* 128 Bytes */
519120758fbSPaolo Bonzini #define  PCI_EXP_DEVCTL_READRQ_256B  0x1000 /* 256 Bytes */
520120758fbSPaolo Bonzini #define  PCI_EXP_DEVCTL_READRQ_512B  0x2000 /* 512 Bytes */
521120758fbSPaolo Bonzini #define  PCI_EXP_DEVCTL_READRQ_1024B 0x3000 /* 1024 Bytes */
52277d361b1SEric Auger #define  PCI_EXP_DEVCTL_READRQ_2048B 0x4000 /* 2048 Bytes */
52377d361b1SEric Auger #define  PCI_EXP_DEVCTL_READRQ_4096B 0x5000 /* 4096 Bytes */
524412a8245SMichael S. Tsirkin #define  PCI_EXP_DEVCTL_BCR_FLR 0x8000  /* Bridge Configuration Retry / FLR */
525ef17dd6aSVivek Goyal #define PCI_EXP_DEVSTA		0x0a	/* Device Status */
526120758fbSPaolo Bonzini #define  PCI_EXP_DEVSTA_CED	0x0001	/* Correctable Error Detected */
527120758fbSPaolo Bonzini #define  PCI_EXP_DEVSTA_NFED	0x0002	/* Non-Fatal Error Detected */
528120758fbSPaolo Bonzini #define  PCI_EXP_DEVSTA_FED	0x0004	/* Fatal Error Detected */
529120758fbSPaolo Bonzini #define  PCI_EXP_DEVSTA_URD	0x0008	/* Unsupported Request Detected */
530120758fbSPaolo Bonzini #define  PCI_EXP_DEVSTA_AUXPD	0x0010	/* AUX Power Detected */
531120758fbSPaolo Bonzini #define  PCI_EXP_DEVSTA_TRPND	0x0020	/* Transactions Pending */
532d4083f50SAlexey Perevalov #define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V1	12	/* v1 endpoints without link end here */
533ef17dd6aSVivek Goyal #define PCI_EXP_LNKCAP		0x0c	/* Link Capabilities */
534412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCAP_SLS	0x0000000f /* Supported Link Speeds */
535120758fbSPaolo Bonzini #define  PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */
536120758fbSPaolo Bonzini #define  PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
5373272f0e2SChristian Borntraeger #define  PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
53865a6d8ddSPeter Maydell #define  PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */
539f363d039SEric Auger #define  PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */
540b3c818a4SEric Farman #define  PCI_EXP_LNKCAP_SLS_64_0GB 0x00000006 /* LNKCAP2 SLS Vector bit 5 */
541412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCAP_MLW	0x000003f0 /* Maximum Link Width */
542412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCAP_ASPMS	0x00000c00 /* ASPM Support */
54353ba2eeeSMatthew Rosato #define  PCI_EXP_LNKCAP_ASPM_L0S 0x00000400 /* ASPM L0s Support */
54453ba2eeeSMatthew Rosato #define  PCI_EXP_LNKCAP_ASPM_L1  0x00000800 /* ASPM L1 Support */
545412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCAP_L0SEL	0x00007000 /* L0s Exit Latency */
546412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCAP_L1EL	0x00038000 /* L1 Exit Latency */
547120758fbSPaolo Bonzini #define  PCI_EXP_LNKCAP_CLKPM	0x00040000 /* Clock Power Management */
548412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCAP_SDERC	0x00080000 /* Surprise Down Error Reporting Capable */
549412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCAP_DLLLARC	0x00100000 /* Data Link Layer Link Active Reporting Capable */
550412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCAP_LBNC	0x00200000 /* Link Bandwidth Notification Capability */
551412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCAP_PN	0xff000000 /* Port Number */
552ef17dd6aSVivek Goyal #define PCI_EXP_LNKCTL		0x10	/* Link Control */
553412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCTL_ASPMC	0x0003	/* ASPM Control */
554120758fbSPaolo Bonzini #define  PCI_EXP_LNKCTL_ASPM_L0S 0x0001	/* L0s Enable */
555120758fbSPaolo Bonzini #define  PCI_EXP_LNKCTL_ASPM_L1  0x0002	/* L1 Enable */
556412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCTL_RCB	0x0008	/* Read Completion Boundary */
557412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCTL_LD	0x0010	/* Link Disable */
558412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCTL_RL	0x0020	/* Retrain Link */
559412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCTL_CCC	0x0040	/* Common Clock Configuration */
560412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCTL_ES	0x0080	/* Extended Synch */
561120758fbSPaolo Bonzini #define  PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 /* Enable clkreq */
562412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCTL_HAWD	0x0200	/* Hardware Autonomous Width Disable */
563412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKCTL_LBMIE	0x0400	/* Link Bandwidth Management Interrupt Enable */
564120758fbSPaolo Bonzini #define  PCI_EXP_LNKCTL_LABIE	0x0800	/* Link Autonomous Bandwidth Interrupt Enable */
565ef17dd6aSVivek Goyal #define PCI_EXP_LNKSTA		0x12	/* Link Status */
566412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKSTA_CLS	0x000f	/* Current Link Speed */
567120758fbSPaolo Bonzini #define  PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
568120758fbSPaolo Bonzini #define  PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
569120758fbSPaolo Bonzini #define  PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
57065a6d8ddSPeter Maydell #define  PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */
571f363d039SEric Auger #define  PCI_EXP_LNKSTA_CLS_32_0GB 0x0005 /* Current Link Speed 32.0GT/s */
572b3c818a4SEric Farman #define  PCI_EXP_LNKSTA_CLS_64_0GB 0x0006 /* Current Link Speed 64.0GT/s */
573120758fbSPaolo Bonzini #define  PCI_EXP_LNKSTA_NLW	0x03f0	/* Negotiated Link Width */
574120758fbSPaolo Bonzini #define  PCI_EXP_LNKSTA_NLW_X1	0x0010	/* Current Link Width x1 */
575120758fbSPaolo Bonzini #define  PCI_EXP_LNKSTA_NLW_X2	0x0020	/* Current Link Width x2 */
576120758fbSPaolo Bonzini #define  PCI_EXP_LNKSTA_NLW_X4	0x0040	/* Current Link Width x4 */
577120758fbSPaolo Bonzini #define  PCI_EXP_LNKSTA_NLW_X8	0x0080	/* Current Link Width x8 */
578412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKSTA_NLW_SHIFT 4	/* start of NLW mask in link status */
579412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKSTA_LT	0x0800	/* Link Training */
580412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKSTA_SLC	0x1000	/* Slot Clock Configuration */
581412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKSTA_DLLLA	0x2000	/* Data Link Layer Link Active */
582412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKSTA_LBMS	0x4000	/* Link Bandwidth Management Status */
583412a8245SMichael S. Tsirkin #define  PCI_EXP_LNKSTA_LABS	0x8000	/* Link Autonomous Bandwidth Status */
584d4083f50SAlexey Perevalov #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1	20	/* v1 endpoints with link end here */
585ef17dd6aSVivek Goyal #define PCI_EXP_SLTCAP		0x14	/* Slot Capabilities */
586412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCAP_ABP	0x00000001 /* Attention Button Present */
587412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCAP_PCP	0x00000002 /* Power Controller Present */
588412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCAP_MRLSP	0x00000004 /* MRL Sensor Present */
589412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCAP_AIP	0x00000008 /* Attention Indicator Present */
590412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCAP_PIP	0x00000010 /* Power Indicator Present */
591412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCAP_HPS	0x00000020 /* Hot-Plug Surprise */
592412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCAP_HPC	0x00000040 /* Hot-Plug Capable */
593412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCAP_SPLV	0x00007f80 /* Slot Power Limit Value */
594412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCAP_SPLS	0x00018000 /* Slot Power Limit Scale */
595412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCAP_EIP	0x00020000 /* Electromechanical Interlock Present */
596412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCAP_NCCS	0x00040000 /* No Command Completed Support */
597412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCAP_PSN	0xfff80000 /* Physical Slot Number */
598ef17dd6aSVivek Goyal #define PCI_EXP_SLTCTL		0x18	/* Slot Control */
599412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCTL_ABPE	0x0001	/* Attention Button Pressed Enable */
600412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCTL_PFDE	0x0002	/* Power Fault Detected Enable */
601412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCTL_MRLSCE	0x0004	/* MRL Sensor Changed Enable */
602412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCTL_PDCE	0x0008	/* Presence Detect Changed Enable */
603412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCTL_CCIE	0x0010	/* Command Completed Interrupt Enable */
604412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCTL_HPIE	0x0020	/* Hot-Plug Interrupt Enable */
605412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCTL_AIC	0x00c0	/* Attention Indicator Control */
606f363d039SEric Auger #define  PCI_EXP_SLTCTL_ATTN_IND_SHIFT 6      /* Attention Indicator shift */
607120758fbSPaolo Bonzini #define  PCI_EXP_SLTCTL_ATTN_IND_ON    0x0040 /* Attention Indicator on */
608120758fbSPaolo Bonzini #define  PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 /* Attention Indicator blinking */
609120758fbSPaolo Bonzini #define  PCI_EXP_SLTCTL_ATTN_IND_OFF   0x00c0 /* Attention Indicator off */
610412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCTL_PIC	0x0300	/* Power Indicator Control */
611120758fbSPaolo Bonzini #define  PCI_EXP_SLTCTL_PWR_IND_ON     0x0100 /* Power Indicator on */
612120758fbSPaolo Bonzini #define  PCI_EXP_SLTCTL_PWR_IND_BLINK  0x0200 /* Power Indicator blinking */
613120758fbSPaolo Bonzini #define  PCI_EXP_SLTCTL_PWR_IND_OFF    0x0300 /* Power Indicator off */
614412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCTL_PCC	0x0400	/* Power Controller Control */
615120758fbSPaolo Bonzini #define  PCI_EXP_SLTCTL_PWR_ON         0x0000 /* Power On */
616120758fbSPaolo Bonzini #define  PCI_EXP_SLTCTL_PWR_OFF        0x0400 /* Power Off */
617412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCTL_EIC	0x0800	/* Electromechanical Interlock Control */
618412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTCTL_DLLSCE	0x1000	/* Data Link Layer State Changed Enable */
619d525f73fSChenyi Qiang #define  PCI_EXP_SLTCTL_ASPL_DISABLE	0x2000 /* Auto Slot Power Limit Disable */
620dc6f8d45SCornelia Huck #define  PCI_EXP_SLTCTL_IBPD_DISABLE	0x4000 /* In-band PD disable */
621ef17dd6aSVivek Goyal #define PCI_EXP_SLTSTA		0x1a	/* Slot Status */
622412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTSTA_ABP	0x0001	/* Attention Button Pressed */
623412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTSTA_PFD	0x0002	/* Power Fault Detected */
624412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTSTA_MRLSC	0x0004	/* MRL Sensor Changed */
625412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTSTA_PDC	0x0008	/* Presence Detect Changed */
626412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTSTA_CC	0x0010	/* Command Completed */
627412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTSTA_MRLSS	0x0020	/* MRL Sensor State */
628412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTSTA_PDS	0x0040	/* Presence Detect State */
629412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTSTA_EIS	0x0080	/* Electromechanical Interlock Status */
630412a8245SMichael S. Tsirkin #define  PCI_EXP_SLTSTA_DLLSC	0x0100	/* Data Link Layer State Changed */
631ef17dd6aSVivek Goyal #define PCI_EXP_RTCTL		0x1c	/* Root Control */
632120758fbSPaolo Bonzini #define  PCI_EXP_RTCTL_SECEE	0x0001	/* System Error on Correctable Error */
633120758fbSPaolo Bonzini #define  PCI_EXP_RTCTL_SENFEE	0x0002	/* System Error on Non-Fatal Error */
634120758fbSPaolo Bonzini #define  PCI_EXP_RTCTL_SEFEE	0x0004	/* System Error on Fatal Error */
635120758fbSPaolo Bonzini #define  PCI_EXP_RTCTL_PMEIE	0x0008	/* PME Interrupt Enable */
636120758fbSPaolo Bonzini #define  PCI_EXP_RTCTL_CRSSVE	0x0010	/* CRS Software Visibility Enable */
637ef17dd6aSVivek Goyal #define PCI_EXP_RTCAP		0x1e	/* Root Capabilities */
638120758fbSPaolo Bonzini #define  PCI_EXP_RTCAP_CRSVIS	0x0001	/* CRS Software Visibility capability */
639ef17dd6aSVivek Goyal #define PCI_EXP_RTSTA		0x20	/* Root Status */
640120758fbSPaolo Bonzini #define  PCI_EXP_RTSTA_PME	0x00010000 /* PME status */
641120758fbSPaolo Bonzini #define  PCI_EXP_RTSTA_PENDING	0x00020000 /* PME pending */
642120758fbSPaolo Bonzini /*
643120758fbSPaolo Bonzini  * The Device Capabilities 2, Device Status 2, Device Control 2,
644120758fbSPaolo Bonzini  * Link Capabilities 2, Link Status 2, Link Control 2,
645120758fbSPaolo Bonzini  * Slot Capabilities 2, Slot Status 2, and Slot Control 2 registers
646120758fbSPaolo Bonzini  * are only present on devices with PCIe Capability version 2.
647120758fbSPaolo Bonzini  * Use pcie_capability_read_word() and similar interfaces to use them
648120758fbSPaolo Bonzini  * safely.
649120758fbSPaolo Bonzini  */
650ef17dd6aSVivek Goyal #define PCI_EXP_DEVCAP2		0x24	/* Device Capabilities 2 */
6519f2d175dSPaolo Bonzini #define  PCI_EXP_DEVCAP2_COMP_TMOUT_DIS	0x00000010 /* Completion Timeout Disable supported */
652120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP2_ARI		0x00000020 /* Alternative Routing-ID */
653bc204035SMarcelo Tosatti #define  PCI_EXP_DEVCAP2_ATOMIC_ROUTE	0x00000040 /* Atomic Op routing */
6549f2d175dSPaolo Bonzini #define  PCI_EXP_DEVCAP2_ATOMIC_COMP32	0x00000080 /* 32b AtomicOp completion */
6559f2d175dSPaolo Bonzini #define  PCI_EXP_DEVCAP2_ATOMIC_COMP64	0x00000100 /* 64b AtomicOp completion */
6569f2d175dSPaolo Bonzini #define  PCI_EXP_DEVCAP2_ATOMIC_COMP128	0x00000200 /* 128b AtomicOp completion */
657120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP2_LTR		0x00000800 /* Latency tolerance reporting */
658120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP2_OBFF_MASK	0x000c0000 /* OBFF support mechanism */
659120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP2_OBFF_MSG	0x00040000 /* New message signaling */
660120758fbSPaolo Bonzini #define  PCI_EXP_DEVCAP2_OBFF_WAKE	0x00080000 /* Re-use WAKE# for OBFF */
661d36f7de8SCornelia Huck #define  PCI_EXP_DEVCAP2_EE_PREFIX	0x00200000 /* End-End TLP Prefix */
662ef17dd6aSVivek Goyal #define PCI_EXP_DEVCTL2		0x28	/* Device Control 2 */
663120758fbSPaolo Bonzini #define  PCI_EXP_DEVCTL2_COMP_TIMEOUT	0x000f	/* Completion Timeout Value */
6649f2d175dSPaolo Bonzini #define  PCI_EXP_DEVCTL2_COMP_TMOUT_DIS	0x0010	/* Completion Timeout Disable */
665120758fbSPaolo Bonzini #define  PCI_EXP_DEVCTL2_ARI		0x0020	/* Alternative Routing-ID */
666bc204035SMarcelo Tosatti #define  PCI_EXP_DEVCTL2_ATOMIC_REQ	0x0040	/* Set Atomic requests */
66774c98e20SCornelia Huck #define  PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */
668120758fbSPaolo Bonzini #define  PCI_EXP_DEVCTL2_IDO_REQ_EN	0x0100	/* Allow IDO for requests */
669120758fbSPaolo Bonzini #define  PCI_EXP_DEVCTL2_IDO_CMP_EN	0x0200	/* Allow IDO for completions */
670120758fbSPaolo Bonzini #define  PCI_EXP_DEVCTL2_LTR_EN		0x0400	/* Enable LTR mechanism */
671120758fbSPaolo Bonzini #define  PCI_EXP_DEVCTL2_OBFF_MSGA_EN	0x2000	/* Enable OBFF Message type A */
672120758fbSPaolo Bonzini #define  PCI_EXP_DEVCTL2_OBFF_MSGB_EN	0x4000	/* Enable OBFF Message type B */
673120758fbSPaolo Bonzini #define  PCI_EXP_DEVCTL2_OBFF_WAKE_EN	0x6000	/* OBFF using WAKE# signaling */
674ef17dd6aSVivek Goyal #define PCI_EXP_DEVSTA2		0x2a	/* Device Status 2 */
675ef17dd6aSVivek Goyal #define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 0x2c	/* end of v2 EPs w/o link */
676ef17dd6aSVivek Goyal #define PCI_EXP_LNKCAP2		0x2c	/* Link Capabilities 2 */
677120758fbSPaolo Bonzini #define  PCI_EXP_LNKCAP2_SLS_2_5GB	0x00000002 /* Supported Speed 2.5GT/s */
67865a6d8ddSPeter Maydell #define  PCI_EXP_LNKCAP2_SLS_5_0GB	0x00000004 /* Supported Speed 5GT/s */
67965a6d8ddSPeter Maydell #define  PCI_EXP_LNKCAP2_SLS_8_0GB	0x00000008 /* Supported Speed 8GT/s */
68065a6d8ddSPeter Maydell #define  PCI_EXP_LNKCAP2_SLS_16_0GB	0x00000010 /* Supported Speed 16GT/s */
681f363d039SEric Auger #define  PCI_EXP_LNKCAP2_SLS_32_0GB	0x00000020 /* Supported Speed 32GT/s */
682b3c818a4SEric Farman #define  PCI_EXP_LNKCAP2_SLS_64_0GB	0x00000040 /* Supported Speed 64GT/s */
683120758fbSPaolo Bonzini #define  PCI_EXP_LNKCAP2_CROSSLINK	0x00000100 /* Crosslink supported */
684ef17dd6aSVivek Goyal #define PCI_EXP_LNKCTL2		0x30	/* Link Control 2 */
68577d361b1SEric Auger #define  PCI_EXP_LNKCTL2_TLS		0x000f
68677d361b1SEric Auger #define  PCI_EXP_LNKCTL2_TLS_2_5GT	0x0001 /* Supported Speed 2.5GT/s */
68777d361b1SEric Auger #define  PCI_EXP_LNKCTL2_TLS_5_0GT	0x0002 /* Supported Speed 5GT/s */
68877d361b1SEric Auger #define  PCI_EXP_LNKCTL2_TLS_8_0GT	0x0003 /* Supported Speed 8GT/s */
68977d361b1SEric Auger #define  PCI_EXP_LNKCTL2_TLS_16_0GT	0x0004 /* Supported Speed 16GT/s */
690f363d039SEric Auger #define  PCI_EXP_LNKCTL2_TLS_32_0GT	0x0005 /* Supported Speed 32GT/s */
691b3c818a4SEric Farman #define  PCI_EXP_LNKCTL2_TLS_64_0GT	0x0006 /* Supported Speed 64GT/s */
69250fd0c37SBharata B Rao #define  PCI_EXP_LNKCTL2_ENTER_COMP	0x0010 /* Enter Compliance */
69350fd0c37SBharata B Rao #define  PCI_EXP_LNKCTL2_TX_MARGIN	0x0380 /* Transmit Margin */
694ddda3748SCornelia Huck #define  PCI_EXP_LNKCTL2_HASD		0x0020 /* HW Autonomous Speed Disable */
695ef17dd6aSVivek Goyal #define PCI_EXP_LNKSTA2		0x32	/* Link Status 2 */
696c5c0fdbeSDavid 'Digit' Turner #define  PCI_EXP_LNKSTA2_FLIT		0x0400 /* Flit Mode Status */
697ef17dd6aSVivek Goyal #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2	0x32	/* end of v2 EPs w/ link */
698ef17dd6aSVivek Goyal #define PCI_EXP_SLTCAP2		0x34	/* Slot Capabilities 2 */
699dc6f8d45SCornelia Huck #define  PCI_EXP_SLTCAP2_IBPD	0x00000001 /* In-band PD Disable Supported */
700ef17dd6aSVivek Goyal #define PCI_EXP_SLTCTL2		0x38	/* Slot Control 2 */
701ef17dd6aSVivek Goyal #define PCI_EXP_SLTSTA2		0x3a	/* Slot Status 2 */
702412a8245SMichael S. Tsirkin 
703412a8245SMichael S. Tsirkin /* Extended Capabilities (PCI-X 2.0 and Express) */
704412a8245SMichael S. Tsirkin #define PCI_EXT_CAP_ID(header)		(header & 0x0000ffff)
705412a8245SMichael S. Tsirkin #define PCI_EXT_CAP_VER(header)		((header >> 16) & 0xf)
706412a8245SMichael S. Tsirkin #define PCI_EXT_CAP_NEXT(header)	((header >> 20) & 0xffc)
707412a8245SMichael S. Tsirkin 
708120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_ERR	0x01	/* Advanced Error Reporting */
709120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_VC	0x02	/* Virtual Channel Capability */
710120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_DSN	0x03	/* Device Serial Number */
711120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_PWR	0x04	/* Power Budgeting */
712120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_RCLD	0x05	/* Root Complex Link Declaration */
713120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_RCILC	0x06	/* Root Complex Internal Link Control */
714120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_RCEC	0x07	/* Root Complex Event Collector */
715120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_MFVC	0x08	/* Multi-Function VC Capability */
716120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_VC9	0x09	/* same as _VC */
717120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_RCRB	0x0A	/* Root Complex RB? */
718120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_VNDR	0x0B	/* Vendor-Specific */
719120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_CAC	0x0C	/* Config Access - obsolete */
720120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_ACS	0x0D	/* Access Control Services */
721120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_ARI	0x0E	/* Alternate Routing ID */
722120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_ATS	0x0F	/* Address Translation Services */
723120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_SRIOV	0x10	/* Single Root I/O Virtualization */
724120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_MRIOV	0x11	/* Multi Root I/O Virtualization */
725120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_MCAST	0x12	/* Multicast */
726120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_PRI	0x13	/* Page Request Interface */
727120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_AMD_XXX	0x14	/* Reserved for AMD */
728120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_REBAR	0x15	/* Resizable BAR */
729120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_DPA	0x16	/* Dynamic Power Allocation */
730120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_TPH	0x17	/* TPH Requester */
731120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_LTR	0x18	/* Latency Tolerance Reporting */
732120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_SECPCI	0x19	/* Secondary PCIe Capability */
733120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_PMUX	0x1A	/* Protocol Multiplexing */
734120758fbSPaolo Bonzini #define PCI_EXT_CAP_ID_PASID	0x1B	/* Process Address Space ID */
735ff804f15SCornelia Huck #define PCI_EXT_CAP_ID_DPC	0x1D	/* Downstream Port Containment */
7363a5eb5b4SPaolo Bonzini #define PCI_EXT_CAP_ID_L1SS	0x1E	/* L1 PM Substates */
737bc204035SMarcelo Tosatti #define PCI_EXT_CAP_ID_PTM	0x1F	/* Precision Time Measurement */
738b3c818a4SEric Farman #define PCI_EXT_CAP_ID_DVSEC	0x23	/* Designated Vendor-Specific */
739f363d039SEric Auger #define PCI_EXT_CAP_ID_DLF	0x25	/* Data Link Feature */
740f363d039SEric Auger #define PCI_EXT_CAP_ID_PL_16GT	0x26	/* Physical Layer 16.0 GT/s */
741*d0bf492fSCédric Le Goater #define PCI_EXT_CAP_ID_PL_32GT  0x2A    /* Physical Layer 32.0 GT/s */
742d525f73fSChenyi Qiang #define PCI_EXT_CAP_ID_DOE	0x2E	/* Data Object Exchange */
743d525f73fSChenyi Qiang #define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_DOE
744120758fbSPaolo Bonzini 
745120758fbSPaolo Bonzini #define PCI_EXT_CAP_DSN_SIZEOF	12
746120758fbSPaolo Bonzini #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
747412a8245SMichael S. Tsirkin 
748412a8245SMichael S. Tsirkin /* Advanced Error Reporting */
749ef17dd6aSVivek Goyal #define PCI_ERR_UNCOR_STATUS	0x04	/* Uncorrectable Error Status */
750120758fbSPaolo Bonzini #define  PCI_ERR_UNC_UND	0x00000001	/* Undefined */
751412a8245SMichael S. Tsirkin #define  PCI_ERR_UNC_DLP	0x00000010	/* Data Link Protocol */
752120758fbSPaolo Bonzini #define  PCI_ERR_UNC_SURPDN	0x00000020	/* Surprise Down */
753412a8245SMichael S. Tsirkin #define  PCI_ERR_UNC_POISON_TLP	0x00001000	/* Poisoned TLP */
754412a8245SMichael S. Tsirkin #define  PCI_ERR_UNC_FCP	0x00002000	/* Flow Control Protocol */
755412a8245SMichael S. Tsirkin #define  PCI_ERR_UNC_COMP_TIME	0x00004000	/* Completion Timeout */
756412a8245SMichael S. Tsirkin #define  PCI_ERR_UNC_COMP_ABORT	0x00008000	/* Completer Abort */
757412a8245SMichael S. Tsirkin #define  PCI_ERR_UNC_UNX_COMP	0x00010000	/* Unexpected Completion */
758412a8245SMichael S. Tsirkin #define  PCI_ERR_UNC_RX_OVER	0x00020000	/* Receiver Overflow */
759412a8245SMichael S. Tsirkin #define  PCI_ERR_UNC_MALF_TLP	0x00040000	/* Malformed TLP */
760412a8245SMichael S. Tsirkin #define  PCI_ERR_UNC_ECRC	0x00080000	/* ECRC Error Status */
761412a8245SMichael S. Tsirkin #define  PCI_ERR_UNC_UNSUP	0x00100000	/* Unsupported Request */
762120758fbSPaolo Bonzini #define  PCI_ERR_UNC_ACSV	0x00200000	/* ACS Violation */
763120758fbSPaolo Bonzini #define  PCI_ERR_UNC_INTN	0x00400000	/* internal error */
764120758fbSPaolo Bonzini #define  PCI_ERR_UNC_MCBTLP	0x00800000	/* MC blocked TLP */
765120758fbSPaolo Bonzini #define  PCI_ERR_UNC_ATOMEG	0x01000000	/* Atomic egress blocked */
766120758fbSPaolo Bonzini #define  PCI_ERR_UNC_TLPPRE	0x02000000	/* TLP prefix blocked */
767ef17dd6aSVivek Goyal #define PCI_ERR_UNCOR_MASK	0x08	/* Uncorrectable Error Mask */
768412a8245SMichael S. Tsirkin 	/* Same bits as above */
769ef17dd6aSVivek Goyal #define PCI_ERR_UNCOR_SEVER	0x0c	/* Uncorrectable Error Severity */
770412a8245SMichael S. Tsirkin 	/* Same bits as above */
771ef17dd6aSVivek Goyal #define PCI_ERR_COR_STATUS	0x10	/* Correctable Error Status */
772412a8245SMichael S. Tsirkin #define  PCI_ERR_COR_RCVR	0x00000001	/* Receiver Error Status */
773412a8245SMichael S. Tsirkin #define  PCI_ERR_COR_BAD_TLP	0x00000040	/* Bad TLP Status */
774412a8245SMichael S. Tsirkin #define  PCI_ERR_COR_BAD_DLLP	0x00000080	/* Bad DLLP Status */
775412a8245SMichael S. Tsirkin #define  PCI_ERR_COR_REP_ROLL	0x00000100	/* REPLAY_NUM Rollover */
776412a8245SMichael S. Tsirkin #define  PCI_ERR_COR_REP_TIMER	0x00001000	/* Replay Timer Timeout */
777120758fbSPaolo Bonzini #define  PCI_ERR_COR_ADV_NFAT	0x00002000	/* Advisory Non-Fatal */
778120758fbSPaolo Bonzini #define  PCI_ERR_COR_INTERNAL	0x00004000	/* Corrected Internal */
779120758fbSPaolo Bonzini #define  PCI_ERR_COR_LOG_OVER	0x00008000	/* Header Log Overflow */
780ef17dd6aSVivek Goyal #define PCI_ERR_COR_MASK	0x14	/* Correctable Error Mask */
781412a8245SMichael S. Tsirkin 	/* Same bits as above */
782ef17dd6aSVivek Goyal #define PCI_ERR_CAP		0x18	/* Advanced Error Capabilities & Ctrl*/
783ef17dd6aSVivek Goyal #define  PCI_ERR_CAP_FEP(x)	((x) & 0x1f)	/* First Error Pointer */
784412a8245SMichael S. Tsirkin #define  PCI_ERR_CAP_ECRC_GENC	0x00000020	/* ECRC Generation Capable */
785412a8245SMichael S. Tsirkin #define  PCI_ERR_CAP_ECRC_GENE	0x00000040	/* ECRC Generation Enable */
786412a8245SMichael S. Tsirkin #define  PCI_ERR_CAP_ECRC_CHKC	0x00000080	/* ECRC Check Capable */
787412a8245SMichael S. Tsirkin #define  PCI_ERR_CAP_ECRC_CHKE	0x00000100	/* ECRC Check Enable */
788ef17dd6aSVivek Goyal #define PCI_ERR_HEADER_LOG	0x1c	/* Header Log Register (16 bytes) */
789ef17dd6aSVivek Goyal #define PCI_ERR_ROOT_COMMAND	0x2c	/* Root Error Command */
790d4083f50SAlexey Perevalov #define  PCI_ERR_ROOT_CMD_COR_EN	0x00000001 /* Correctable Err Reporting Enable */
791d4083f50SAlexey Perevalov #define  PCI_ERR_ROOT_CMD_NONFATAL_EN	0x00000002 /* Non-Fatal Err Reporting Enable */
792d4083f50SAlexey Perevalov #define  PCI_ERR_ROOT_CMD_FATAL_EN	0x00000004 /* Fatal Err Reporting Enable */
793ef17dd6aSVivek Goyal #define PCI_ERR_ROOT_STATUS	0x30
794412a8245SMichael S. Tsirkin #define  PCI_ERR_ROOT_COR_RCV		0x00000001 /* ERR_COR Received */
795d4083f50SAlexey Perevalov #define  PCI_ERR_ROOT_MULTI_COR_RCV	0x00000002 /* Multiple ERR_COR */
796d4083f50SAlexey Perevalov #define  PCI_ERR_ROOT_UNCOR_RCV		0x00000004 /* ERR_FATAL/NONFATAL */
797d4083f50SAlexey Perevalov #define  PCI_ERR_ROOT_MULTI_UNCOR_RCV	0x00000008 /* Multiple FATAL/NONFATAL */
798d4083f50SAlexey Perevalov #define  PCI_ERR_ROOT_FIRST_FATAL	0x00000010 /* First UNC is Fatal */
799412a8245SMichael S. Tsirkin #define  PCI_ERR_ROOT_NONFATAL_RCV	0x00000020 /* Non-Fatal Received */
800412a8245SMichael S. Tsirkin #define  PCI_ERR_ROOT_FATAL_RCV		0x00000040 /* Fatal Received */
801dd873966SEric Auger #define  PCI_ERR_ROOT_AER_IRQ		0xf8000000 /* Advanced Error Interrupt Message Number */
802ef17dd6aSVivek Goyal #define PCI_ERR_ROOT_ERR_SRC	0x34	/* Error Source Identification */
803412a8245SMichael S. Tsirkin 
804412a8245SMichael S. Tsirkin /* Virtual Channel */
805ef17dd6aSVivek Goyal #define PCI_VC_PORT_CAP1	0x04
806120758fbSPaolo Bonzini #define  PCI_VC_CAP1_EVCC	0x00000007	/* extended VC count */
807120758fbSPaolo Bonzini #define  PCI_VC_CAP1_LPEVCC	0x00000070	/* low prio extended VC count */
808120758fbSPaolo Bonzini #define  PCI_VC_CAP1_ARB_SIZE	0x00000c00
809ef17dd6aSVivek Goyal #define PCI_VC_PORT_CAP2	0x08
810120758fbSPaolo Bonzini #define  PCI_VC_CAP2_32_PHASE		0x00000002
811120758fbSPaolo Bonzini #define  PCI_VC_CAP2_64_PHASE		0x00000004
812120758fbSPaolo Bonzini #define  PCI_VC_CAP2_128_PHASE		0x00000008
813120758fbSPaolo Bonzini #define  PCI_VC_CAP2_ARB_OFF		0xff000000
814ef17dd6aSVivek Goyal #define PCI_VC_PORT_CTRL	0x0c
815120758fbSPaolo Bonzini #define  PCI_VC_PORT_CTRL_LOAD_TABLE	0x00000001
816ef17dd6aSVivek Goyal #define PCI_VC_PORT_STATUS	0x0e
817120758fbSPaolo Bonzini #define  PCI_VC_PORT_STATUS_TABLE	0x00000001
818ef17dd6aSVivek Goyal #define PCI_VC_RES_CAP		0x10
819120758fbSPaolo Bonzini #define  PCI_VC_RES_CAP_32_PHASE	0x00000002
820120758fbSPaolo Bonzini #define  PCI_VC_RES_CAP_64_PHASE	0x00000004
821120758fbSPaolo Bonzini #define  PCI_VC_RES_CAP_128_PHASE	0x00000008
822120758fbSPaolo Bonzini #define  PCI_VC_RES_CAP_128_PHASE_TB	0x00000010
823120758fbSPaolo Bonzini #define  PCI_VC_RES_CAP_256_PHASE	0x00000020
824120758fbSPaolo Bonzini #define  PCI_VC_RES_CAP_ARB_OFF		0xff000000
825ef17dd6aSVivek Goyal #define PCI_VC_RES_CTRL		0x14
826120758fbSPaolo Bonzini #define  PCI_VC_RES_CTRL_LOAD_TABLE	0x00010000
827120758fbSPaolo Bonzini #define  PCI_VC_RES_CTRL_ARB_SELECT	0x000e0000
828120758fbSPaolo Bonzini #define  PCI_VC_RES_CTRL_ID		0x07000000
829120758fbSPaolo Bonzini #define  PCI_VC_RES_CTRL_ENABLE		0x80000000
830ef17dd6aSVivek Goyal #define PCI_VC_RES_STATUS	0x1a
831120758fbSPaolo Bonzini #define  PCI_VC_RES_STATUS_TABLE	0x00000001
832120758fbSPaolo Bonzini #define  PCI_VC_RES_STATUS_NEGO		0x00000002
833120758fbSPaolo Bonzini #define PCI_CAP_VC_BASE_SIZEOF		0x10
834ef17dd6aSVivek Goyal #define PCI_CAP_VC_PER_VC_SIZEOF	0x0c
835412a8245SMichael S. Tsirkin 
836412a8245SMichael S. Tsirkin /* Power Budgeting */
837ef17dd6aSVivek Goyal #define PCI_PWR_DSR		0x04	/* Data Select Register */
838ef17dd6aSVivek Goyal #define PCI_PWR_DATA		0x08	/* Data Register */
839412a8245SMichael S. Tsirkin #define  PCI_PWR_DATA_BASE(x)	((x) & 0xff)	    /* Base Power */
840412a8245SMichael S. Tsirkin #define  PCI_PWR_DATA_SCALE(x)	(((x) >> 8) & 3)    /* Data Scale */
841412a8245SMichael S. Tsirkin #define  PCI_PWR_DATA_PM_SUB(x)	(((x) >> 10) & 7)   /* PM Sub State */
842412a8245SMichael S. Tsirkin #define  PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
843412a8245SMichael S. Tsirkin #define  PCI_PWR_DATA_TYPE(x)	(((x) >> 15) & 7)   /* Type */
844412a8245SMichael S. Tsirkin #define  PCI_PWR_DATA_RAIL(x)	(((x) >> 18) & 7)   /* Power Rail */
845ef17dd6aSVivek Goyal #define PCI_PWR_CAP		0x0c	/* Capability */
846412a8245SMichael S. Tsirkin #define  PCI_PWR_CAP_BUDGET(x)	((x) & 1)	/* Included in system budget */
847ef17dd6aSVivek Goyal #define PCI_EXT_CAP_PWR_SIZEOF	0x10
848120758fbSPaolo Bonzini 
849b3c818a4SEric Farman /* Root Complex Event Collector Endpoint Association  */
850b3c818a4SEric Farman #define PCI_RCEC_RCIEP_BITMAP	4	/* Associated Bitmap for RCiEPs */
851b3c818a4SEric Farman #define PCI_RCEC_BUSN		8	/* RCEC Associated Bus Numbers */
852b3c818a4SEric Farman #define  PCI_RCEC_BUSN_REG_VER	0x02	/* Least version with BUSN present */
853b3c818a4SEric Farman #define  PCI_RCEC_BUSN_NEXT(x)	(((x) >> 8) & 0xff)
854b3c818a4SEric Farman #define  PCI_RCEC_BUSN_LAST(x)	(((x) >> 16) & 0xff)
855b3c818a4SEric Farman 
856120758fbSPaolo Bonzini /* Vendor-Specific (VSEC, PCI_EXT_CAP_ID_VNDR) */
857120758fbSPaolo Bonzini #define PCI_VNDR_HEADER		4	/* Vendor-Specific Header */
858120758fbSPaolo Bonzini #define  PCI_VNDR_HEADER_ID(x)	((x) & 0xffff)
859120758fbSPaolo Bonzini #define  PCI_VNDR_HEADER_REV(x)	(((x) >> 16) & 0xf)
860120758fbSPaolo Bonzini #define  PCI_VNDR_HEADER_LEN(x)	(((x) >> 20) & 0xfff)
861412a8245SMichael S. Tsirkin 
862412a8245SMichael S. Tsirkin /*
863120758fbSPaolo Bonzini  * HyperTransport sub capability types
864412a8245SMichael S. Tsirkin  *
865412a8245SMichael S. Tsirkin  * Unfortunately there are both 3 bit and 5 bit capability types defined
866412a8245SMichael S. Tsirkin  * in the HT spec, catering for that is a little messy. You probably don't
867412a8245SMichael S. Tsirkin  * want to use these directly, just use pci_find_ht_capability() and it
868412a8245SMichael S. Tsirkin  * will do the right thing for you.
869412a8245SMichael S. Tsirkin  */
870412a8245SMichael S. Tsirkin #define HT_3BIT_CAP_MASK	0xE0
871412a8245SMichael S. Tsirkin #define HT_CAPTYPE_SLAVE	0x00	/* Slave/Primary link configuration */
872412a8245SMichael S. Tsirkin #define HT_CAPTYPE_HOST		0x20	/* Host/Secondary link configuration */
873412a8245SMichael S. Tsirkin 
874412a8245SMichael S. Tsirkin #define HT_5BIT_CAP_MASK	0xF8
875412a8245SMichael S. Tsirkin #define HT_CAPTYPE_IRQ		0x80	/* IRQ Configuration */
876412a8245SMichael S. Tsirkin #define HT_CAPTYPE_REMAPPING_40	0xA0	/* 40 bit address remapping */
877412a8245SMichael S. Tsirkin #define HT_CAPTYPE_REMAPPING_64 0xA2	/* 64 bit address remapping */
878412a8245SMichael S. Tsirkin #define HT_CAPTYPE_UNITID_CLUMP	0x90	/* Unit ID clumping */
879412a8245SMichael S. Tsirkin #define HT_CAPTYPE_EXTCONF	0x98	/* Extended Configuration Space Access */
880412a8245SMichael S. Tsirkin #define HT_CAPTYPE_MSI_MAPPING	0xA8	/* MSI Mapping Capability */
881412a8245SMichael S. Tsirkin #define  HT_MSI_FLAGS		0x02		/* Offset to flags */
882412a8245SMichael S. Tsirkin #define  HT_MSI_FLAGS_ENABLE	0x1		/* Mapping enable */
883412a8245SMichael S. Tsirkin #define  HT_MSI_FLAGS_FIXED	0x2		/* Fixed mapping only */
884412a8245SMichael S. Tsirkin #define  HT_MSI_FIXED_ADDR	0x00000000FEE00000ULL	/* Fixed addr */
885412a8245SMichael S. Tsirkin #define  HT_MSI_ADDR_LO		0x04		/* Offset to low addr bits */
886412a8245SMichael S. Tsirkin #define  HT_MSI_ADDR_LO_MASK	0xFFF00000	/* Low address bit mask */
887412a8245SMichael S. Tsirkin #define  HT_MSI_ADDR_HI		0x08		/* Offset to high addr bits */
888412a8245SMichael S. Tsirkin #define HT_CAPTYPE_DIRECT_ROUTE	0xB0	/* Direct routing configuration */
889412a8245SMichael S. Tsirkin #define HT_CAPTYPE_VCSET	0xB8	/* Virtual Channel configuration */
890412a8245SMichael S. Tsirkin #define HT_CAPTYPE_ERROR_RETRY	0xC0	/* Retry on error configuration */
891120758fbSPaolo Bonzini #define HT_CAPTYPE_GEN3		0xD0	/* Generation 3 HyperTransport configuration */
892120758fbSPaolo Bonzini #define HT_CAPTYPE_PM		0xE0	/* HyperTransport power management configuration */
893120758fbSPaolo Bonzini #define HT_CAP_SIZEOF_LONG	28	/* slave & primary */
894120758fbSPaolo Bonzini #define HT_CAP_SIZEOF_SHORT	24	/* host & secondary */
895412a8245SMichael S. Tsirkin 
896412a8245SMichael S. Tsirkin /* Alternative Routing-ID Interpretation */
897412a8245SMichael S. Tsirkin #define PCI_ARI_CAP		0x04	/* ARI Capability Register */
898412a8245SMichael S. Tsirkin #define  PCI_ARI_CAP_MFVC	0x0001	/* MFVC Function Groups Capability */
899412a8245SMichael S. Tsirkin #define  PCI_ARI_CAP_ACS	0x0002	/* ACS Function Groups Capability */
900412a8245SMichael S. Tsirkin #define  PCI_ARI_CAP_NFN(x)	(((x) >> 8) & 0xff) /* Next Function Number */
901412a8245SMichael S. Tsirkin #define PCI_ARI_CTRL		0x06	/* ARI Control Register */
902412a8245SMichael S. Tsirkin #define  PCI_ARI_CTRL_MFVC	0x0001	/* MFVC Function Groups Enable */
903412a8245SMichael S. Tsirkin #define  PCI_ARI_CTRL_ACS	0x0002	/* ACS Function Groups Enable */
904412a8245SMichael S. Tsirkin #define  PCI_ARI_CTRL_FG(x)	(((x) >> 4) & 7) /* Function Group */
905120758fbSPaolo Bonzini #define PCI_EXT_CAP_ARI_SIZEOF	8
906412a8245SMichael S. Tsirkin 
907412a8245SMichael S. Tsirkin /* Address Translation Service */
908412a8245SMichael S. Tsirkin #define PCI_ATS_CAP		0x04	/* ATS Capability Register */
909412a8245SMichael S. Tsirkin #define  PCI_ATS_CAP_QDEP(x)	((x) & 0x1f)	/* Invalidate Queue Depth */
910412a8245SMichael S. Tsirkin #define  PCI_ATS_MAX_QDEP	32	/* Max Invalidate Queue Depth */
911d9cb4336SCornelia Huck #define  PCI_ATS_CAP_PAGE_ALIGNED	0x0020 /* Page Aligned Request */
912412a8245SMichael S. Tsirkin #define PCI_ATS_CTRL		0x06	/* ATS Control Register */
913412a8245SMichael S. Tsirkin #define  PCI_ATS_CTRL_ENABLE	0x8000	/* ATS Enable */
914412a8245SMichael S. Tsirkin #define  PCI_ATS_CTRL_STU(x)	((x) & 0x1f)	/* Smallest Translation Unit */
915412a8245SMichael S. Tsirkin #define  PCI_ATS_MIN_STU	12	/* shift of minimum STU block */
916120758fbSPaolo Bonzini #define PCI_EXT_CAP_ATS_SIZEOF	8
917120758fbSPaolo Bonzini 
918120758fbSPaolo Bonzini /* Page Request Interface */
919120758fbSPaolo Bonzini #define PCI_PRI_CTRL		0x04	/* PRI control register */
920d9cb4336SCornelia Huck #define  PCI_PRI_CTRL_ENABLE	0x0001	/* Enable */
921d9cb4336SCornelia Huck #define  PCI_PRI_CTRL_RESET	0x0002	/* Reset */
922120758fbSPaolo Bonzini #define PCI_PRI_STATUS		0x06	/* PRI status register */
923d9cb4336SCornelia Huck #define  PCI_PRI_STATUS_RF	0x0001	/* Response Failure */
924d9cb4336SCornelia Huck #define  PCI_PRI_STATUS_UPRGI	0x0002	/* Unexpected PRG index */
925d9cb4336SCornelia Huck #define  PCI_PRI_STATUS_STOPPED	0x0100	/* PRI Stopped */
926d9cb4336SCornelia Huck #define  PCI_PRI_STATUS_PASID	0x8000	/* PRG Response PASID Required */
927120758fbSPaolo Bonzini #define PCI_PRI_MAX_REQ		0x08	/* PRI max reqs supported */
928120758fbSPaolo Bonzini #define PCI_PRI_ALLOC_REQ	0x0c	/* PRI max reqs allowed */
929120758fbSPaolo Bonzini #define PCI_EXT_CAP_PRI_SIZEOF	16
930120758fbSPaolo Bonzini 
931120758fbSPaolo Bonzini /* Process Address Space ID */
932120758fbSPaolo Bonzini #define PCI_PASID_CAP		0x04    /* PASID feature register */
933120758fbSPaolo Bonzini #define  PCI_PASID_CAP_EXEC	0x02	/* Exec permissions Supported */
934120758fbSPaolo Bonzini #define  PCI_PASID_CAP_PRIV	0x04	/* Privilege Mode Supported */
935120758fbSPaolo Bonzini #define PCI_PASID_CTRL		0x06    /* PASID control register */
936120758fbSPaolo Bonzini #define  PCI_PASID_CTRL_ENABLE	0x01	/* Enable bit */
937120758fbSPaolo Bonzini #define  PCI_PASID_CTRL_EXEC	0x02	/* Exec permissions Enable */
938120758fbSPaolo Bonzini #define  PCI_PASID_CTRL_PRIV	0x04	/* Privilege Mode Enable */
939120758fbSPaolo Bonzini #define PCI_EXT_CAP_PASID_SIZEOF	8
940412a8245SMichael S. Tsirkin 
941412a8245SMichael S. Tsirkin /* Single Root I/O Virtualization */
942412a8245SMichael S. Tsirkin #define PCI_SRIOV_CAP		0x04	/* SR-IOV Capabilities */
943d9cb4336SCornelia Huck #define  PCI_SRIOV_CAP_VFM	0x00000001  /* VF Migration Capable */
944412a8245SMichael S. Tsirkin #define  PCI_SRIOV_CAP_INTR(x)	((x) >> 21) /* Interrupt Message Number */
945412a8245SMichael S. Tsirkin #define PCI_SRIOV_CTRL		0x08	/* SR-IOV Control */
946d9cb4336SCornelia Huck #define  PCI_SRIOV_CTRL_VFE	0x0001	/* VF Enable */
947d9cb4336SCornelia Huck #define  PCI_SRIOV_CTRL_VFM	0x0002	/* VF Migration Enable */
948d9cb4336SCornelia Huck #define  PCI_SRIOV_CTRL_INTR	0x0004	/* VF Migration Interrupt Enable */
949d9cb4336SCornelia Huck #define  PCI_SRIOV_CTRL_MSE	0x0008	/* VF Memory Space Enable */
950d9cb4336SCornelia Huck #define  PCI_SRIOV_CTRL_ARI	0x0010	/* ARI Capable Hierarchy */
951412a8245SMichael S. Tsirkin #define PCI_SRIOV_STATUS	0x0a	/* SR-IOV Status */
952d9cb4336SCornelia Huck #define  PCI_SRIOV_STATUS_VFM	0x0001	/* VF Migration Status */
953412a8245SMichael S. Tsirkin #define PCI_SRIOV_INITIAL_VF	0x0c	/* Initial VFs */
954412a8245SMichael S. Tsirkin #define PCI_SRIOV_TOTAL_VF	0x0e	/* Total VFs */
955412a8245SMichael S. Tsirkin #define PCI_SRIOV_NUM_VF	0x10	/* Number of VFs */
956412a8245SMichael S. Tsirkin #define PCI_SRIOV_FUNC_LINK	0x12	/* Function Dependency Link */
957412a8245SMichael S. Tsirkin #define PCI_SRIOV_VF_OFFSET	0x14	/* First VF Offset */
958412a8245SMichael S. Tsirkin #define PCI_SRIOV_VF_STRIDE	0x16	/* Following VF Stride */
959412a8245SMichael S. Tsirkin #define PCI_SRIOV_VF_DID	0x1a	/* VF Device ID */
960412a8245SMichael S. Tsirkin #define PCI_SRIOV_SUP_PGSIZE	0x1c	/* Supported Page Sizes */
961412a8245SMichael S. Tsirkin #define PCI_SRIOV_SYS_PGSIZE	0x20	/* System Page Size */
962412a8245SMichael S. Tsirkin #define PCI_SRIOV_BAR		0x24	/* VF BAR0 */
963412a8245SMichael S. Tsirkin #define  PCI_SRIOV_NUM_BARS	6	/* Number of VF BARs */
964412a8245SMichael S. Tsirkin #define PCI_SRIOV_VFM		0x3c	/* VF Migration State Array Offset*/
965412a8245SMichael S. Tsirkin #define  PCI_SRIOV_VFM_BIR(x)	((x) & 7)	/* State BIR */
966412a8245SMichael S. Tsirkin #define  PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7)	/* State Offset */
967412a8245SMichael S. Tsirkin #define  PCI_SRIOV_VFM_UA	0x0	/* Inactive.Unavailable */
968412a8245SMichael S. Tsirkin #define  PCI_SRIOV_VFM_MI	0x1	/* Dormant.MigrateIn */
969412a8245SMichael S. Tsirkin #define  PCI_SRIOV_VFM_MO	0x2	/* Active.MigrateOut */
970412a8245SMichael S. Tsirkin #define  PCI_SRIOV_VFM_AV	0x3	/* Active.Available */
971ef17dd6aSVivek Goyal #define PCI_EXT_CAP_SRIOV_SIZEOF 0x40
972412a8245SMichael S. Tsirkin 
973412a8245SMichael S. Tsirkin #define PCI_LTR_MAX_SNOOP_LAT	0x4
974412a8245SMichael S. Tsirkin #define PCI_LTR_MAX_NOSNOOP_LAT	0x6
975412a8245SMichael S. Tsirkin #define  PCI_LTR_VALUE_MASK	0x000003ff
976412a8245SMichael S. Tsirkin #define  PCI_LTR_SCALE_MASK	0x00001c00
977412a8245SMichael S. Tsirkin #define  PCI_LTR_SCALE_SHIFT	10
978120758fbSPaolo Bonzini #define PCI_EXT_CAP_LTR_SIZEOF	8
979412a8245SMichael S. Tsirkin 
980412a8245SMichael S. Tsirkin /* Access Control Service */
981412a8245SMichael S. Tsirkin #define PCI_ACS_CAP		0x04	/* ACS Capability Register */
982d9cb4336SCornelia Huck #define  PCI_ACS_SV		0x0001	/* Source Validation */
983d9cb4336SCornelia Huck #define  PCI_ACS_TB		0x0002	/* Translation Blocking */
984d9cb4336SCornelia Huck #define  PCI_ACS_RR		0x0004	/* P2P Request Redirect */
985d9cb4336SCornelia Huck #define  PCI_ACS_CR		0x0008	/* P2P Completion Redirect */
986d9cb4336SCornelia Huck #define  PCI_ACS_UF		0x0010	/* Upstream Forwarding */
987d9cb4336SCornelia Huck #define  PCI_ACS_EC		0x0020	/* P2P Egress Control */
988d9cb4336SCornelia Huck #define  PCI_ACS_DT		0x0040	/* Direct Translated P2P */
989120758fbSPaolo Bonzini #define PCI_ACS_EGRESS_BITS	0x05	/* ACS Egress Control Vector Size */
990412a8245SMichael S. Tsirkin #define PCI_ACS_CTRL		0x06	/* ACS Control Register */
991412a8245SMichael S. Tsirkin #define PCI_ACS_EGRESS_CTL_V	0x08	/* ACS Egress Control Vector */
992412a8245SMichael S. Tsirkin 
993120758fbSPaolo Bonzini #define PCI_VSEC_HDR		4	/* extended cap - vendor-specific */
994120758fbSPaolo Bonzini #define  PCI_VSEC_HDR_LEN_SHIFT	20	/* shift for length field */
995120758fbSPaolo Bonzini 
996120758fbSPaolo Bonzini /* SATA capability */
997120758fbSPaolo Bonzini #define PCI_SATA_REGS		4	/* SATA REGs specifier */
998120758fbSPaolo Bonzini #define  PCI_SATA_REGS_MASK	0xF	/* location - BAR#/inline */
999120758fbSPaolo Bonzini #define  PCI_SATA_REGS_INLINE	0xF	/* REGS in config space */
1000120758fbSPaolo Bonzini #define PCI_SATA_SIZEOF_SHORT	8
1001120758fbSPaolo Bonzini #define PCI_SATA_SIZEOF_LONG	16
1002120758fbSPaolo Bonzini 
1003120758fbSPaolo Bonzini /* Resizable BARs */
1004dd873966SEric Auger #define PCI_REBAR_CAP		4	/* capability register */
1005dd873966SEric Auger #define  PCI_REBAR_CAP_SIZES		0x00FFFFF0  /* supported BAR sizes */
1006120758fbSPaolo Bonzini #define PCI_REBAR_CTRL		8	/* control register */
1007dd873966SEric Auger #define  PCI_REBAR_CTRL_BAR_IDX		0x00000007  /* BAR index */
1008dd873966SEric Auger #define  PCI_REBAR_CTRL_NBAR_MASK	0x000000E0  /* # of resizable BARs */
1009dd873966SEric Auger #define  PCI_REBAR_CTRL_NBAR_SHIFT	5	    /* shift for # of BARs */
1010dd873966SEric Auger #define  PCI_REBAR_CTRL_BAR_SIZE	0x00001F00  /* BAR size */
1011d36f7de8SCornelia Huck #define  PCI_REBAR_CTRL_BAR_SHIFT	8	    /* shift for BAR size */
1012120758fbSPaolo Bonzini 
1013120758fbSPaolo Bonzini /* Dynamic Power Allocation */
1014120758fbSPaolo Bonzini #define PCI_DPA_CAP		4	/* capability register */
1015120758fbSPaolo Bonzini #define  PCI_DPA_CAP_SUBSTATE_MASK	0x1F	/* # substates - 1 */
1016120758fbSPaolo Bonzini #define PCI_DPA_BASE_SIZEOF	16	/* size with 0 substates */
1017120758fbSPaolo Bonzini 
1018120758fbSPaolo Bonzini /* TPH Requester */
1019120758fbSPaolo Bonzini #define PCI_TPH_CAP		4	/* capability register */
1020120758fbSPaolo Bonzini #define  PCI_TPH_CAP_LOC_MASK	0x600	/* location mask */
1021120758fbSPaolo Bonzini #define   PCI_TPH_LOC_NONE	0x000	/* no location */
1022120758fbSPaolo Bonzini #define   PCI_TPH_LOC_CAP	0x200	/* in capability */
1023120758fbSPaolo Bonzini #define   PCI_TPH_LOC_MSIX	0x400	/* in MSI-X */
1024ef17dd6aSVivek Goyal #define PCI_TPH_CAP_ST_MASK	0x07FF0000	/* ST table mask */
1025ef17dd6aSVivek Goyal #define PCI_TPH_CAP_ST_SHIFT	16	/* ST table shift */
1026ef17dd6aSVivek Goyal #define PCI_TPH_BASE_SIZEOF	0xc	/* size with no ST table */
1027120758fbSPaolo Bonzini 
1028ff804f15SCornelia Huck /* Downstream Port Containment */
1029ef17dd6aSVivek Goyal #define PCI_EXP_DPC_CAP			0x04	/* DPC Capability */
10309f2d175dSPaolo Bonzini #define PCI_EXP_DPC_IRQ			0x001F	/* Interrupt Message Number */
10319f2d175dSPaolo Bonzini #define  PCI_EXP_DPC_CAP_RP_EXT		0x0020	/* Root Port Extensions */
10329f2d175dSPaolo Bonzini #define  PCI_EXP_DPC_CAP_POISONED_TLP	0x0040	/* Poisoned TLP Egress Blocking Supported */
10339f2d175dSPaolo Bonzini #define  PCI_EXP_DPC_CAP_SW_TRIGGER	0x0080	/* Software Triggering Supported */
10349f2d175dSPaolo Bonzini #define  PCI_EXP_DPC_RP_PIO_LOG_SIZE	0x0F00	/* RP PIO Log Size */
1035ff804f15SCornelia Huck #define  PCI_EXP_DPC_CAP_DL_ACTIVE	0x1000	/* ERR_COR signal on DL_Active supported */
1036ff804f15SCornelia Huck 
1037ef17dd6aSVivek Goyal #define PCI_EXP_DPC_CTL			0x06	/* DPC control */
103877d361b1SEric Auger #define  PCI_EXP_DPC_CTL_EN_FATAL	0x0001	/* Enable trigger on ERR_FATAL message */
10399f2d175dSPaolo Bonzini #define  PCI_EXP_DPC_CTL_EN_NONFATAL	0x0002	/* Enable trigger on ERR_NONFATAL message */
10409f2d175dSPaolo Bonzini #define  PCI_EXP_DPC_CTL_INT_EN		0x0008	/* DPC Interrupt Enable */
1041ff804f15SCornelia Huck 
1042ef17dd6aSVivek Goyal #define PCI_EXP_DPC_STATUS		0x08	/* DPC Status */
10439f2d175dSPaolo Bonzini #define  PCI_EXP_DPC_STATUS_TRIGGER	    0x0001 /* Trigger Status */
10449f2d175dSPaolo Bonzini #define  PCI_EXP_DPC_STATUS_TRIGGER_RSN	    0x0006 /* Trigger Reason */
10459f2d175dSPaolo Bonzini #define  PCI_EXP_DPC_STATUS_INTERRUPT	    0x0008 /* Interrupt Status */
10469f2d175dSPaolo Bonzini #define  PCI_EXP_DPC_RP_BUSY		    0x0010 /* Root Port Busy */
10479f2d175dSPaolo Bonzini #define  PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT 0x0060 /* Trig Reason Extension */
1048ff804f15SCornelia Huck 
1049ef17dd6aSVivek Goyal #define PCI_EXP_DPC_SOURCE_ID		 0x0A	/* DPC Source Identifier */
1050ff804f15SCornelia Huck 
1051d4083f50SAlexey Perevalov #define PCI_EXP_DPC_RP_PIO_STATUS	 0x0C	/* RP PIO Status */
10529f2d175dSPaolo Bonzini #define PCI_EXP_DPC_RP_PIO_MASK		 0x10	/* RP PIO Mask */
1053d4083f50SAlexey Perevalov #define PCI_EXP_DPC_RP_PIO_SEVERITY	 0x14	/* RP PIO Severity */
1054d4083f50SAlexey Perevalov #define PCI_EXP_DPC_RP_PIO_SYSERROR	 0x18	/* RP PIO SysError */
1055d4083f50SAlexey Perevalov #define PCI_EXP_DPC_RP_PIO_EXCEPTION	 0x1C	/* RP PIO Exception */
1056d4083f50SAlexey Perevalov #define PCI_EXP_DPC_RP_PIO_HEADER_LOG	 0x20	/* RP PIO Header Log */
1057d4083f50SAlexey Perevalov #define PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG	 0x30	/* RP PIO ImpSpec Log */
1058d4083f50SAlexey Perevalov #define PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG 0x34	/* RP PIO TLP Prefix Log */
1059d4083f50SAlexey Perevalov 
1060bc204035SMarcelo Tosatti /* Precision Time Measurement */
1061bc204035SMarcelo Tosatti #define PCI_PTM_CAP			0x04	    /* PTM Capability */
1062bc204035SMarcelo Tosatti #define  PCI_PTM_CAP_REQ		0x00000001  /* Requester capable */
106393d7620cSAvihai Horon #define  PCI_PTM_CAP_RES		0x00000002  /* Responder capable */
1064bc204035SMarcelo Tosatti #define  PCI_PTM_CAP_ROOT		0x00000004  /* Root capable */
1065bc204035SMarcelo Tosatti #define  PCI_PTM_GRANULARITY_MASK	0x0000FF00  /* Clock granularity */
1066bc204035SMarcelo Tosatti #define PCI_PTM_CTRL			0x08	    /* PTM Control */
1067bc204035SMarcelo Tosatti #define  PCI_PTM_CTRL_ENABLE		0x00000001  /* PTM enable */
1068bc204035SMarcelo Tosatti #define  PCI_PTM_CTRL_ROOT		0x00000002  /* Root select */
1069bc204035SMarcelo Tosatti 
1070dd873966SEric Auger /* ASPM L1 PM Substates */
1071dd873966SEric Auger #define PCI_L1SS_CAP		0x04	/* Capabilities Register */
1072dd873966SEric Auger #define  PCI_L1SS_CAP_PCIPM_L1_2	0x00000001  /* PCI-PM L1.2 Supported */
1073dd873966SEric Auger #define  PCI_L1SS_CAP_PCIPM_L1_1	0x00000002  /* PCI-PM L1.1 Supported */
1074dd873966SEric Auger #define  PCI_L1SS_CAP_ASPM_L1_2		0x00000004  /* ASPM L1.2 Supported */
1075dd873966SEric Auger #define  PCI_L1SS_CAP_ASPM_L1_1		0x00000008  /* ASPM L1.1 Supported */
1076dd873966SEric Auger #define  PCI_L1SS_CAP_L1_PM_SS		0x00000010  /* L1 PM Substates Supported */
1077dd873966SEric Auger #define  PCI_L1SS_CAP_CM_RESTORE_TIME	0x0000ff00  /* Port Common_Mode_Restore_Time */
1078dd873966SEric Auger #define  PCI_L1SS_CAP_P_PWR_ON_SCALE	0x00030000  /* Port T_POWER_ON scale */
1079dd873966SEric Auger #define  PCI_L1SS_CAP_P_PWR_ON_VALUE	0x00f80000  /* Port T_POWER_ON value */
1080dd873966SEric Auger #define PCI_L1SS_CTL1		0x08	/* Control 1 Register */
1081dd873966SEric Auger #define  PCI_L1SS_CTL1_PCIPM_L1_2	0x00000001  /* PCI-PM L1.2 Enable */
1082dd873966SEric Auger #define  PCI_L1SS_CTL1_PCIPM_L1_1	0x00000002  /* PCI-PM L1.1 Enable */
1083dd873966SEric Auger #define  PCI_L1SS_CTL1_ASPM_L1_2	0x00000004  /* ASPM L1.2 Enable */
1084dd873966SEric Auger #define  PCI_L1SS_CTL1_ASPM_L1_1	0x00000008  /* ASPM L1.1 Enable */
108553ba2eeeSMatthew Rosato #define  PCI_L1SS_CTL1_L1_2_MASK	0x00000005
1086dd873966SEric Auger #define  PCI_L1SS_CTL1_L1SS_MASK	0x0000000f
1087dd873966SEric Auger #define  PCI_L1SS_CTL1_CM_RESTORE_TIME	0x0000ff00  /* Common_Mode_Restore_Time */
1088dd873966SEric Auger #define  PCI_L1SS_CTL1_LTR_L12_TH_VALUE	0x03ff0000  /* LTR_L1.2_THRESHOLD_Value */
1089dd873966SEric Auger #define  PCI_L1SS_CTL1_LTR_L12_TH_SCALE	0xe0000000  /* LTR_L1.2_THRESHOLD_Scale */
1090dd873966SEric Auger #define PCI_L1SS_CTL2		0x0c	/* Control 2 Register */
10913a5eb5b4SPaolo Bonzini 
1092b3c818a4SEric Farman /* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */
1093b3c818a4SEric Farman #define PCI_DVSEC_HEADER1		0x4 /* Designated Vendor-Specific Header1 */
1094ef17dd6aSVivek Goyal #define  PCI_DVSEC_HEADER1_VID(x)	((x) & 0xffff)
1095ef17dd6aSVivek Goyal #define  PCI_DVSEC_HEADER1_REV(x)	(((x) >> 16) & 0xf)
1096ef17dd6aSVivek Goyal #define  PCI_DVSEC_HEADER1_LEN(x)	(((x) >> 20) & 0xfff)
1097b3c818a4SEric Farman #define PCI_DVSEC_HEADER2		0x8 /* Designated Vendor-Specific Header2 */
1098ef17dd6aSVivek Goyal #define  PCI_DVSEC_HEADER2_ID(x)		((x) & 0xffff)
1099b3c818a4SEric Farman 
1100f363d039SEric Auger /* Data Link Feature */
1101f363d039SEric Auger #define PCI_DLF_CAP		0x04	/* Capabilities Register */
1102f363d039SEric Auger #define  PCI_DLF_EXCHANGE_ENABLE	0x80000000  /* Data Link Feature Exchange Enable */
1103f363d039SEric Auger 
1104f363d039SEric Auger /* Physical Layer 16.0 GT/s */
1105f363d039SEric Auger #define PCI_PL_16GT_LE_CTRL	0x20	/* Lane Equalization Control Register */
1106f363d039SEric Auger #define  PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK		0x0000000F
1107f363d039SEric Auger #define  PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK		0x000000F0
1108f363d039SEric Auger #define  PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT	4
1109f363d039SEric Auger 
1110d525f73fSChenyi Qiang /* Data Object Exchange */
1111d525f73fSChenyi Qiang #define PCI_DOE_CAP		0x04    /* DOE Capabilities Register */
1112d525f73fSChenyi Qiang #define  PCI_DOE_CAP_INT_SUP			0x00000001  /* Interrupt Support */
1113d525f73fSChenyi Qiang #define  PCI_DOE_CAP_INT_MSG_NUM		0x00000ffe  /* Interrupt Message Number */
1114d525f73fSChenyi Qiang #define PCI_DOE_CTRL		0x08    /* DOE Control Register */
1115d525f73fSChenyi Qiang #define  PCI_DOE_CTRL_ABORT			0x00000001  /* DOE Abort */
1116d525f73fSChenyi Qiang #define  PCI_DOE_CTRL_INT_EN			0x00000002  /* DOE Interrupt Enable */
1117d525f73fSChenyi Qiang #define  PCI_DOE_CTRL_GO			0x80000000  /* DOE Go */
1118d525f73fSChenyi Qiang #define PCI_DOE_STATUS		0x0c    /* DOE Status Register */
1119d525f73fSChenyi Qiang #define  PCI_DOE_STATUS_BUSY			0x00000001  /* DOE Busy */
1120d525f73fSChenyi Qiang #define  PCI_DOE_STATUS_INT_STATUS		0x00000002  /* DOE Interrupt Status */
1121d525f73fSChenyi Qiang #define  PCI_DOE_STATUS_ERROR			0x00000004  /* DOE Error */
1122d525f73fSChenyi Qiang #define  PCI_DOE_STATUS_DATA_OBJECT_READY	0x80000000  /* Data Object Ready */
1123d525f73fSChenyi Qiang #define PCI_DOE_WRITE		0x10    /* DOE Write Data Mailbox Register */
1124d525f73fSChenyi Qiang #define PCI_DOE_READ		0x14    /* DOE Read Data Mailbox Register */
112593d7620cSAvihai Horon #define PCI_DOE_CAP_SIZEOF	0x18	/* Size of DOE register block */
1126d525f73fSChenyi Qiang 
1127d525f73fSChenyi Qiang /* DOE Data Object - note not actually registers */
1128d525f73fSChenyi Qiang #define PCI_DOE_DATA_OBJECT_HEADER_1_VID		0x0000ffff
1129d525f73fSChenyi Qiang #define PCI_DOE_DATA_OBJECT_HEADER_1_TYPE		0x00ff0000
1130d525f73fSChenyi Qiang #define PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH		0x0003ffff
1131d525f73fSChenyi Qiang 
1132d525f73fSChenyi Qiang #define PCI_DOE_DATA_OBJECT_DISC_REQ_3_INDEX		0x000000ff
1133d525f73fSChenyi Qiang #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_VID		0x0000ffff
1134d525f73fSChenyi Qiang #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL		0x00ff0000
1135d525f73fSChenyi Qiang #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX	0xff000000
1136d525f73fSChenyi Qiang 
1137412a8245SMichael S. Tsirkin #endif /* LINUX_PCI_REGS_H */
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