1 /* 2 * Virtio GPU Device 3 * 4 * Copyright Red Hat, Inc. 2013-2014 5 * 6 * Authors: 7 * Dave Airlie <airlied@redhat.com> 8 * Gerd Hoffmann <kraxel@redhat.com> 9 * 10 * This header is BSD licensed so anyone can use the definitions 11 * to implement compatible drivers/servers: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. Neither the name of IBM nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 27 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL IBM OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 31 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 32 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 34 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 */ 37 38 #ifndef VIRTIO_GPU_HW_H 39 #define VIRTIO_GPU_HW_H 40 41 #include "standard-headers/linux/types.h" 42 43 #define VIRTIO_GPU_F_VIRGL 0 44 #define VIRTIO_GPU_F_EDID 1 45 46 enum virtio_gpu_ctrl_type { 47 VIRTIO_GPU_UNDEFINED = 0, 48 49 /* 2d commands */ 50 VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100, 51 VIRTIO_GPU_CMD_RESOURCE_CREATE_2D, 52 VIRTIO_GPU_CMD_RESOURCE_UNREF, 53 VIRTIO_GPU_CMD_SET_SCANOUT, 54 VIRTIO_GPU_CMD_RESOURCE_FLUSH, 55 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D, 56 VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING, 57 VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING, 58 VIRTIO_GPU_CMD_GET_CAPSET_INFO, 59 VIRTIO_GPU_CMD_GET_CAPSET, 60 VIRTIO_GPU_CMD_GET_EDID, 61 62 /* 3d commands */ 63 VIRTIO_GPU_CMD_CTX_CREATE = 0x0200, 64 VIRTIO_GPU_CMD_CTX_DESTROY, 65 VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, 66 VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE, 67 VIRTIO_GPU_CMD_RESOURCE_CREATE_3D, 68 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, 69 VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D, 70 VIRTIO_GPU_CMD_SUBMIT_3D, 71 72 /* cursor commands */ 73 VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300, 74 VIRTIO_GPU_CMD_MOVE_CURSOR, 75 76 /* success responses */ 77 VIRTIO_GPU_RESP_OK_NODATA = 0x1100, 78 VIRTIO_GPU_RESP_OK_DISPLAY_INFO, 79 VIRTIO_GPU_RESP_OK_CAPSET_INFO, 80 VIRTIO_GPU_RESP_OK_CAPSET, 81 VIRTIO_GPU_RESP_OK_EDID, 82 83 /* error responses */ 84 VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200, 85 VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY, 86 VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID, 87 VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID, 88 VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID, 89 VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER, 90 }; 91 92 #define VIRTIO_GPU_FLAG_FENCE (1 << 0) 93 94 struct virtio_gpu_ctrl_hdr { 95 uint32_t type; 96 uint32_t flags; 97 uint64_t fence_id; 98 uint32_t ctx_id; 99 uint32_t padding; 100 }; 101 102 /* data passed in the cursor vq */ 103 104 struct virtio_gpu_cursor_pos { 105 uint32_t scanout_id; 106 uint32_t x; 107 uint32_t y; 108 uint32_t padding; 109 }; 110 111 /* VIRTIO_GPU_CMD_UPDATE_CURSOR, VIRTIO_GPU_CMD_MOVE_CURSOR */ 112 struct virtio_gpu_update_cursor { 113 struct virtio_gpu_ctrl_hdr hdr; 114 struct virtio_gpu_cursor_pos pos; /* update & move */ 115 uint32_t resource_id; /* update only */ 116 uint32_t hot_x; /* update only */ 117 uint32_t hot_y; /* update only */ 118 uint32_t padding; 119 }; 120 121 /* data passed in the control vq, 2d related */ 122 123 struct virtio_gpu_rect { 124 uint32_t x; 125 uint32_t y; 126 uint32_t width; 127 uint32_t height; 128 }; 129 130 /* VIRTIO_GPU_CMD_RESOURCE_UNREF */ 131 struct virtio_gpu_resource_unref { 132 struct virtio_gpu_ctrl_hdr hdr; 133 uint32_t resource_id; 134 uint32_t padding; 135 }; 136 137 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: create a 2d resource with a format */ 138 struct virtio_gpu_resource_create_2d { 139 struct virtio_gpu_ctrl_hdr hdr; 140 uint32_t resource_id; 141 uint32_t format; 142 uint32_t width; 143 uint32_t height; 144 }; 145 146 /* VIRTIO_GPU_CMD_SET_SCANOUT */ 147 struct virtio_gpu_set_scanout { 148 struct virtio_gpu_ctrl_hdr hdr; 149 struct virtio_gpu_rect r; 150 uint32_t scanout_id; 151 uint32_t resource_id; 152 }; 153 154 /* VIRTIO_GPU_CMD_RESOURCE_FLUSH */ 155 struct virtio_gpu_resource_flush { 156 struct virtio_gpu_ctrl_hdr hdr; 157 struct virtio_gpu_rect r; 158 uint32_t resource_id; 159 uint32_t padding; 160 }; 161 162 /* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: simple transfer to_host */ 163 struct virtio_gpu_transfer_to_host_2d { 164 struct virtio_gpu_ctrl_hdr hdr; 165 struct virtio_gpu_rect r; 166 uint64_t offset; 167 uint32_t resource_id; 168 uint32_t padding; 169 }; 170 171 struct virtio_gpu_mem_entry { 172 uint64_t addr; 173 uint32_t length; 174 uint32_t padding; 175 }; 176 177 /* VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING */ 178 struct virtio_gpu_resource_attach_backing { 179 struct virtio_gpu_ctrl_hdr hdr; 180 uint32_t resource_id; 181 uint32_t nr_entries; 182 }; 183 184 /* VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING */ 185 struct virtio_gpu_resource_detach_backing { 186 struct virtio_gpu_ctrl_hdr hdr; 187 uint32_t resource_id; 188 uint32_t padding; 189 }; 190 191 /* VIRTIO_GPU_RESP_OK_DISPLAY_INFO */ 192 #define VIRTIO_GPU_MAX_SCANOUTS 16 193 struct virtio_gpu_resp_display_info { 194 struct virtio_gpu_ctrl_hdr hdr; 195 struct virtio_gpu_display_one { 196 struct virtio_gpu_rect r; 197 uint32_t enabled; 198 uint32_t flags; 199 } pmodes[VIRTIO_GPU_MAX_SCANOUTS]; 200 }; 201 202 /* data passed in the control vq, 3d related */ 203 204 struct virtio_gpu_box { 205 uint32_t x, y, z; 206 uint32_t w, h, d; 207 }; 208 209 /* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D */ 210 struct virtio_gpu_transfer_host_3d { 211 struct virtio_gpu_ctrl_hdr hdr; 212 struct virtio_gpu_box box; 213 uint64_t offset; 214 uint32_t resource_id; 215 uint32_t level; 216 uint32_t stride; 217 uint32_t layer_stride; 218 }; 219 220 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_3D */ 221 #define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0) 222 struct virtio_gpu_resource_create_3d { 223 struct virtio_gpu_ctrl_hdr hdr; 224 uint32_t resource_id; 225 uint32_t target; 226 uint32_t format; 227 uint32_t bind; 228 uint32_t width; 229 uint32_t height; 230 uint32_t depth; 231 uint32_t array_size; 232 uint32_t last_level; 233 uint32_t nr_samples; 234 uint32_t flags; 235 uint32_t padding; 236 }; 237 238 /* VIRTIO_GPU_CMD_CTX_CREATE */ 239 struct virtio_gpu_ctx_create { 240 struct virtio_gpu_ctrl_hdr hdr; 241 uint32_t nlen; 242 uint32_t padding; 243 char debug_name[64]; 244 }; 245 246 /* VIRTIO_GPU_CMD_CTX_DESTROY */ 247 struct virtio_gpu_ctx_destroy { 248 struct virtio_gpu_ctrl_hdr hdr; 249 }; 250 251 /* VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE */ 252 struct virtio_gpu_ctx_resource { 253 struct virtio_gpu_ctrl_hdr hdr; 254 uint32_t resource_id; 255 uint32_t padding; 256 }; 257 258 /* VIRTIO_GPU_CMD_SUBMIT_3D */ 259 struct virtio_gpu_cmd_submit { 260 struct virtio_gpu_ctrl_hdr hdr; 261 uint32_t size; 262 uint32_t padding; 263 }; 264 265 #define VIRTIO_GPU_CAPSET_VIRGL 1 266 #define VIRTIO_GPU_CAPSET_VIRGL2 2 267 268 /* VIRTIO_GPU_CMD_GET_CAPSET_INFO */ 269 struct virtio_gpu_get_capset_info { 270 struct virtio_gpu_ctrl_hdr hdr; 271 uint32_t capset_index; 272 uint32_t padding; 273 }; 274 275 /* VIRTIO_GPU_RESP_OK_CAPSET_INFO */ 276 struct virtio_gpu_resp_capset_info { 277 struct virtio_gpu_ctrl_hdr hdr; 278 uint32_t capset_id; 279 uint32_t capset_max_version; 280 uint32_t capset_max_size; 281 uint32_t padding; 282 }; 283 284 /* VIRTIO_GPU_CMD_GET_CAPSET */ 285 struct virtio_gpu_get_capset { 286 struct virtio_gpu_ctrl_hdr hdr; 287 uint32_t capset_id; 288 uint32_t capset_version; 289 }; 290 291 /* VIRTIO_GPU_RESP_OK_CAPSET */ 292 struct virtio_gpu_resp_capset { 293 struct virtio_gpu_ctrl_hdr hdr; 294 uint8_t capset_data[]; 295 }; 296 297 /* VIRTIO_GPU_CMD_GET_EDID */ 298 struct virtio_gpu_cmd_get_edid { 299 struct virtio_gpu_ctrl_hdr hdr; 300 uint32_t scanout; 301 uint32_t padding; 302 }; 303 304 /* VIRTIO_GPU_RESP_OK_EDID */ 305 struct virtio_gpu_resp_edid { 306 struct virtio_gpu_ctrl_hdr hdr; 307 uint32_t size; 308 uint32_t padding; 309 uint8_t edid[1024]; 310 }; 311 312 #define VIRTIO_GPU_EVENT_DISPLAY (1 << 0) 313 314 struct virtio_gpu_config { 315 uint32_t events_read; 316 uint32_t events_clear; 317 uint32_t num_scanouts; 318 uint32_t num_capsets; 319 }; 320 321 /* simple formats for fbcon/X use */ 322 enum virtio_gpu_formats { 323 VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1, 324 VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2, 325 VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3, 326 VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4, 327 328 VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67, 329 VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68, 330 331 VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121, 332 VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134, 333 }; 334 335 #endif 336