1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * PCI standard defines 4 * Copyright 1994, Drew Eckhardt 5 * Copyright 1997--1999 Martin Mares <mj@ucw.cz> 6 * 7 * For more information, please consult the following manuals (look at 8 * http://www.pcisig.com/ for how to get them): 9 * 10 * PCI BIOS Specification 11 * PCI Local Bus Specification 12 * PCI to PCI Bridge Specification 13 * PCI System Design Guide 14 * 15 * For HyperTransport information, please consult the following manuals 16 * from http://www.hypertransport.org : 17 * 18 * The HyperTransport I/O Link Specification 19 */ 20 21 #ifndef LINUX_PCI_REGS_H 22 #define LINUX_PCI_REGS_H 23 24 /* 25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of 26 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of 27 * configuration space. 28 */ 29 #define PCI_CFG_SPACE_SIZE 256 30 #define PCI_CFG_SPACE_EXP_SIZE 4096 31 32 /* 33 * Under PCI, each device has 256 bytes of configuration address space, 34 * of which the first 64 bytes are standardized as follows: 35 */ 36 #define PCI_STD_HEADER_SIZEOF 64 37 #define PCI_STD_NUM_BARS 6 /* Number of standard BARs */ 38 #define PCI_VENDOR_ID 0x00 /* 16 bits */ 39 #define PCI_DEVICE_ID 0x02 /* 16 bits */ 40 #define PCI_COMMAND 0x04 /* 16 bits */ 41 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ 42 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ 43 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ 44 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ 45 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ 46 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ 47 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ 48 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ 49 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ 50 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ 51 #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ 52 53 #define PCI_STATUS 0x06 /* 16 bits */ 54 #define PCI_STATUS_IMM_READY 0x01 /* Immediate Readiness */ 55 #define PCI_STATUS_INTERRUPT 0x08 /* Interrupt status */ 56 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ 57 #define PCI_STATUS_66MHZ 0x20 /* Support 66 MHz PCI 2.1 bus */ 58 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ 59 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ 60 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ 61 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ 62 #define PCI_STATUS_DEVSEL_FAST 0x000 63 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 64 #define PCI_STATUS_DEVSEL_SLOW 0x400 65 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ 66 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ 67 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ 68 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ 69 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ 70 71 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */ 72 #define PCI_REVISION_ID 0x08 /* Revision ID */ 73 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ 74 #define PCI_CLASS_DEVICE 0x0a /* Device class */ 75 76 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ 77 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ 78 #define PCI_HEADER_TYPE 0x0e /* 8 bits */ 79 #define PCI_HEADER_TYPE_NORMAL 0 80 #define PCI_HEADER_TYPE_BRIDGE 1 81 #define PCI_HEADER_TYPE_CARDBUS 2 82 83 #define PCI_BIST 0x0f /* 8 bits */ 84 #define PCI_BIST_CODE_MASK 0x0f /* Return result */ 85 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ 86 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ 87 88 /* 89 * Base addresses specify locations in memory or I/O space. 90 * Decoded size can be determined by writing a value of 91 * 0xffffffff to the register, and reading it back. Only 92 * 1 bits are decoded. 93 */ 94 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ 95 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ 96 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ 97 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ 98 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ 99 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ 100 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ 101 #define PCI_BASE_ADDRESS_SPACE_IO 0x01 102 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 103 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 104 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ 105 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ 106 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ 107 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ 108 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) 109 #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) 110 /* bit 1 is reserved if address_space = 1 */ 111 112 /* Header type 0 (normal devices) */ 113 #define PCI_CARDBUS_CIS 0x28 114 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c 115 #define PCI_SUBSYSTEM_ID 0x2e 116 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ 117 #define PCI_ROM_ADDRESS_ENABLE 0x01 118 #define PCI_ROM_ADDRESS_MASK (~0x7ffU) 119 120 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ 121 122 /* 0x35-0x3b are reserved */ 123 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ 124 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ 125 #define PCI_MIN_GNT 0x3e /* 8 bits */ 126 #define PCI_MAX_LAT 0x3f /* 8 bits */ 127 128 /* Header type 1 (PCI-to-PCI bridges) */ 129 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ 130 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ 131 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ 132 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ 133 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ 134 #define PCI_IO_LIMIT 0x1d 135 #define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */ 136 #define PCI_IO_RANGE_TYPE_16 0x00 137 #define PCI_IO_RANGE_TYPE_32 0x01 138 #define PCI_IO_RANGE_MASK (~0x0fUL) /* Standard 4K I/O windows */ 139 #define PCI_IO_1K_RANGE_MASK (~0x03UL) /* Intel 1K I/O windows */ 140 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ 141 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ 142 #define PCI_MEMORY_LIMIT 0x22 143 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL 144 #define PCI_MEMORY_RANGE_MASK (~0x0fUL) 145 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ 146 #define PCI_PREF_MEMORY_LIMIT 0x26 147 #define PCI_PREF_RANGE_TYPE_MASK 0x0fUL 148 #define PCI_PREF_RANGE_TYPE_32 0x00 149 #define PCI_PREF_RANGE_TYPE_64 0x01 150 #define PCI_PREF_RANGE_MASK (~0x0fUL) 151 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ 152 #define PCI_PREF_LIMIT_UPPER32 0x2c 153 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ 154 #define PCI_IO_LIMIT_UPPER16 0x32 155 /* 0x34 same as for htype 0 */ 156 /* 0x35-0x3b is reserved */ 157 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ 158 /* 0x3c-0x3d are same as for htype 0 */ 159 #define PCI_BRIDGE_CONTROL 0x3e 160 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ 161 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ 162 #define PCI_BRIDGE_CTL_ISA 0x04 /* Enable ISA mode */ 163 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ 164 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ 165 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ 166 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ 167 168 /* Header type 2 (CardBus bridges) */ 169 #define PCI_CB_CAPABILITY_LIST 0x14 170 /* 0x15 reserved */ 171 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ 172 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ 173 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ 174 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ 175 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ 176 #define PCI_CB_MEMORY_BASE_0 0x1c 177 #define PCI_CB_MEMORY_LIMIT_0 0x20 178 #define PCI_CB_MEMORY_BASE_1 0x24 179 #define PCI_CB_MEMORY_LIMIT_1 0x28 180 #define PCI_CB_IO_BASE_0 0x2c 181 #define PCI_CB_IO_BASE_0_HI 0x2e 182 #define PCI_CB_IO_LIMIT_0 0x30 183 #define PCI_CB_IO_LIMIT_0_HI 0x32 184 #define PCI_CB_IO_BASE_1 0x34 185 #define PCI_CB_IO_BASE_1_HI 0x36 186 #define PCI_CB_IO_LIMIT_1 0x38 187 #define PCI_CB_IO_LIMIT_1_HI 0x3a 188 #define PCI_CB_IO_RANGE_MASK (~0x03UL) 189 /* 0x3c-0x3d are same as for htype 0 */ 190 #define PCI_CB_BRIDGE_CONTROL 0x3e 191 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ 192 #define PCI_CB_BRIDGE_CTL_SERR 0x02 193 #define PCI_CB_BRIDGE_CTL_ISA 0x04 194 #define PCI_CB_BRIDGE_CTL_VGA 0x08 195 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 196 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ 197 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ 198 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ 199 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 200 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 201 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 202 #define PCI_CB_SUBSYSTEM_ID 0x42 203 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ 204 /* 0x48-0x7f reserved */ 205 206 /* Capability lists */ 207 208 #define PCI_CAP_LIST_ID 0 /* Capability ID */ 209 #define PCI_CAP_ID_PM 0x01 /* Power Management */ 210 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ 211 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ 212 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ 213 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ 214 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ 215 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ 216 #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ 217 #define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */ 218 #define PCI_CAP_ID_DBG 0x0A /* Debug port */ 219 #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ 220 #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ 221 #define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ 222 #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */ 223 #define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */ 224 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 225 #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ 226 #define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */ 227 #define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */ 228 #define PCI_CAP_ID_EA 0x14 /* PCI Enhanced Allocation */ 229 #define PCI_CAP_ID_MAX PCI_CAP_ID_EA 230 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ 231 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ 232 #define PCI_CAP_SIZEOF 4 233 234 /* Power Management Registers */ 235 236 #define PCI_PM_PMC 2 /* PM Capabilities Register */ 237 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ 238 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ 239 #define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */ 240 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ 241 #define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxiliary power support mask */ 242 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ 243 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ 244 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ 245 #define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */ 246 #define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */ 247 #define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */ 248 #define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */ 249 #define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */ 250 #define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */ 251 #define PCI_PM_CAP_PME_SHIFT 11 /* Start of the PME Mask in PMC */ 252 #define PCI_PM_CTRL 4 /* PM control and status register */ 253 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ 254 #define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */ 255 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ 256 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ 257 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ 258 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ 259 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ 260 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ 261 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ 262 #define PCI_PM_DATA_REGISTER 7 /* (??) */ 263 #define PCI_PM_SIZEOF 8 264 265 /* AGP registers */ 266 267 #define PCI_AGP_VERSION 2 /* BCD version number */ 268 #define PCI_AGP_RFU 3 /* Rest of capability flags */ 269 #define PCI_AGP_STATUS 4 /* Status register */ 270 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ 271 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ 272 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ 273 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ 274 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ 275 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ 276 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ 277 #define PCI_AGP_COMMAND 8 /* Control register */ 278 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ 279 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ 280 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ 281 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ 282 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ 283 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ 284 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */ 285 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */ 286 #define PCI_AGP_SIZEOF 12 287 288 /* Vital Product Data */ 289 290 #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */ 291 #define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */ 292 #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */ 293 #define PCI_VPD_DATA 4 /* 32-bits of data returned here */ 294 #define PCI_CAP_VPD_SIZEOF 8 295 296 /* Slot Identification */ 297 298 #define PCI_SID_ESR 2 /* Expansion Slot Register */ 299 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ 300 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ 301 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ 302 303 /* Message Signalled Interrupt registers */ 304 305 #define PCI_MSI_FLAGS 2 /* Message Control */ 306 #define PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */ 307 #define PCI_MSI_FLAGS_QMASK 0x000e /* Maximum queue size available */ 308 #define PCI_MSI_FLAGS_QSIZE 0x0070 /* Message queue size configured */ 309 #define PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */ 310 #define PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking capable */ 311 #define PCI_MSI_RFU 3 /* Rest of capability flags */ 312 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ 313 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ 314 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ 315 #define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit devices */ 316 #define PCI_MSI_PENDING_32 16 /* Pending intrs for 32-bit devices */ 317 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ 318 #define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */ 319 #define PCI_MSI_PENDING_64 20 /* Pending intrs for 64-bit devices */ 320 321 /* MSI-X registers (in MSI-X capability) */ 322 #define PCI_MSIX_FLAGS 2 /* Message Control */ 323 #define PCI_MSIX_FLAGS_QSIZE 0x07FF /* Table size */ 324 #define PCI_MSIX_FLAGS_MASKALL 0x4000 /* Mask all vectors for this function */ 325 #define PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */ 326 #define PCI_MSIX_TABLE 4 /* Table offset */ 327 #define PCI_MSIX_TABLE_BIR 0x00000007 /* BAR index */ 328 #define PCI_MSIX_TABLE_OFFSET 0xfffffff8 /* Offset into specified BAR */ 329 #define PCI_MSIX_PBA 8 /* Pending Bit Array offset */ 330 #define PCI_MSIX_PBA_BIR 0x00000007 /* BAR index */ 331 #define PCI_MSIX_PBA_OFFSET 0xfffffff8 /* Offset into specified BAR */ 332 #define PCI_MSIX_FLAGS_BIRMASK PCI_MSIX_PBA_BIR /* deprecated */ 333 #define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */ 334 335 /* MSI-X Table entry format (in memory mapped by a BAR) */ 336 #define PCI_MSIX_ENTRY_SIZE 16 337 #define PCI_MSIX_ENTRY_LOWER_ADDR 0 /* Message Address */ 338 #define PCI_MSIX_ENTRY_UPPER_ADDR 4 /* Message Upper Address */ 339 #define PCI_MSIX_ENTRY_DATA 8 /* Message Data */ 340 #define PCI_MSIX_ENTRY_VECTOR_CTRL 12 /* Vector Control */ 341 #define PCI_MSIX_ENTRY_CTRL_MASKBIT 0x00000001 342 343 /* CompactPCI Hotswap Register */ 344 345 #define PCI_CHSWP_CSR 2 /* Control and Status Register */ 346 #define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */ 347 #define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */ 348 #define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */ 349 #define PCI_CHSWP_LOO 0x08 /* LED On / Off */ 350 #define PCI_CHSWP_PI 0x30 /* Programming Interface */ 351 #define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */ 352 #define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */ 353 354 /* PCI Advanced Feature registers */ 355 356 #define PCI_AF_LENGTH 2 357 #define PCI_AF_CAP 3 358 #define PCI_AF_CAP_TP 0x01 359 #define PCI_AF_CAP_FLR 0x02 360 #define PCI_AF_CTRL 4 361 #define PCI_AF_CTRL_FLR 0x01 362 #define PCI_AF_STATUS 5 363 #define PCI_AF_STATUS_TP 0x01 364 #define PCI_CAP_AF_SIZEOF 6 /* size of AF registers */ 365 366 /* PCI Enhanced Allocation registers */ 367 368 #define PCI_EA_NUM_ENT 2 /* Number of Capability Entries */ 369 #define PCI_EA_NUM_ENT_MASK 0x3f /* Num Entries Mask */ 370 #define PCI_EA_FIRST_ENT 4 /* First EA Entry in List */ 371 #define PCI_EA_FIRST_ENT_BRIDGE 8 /* First EA Entry for Bridges */ 372 #define PCI_EA_ES 0x00000007 /* Entry Size */ 373 #define PCI_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */ 374 375 /* EA fixed Secondary and Subordinate bus numbers for Bridge */ 376 #define PCI_EA_SEC_BUS_MASK 0xff 377 #define PCI_EA_SUB_BUS_MASK 0xff00 378 #define PCI_EA_SUB_BUS_SHIFT 8 379 380 /* 0-5 map to BARs 0-5 respectively */ 381 #define PCI_EA_BEI_BAR0 0 382 #define PCI_EA_BEI_BAR5 5 383 #define PCI_EA_BEI_BRIDGE 6 /* Resource behind bridge */ 384 #define PCI_EA_BEI_ENI 7 /* Equivalent Not Indicated */ 385 #define PCI_EA_BEI_ROM 8 /* Expansion ROM */ 386 /* 9-14 map to VF BARs 0-5 respectively */ 387 #define PCI_EA_BEI_VF_BAR0 9 388 #define PCI_EA_BEI_VF_BAR5 14 389 #define PCI_EA_BEI_RESERVED 15 /* Reserved - Treat like ENI */ 390 #define PCI_EA_PP 0x0000ff00 /* Primary Properties */ 391 #define PCI_EA_SP 0x00ff0000 /* Secondary Properties */ 392 #define PCI_EA_P_MEM 0x00 /* Non-Prefetch Memory */ 393 #define PCI_EA_P_MEM_PREFETCH 0x01 /* Prefetchable Memory */ 394 #define PCI_EA_P_IO 0x02 /* I/O Space */ 395 #define PCI_EA_P_VF_MEM_PREFETCH 0x03 /* VF Prefetchable Memory */ 396 #define PCI_EA_P_VF_MEM 0x04 /* VF Non-Prefetch Memory */ 397 #define PCI_EA_P_BRIDGE_MEM 0x05 /* Bridge Non-Prefetch Memory */ 398 #define PCI_EA_P_BRIDGE_MEM_PREFETCH 0x06 /* Bridge Prefetchable Memory */ 399 #define PCI_EA_P_BRIDGE_IO 0x07 /* Bridge I/O Space */ 400 /* 0x08-0xfc reserved */ 401 #define PCI_EA_P_MEM_RESERVED 0xfd /* Reserved Memory */ 402 #define PCI_EA_P_IO_RESERVED 0xfe /* Reserved I/O Space */ 403 #define PCI_EA_P_UNAVAILABLE 0xff /* Entry Unavailable */ 404 #define PCI_EA_WRITABLE 0x40000000 /* Writable: 1 = RW, 0 = HwInit */ 405 #define PCI_EA_ENABLE 0x80000000 /* Enable for this entry */ 406 #define PCI_EA_BASE 4 /* Base Address Offset */ 407 #define PCI_EA_MAX_OFFSET 8 /* MaxOffset (resource length) */ 408 /* bit 0 is reserved */ 409 #define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */ 410 #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ 411 412 /* PCI-X registers (Type 0 (non-bridge) devices) */ 413 414 #define PCI_X_CMD 2 /* Modes & Features */ 415 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ 416 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ 417 #define PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */ 418 #define PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */ 419 #define PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */ 420 #define PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */ 421 #define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */ 422 /* Max # of outstanding split transactions */ 423 #define PCI_X_CMD_SPLIT_1 0x0000 /* Max 1 */ 424 #define PCI_X_CMD_SPLIT_2 0x0010 /* Max 2 */ 425 #define PCI_X_CMD_SPLIT_3 0x0020 /* Max 3 */ 426 #define PCI_X_CMD_SPLIT_4 0x0030 /* Max 4 */ 427 #define PCI_X_CMD_SPLIT_8 0x0040 /* Max 8 */ 428 #define PCI_X_CMD_SPLIT_12 0x0050 /* Max 12 */ 429 #define PCI_X_CMD_SPLIT_16 0x0060 /* Max 16 */ 430 #define PCI_X_CMD_SPLIT_32 0x0070 /* Max 32 */ 431 #define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */ 432 #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ 433 #define PCI_X_STATUS 4 /* PCI-X capabilities */ 434 #define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */ 435 #define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */ 436 #define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */ 437 #define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */ 438 #define PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */ 439 #define PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */ 440 #define PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity */ 441 #define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */ 442 #define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */ 443 #define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */ 444 #define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */ 445 #define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */ 446 #define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */ 447 #define PCI_X_ECC_CSR 8 /* ECC control and status */ 448 #define PCI_CAP_PCIX_SIZEOF_V0 8 /* size of registers for Version 0 */ 449 #define PCI_CAP_PCIX_SIZEOF_V1 24 /* size for Version 1 */ 450 #define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 /* Same for v2 */ 451 452 /* PCI-X registers (Type 1 (bridge) devices) */ 453 454 #define PCI_X_BRIDGE_SSTATUS 2 /* Secondary Status */ 455 #define PCI_X_SSTATUS_64BIT 0x0001 /* Secondary AD interface is 64 bits */ 456 #define PCI_X_SSTATUS_133MHZ 0x0002 /* 133 MHz capable */ 457 #define PCI_X_SSTATUS_FREQ 0x03c0 /* Secondary Bus Mode and Frequency */ 458 #define PCI_X_SSTATUS_VERS 0x3000 /* PCI-X Capability Version */ 459 #define PCI_X_SSTATUS_V1 0x1000 /* Mode 2, not Mode 1 */ 460 #define PCI_X_SSTATUS_V2 0x2000 /* Mode 1 or Modes 1 and 2 */ 461 #define PCI_X_SSTATUS_266MHZ 0x4000 /* 266 MHz capable */ 462 #define PCI_X_SSTATUS_533MHZ 0x8000 /* 533 MHz capable */ 463 #define PCI_X_BRIDGE_STATUS 4 /* Bridge Status */ 464 465 /* PCI Bridge Subsystem ID registers */ 466 467 #define PCI_SSVID_VENDOR_ID 4 /* PCI Bridge subsystem vendor ID */ 468 #define PCI_SSVID_DEVICE_ID 6 /* PCI Bridge subsystem device ID */ 469 470 /* PCI Express capability registers */ 471 472 #define PCI_EXP_FLAGS 2 /* Capabilities register */ 473 #define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */ 474 #define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ 475 #define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */ 476 #define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */ 477 #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ 478 #define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ 479 #define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ 480 #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */ 481 #define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */ 482 #define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */ 483 #define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */ 484 #define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ 485 #define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ 486 #define PCI_EXP_DEVCAP 4 /* Device capabilities */ 487 #define PCI_EXP_DEVCAP_PAYLOAD 0x00000007 /* Max_Payload_Size */ 488 #define PCI_EXP_DEVCAP_PHANTOM 0x00000018 /* Phantom functions */ 489 #define PCI_EXP_DEVCAP_EXT_TAG 0x00000020 /* Extended tags */ 490 #define PCI_EXP_DEVCAP_L0S 0x000001c0 /* L0s Acceptable Latency */ 491 #define PCI_EXP_DEVCAP_L1 0x00000e00 /* L1 Acceptable Latency */ 492 #define PCI_EXP_DEVCAP_ATN_BUT 0x00001000 /* Attention Button Present */ 493 #define PCI_EXP_DEVCAP_ATN_IND 0x00002000 /* Attention Indicator Present */ 494 #define PCI_EXP_DEVCAP_PWR_IND 0x00004000 /* Power Indicator Present */ 495 #define PCI_EXP_DEVCAP_RBER 0x00008000 /* Role-Based Error Reporting */ 496 #define PCI_EXP_DEVCAP_PWR_VAL 0x03fc0000 /* Slot Power Limit Value */ 497 #define PCI_EXP_DEVCAP_PWR_SCL 0x0c000000 /* Slot Power Limit Scale */ 498 #define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ 499 #define PCI_EXP_DEVCTL 8 /* Device Control */ 500 #define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */ 501 #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ 502 #define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */ 503 #define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */ 504 #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */ 505 #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ 506 #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */ 507 #define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */ 508 #define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */ 509 #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */ 510 #define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ 511 #define PCI_EXP_DEVCTL_READRQ_128B 0x0000 /* 128 Bytes */ 512 #define PCI_EXP_DEVCTL_READRQ_256B 0x1000 /* 256 Bytes */ 513 #define PCI_EXP_DEVCTL_READRQ_512B 0x2000 /* 512 Bytes */ 514 #define PCI_EXP_DEVCTL_READRQ_1024B 0x3000 /* 1024 Bytes */ 515 #define PCI_EXP_DEVCTL_READRQ_2048B 0x4000 /* 2048 Bytes */ 516 #define PCI_EXP_DEVCTL_READRQ_4096B 0x5000 /* 4096 Bytes */ 517 #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ 518 #define PCI_EXP_DEVSTA 10 /* Device Status */ 519 #define PCI_EXP_DEVSTA_CED 0x0001 /* Correctable Error Detected */ 520 #define PCI_EXP_DEVSTA_NFED 0x0002 /* Non-Fatal Error Detected */ 521 #define PCI_EXP_DEVSTA_FED 0x0004 /* Fatal Error Detected */ 522 #define PCI_EXP_DEVSTA_URD 0x0008 /* Unsupported Request Detected */ 523 #define PCI_EXP_DEVSTA_AUXPD 0x0010 /* AUX Power Detected */ 524 #define PCI_EXP_DEVSTA_TRPND 0x0020 /* Transactions Pending */ 525 #define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V1 12 /* v1 endpoints without link end here */ 526 #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ 527 #define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ 528 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */ 529 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */ 530 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */ 531 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */ 532 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */ 533 #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ 534 #define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */ 535 #define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */ 536 #define PCI_EXP_LNKCAP_L1EL 0x00038000 /* L1 Exit Latency */ 537 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 /* Clock Power Management */ 538 #define PCI_EXP_LNKCAP_SDERC 0x00080000 /* Surprise Down Error Reporting Capable */ 539 #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ 540 #define PCI_EXP_LNKCAP_LBNC 0x00200000 /* Link Bandwidth Notification Capability */ 541 #define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */ 542 #define PCI_EXP_LNKCTL 16 /* Link Control */ 543 #define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */ 544 #define PCI_EXP_LNKCTL_ASPM_L0S 0x0001 /* L0s Enable */ 545 #define PCI_EXP_LNKCTL_ASPM_L1 0x0002 /* L1 Enable */ 546 #define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */ 547 #define PCI_EXP_LNKCTL_LD 0x0010 /* Link Disable */ 548 #define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */ 549 #define PCI_EXP_LNKCTL_CCC 0x0040 /* Common Clock Configuration */ 550 #define PCI_EXP_LNKCTL_ES 0x0080 /* Extended Synch */ 551 #define PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 /* Enable clkreq */ 552 #define PCI_EXP_LNKCTL_HAWD 0x0200 /* Hardware Autonomous Width Disable */ 553 #define PCI_EXP_LNKCTL_LBMIE 0x0400 /* Link Bandwidth Management Interrupt Enable */ 554 #define PCI_EXP_LNKCTL_LABIE 0x0800 /* Link Autonomous Bandwidth Interrupt Enable */ 555 #define PCI_EXP_LNKSTA 18 /* Link Status */ 556 #define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ 557 #define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */ 558 #define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ 559 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ 560 #define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */ 561 #define PCI_EXP_LNKSTA_CLS_32_0GB 0x0005 /* Current Link Speed 32.0GT/s */ 562 #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ 563 #define PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */ 564 #define PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */ 565 #define PCI_EXP_LNKSTA_NLW_X4 0x0040 /* Current Link Width x4 */ 566 #define PCI_EXP_LNKSTA_NLW_X8 0x0080 /* Current Link Width x8 */ 567 #define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ 568 #define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */ 569 #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ 570 #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ 571 #define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */ 572 #define PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */ 573 #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 /* v1 endpoints with link end here */ 574 #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ 575 #define PCI_EXP_SLTCAP_ABP 0x00000001 /* Attention Button Present */ 576 #define PCI_EXP_SLTCAP_PCP 0x00000002 /* Power Controller Present */ 577 #define PCI_EXP_SLTCAP_MRLSP 0x00000004 /* MRL Sensor Present */ 578 #define PCI_EXP_SLTCAP_AIP 0x00000008 /* Attention Indicator Present */ 579 #define PCI_EXP_SLTCAP_PIP 0x00000010 /* Power Indicator Present */ 580 #define PCI_EXP_SLTCAP_HPS 0x00000020 /* Hot-Plug Surprise */ 581 #define PCI_EXP_SLTCAP_HPC 0x00000040 /* Hot-Plug Capable */ 582 #define PCI_EXP_SLTCAP_SPLV 0x00007f80 /* Slot Power Limit Value */ 583 #define PCI_EXP_SLTCAP_SPLS 0x00018000 /* Slot Power Limit Scale */ 584 #define PCI_EXP_SLTCAP_EIP 0x00020000 /* Electromechanical Interlock Present */ 585 #define PCI_EXP_SLTCAP_NCCS 0x00040000 /* No Command Completed Support */ 586 #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ 587 #define PCI_EXP_SLTCTL 24 /* Slot Control */ 588 #define PCI_EXP_SLTCTL_ABPE 0x0001 /* Attention Button Pressed Enable */ 589 #define PCI_EXP_SLTCTL_PFDE 0x0002 /* Power Fault Detected Enable */ 590 #define PCI_EXP_SLTCTL_MRLSCE 0x0004 /* MRL Sensor Changed Enable */ 591 #define PCI_EXP_SLTCTL_PDCE 0x0008 /* Presence Detect Changed Enable */ 592 #define PCI_EXP_SLTCTL_CCIE 0x0010 /* Command Completed Interrupt Enable */ 593 #define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */ 594 #define PCI_EXP_SLTCTL_AIC 0x00c0 /* Attention Indicator Control */ 595 #define PCI_EXP_SLTCTL_ATTN_IND_SHIFT 6 /* Attention Indicator shift */ 596 #define PCI_EXP_SLTCTL_ATTN_IND_ON 0x0040 /* Attention Indicator on */ 597 #define PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 /* Attention Indicator blinking */ 598 #define PCI_EXP_SLTCTL_ATTN_IND_OFF 0x00c0 /* Attention Indicator off */ 599 #define PCI_EXP_SLTCTL_PIC 0x0300 /* Power Indicator Control */ 600 #define PCI_EXP_SLTCTL_PWR_IND_ON 0x0100 /* Power Indicator on */ 601 #define PCI_EXP_SLTCTL_PWR_IND_BLINK 0x0200 /* Power Indicator blinking */ 602 #define PCI_EXP_SLTCTL_PWR_IND_OFF 0x0300 /* Power Indicator off */ 603 #define PCI_EXP_SLTCTL_PCC 0x0400 /* Power Controller Control */ 604 #define PCI_EXP_SLTCTL_PWR_ON 0x0000 /* Power On */ 605 #define PCI_EXP_SLTCTL_PWR_OFF 0x0400 /* Power Off */ 606 #define PCI_EXP_SLTCTL_EIC 0x0800 /* Electromechanical Interlock Control */ 607 #define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */ 608 #define PCI_EXP_SLTSTA 26 /* Slot Status */ 609 #define PCI_EXP_SLTSTA_ABP 0x0001 /* Attention Button Pressed */ 610 #define PCI_EXP_SLTSTA_PFD 0x0002 /* Power Fault Detected */ 611 #define PCI_EXP_SLTSTA_MRLSC 0x0004 /* MRL Sensor Changed */ 612 #define PCI_EXP_SLTSTA_PDC 0x0008 /* Presence Detect Changed */ 613 #define PCI_EXP_SLTSTA_CC 0x0010 /* Command Completed */ 614 #define PCI_EXP_SLTSTA_MRLSS 0x0020 /* MRL Sensor State */ 615 #define PCI_EXP_SLTSTA_PDS 0x0040 /* Presence Detect State */ 616 #define PCI_EXP_SLTSTA_EIS 0x0080 /* Electromechanical Interlock Status */ 617 #define PCI_EXP_SLTSTA_DLLSC 0x0100 /* Data Link Layer State Changed */ 618 #define PCI_EXP_RTCTL 28 /* Root Control */ 619 #define PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */ 620 #define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */ 621 #define PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */ 622 #define PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */ 623 #define PCI_EXP_RTCTL_CRSSVE 0x0010 /* CRS Software Visibility Enable */ 624 #define PCI_EXP_RTCAP 30 /* Root Capabilities */ 625 #define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */ 626 #define PCI_EXP_RTSTA 32 /* Root Status */ 627 #define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */ 628 #define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */ 629 /* 630 * The Device Capabilities 2, Device Status 2, Device Control 2, 631 * Link Capabilities 2, Link Status 2, Link Control 2, 632 * Slot Capabilities 2, Slot Status 2, and Slot Control 2 registers 633 * are only present on devices with PCIe Capability version 2. 634 * Use pcie_capability_read_word() and similar interfaces to use them 635 * safely. 636 */ 637 #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ 638 #define PCI_EXP_DEVCAP2_COMP_TMOUT_DIS 0x00000010 /* Completion Timeout Disable supported */ 639 #define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */ 640 #define PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040 /* Atomic Op routing */ 641 #define PCI_EXP_DEVCAP2_ATOMIC_COMP32 0x00000080 /* 32b AtomicOp completion */ 642 #define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* 64b AtomicOp completion */ 643 #define PCI_EXP_DEVCAP2_ATOMIC_COMP128 0x00000200 /* 128b AtomicOp completion */ 644 #define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */ 645 #define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */ 646 #define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */ 647 #define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */ 648 #define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */ 649 #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ 650 #define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */ 651 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010 /* Completion Timeout Disable */ 652 #define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */ 653 #define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */ 654 #define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */ 655 #define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */ 656 #define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */ 657 #define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */ 658 #define PCI_EXP_DEVCTL2_OBFF_MSGA_EN 0x2000 /* Enable OBFF Message type A */ 659 #define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000 /* Enable OBFF Message type B */ 660 #define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */ 661 #define PCI_EXP_DEVSTA2 42 /* Device Status 2 */ 662 #define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints without link end here */ 663 #define PCI_EXP_LNKCAP2 44 /* Link Capabilities 2 */ 664 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 /* Supported Speed 2.5GT/s */ 665 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5GT/s */ 666 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */ 667 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */ 668 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x00000020 /* Supported Speed 32GT/s */ 669 #define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */ 670 #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ 671 #define PCI_EXP_LNKCTL2_TLS 0x000f 672 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 673 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 674 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 675 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 676 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 677 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 678 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 679 #define PCI_EXP_LNKCTL2_HASD 0x0020 /* HW Autonomous Speed Disable */ 680 #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ 681 #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */ 682 #define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */ 683 #define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */ 684 #define PCI_EXP_SLTSTA2 58 /* Slot Status 2 */ 685 686 /* Extended Capabilities (PCI-X 2.0 and Express) */ 687 #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 688 #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 689 #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 690 691 #define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ 692 #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */ 693 #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ 694 #define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */ 695 #define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */ 696 #define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */ 697 #define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */ 698 #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */ 699 #define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */ 700 #define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */ 701 #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */ 702 #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */ 703 #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */ 704 #define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */ 705 #define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */ 706 #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ 707 #define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */ 708 #define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */ 709 #define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ 710 #define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */ 711 #define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */ 712 #define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */ 713 #define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */ 714 #define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */ 715 #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */ 716 #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ 717 #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ 718 #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ 719 #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ 720 #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ 721 #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ 722 #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ 723 #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT 724 725 #define PCI_EXT_CAP_DSN_SIZEOF 12 726 #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 727 728 /* Advanced Error Reporting */ 729 #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ 730 #define PCI_ERR_UNC_UND 0x00000001 /* Undefined */ 731 #define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */ 732 #define PCI_ERR_UNC_SURPDN 0x00000020 /* Surprise Down */ 733 #define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ 734 #define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */ 735 #define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */ 736 #define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */ 737 #define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */ 738 #define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */ 739 #define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */ 740 #define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */ 741 #define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */ 742 #define PCI_ERR_UNC_ACSV 0x00200000 /* ACS Violation */ 743 #define PCI_ERR_UNC_INTN 0x00400000 /* internal error */ 744 #define PCI_ERR_UNC_MCBTLP 0x00800000 /* MC blocked TLP */ 745 #define PCI_ERR_UNC_ATOMEG 0x01000000 /* Atomic egress blocked */ 746 #define PCI_ERR_UNC_TLPPRE 0x02000000 /* TLP prefix blocked */ 747 #define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */ 748 /* Same bits as above */ 749 #define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */ 750 /* Same bits as above */ 751 #define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */ 752 #define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */ 753 #define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */ 754 #define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */ 755 #define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */ 756 #define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */ 757 #define PCI_ERR_COR_ADV_NFAT 0x00002000 /* Advisory Non-Fatal */ 758 #define PCI_ERR_COR_INTERNAL 0x00004000 /* Corrected Internal */ 759 #define PCI_ERR_COR_LOG_OVER 0x00008000 /* Header Log Overflow */ 760 #define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */ 761 /* Same bits as above */ 762 #define PCI_ERR_CAP 24 /* Advanced Error Capabilities */ 763 #define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */ 764 #define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */ 765 #define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */ 766 #define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */ 767 #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */ 768 #define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */ 769 #define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */ 770 #define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 /* Correctable Err Reporting Enable */ 771 #define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Err Reporting Enable */ 772 #define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 /* Fatal Err Reporting Enable */ 773 #define PCI_ERR_ROOT_STATUS 48 774 #define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */ 775 #define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 /* Multiple ERR_COR */ 776 #define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 /* ERR_FATAL/NONFATAL */ 777 #define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 /* Multiple FATAL/NONFATAL */ 778 #define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First UNC is Fatal */ 779 #define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */ 780 #define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */ 781 #define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */ 782 #define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */ 783 784 /* Virtual Channel */ 785 #define PCI_VC_PORT_CAP1 4 786 #define PCI_VC_CAP1_EVCC 0x00000007 /* extended VC count */ 787 #define PCI_VC_CAP1_LPEVCC 0x00000070 /* low prio extended VC count */ 788 #define PCI_VC_CAP1_ARB_SIZE 0x00000c00 789 #define PCI_VC_PORT_CAP2 8 790 #define PCI_VC_CAP2_32_PHASE 0x00000002 791 #define PCI_VC_CAP2_64_PHASE 0x00000004 792 #define PCI_VC_CAP2_128_PHASE 0x00000008 793 #define PCI_VC_CAP2_ARB_OFF 0xff000000 794 #define PCI_VC_PORT_CTRL 12 795 #define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001 796 #define PCI_VC_PORT_STATUS 14 797 #define PCI_VC_PORT_STATUS_TABLE 0x00000001 798 #define PCI_VC_RES_CAP 16 799 #define PCI_VC_RES_CAP_32_PHASE 0x00000002 800 #define PCI_VC_RES_CAP_64_PHASE 0x00000004 801 #define PCI_VC_RES_CAP_128_PHASE 0x00000008 802 #define PCI_VC_RES_CAP_128_PHASE_TB 0x00000010 803 #define PCI_VC_RES_CAP_256_PHASE 0x00000020 804 #define PCI_VC_RES_CAP_ARB_OFF 0xff000000 805 #define PCI_VC_RES_CTRL 20 806 #define PCI_VC_RES_CTRL_LOAD_TABLE 0x00010000 807 #define PCI_VC_RES_CTRL_ARB_SELECT 0x000e0000 808 #define PCI_VC_RES_CTRL_ID 0x07000000 809 #define PCI_VC_RES_CTRL_ENABLE 0x80000000 810 #define PCI_VC_RES_STATUS 26 811 #define PCI_VC_RES_STATUS_TABLE 0x00000001 812 #define PCI_VC_RES_STATUS_NEGO 0x00000002 813 #define PCI_CAP_VC_BASE_SIZEOF 0x10 814 #define PCI_CAP_VC_PER_VC_SIZEOF 0x0C 815 816 /* Power Budgeting */ 817 #define PCI_PWR_DSR 4 /* Data Select Register */ 818 #define PCI_PWR_DATA 8 /* Data Register */ 819 #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */ 820 #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */ 821 #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */ 822 #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */ 823 #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ 824 #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ 825 #define PCI_PWR_CAP 12 /* Capability */ 826 #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ 827 #define PCI_EXT_CAP_PWR_SIZEOF 16 828 829 /* Vendor-Specific (VSEC, PCI_EXT_CAP_ID_VNDR) */ 830 #define PCI_VNDR_HEADER 4 /* Vendor-Specific Header */ 831 #define PCI_VNDR_HEADER_ID(x) ((x) & 0xffff) 832 #define PCI_VNDR_HEADER_REV(x) (((x) >> 16) & 0xf) 833 #define PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff) 834 835 /* 836 * HyperTransport sub capability types 837 * 838 * Unfortunately there are both 3 bit and 5 bit capability types defined 839 * in the HT spec, catering for that is a little messy. You probably don't 840 * want to use these directly, just use pci_find_ht_capability() and it 841 * will do the right thing for you. 842 */ 843 #define HT_3BIT_CAP_MASK 0xE0 844 #define HT_CAPTYPE_SLAVE 0x00 /* Slave/Primary link configuration */ 845 #define HT_CAPTYPE_HOST 0x20 /* Host/Secondary link configuration */ 846 847 #define HT_5BIT_CAP_MASK 0xF8 848 #define HT_CAPTYPE_IRQ 0x80 /* IRQ Configuration */ 849 #define HT_CAPTYPE_REMAPPING_40 0xA0 /* 40 bit address remapping */ 850 #define HT_CAPTYPE_REMAPPING_64 0xA2 /* 64 bit address remapping */ 851 #define HT_CAPTYPE_UNITID_CLUMP 0x90 /* Unit ID clumping */ 852 #define HT_CAPTYPE_EXTCONF 0x98 /* Extended Configuration Space Access */ 853 #define HT_CAPTYPE_MSI_MAPPING 0xA8 /* MSI Mapping Capability */ 854 #define HT_MSI_FLAGS 0x02 /* Offset to flags */ 855 #define HT_MSI_FLAGS_ENABLE 0x1 /* Mapping enable */ 856 #define HT_MSI_FLAGS_FIXED 0x2 /* Fixed mapping only */ 857 #define HT_MSI_FIXED_ADDR 0x00000000FEE00000ULL /* Fixed addr */ 858 #define HT_MSI_ADDR_LO 0x04 /* Offset to low addr bits */ 859 #define HT_MSI_ADDR_LO_MASK 0xFFF00000 /* Low address bit mask */ 860 #define HT_MSI_ADDR_HI 0x08 /* Offset to high addr bits */ 861 #define HT_CAPTYPE_DIRECT_ROUTE 0xB0 /* Direct routing configuration */ 862 #define HT_CAPTYPE_VCSET 0xB8 /* Virtual Channel configuration */ 863 #define HT_CAPTYPE_ERROR_RETRY 0xC0 /* Retry on error configuration */ 864 #define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 HyperTransport configuration */ 865 #define HT_CAPTYPE_PM 0xE0 /* HyperTransport power management configuration */ 866 #define HT_CAP_SIZEOF_LONG 28 /* slave & primary */ 867 #define HT_CAP_SIZEOF_SHORT 24 /* host & secondary */ 868 869 /* Alternative Routing-ID Interpretation */ 870 #define PCI_ARI_CAP 0x04 /* ARI Capability Register */ 871 #define PCI_ARI_CAP_MFVC 0x0001 /* MFVC Function Groups Capability */ 872 #define PCI_ARI_CAP_ACS 0x0002 /* ACS Function Groups Capability */ 873 #define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */ 874 #define PCI_ARI_CTRL 0x06 /* ARI Control Register */ 875 #define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */ 876 #define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */ 877 #define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */ 878 #define PCI_EXT_CAP_ARI_SIZEOF 8 879 880 /* Address Translation Service */ 881 #define PCI_ATS_CAP 0x04 /* ATS Capability Register */ 882 #define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f) /* Invalidate Queue Depth */ 883 #define PCI_ATS_MAX_QDEP 32 /* Max Invalidate Queue Depth */ 884 #define PCI_ATS_CAP_PAGE_ALIGNED 0x0020 /* Page Aligned Request */ 885 #define PCI_ATS_CTRL 0x06 /* ATS Control Register */ 886 #define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */ 887 #define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */ 888 #define PCI_ATS_MIN_STU 12 /* shift of minimum STU block */ 889 #define PCI_EXT_CAP_ATS_SIZEOF 8 890 891 /* Page Request Interface */ 892 #define PCI_PRI_CTRL 0x04 /* PRI control register */ 893 #define PCI_PRI_CTRL_ENABLE 0x0001 /* Enable */ 894 #define PCI_PRI_CTRL_RESET 0x0002 /* Reset */ 895 #define PCI_PRI_STATUS 0x06 /* PRI status register */ 896 #define PCI_PRI_STATUS_RF 0x0001 /* Response Failure */ 897 #define PCI_PRI_STATUS_UPRGI 0x0002 /* Unexpected PRG index */ 898 #define PCI_PRI_STATUS_STOPPED 0x0100 /* PRI Stopped */ 899 #define PCI_PRI_STATUS_PASID 0x8000 /* PRG Response PASID Required */ 900 #define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */ 901 #define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */ 902 #define PCI_EXT_CAP_PRI_SIZEOF 16 903 904 /* Process Address Space ID */ 905 #define PCI_PASID_CAP 0x04 /* PASID feature register */ 906 #define PCI_PASID_CAP_EXEC 0x02 /* Exec permissions Supported */ 907 #define PCI_PASID_CAP_PRIV 0x04 /* Privilege Mode Supported */ 908 #define PCI_PASID_CTRL 0x06 /* PASID control register */ 909 #define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */ 910 #define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */ 911 #define PCI_PASID_CTRL_PRIV 0x04 /* Privilege Mode Enable */ 912 #define PCI_EXT_CAP_PASID_SIZEOF 8 913 914 /* Single Root I/O Virtualization */ 915 #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ 916 #define PCI_SRIOV_CAP_VFM 0x00000001 /* VF Migration Capable */ 917 #define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */ 918 #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ 919 #define PCI_SRIOV_CTRL_VFE 0x0001 /* VF Enable */ 920 #define PCI_SRIOV_CTRL_VFM 0x0002 /* VF Migration Enable */ 921 #define PCI_SRIOV_CTRL_INTR 0x0004 /* VF Migration Interrupt Enable */ 922 #define PCI_SRIOV_CTRL_MSE 0x0008 /* VF Memory Space Enable */ 923 #define PCI_SRIOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */ 924 #define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */ 925 #define PCI_SRIOV_STATUS_VFM 0x0001 /* VF Migration Status */ 926 #define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */ 927 #define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */ 928 #define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */ 929 #define PCI_SRIOV_FUNC_LINK 0x12 /* Function Dependency Link */ 930 #define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */ 931 #define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */ 932 #define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */ 933 #define PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */ 934 #define PCI_SRIOV_SYS_PGSIZE 0x20 /* System Page Size */ 935 #define PCI_SRIOV_BAR 0x24 /* VF BAR0 */ 936 #define PCI_SRIOV_NUM_BARS 6 /* Number of VF BARs */ 937 #define PCI_SRIOV_VFM 0x3c /* VF Migration State Array Offset*/ 938 #define PCI_SRIOV_VFM_BIR(x) ((x) & 7) /* State BIR */ 939 #define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7) /* State Offset */ 940 #define PCI_SRIOV_VFM_UA 0x0 /* Inactive.Unavailable */ 941 #define PCI_SRIOV_VFM_MI 0x1 /* Dormant.MigrateIn */ 942 #define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */ 943 #define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */ 944 #define PCI_EXT_CAP_SRIOV_SIZEOF 64 945 946 #define PCI_LTR_MAX_SNOOP_LAT 0x4 947 #define PCI_LTR_MAX_NOSNOOP_LAT 0x6 948 #define PCI_LTR_VALUE_MASK 0x000003ff 949 #define PCI_LTR_SCALE_MASK 0x00001c00 950 #define PCI_LTR_SCALE_SHIFT 10 951 #define PCI_EXT_CAP_LTR_SIZEOF 8 952 953 /* Access Control Service */ 954 #define PCI_ACS_CAP 0x04 /* ACS Capability Register */ 955 #define PCI_ACS_SV 0x0001 /* Source Validation */ 956 #define PCI_ACS_TB 0x0002 /* Translation Blocking */ 957 #define PCI_ACS_RR 0x0004 /* P2P Request Redirect */ 958 #define PCI_ACS_CR 0x0008 /* P2P Completion Redirect */ 959 #define PCI_ACS_UF 0x0010 /* Upstream Forwarding */ 960 #define PCI_ACS_EC 0x0020 /* P2P Egress Control */ 961 #define PCI_ACS_DT 0x0040 /* Direct Translated P2P */ 962 #define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */ 963 #define PCI_ACS_CTRL 0x06 /* ACS Control Register */ 964 #define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */ 965 966 #define PCI_VSEC_HDR 4 /* extended cap - vendor-specific */ 967 #define PCI_VSEC_HDR_LEN_SHIFT 20 /* shift for length field */ 968 969 /* SATA capability */ 970 #define PCI_SATA_REGS 4 /* SATA REGs specifier */ 971 #define PCI_SATA_REGS_MASK 0xF /* location - BAR#/inline */ 972 #define PCI_SATA_REGS_INLINE 0xF /* REGS in config space */ 973 #define PCI_SATA_SIZEOF_SHORT 8 974 #define PCI_SATA_SIZEOF_LONG 16 975 976 /* Resizable BARs */ 977 #define PCI_REBAR_CAP 4 /* capability register */ 978 #define PCI_REBAR_CAP_SIZES 0x00FFFFF0 /* supported BAR sizes */ 979 #define PCI_REBAR_CTRL 8 /* control register */ 980 #define PCI_REBAR_CTRL_BAR_IDX 0x00000007 /* BAR index */ 981 #define PCI_REBAR_CTRL_NBAR_MASK 0x000000E0 /* # of resizable BARs */ 982 #define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # of BARs */ 983 #define PCI_REBAR_CTRL_BAR_SIZE 0x00001F00 /* BAR size */ 984 #define PCI_REBAR_CTRL_BAR_SHIFT 8 /* shift for BAR size */ 985 986 /* Dynamic Power Allocation */ 987 #define PCI_DPA_CAP 4 /* capability register */ 988 #define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */ 989 #define PCI_DPA_BASE_SIZEOF 16 /* size with 0 substates */ 990 991 /* TPH Requester */ 992 #define PCI_TPH_CAP 4 /* capability register */ 993 #define PCI_TPH_CAP_LOC_MASK 0x600 /* location mask */ 994 #define PCI_TPH_LOC_NONE 0x000 /* no location */ 995 #define PCI_TPH_LOC_CAP 0x200 /* in capability */ 996 #define PCI_TPH_LOC_MSIX 0x400 /* in MSI-X */ 997 #define PCI_TPH_CAP_ST_MASK 0x07FF0000 /* st table mask */ 998 #define PCI_TPH_CAP_ST_SHIFT 16 /* st table shift */ 999 #define PCI_TPH_BASE_SIZEOF 12 /* size with no st table */ 1000 1001 /* Downstream Port Containment */ 1002 #define PCI_EXP_DPC_CAP 4 /* DPC Capability */ 1003 #define PCI_EXP_DPC_IRQ 0x001F /* Interrupt Message Number */ 1004 #define PCI_EXP_DPC_CAP_RP_EXT 0x0020 /* Root Port Extensions */ 1005 #define PCI_EXP_DPC_CAP_POISONED_TLP 0x0040 /* Poisoned TLP Egress Blocking Supported */ 1006 #define PCI_EXP_DPC_CAP_SW_TRIGGER 0x0080 /* Software Triggering Supported */ 1007 #define PCI_EXP_DPC_RP_PIO_LOG_SIZE 0x0F00 /* RP PIO Log Size */ 1008 #define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */ 1009 1010 #define PCI_EXP_DPC_CTL 6 /* DPC control */ 1011 #define PCI_EXP_DPC_CTL_EN_FATAL 0x0001 /* Enable trigger on ERR_FATAL message */ 1012 #define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002 /* Enable trigger on ERR_NONFATAL message */ 1013 #define PCI_EXP_DPC_CTL_INT_EN 0x0008 /* DPC Interrupt Enable */ 1014 1015 #define PCI_EXP_DPC_STATUS 8 /* DPC Status */ 1016 #define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 /* Trigger Status */ 1017 #define PCI_EXP_DPC_STATUS_TRIGGER_RSN 0x0006 /* Trigger Reason */ 1018 #define PCI_EXP_DPC_STATUS_INTERRUPT 0x0008 /* Interrupt Status */ 1019 #define PCI_EXP_DPC_RP_BUSY 0x0010 /* Root Port Busy */ 1020 #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT 0x0060 /* Trig Reason Extension */ 1021 1022 #define PCI_EXP_DPC_SOURCE_ID 10 /* DPC Source Identifier */ 1023 1024 #define PCI_EXP_DPC_RP_PIO_STATUS 0x0C /* RP PIO Status */ 1025 #define PCI_EXP_DPC_RP_PIO_MASK 0x10 /* RP PIO Mask */ 1026 #define PCI_EXP_DPC_RP_PIO_SEVERITY 0x14 /* RP PIO Severity */ 1027 #define PCI_EXP_DPC_RP_PIO_SYSERROR 0x18 /* RP PIO SysError */ 1028 #define PCI_EXP_DPC_RP_PIO_EXCEPTION 0x1C /* RP PIO Exception */ 1029 #define PCI_EXP_DPC_RP_PIO_HEADER_LOG 0x20 /* RP PIO Header Log */ 1030 #define PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG 0x30 /* RP PIO ImpSpec Log */ 1031 #define PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG 0x34 /* RP PIO TLP Prefix Log */ 1032 1033 /* Precision Time Measurement */ 1034 #define PCI_PTM_CAP 0x04 /* PTM Capability */ 1035 #define PCI_PTM_CAP_REQ 0x00000001 /* Requester capable */ 1036 #define PCI_PTM_CAP_ROOT 0x00000004 /* Root capable */ 1037 #define PCI_PTM_GRANULARITY_MASK 0x0000FF00 /* Clock granularity */ 1038 #define PCI_PTM_CTRL 0x08 /* PTM Control */ 1039 #define PCI_PTM_CTRL_ENABLE 0x00000001 /* PTM enable */ 1040 #define PCI_PTM_CTRL_ROOT 0x00000002 /* Root select */ 1041 1042 /* ASPM L1 PM Substates */ 1043 #define PCI_L1SS_CAP 0x04 /* Capabilities Register */ 1044 #define PCI_L1SS_CAP_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Supported */ 1045 #define PCI_L1SS_CAP_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Supported */ 1046 #define PCI_L1SS_CAP_ASPM_L1_2 0x00000004 /* ASPM L1.2 Supported */ 1047 #define PCI_L1SS_CAP_ASPM_L1_1 0x00000008 /* ASPM L1.1 Supported */ 1048 #define PCI_L1SS_CAP_L1_PM_SS 0x00000010 /* L1 PM Substates Supported */ 1049 #define PCI_L1SS_CAP_CM_RESTORE_TIME 0x0000ff00 /* Port Common_Mode_Restore_Time */ 1050 #define PCI_L1SS_CAP_P_PWR_ON_SCALE 0x00030000 /* Port T_POWER_ON scale */ 1051 #define PCI_L1SS_CAP_P_PWR_ON_VALUE 0x00f80000 /* Port T_POWER_ON value */ 1052 #define PCI_L1SS_CTL1 0x08 /* Control 1 Register */ 1053 #define PCI_L1SS_CTL1_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Enable */ 1054 #define PCI_L1SS_CTL1_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Enable */ 1055 #define PCI_L1SS_CTL1_ASPM_L1_2 0x00000004 /* ASPM L1.2 Enable */ 1056 #define PCI_L1SS_CTL1_ASPM_L1_1 0x00000008 /* ASPM L1.1 Enable */ 1057 #define PCI_L1SS_CTL1_L1SS_MASK 0x0000000f 1058 #define PCI_L1SS_CTL1_CM_RESTORE_TIME 0x0000ff00 /* Common_Mode_Restore_Time */ 1059 #define PCI_L1SS_CTL1_LTR_L12_TH_VALUE 0x03ff0000 /* LTR_L1.2_THRESHOLD_Value */ 1060 #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ 1061 #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ 1062 1063 /* Data Link Feature */ 1064 #define PCI_DLF_CAP 0x04 /* Capabilities Register */ 1065 #define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */ 1066 1067 /* Physical Layer 16.0 GT/s */ 1068 #define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ 1069 #define PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK 0x0000000F 1070 #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0 1071 #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4 1072 1073 #endif /* LINUX_PCI_REGS_H */ 1074