1#!/usr/bin/python 2# 3# tool for querying VMX capabilities 4# 5# Copyright 2009-2010 Red Hat, Inc. 6# 7# Authors: 8# Avi Kivity <avi@redhat.com> 9# 10# This work is licensed under the terms of the GNU GPL, version 2. See 11# the COPYING file in the top-level directory. 12 13from __future__ import print_function 14MSR_IA32_VMX_BASIC = 0x480 15MSR_IA32_VMX_PINBASED_CTLS = 0x481 16MSR_IA32_VMX_PROCBASED_CTLS = 0x482 17MSR_IA32_VMX_EXIT_CTLS = 0x483 18MSR_IA32_VMX_ENTRY_CTLS = 0x484 19MSR_IA32_VMX_MISC_CTLS = 0x485 20MSR_IA32_VMX_PROCBASED_CTLS2 = 0x48B 21MSR_IA32_VMX_EPT_VPID_CAP = 0x48C 22MSR_IA32_VMX_TRUE_PINBASED_CTLS = 0x48D 23MSR_IA32_VMX_TRUE_PROCBASED_CTLS = 0x48E 24MSR_IA32_VMX_TRUE_EXIT_CTLS = 0x48F 25MSR_IA32_VMX_TRUE_ENTRY_CTLS = 0x490 26MSR_IA32_VMX_VMFUNC = 0x491 27 28class msr(object): 29 def __init__(self): 30 try: 31 self.f = open('/dev/cpu/0/msr', 'rb', 0) 32 except: 33 self.f = open('/dev/msr0', 'rb', 0) 34 def read(self, index, default = None): 35 import struct 36 self.f.seek(index) 37 try: 38 return struct.unpack('Q', self.f.read(8))[0] 39 except: 40 return default 41 42class Control(object): 43 def __init__(self, name, bits, cap_msr, true_cap_msr = None): 44 self.name = name 45 self.bits = bits 46 self.cap_msr = cap_msr 47 self.true_cap_msr = true_cap_msr 48 def read2(self, nr): 49 m = msr() 50 val = m.read(nr, 0) 51 return (val & 0xffffffff, val >> 32) 52 def show(self): 53 print(self.name) 54 mb1, cb1 = self.read2(self.cap_msr) 55 tmb1, tcb1 = 0, 0 56 if self.true_cap_msr: 57 tmb1, tcb1 = self.read2(self.true_cap_msr) 58 for bit in sorted(self.bits.keys()): 59 zero = not (mb1 & (1 << bit)) 60 one = cb1 & (1 << bit) 61 true_zero = not (tmb1 & (1 << bit)) 62 true_one = tcb1 & (1 << bit) 63 s= '?' 64 if (self.true_cap_msr and true_zero and true_one 65 and one and not zero): 66 s = 'default' 67 elif zero and not one: 68 s = 'no' 69 elif one and not zero: 70 s = 'forced' 71 elif one and zero: 72 s = 'yes' 73 print(' %-40s %s' % (self.bits[bit], s)) 74 75class Misc(object): 76 def __init__(self, name, bits, msr): 77 self.name = name 78 self.bits = bits 79 self.msr = msr 80 def show(self): 81 print(self.name) 82 value = msr().read(self.msr, 0) 83 print(' Hex: 0x%x' % (value)) 84 def first_bit(key): 85 if type(key) is tuple: 86 return key[0] 87 else: 88 return key 89 for bits in sorted(self.bits.keys(), key = first_bit): 90 if type(bits) is tuple: 91 lo, hi = bits 92 fmt = int 93 else: 94 lo = hi = bits 95 def fmt(x): 96 return { True: 'yes', False: 'no' }[x] 97 v = (value >> lo) & ((1 << (hi - lo + 1)) - 1) 98 print(' %-40s %s' % (self.bits[bits], fmt(v))) 99 100controls = [ 101 Misc( 102 name = 'Basic VMX Information', 103 bits = { 104 (0, 30): 'Revision', 105 (32,44): 'VMCS size', 106 48: 'VMCS restricted to 32 bit addresses', 107 49: 'Dual-monitor support', 108 (50, 53): 'VMCS memory type', 109 54: 'INS/OUTS instruction information', 110 55: 'IA32_VMX_TRUE_*_CTLS support', 111 }, 112 msr = MSR_IA32_VMX_BASIC, 113 ), 114 Control( 115 name = 'pin-based controls', 116 bits = { 117 0: 'External interrupt exiting', 118 3: 'NMI exiting', 119 5: 'Virtual NMIs', 120 6: 'Activate VMX-preemption timer', 121 7: 'Process posted interrupts', 122 }, 123 cap_msr = MSR_IA32_VMX_PINBASED_CTLS, 124 true_cap_msr = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 125 ), 126 127 Control( 128 name = 'primary processor-based controls', 129 bits = { 130 2: 'Interrupt window exiting', 131 3: 'Use TSC offsetting', 132 7: 'HLT exiting', 133 9: 'INVLPG exiting', 134 10: 'MWAIT exiting', 135 11: 'RDPMC exiting', 136 12: 'RDTSC exiting', 137 15: 'CR3-load exiting', 138 16: 'CR3-store exiting', 139 19: 'CR8-load exiting', 140 20: 'CR8-store exiting', 141 21: 'Use TPR shadow', 142 22: 'NMI-window exiting', 143 23: 'MOV-DR exiting', 144 24: 'Unconditional I/O exiting', 145 25: 'Use I/O bitmaps', 146 27: 'Monitor trap flag', 147 28: 'Use MSR bitmaps', 148 29: 'MONITOR exiting', 149 30: 'PAUSE exiting', 150 31: 'Activate secondary control', 151 }, 152 cap_msr = MSR_IA32_VMX_PROCBASED_CTLS, 153 true_cap_msr = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 154 ), 155 156 Control( 157 name = 'secondary processor-based controls', 158 bits = { 159 0: 'Virtualize APIC accesses', 160 1: 'Enable EPT', 161 2: 'Descriptor-table exiting', 162 3: 'Enable RDTSCP', 163 4: 'Virtualize x2APIC mode', 164 5: 'Enable VPID', 165 6: 'WBINVD exiting', 166 7: 'Unrestricted guest', 167 8: 'APIC register emulation', 168 9: 'Virtual interrupt delivery', 169 10: 'PAUSE-loop exiting', 170 11: 'RDRAND exiting', 171 12: 'Enable INVPCID', 172 13: 'Enable VM functions', 173 14: 'VMCS shadowing', 174 15: 'Enable ENCLS exiting', 175 16: 'RDSEED exiting', 176 17: 'Enable PML', 177 18: 'EPT-violation #VE', 178 19: 'Conceal non-root operation from PT', 179 20: 'Enable XSAVES/XRSTORS', 180 22: 'Mode-based execute control (XS/XU)', 181 23: 'Sub-page write permissions', 182 24: 'GPA translation for PT', 183 25: 'TSC scaling', 184 26: 'User wait and pause', 185 28: 'ENCLV exiting', 186 }, 187 cap_msr = MSR_IA32_VMX_PROCBASED_CTLS2, 188 ), 189 190 Control( 191 name = 'VM-Exit controls', 192 bits = { 193 2: 'Save debug controls', 194 9: 'Host address-space size', 195 12: 'Load IA32_PERF_GLOBAL_CTRL', 196 15: 'Acknowledge interrupt on exit', 197 18: 'Save IA32_PAT', 198 19: 'Load IA32_PAT', 199 20: 'Save IA32_EFER', 200 21: 'Load IA32_EFER', 201 22: 'Save VMX-preemption timer value', 202 23: 'Clear IA32_BNDCFGS', 203 24: 'Conceal VM exits from PT', 204 25: 'Clear IA32_RTIT_CTL', 205 }, 206 cap_msr = MSR_IA32_VMX_EXIT_CTLS, 207 true_cap_msr = MSR_IA32_VMX_TRUE_EXIT_CTLS, 208 ), 209 210 Control( 211 name = 'VM-Entry controls', 212 bits = { 213 2: 'Load debug controls', 214 9: 'IA-32e mode guest', 215 10: 'Entry to SMM', 216 11: 'Deactivate dual-monitor treatment', 217 13: 'Load IA32_PERF_GLOBAL_CTRL', 218 14: 'Load IA32_PAT', 219 15: 'Load IA32_EFER', 220 16: 'Load IA32_BNDCFGS', 221 17: 'Conceal VM entries from PT', 222 18: 'Load IA32_RTIT_CTL', 223 }, 224 cap_msr = MSR_IA32_VMX_ENTRY_CTLS, 225 true_cap_msr = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 226 ), 227 228 Misc( 229 name = 'Miscellaneous data', 230 bits = { 231 (0,4): 'VMX-preemption timer scale (log2)', 232 5: 'Store EFER.LMA into IA-32e mode guest control', 233 6: 'HLT activity state', 234 7: 'Shutdown activity state', 235 8: 'Wait-for-SIPI activity state', 236 14: 'PT in VMX operation', 237 15: 'IA32_SMBASE support', 238 (16,24): 'Number of CR3-target values', 239 (25,27): 'MSR-load/store count recommendation', 240 28: 'IA32_SMM_MONITOR_CTL[2] can be set to 1', 241 29: 'VMWRITE to VM-exit information fields', 242 30: 'Inject event with insn length=0', 243 (32,63): 'MSEG revision identifier', 244 }, 245 msr = MSR_IA32_VMX_MISC_CTLS, 246 ), 247 248 Misc( 249 name = 'VPID and EPT capabilities', 250 bits = { 251 0: 'Execute-only EPT translations', 252 6: 'Page-walk length 4', 253 8: 'Paging-structure memory type UC', 254 14: 'Paging-structure memory type WB', 255 16: '2MB EPT pages', 256 17: '1GB EPT pages', 257 20: 'INVEPT supported', 258 21: 'EPT accessed and dirty flags', 259 22: 'Advanced VM-exit information for EPT violations', 260 25: 'Single-context INVEPT', 261 26: 'All-context INVEPT', 262 32: 'INVVPID supported', 263 40: 'Individual-address INVVPID', 264 41: 'Single-context INVVPID', 265 42: 'All-context INVVPID', 266 43: 'Single-context-retaining-globals INVVPID', 267 }, 268 msr = MSR_IA32_VMX_EPT_VPID_CAP, 269 ), 270 Misc( 271 name = 'VM Functions', 272 bits = { 273 0: 'EPTP Switching', 274 }, 275 msr = MSR_IA32_VMX_VMFUNC, 276 ), 277 ] 278 279for c in controls: 280 c.show() 281