xref: /openbmc/qemu/rust/hw/char/pl011/src/lib.rs (revision 2e1cacfb)
1 // Copyright 2024, Linaro Limited
2 // Author(s): Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
3 // SPDX-License-Identifier: GPL-2.0-or-later
4 //
5 // PL011 QEMU Device Model
6 //
7 // This library implements a device model for the PrimeCell® UART (PL011)
8 // device in QEMU.
9 //
10 #![doc = include_str!("../README.md")]
11 //! # Library crate
12 //!
13 //! See [`PL011State`](crate::device::PL011State) for the device model type and
14 //! the [`registers`] module for register types.
15 
16 #![deny(
17     rustdoc::broken_intra_doc_links,
18     rustdoc::redundant_explicit_links,
19     clippy::correctness,
20     clippy::suspicious,
21     clippy::complexity,
22     clippy::perf,
23     clippy::cargo,
24     clippy::nursery,
25     clippy::style,
26     // restriction group
27     clippy::dbg_macro,
28     clippy::as_underscore,
29     clippy::assertions_on_result_states,
30     // pedantic group
31     clippy::doc_markdown,
32     clippy::borrow_as_ptr,
33     clippy::cast_lossless,
34     clippy::option_if_let_else,
35     clippy::missing_const_for_fn,
36     clippy::cognitive_complexity,
37     clippy::missing_safety_doc,
38     )]
39 
40 extern crate bilge;
41 extern crate bilge_impl;
42 extern crate qemu_api;
43 
44 pub mod device;
45 pub mod device_class;
46 pub mod memory_ops;
47 
48 pub const TYPE_PL011: &::core::ffi::CStr = c"pl011";
49 
50 /// Offset of each register from the base memory address of the device.
51 ///
52 /// # Source
53 /// ARM DDI 0183G, Table 3-1 p.3-3
54 #[doc(alias = "offset")]
55 #[allow(non_camel_case_types)]
56 #[repr(u64)]
57 #[derive(Debug)]
58 pub enum RegisterOffset {
59     /// Data Register
60     ///
61     /// A write to this register initiates the actual data transmission
62     #[doc(alias = "UARTDR")]
63     DR = 0x000,
64     /// Receive Status Register or Error Clear Register
65     #[doc(alias = "UARTRSR")]
66     #[doc(alias = "UARTECR")]
67     RSR = 0x004,
68     /// Flag Register
69     ///
70     /// A read of this register shows if transmission is complete
71     #[doc(alias = "UARTFR")]
72     FR = 0x018,
73     /// Fractional Baud Rate Register
74     ///
75     /// responsible for baud rate speed
76     #[doc(alias = "UARTFBRD")]
77     FBRD = 0x028,
78     /// `IrDA` Low-Power Counter Register
79     #[doc(alias = "UARTILPR")]
80     ILPR = 0x020,
81     /// Integer Baud Rate Register
82     ///
83     /// Responsible for baud rate speed
84     #[doc(alias = "UARTIBRD")]
85     IBRD = 0x024,
86     /// line control register (data frame format)
87     #[doc(alias = "UARTLCR_H")]
88     LCR_H = 0x02C,
89     /// Toggle UART, transmission or reception
90     #[doc(alias = "UARTCR")]
91     CR = 0x030,
92     /// Interrupt FIFO Level Select Register
93     #[doc(alias = "UARTIFLS")]
94     FLS = 0x034,
95     /// Interrupt Mask Set/Clear Register
96     #[doc(alias = "UARTIMSC")]
97     IMSC = 0x038,
98     /// Raw Interrupt Status Register
99     #[doc(alias = "UARTRIS")]
100     RIS = 0x03C,
101     /// Masked Interrupt Status Register
102     #[doc(alias = "UARTMIS")]
103     MIS = 0x040,
104     /// Interrupt Clear Register
105     #[doc(alias = "UARTICR")]
106     ICR = 0x044,
107     /// DMA control Register
108     #[doc(alias = "UARTDMACR")]
109     DMACR = 0x048,
110     ///// Reserved, offsets `0x04C` to `0x07C`.
111     //Reserved = 0x04C,
112 }
113 
114 impl core::convert::TryFrom<u64> for RegisterOffset {
115     type Error = u64;
116 
117     fn try_from(value: u64) -> Result<Self, Self::Error> {
118         macro_rules! case {
119             ($($discriminant:ident),*$(,)*) => {
120                 /* check that matching on all macro arguments compiles, which means we are not
121                  * missing any enum value; if the type definition ever changes this will stop
122                  * compiling.
123                  */
124                 const fn _assert_exhaustive(val: RegisterOffset) {
125                     match val {
126                         $(RegisterOffset::$discriminant => (),)*
127                     }
128                 }
129 
130                 match value {
131                     $(x if x == Self::$discriminant as u64 => Ok(Self::$discriminant),)*
132                      _ => Err(value),
133                 }
134             }
135         }
136         case! { DR, RSR, FR, FBRD, ILPR, IBRD, LCR_H, CR, FLS, IMSC, RIS, MIS, ICR, DMACR }
137     }
138 }
139 
140 pub mod registers {
141     //! Device registers exposed as typed structs which are backed by arbitrary
142     //! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc.
143     //!
144     //! All PL011 registers are essentially 32-bit wide, but are typed here as
145     //! bitmaps with only the necessary width. That is, if a struct bitmap
146     //! in this module is for example 16 bits long, it should be conceived
147     //! as a 32-bit register where the unmentioned higher bits are always
148     //! unused thus treated as zero when read or written.
149     use bilge::prelude::*;
150 
151     // TODO: FIFO Mode has different semantics
152     /// Data Register, `UARTDR`
153     ///
154     /// The `UARTDR` register is the data register.
155     ///
156     /// For words to be transmitted:
157     ///
158     /// - if the FIFOs are enabled, data written to this location is pushed onto
159     ///   the transmit
160     /// FIFO
161     /// - if the FIFOs are not enabled, data is stored in the transmitter
162     ///   holding register (the
163     /// bottom word of the transmit FIFO).
164     ///
165     /// The write operation initiates transmission from the UART. The data is
166     /// prefixed with a start bit, appended with the appropriate parity bit
167     /// (if parity is enabled), and a stop bit. The resultant word is then
168     /// transmitted.
169     ///
170     /// For received words:
171     ///
172     /// - if the FIFOs are enabled, the data byte and the 4-bit status (break,
173     ///   frame, parity,
174     /// and overrun) is pushed onto the 12-bit wide receive FIFO
175     /// - if the FIFOs are not enabled, the data byte and status are stored in
176     ///   the receiving
177     /// holding register (the bottom word of the receive FIFO).
178     ///
179     /// The received data byte is read by performing reads from the `UARTDR`
180     /// register along with the corresponding status information. The status
181     /// information can also be read by a read of the `UARTRSR/UARTECR`
182     /// register.
183     ///
184     /// # Note
185     ///
186     /// You must disable the UART before any of the control registers are
187     /// reprogrammed. When the UART is disabled in the middle of
188     /// transmission or reception, it completes the current character before
189     /// stopping.
190     ///
191     /// # Source
192     /// ARM DDI 0183G 3.3.1 Data Register, UARTDR
193     #[bitsize(16)]
194     #[derive(Clone, Copy, DebugBits, FromBits)]
195     #[doc(alias = "UARTDR")]
196     pub struct Data {
197         _reserved: u4,
198         pub data: u8,
199         pub framing_error: bool,
200         pub parity_error: bool,
201         pub break_error: bool,
202         pub overrun_error: bool,
203     }
204 
205     // TODO: FIFO Mode has different semantics
206     /// Receive Status Register / Error Clear Register, `UARTRSR/UARTECR`
207     ///
208     /// The UARTRSR/UARTECR register is the receive status register/error clear
209     /// register. Receive status can also be read from the `UARTRSR`
210     /// register. If the status is read from this register, then the status
211     /// information for break, framing and parity corresponds to the
212     /// data character read from the [Data register](Data), `UARTDR` prior to
213     /// reading the UARTRSR register. The status information for overrun is
214     /// set immediately when an overrun condition occurs.
215     ///
216     ///
217     /// # Note
218     /// The received data character must be read first from the [Data
219     /// Register](Data), `UARTDR` before reading the error status associated
220     /// with that data character from the `UARTRSR` register. This read
221     /// sequence cannot be reversed, because the `UARTRSR` register is
222     /// updated only when a read occurs from the `UARTDR` register. However,
223     /// the status information can also be obtained by reading the `UARTDR`
224     /// register
225     ///
226     /// # Source
227     /// ARM DDI 0183G 3.3.2 Receive Status Register/Error Clear Register,
228     /// UARTRSR/UARTECR
229     #[bitsize(8)]
230     #[derive(Clone, Copy, DebugBits, FromBits)]
231     pub struct ReceiveStatusErrorClear {
232         pub framing_error: bool,
233         pub parity_error: bool,
234         pub break_error: bool,
235         pub overrun_error: bool,
236         _reserved_unpredictable: u4,
237     }
238 
239     impl ReceiveStatusErrorClear {
240         pub fn reset(&mut self) {
241             // All the bits are cleared to 0 on reset.
242             *self = 0.into();
243         }
244     }
245 
246     impl Default for ReceiveStatusErrorClear {
247         fn default() -> Self {
248             0.into()
249         }
250     }
251 
252     #[bitsize(16)]
253     #[derive(Clone, Copy, DebugBits, FromBits)]
254     /// Flag Register, `UARTFR`
255     #[doc(alias = "UARTFR")]
256     pub struct Flags {
257         /// CTS Clear to send. This bit is the complement of the UART clear to
258         /// send, `nUARTCTS`, modem status input. That is, the bit is 1
259         /// when `nUARTCTS` is LOW.
260         pub clear_to_send: bool,
261         /// DSR Data set ready. This bit is the complement of the UART data set
262         /// ready, `nUARTDSR`, modem status input. That is, the bit is 1 when
263         /// `nUARTDSR` is LOW.
264         pub data_set_ready: bool,
265         /// DCD Data carrier detect. This bit is the complement of the UART data
266         /// carrier detect, `nUARTDCD`, modem status input. That is, the bit is
267         /// 1 when `nUARTDCD` is LOW.
268         pub data_carrier_detect: bool,
269         /// BUSY UART busy. If this bit is set to 1, the UART is busy
270         /// transmitting data. This bit remains set until the complete
271         /// byte, including all the stop bits, has been sent from the
272         /// shift register. This bit is set as soon as the transmit FIFO
273         /// becomes non-empty, regardless of whether the UART is enabled
274         /// or not.
275         pub busy: bool,
276         /// RXFE Receive FIFO empty. The meaning of this bit depends on the
277         /// state of the FEN bit in the UARTLCR_H register. If the FIFO
278         /// is disabled, this bit is set when the receive holding
279         /// register is empty. If the FIFO is enabled, the RXFE bit is
280         /// set when the receive FIFO is empty.
281         pub receive_fifo_empty: bool,
282         /// TXFF Transmit FIFO full. The meaning of this bit depends on the
283         /// state of the FEN bit in the UARTLCR_H register. If the FIFO
284         /// is disabled, this bit is set when the transmit holding
285         /// register is full. If the FIFO is enabled, the TXFF bit is
286         /// set when the transmit FIFO is full.
287         pub transmit_fifo_full: bool,
288         /// RXFF Receive FIFO full. The meaning of this bit depends on the state
289         /// of the FEN bit in the UARTLCR_H register. If the FIFO is
290         /// disabled, this bit is set when the receive holding register
291         /// is full. If the FIFO is enabled, the RXFF bit is set when
292         /// the receive FIFO is full.
293         pub receive_fifo_full: bool,
294         /// Transmit FIFO empty. The meaning of this bit depends on the state of
295         /// the FEN bit in the [Line Control register](LineControl),
296         /// `UARTLCR_H`. If the FIFO is disabled, this bit is set when the
297         /// transmit holding register is empty. If the FIFO is enabled,
298         /// the TXFE bit is set when the transmit FIFO is empty. This
299         /// bit does not indicate if there is data in the transmit shift
300         /// register.
301         pub transmit_fifo_empty: bool,
302         /// `RI`, is `true` when `nUARTRI` is `LOW`.
303         pub ring_indicator: bool,
304         _reserved_zero_no_modify: u7,
305     }
306 
307     impl Flags {
308         pub fn reset(&mut self) {
309             // After reset TXFF, RXFF, and BUSY are 0, and TXFE and RXFE are 1
310             self.set_receive_fifo_full(false);
311             self.set_transmit_fifo_full(false);
312             self.set_busy(false);
313             self.set_receive_fifo_empty(true);
314             self.set_transmit_fifo_empty(true);
315         }
316     }
317 
318     impl Default for Flags {
319         fn default() -> Self {
320             let mut ret: Self = 0.into();
321             ret.reset();
322             ret
323         }
324     }
325 
326     #[bitsize(16)]
327     #[derive(Clone, Copy, DebugBits, FromBits)]
328     /// Line Control Register, `UARTLCR_H`
329     #[doc(alias = "UARTLCR_H")]
330     pub struct LineControl {
331         /// 15:8 - Reserved, do not modify, read as zero.
332         _reserved_zero_no_modify: u8,
333         /// 7 SPS Stick parity select.
334         /// 0 = stick parity is disabled
335         /// 1 = either:
336         /// • if the EPS bit is 0 then the parity bit is transmitted and checked
337         /// as a 1 • if the EPS bit is 1 then the parity bit is
338         /// transmitted and checked as a 0. This bit has no effect when
339         /// the PEN bit disables parity checking and generation. See Table 3-11
340         /// on page 3-14 for the parity truth table.
341         pub sticky_parity: bool,
342         /// WLEN Word length. These bits indicate the number of data bits
343         /// transmitted or received in a frame as follows: b11 = 8 bits
344         /// b10 = 7 bits
345         /// b01 = 6 bits
346         /// b00 = 5 bits.
347         pub word_length: WordLength,
348         /// FEN Enable FIFOs:
349         /// 0 = FIFOs are disabled (character mode) that is, the FIFOs become
350         /// 1-byte-deep holding registers 1 = transmit and receive FIFO
351         /// buffers are enabled (FIFO mode).
352         pub fifos_enabled: Mode,
353         /// 3 STP2 Two stop bits select. If this bit is set to 1, two stop bits
354         /// are transmitted at the end of the frame. The receive
355         /// logic does not check for two stop bits being received.
356         pub two_stops_bits: bool,
357         /// EPS Even parity select. Controls the type of parity the UART uses
358         /// during transmission and reception:
359         /// - 0 = odd parity. The UART generates or checks for an odd number of
360         ///   1s in the data and parity bits.
361         /// - 1 = even parity. The UART generates or checks for an even number
362         ///   of 1s in the data and parity bits.
363         /// This bit has no effect when the `PEN` bit disables parity checking
364         /// and generation. See Table 3-11 on page 3-14 for the parity
365         /// truth table.
366         pub parity: Parity,
367         /// 1 PEN Parity enable:
368         ///
369         /// - 0 = parity is disabled and no parity bit added to the data frame
370         /// - 1 = parity checking and generation is enabled.
371         ///
372         /// See Table 3-11 on page 3-14 for the parity truth table.
373         pub parity_enabled: bool,
374         /// BRK Send break.
375         ///
376         /// If this bit is set to `1`, a low-level is continually output on the
377         /// `UARTTXD` output, after completing transmission of the
378         /// current character. For the proper execution of the break command,
379         /// the software must set this bit for at least two complete
380         /// frames. For normal use, this bit must be cleared to `0`.
381         pub send_break: bool,
382     }
383 
384     impl LineControl {
385         pub fn reset(&mut self) {
386             // All the bits are cleared to 0 when reset.
387             *self = 0.into();
388         }
389     }
390 
391     impl Default for LineControl {
392         fn default() -> Self {
393             0.into()
394         }
395     }
396 
397     #[bitsize(1)]
398     #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)]
399     /// `EPS` "Even parity select", field of [Line Control
400     /// register](LineControl).
401     pub enum Parity {
402         /// - 0 = odd parity. The UART generates or checks for an odd number of
403         ///   1s in the data and parity bits.
404         Odd = 0,
405         /// - 1 = even parity. The UART generates or checks for an even number
406         ///   of 1s in the data and parity bits.
407         Even = 1,
408     }
409 
410     #[bitsize(1)]
411     #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)]
412     /// `FEN` "Enable FIFOs" or Device mode, field of [Line Control
413     /// register](LineControl).
414     pub enum Mode {
415         /// 0 = FIFOs are disabled (character mode) that is, the FIFOs become
416         /// 1-byte-deep holding registers
417         Character = 0,
418         /// 1 = transmit and receive FIFO buffers are enabled (FIFO mode).
419         FIFO = 1,
420     }
421 
422     impl From<Mode> for bool {
423         fn from(val: Mode) -> Self {
424             matches!(val, Mode::FIFO)
425         }
426     }
427 
428     #[bitsize(2)]
429     #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)]
430     /// `WLEN` Word length, field of [Line Control register](LineControl).
431     ///
432     /// These bits indicate the number of data bits transmitted or received in a
433     /// frame as follows:
434     pub enum WordLength {
435         /// b11 = 8 bits
436         _8Bits = 0b11,
437         /// b10 = 7 bits
438         _7Bits = 0b10,
439         /// b01 = 6 bits
440         _6Bits = 0b01,
441         /// b00 = 5 bits.
442         _5Bits = 0b00,
443     }
444 
445     /// Control Register, `UARTCR`
446     ///
447     /// The `UARTCR` register is the control register. All the bits are cleared
448     /// to `0` on reset except for bits `9` and `8` that are set to `1`.
449     ///
450     /// # Source
451     /// ARM DDI 0183G, 3.3.8 Control Register, `UARTCR`, Table 3-12
452     #[bitsize(16)]
453     #[doc(alias = "UARTCR")]
454     #[derive(Clone, Copy, DebugBits, FromBits)]
455     pub struct Control {
456         /// `UARTEN` UART enable: 0 = UART is disabled. If the UART is disabled
457         /// in the middle of transmission or reception, it completes the current
458         /// character before stopping. 1 = the UART is enabled. Data
459         /// transmission and reception occurs for either UART signals or SIR
460         /// signals depending on the setting of the SIREN bit.
461         pub enable_uart: bool,
462         /// `SIREN` `SIR` enable: 0 = IrDA SIR ENDEC is disabled. `nSIROUT`
463         /// remains LOW (no light pulse generated), and signal transitions on
464         /// SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is
465         /// transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH,
466         /// in the marking state. Signal transitions on UARTRXD or modem status
467         /// inputs have no effect. This bit has no effect if the UARTEN bit
468         /// disables the UART.
469         pub enable_sir: bool,
470         /// `SIRLP` SIR low-power IrDA mode. This bit selects the IrDA encoding
471         /// mode. If this bit is cleared to 0, low-level bits are transmitted as
472         /// an active high pulse with a width of 3/ 16th of the bit period. If
473         /// this bit is set to 1, low-level bits are transmitted with a pulse
474         /// width that is 3 times the period of the IrLPBaud16 input signal,
475         /// regardless of the selected bit rate. Setting this bit uses less
476         /// power, but might reduce transmission distances.
477         pub sir_lowpower_irda_mode: u1,
478         /// Reserved, do not modify, read as zero.
479         _reserved_zero_no_modify: u4,
480         /// `LBE` Loopback enable. If this bit is set to 1 and the SIREN bit is
481         /// set to 1 and the SIRTEST bit in the Test Control register, UARTTCR
482         /// on page 4-5 is set to 1, then the nSIROUT path is inverted, and fed
483         /// through to the SIRIN path. The SIRTEST bit in the test register must
484         /// be set to 1 to override the normal half-duplex SIR operation. This
485         /// must be the requirement for accessing the test registers during
486         /// normal operation, and SIRTEST must be cleared to 0 when loopback
487         /// testing is finished. This feature reduces the amount of external
488         /// coupling required during system test. If this bit is set to 1, and
489         /// the SIRTEST bit is set to 0, the UARTTXD path is fed through to the
490         /// UARTRXD path. In either SIR mode or UART mode, when this bit is set,
491         /// the modem outputs are also fed through to the modem inputs. This bit
492         /// is cleared to 0 on reset, to disable loopback.
493         pub enable_loopback: bool,
494         /// `TXE` Transmit enable. If this bit is set to 1, the transmit section
495         /// of the UART is enabled. Data transmission occurs for either UART
496         /// signals, or SIR signals depending on the setting of the SIREN bit.
497         /// When the UART is disabled in the middle of transmission, it
498         /// completes the current character before stopping.
499         pub enable_transmit: bool,
500         /// `RXE` Receive enable. If this bit is set to 1, the receive section
501         /// of the UART is enabled. Data reception occurs for either UART
502         /// signals or SIR signals depending on the setting of the SIREN bit.
503         /// When the UART is disabled in the middle of reception, it completes
504         /// the current character before stopping.
505         pub enable_receive: bool,
506         /// `DTR` Data transmit ready. This bit is the complement of the UART
507         /// data transmit ready, `nUARTDTR`, modem status output. That is, when
508         /// the bit is programmed to a 1 then `nUARTDTR` is LOW.
509         pub data_transmit_ready: bool,
510         /// `RTS` Request to send. This bit is the complement of the UART
511         /// request to send, `nUARTRTS`, modem status output. That is, when the
512         /// bit is programmed to a 1 then `nUARTRTS` is LOW.
513         pub request_to_send: bool,
514         /// `Out1` This bit is the complement of the UART Out1 (`nUARTOut1`)
515         /// modem status output. That is, when the bit is programmed to a 1 the
516         /// output is 0. For DTE this can be used as Data Carrier Detect (DCD).
517         pub out_1: bool,
518         /// `Out2` This bit is the complement of the UART Out2 (`nUARTOut2`)
519         /// modem status output. That is, when the bit is programmed to a 1, the
520         /// output is 0. For DTE this can be used as Ring Indicator (RI).
521         pub out_2: bool,
522         /// `RTSEn` RTS hardware flow control enable. If this bit is set to 1,
523         /// RTS hardware flow control is enabled. Data is only requested when
524         /// there is space in the receive FIFO for it to be received.
525         pub rts_hardware_flow_control_enable: bool,
526         /// `CTSEn` CTS hardware flow control enable. If this bit is set to 1,
527         /// CTS hardware flow control is enabled. Data is only transmitted when
528         /// the `nUARTCTS` signal is asserted.
529         pub cts_hardware_flow_control_enable: bool,
530     }
531 
532     impl Control {
533         pub fn reset(&mut self) {
534             *self = 0.into();
535             self.set_enable_receive(true);
536             self.set_enable_transmit(true);
537         }
538     }
539 
540     impl Default for Control {
541         fn default() -> Self {
542             let mut ret: Self = 0.into();
543             ret.reset();
544             ret
545         }
546     }
547 
548     /// Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC
549     pub const INT_OE: u32 = 1 << 10;
550     pub const INT_BE: u32 = 1 << 9;
551     pub const INT_PE: u32 = 1 << 8;
552     pub const INT_FE: u32 = 1 << 7;
553     pub const INT_RT: u32 = 1 << 6;
554     pub const INT_TX: u32 = 1 << 5;
555     pub const INT_RX: u32 = 1 << 4;
556     pub const INT_DSR: u32 = 1 << 3;
557     pub const INT_DCD: u32 = 1 << 2;
558     pub const INT_CTS: u32 = 1 << 1;
559     pub const INT_RI: u32 = 1 << 0;
560     pub const INT_E: u32 = INT_OE | INT_BE | INT_PE | INT_FE;
561     pub const INT_MS: u32 = INT_RI | INT_DSR | INT_DCD | INT_CTS;
562 
563     #[repr(u32)]
564     pub enum Interrupt {
565         OE = 1 << 10,
566         BE = 1 << 9,
567         PE = 1 << 8,
568         FE = 1 << 7,
569         RT = 1 << 6,
570         TX = 1 << 5,
571         RX = 1 << 4,
572         DSR = 1 << 3,
573         DCD = 1 << 2,
574         CTS = 1 << 1,
575         RI = 1 << 0,
576     }
577 
578     impl Interrupt {
579         pub const E: u32 = INT_OE | INT_BE | INT_PE | INT_FE;
580         pub const MS: u32 = INT_RI | INT_DSR | INT_DCD | INT_CTS;
581     }
582 }
583 
584 // TODO: You must disable the UART before any of the control registers are
585 // reprogrammed. When the UART is disabled in the middle of transmission or
586 // reception, it completes the current character before stopping
587