1 // Copyright 2024, Linaro Limited 2 // Author(s): Manos Pitsidianakis <manos.pitsidianakis@linaro.org> 3 // SPDX-License-Identifier: GPL-2.0-or-later 4 5 use core::ptr::{addr_of, addr_of_mut, NonNull}; 6 use std::{ 7 ffi::CStr, 8 ops::ControlFlow, 9 os::raw::{c_int, c_void}, 10 }; 11 12 use qemu_api::{ 13 bindings::{ 14 error_fatal, hwaddr, memory_region_init_io, qdev_init_clock_in, qdev_new, 15 qdev_prop_set_chr, qemu_chr_fe_ioctl, qemu_chr_fe_set_handlers, qemu_chr_fe_write_all, 16 qemu_irq, sysbus_connect_irq, sysbus_mmio_map, sysbus_realize_and_unref, CharBackend, 17 Chardev, Clock, ClockEvent, MemoryRegion, QEMUChrEvent, CHR_IOCTL_SERIAL_SET_BREAK, 18 }, 19 c_str, impl_vmstate_forward, 20 irq::InterruptSource, 21 prelude::*, 22 qdev::{DeviceImpl, DeviceState, Property}, 23 qom::{ClassInitImpl, ObjectImpl, ParentField}, 24 sysbus::{SysBusDevice, SysBusDeviceClass}, 25 vmstate::VMStateDescription, 26 }; 27 28 use crate::{ 29 device_class, 30 memory_ops::PL011_OPS, 31 registers::{self, Interrupt}, 32 RegisterOffset, 33 }; 34 35 /// Integer Baud Rate Divider, `UARTIBRD` 36 const IBRD_MASK: u32 = 0xffff; 37 38 /// Fractional Baud Rate Divider, `UARTFBRD` 39 const FBRD_MASK: u32 = 0x3f; 40 41 /// QEMU sourced constant. 42 pub const PL011_FIFO_DEPTH: u32 = 16; 43 44 #[derive(Clone, Copy)] 45 struct DeviceId(&'static [u8; 8]); 46 47 impl std::ops::Index<hwaddr> for DeviceId { 48 type Output = u8; 49 50 fn index(&self, idx: hwaddr) -> &Self::Output { 51 &self.0[idx as usize] 52 } 53 } 54 55 impl DeviceId { 56 const ARM: Self = Self(&[0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1]); 57 const LUMINARY: Self = Self(&[0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1]); 58 } 59 60 // FIFOs use 32-bit indices instead of usize, for compatibility with 61 // the migration stream produced by the C version of this device. 62 #[repr(transparent)] 63 #[derive(Debug, Default)] 64 pub struct Fifo([registers::Data; PL011_FIFO_DEPTH as usize]); 65 impl_vmstate_forward!(Fifo); 66 67 impl Fifo { 68 const fn len(&self) -> u32 { 69 self.0.len() as u32 70 } 71 } 72 73 impl std::ops::IndexMut<u32> for Fifo { 74 fn index_mut(&mut self, idx: u32) -> &mut Self::Output { 75 &mut self.0[idx as usize] 76 } 77 } 78 79 impl std::ops::Index<u32> for Fifo { 80 type Output = registers::Data; 81 82 fn index(&self, idx: u32) -> &Self::Output { 83 &self.0[idx as usize] 84 } 85 } 86 87 #[repr(C)] 88 #[derive(Debug, qemu_api_macros::Object, qemu_api_macros::offsets)] 89 /// PL011 Device Model in QEMU 90 pub struct PL011State { 91 pub parent_obj: ParentField<SysBusDevice>, 92 pub iomem: MemoryRegion, 93 #[doc(alias = "fr")] 94 pub flags: registers::Flags, 95 #[doc(alias = "lcr")] 96 pub line_control: registers::LineControl, 97 #[doc(alias = "rsr")] 98 pub receive_status_error_clear: registers::ReceiveStatusErrorClear, 99 #[doc(alias = "cr")] 100 pub control: registers::Control, 101 pub dmacr: u32, 102 pub int_enabled: u32, 103 pub int_level: u32, 104 pub read_fifo: Fifo, 105 pub ilpr: u32, 106 pub ibrd: u32, 107 pub fbrd: u32, 108 pub ifl: u32, 109 pub read_pos: u32, 110 pub read_count: u32, 111 pub read_trigger: u32, 112 #[doc(alias = "chr")] 113 pub char_backend: CharBackend, 114 /// QEMU interrupts 115 /// 116 /// ```text 117 /// * sysbus MMIO region 0: device registers 118 /// * sysbus IRQ 0: `UARTINTR` (combined interrupt line) 119 /// * sysbus IRQ 1: `UARTRXINTR` (receive FIFO interrupt line) 120 /// * sysbus IRQ 2: `UARTTXINTR` (transmit FIFO interrupt line) 121 /// * sysbus IRQ 3: `UARTRTINTR` (receive timeout interrupt line) 122 /// * sysbus IRQ 4: `UARTMSINTR` (momem status interrupt line) 123 /// * sysbus IRQ 5: `UARTEINTR` (error interrupt line) 124 /// ``` 125 #[doc(alias = "irq")] 126 pub interrupts: [InterruptSource; IRQMASK.len()], 127 #[doc(alias = "clk")] 128 pub clock: NonNull<Clock>, 129 #[doc(alias = "migrate_clk")] 130 pub migrate_clock: bool, 131 } 132 133 qom_isa!(PL011State : SysBusDevice, DeviceState, Object); 134 135 #[repr(C)] 136 pub struct PL011Class { 137 parent_class: <SysBusDevice as ObjectType>::Class, 138 /// The byte string that identifies the device. 139 device_id: DeviceId, 140 } 141 142 unsafe impl ObjectType for PL011State { 143 type Class = PL011Class; 144 const TYPE_NAME: &'static CStr = crate::TYPE_PL011; 145 } 146 147 impl ClassInitImpl<PL011Class> for PL011State { 148 fn class_init(klass: &mut PL011Class) { 149 klass.device_id = DeviceId::ARM; 150 <Self as ClassInitImpl<SysBusDeviceClass>>::class_init(&mut klass.parent_class); 151 } 152 } 153 154 impl ObjectImpl for PL011State { 155 type ParentType = SysBusDevice; 156 157 const INSTANCE_INIT: Option<unsafe fn(&mut Self)> = Some(Self::init); 158 const INSTANCE_POST_INIT: Option<fn(&Self)> = Some(Self::post_init); 159 } 160 161 impl DeviceImpl for PL011State { 162 fn properties() -> &'static [Property] { 163 &device_class::PL011_PROPERTIES 164 } 165 fn vmsd() -> Option<&'static VMStateDescription> { 166 Some(&device_class::VMSTATE_PL011) 167 } 168 const REALIZE: Option<fn(&Self)> = Some(Self::realize); 169 const RESET: Option<fn(&mut Self)> = Some(Self::reset); 170 } 171 172 impl PL011State { 173 /// Initializes a pre-allocated, unitialized instance of `PL011State`. 174 /// 175 /// # Safety 176 /// 177 /// `self` must point to a correctly sized and aligned location for the 178 /// `PL011State` type. It must not be called more than once on the same 179 /// location/instance. All its fields are expected to hold unitialized 180 /// values with the sole exception of `parent_obj`. 181 unsafe fn init(&mut self) { 182 const CLK_NAME: &CStr = c_str!("clk"); 183 184 // SAFETY: 185 // 186 // self and self.iomem are guaranteed to be valid at this point since callers 187 // must make sure the `self` reference is valid. 188 unsafe { 189 memory_region_init_io( 190 addr_of_mut!(self.iomem), 191 addr_of_mut!(*self).cast::<Object>(), 192 &PL011_OPS, 193 addr_of_mut!(*self).cast::<c_void>(), 194 Self::TYPE_NAME.as_ptr(), 195 0x1000, 196 ); 197 } 198 199 // SAFETY: 200 // 201 // self.clock is not initialized at this point; but since `NonNull<_>` is Copy, 202 // we can overwrite the undefined value without side effects. This is 203 // safe since all PL011State instances are created by QOM code which 204 // calls this function to initialize the fields; therefore no code is 205 // able to access an invalid self.clock value. 206 unsafe { 207 let dev: &mut DeviceState = self.upcast_mut(); 208 self.clock = NonNull::new(qdev_init_clock_in( 209 dev, 210 CLK_NAME.as_ptr(), 211 None, /* pl011_clock_update */ 212 addr_of_mut!(*self).cast::<c_void>(), 213 ClockEvent::ClockUpdate.0, 214 )) 215 .unwrap(); 216 } 217 } 218 219 fn post_init(&self) { 220 self.init_mmio(&self.iomem); 221 for irq in self.interrupts.iter() { 222 self.init_irq(irq); 223 } 224 } 225 226 fn regs_read(&mut self, offset: RegisterOffset) -> ControlFlow<u32, u32> { 227 use RegisterOffset::*; 228 229 ControlFlow::Break(match offset { 230 DR => { 231 self.flags.set_receive_fifo_full(false); 232 let c = self.read_fifo[self.read_pos]; 233 if self.read_count > 0 { 234 self.read_count -= 1; 235 self.read_pos = (self.read_pos + 1) & (self.fifo_depth() - 1); 236 } 237 if self.read_count == 0 { 238 self.flags.set_receive_fifo_empty(true); 239 } 240 if self.read_count + 1 == self.read_trigger { 241 self.int_level &= !registers::INT_RX; 242 } 243 // Update error bits. 244 self.receive_status_error_clear.set_from_data(c); 245 // Must call qemu_chr_fe_accept_input, so return Continue: 246 return ControlFlow::Continue(u32::from(c)); 247 } 248 RSR => u32::from(self.receive_status_error_clear), 249 FR => u32::from(self.flags), 250 FBRD => self.fbrd, 251 ILPR => self.ilpr, 252 IBRD => self.ibrd, 253 LCR_H => u32::from(self.line_control), 254 CR => u32::from(self.control), 255 FLS => self.ifl, 256 IMSC => self.int_enabled, 257 RIS => self.int_level, 258 MIS => self.int_level & self.int_enabled, 259 ICR => { 260 // "The UARTICR Register is the interrupt clear register and is write-only" 261 // Source: ARM DDI 0183G 3.3.13 Interrupt Clear Register, UARTICR 262 0 263 } 264 DMACR => self.dmacr, 265 }) 266 } 267 268 fn regs_write(&mut self, offset: RegisterOffset, value: u32) -> bool { 269 // eprintln!("write offset {offset} value {value}"); 270 use RegisterOffset::*; 271 match offset { 272 DR => { 273 // interrupts always checked 274 let _ = self.loopback_tx(value); 275 self.int_level |= registers::INT_TX; 276 return true; 277 } 278 RSR => { 279 self.receive_status_error_clear = 0.into(); 280 } 281 FR => { 282 // flag writes are ignored 283 } 284 ILPR => { 285 self.ilpr = value; 286 } 287 IBRD => { 288 self.ibrd = value; 289 } 290 FBRD => { 291 self.fbrd = value; 292 } 293 LCR_H => { 294 let new_val: registers::LineControl = value.into(); 295 // Reset the FIFO state on FIFO enable or disable 296 if self.line_control.fifos_enabled() != new_val.fifos_enabled() { 297 self.reset_rx_fifo(); 298 self.reset_tx_fifo(); 299 } 300 let update = (self.line_control.send_break() != new_val.send_break()) && { 301 let mut break_enable: c_int = new_val.send_break().into(); 302 // SAFETY: self.char_backend is a valid CharBackend instance after it's been 303 // initialized in realize(). 304 unsafe { 305 qemu_chr_fe_ioctl( 306 addr_of_mut!(self.char_backend), 307 CHR_IOCTL_SERIAL_SET_BREAK as i32, 308 addr_of_mut!(break_enable).cast::<c_void>(), 309 ); 310 } 311 self.loopback_break(break_enable > 0) 312 }; 313 self.line_control = new_val; 314 self.set_read_trigger(); 315 return update; 316 } 317 CR => { 318 // ??? Need to implement the enable bit. 319 self.control = value.into(); 320 return self.loopback_mdmctrl(); 321 } 322 FLS => { 323 self.ifl = value; 324 self.set_read_trigger(); 325 } 326 IMSC => { 327 self.int_enabled = value; 328 return true; 329 } 330 RIS => {} 331 MIS => {} 332 ICR => { 333 self.int_level &= !value; 334 return true; 335 } 336 DMACR => { 337 self.dmacr = value; 338 if value & 3 > 0 { 339 // qemu_log_mask(LOG_UNIMP, "pl011: DMA not implemented\n"); 340 eprintln!("pl011: DMA not implemented"); 341 } 342 } 343 } 344 false 345 } 346 347 #[inline] 348 #[must_use] 349 fn loopback_tx(&mut self, value: u32) -> bool { 350 // Caveat: 351 // 352 // In real hardware, TX loopback happens at the serial-bit level 353 // and then reassembled by the RX logics back into bytes and placed 354 // into the RX fifo. That is, loopback happens after TX fifo. 355 // 356 // Because the real hardware TX fifo is time-drained at the frame 357 // rate governed by the configured serial format, some loopback 358 // bytes in TX fifo may still be able to get into the RX fifo 359 // that could be full at times while being drained at software 360 // pace. 361 // 362 // In such scenario, the RX draining pace is the major factor 363 // deciding which loopback bytes get into the RX fifo, unless 364 // hardware flow-control is enabled. 365 // 366 // For simplicity, the above described is not emulated. 367 self.loopback_enabled() && self.put_fifo(value) 368 } 369 370 #[must_use] 371 fn loopback_mdmctrl(&mut self) -> bool { 372 if !self.loopback_enabled() { 373 return false; 374 } 375 376 /* 377 * Loopback software-driven modem control outputs to modem status inputs: 378 * FR.RI <= CR.Out2 379 * FR.DCD <= CR.Out1 380 * FR.CTS <= CR.RTS 381 * FR.DSR <= CR.DTR 382 * 383 * The loopback happens immediately even if this call is triggered 384 * by setting only CR.LBE. 385 * 386 * CTS/RTS updates due to enabled hardware flow controls are not 387 * dealt with here. 388 */ 389 390 self.flags.set_ring_indicator(self.control.out_2()); 391 self.flags.set_data_carrier_detect(self.control.out_1()); 392 self.flags.set_clear_to_send(self.control.request_to_send()); 393 self.flags 394 .set_data_set_ready(self.control.data_transmit_ready()); 395 396 // Change interrupts based on updated FR 397 let mut il = self.int_level; 398 399 il &= !Interrupt::MS; 400 401 if self.flags.data_set_ready() { 402 il |= Interrupt::DSR as u32; 403 } 404 if self.flags.data_carrier_detect() { 405 il |= Interrupt::DCD as u32; 406 } 407 if self.flags.clear_to_send() { 408 il |= Interrupt::CTS as u32; 409 } 410 if self.flags.ring_indicator() { 411 il |= Interrupt::RI as u32; 412 } 413 self.int_level = il; 414 true 415 } 416 417 fn loopback_break(&mut self, enable: bool) -> bool { 418 enable && self.loopback_tx(registers::Data::BREAK.into()) 419 } 420 421 fn set_read_trigger(&mut self) { 422 self.read_trigger = 1; 423 } 424 425 pub fn realize(&self) { 426 // SAFETY: self.char_backend has the correct size and alignment for a 427 // CharBackend object, and its callbacks are of the correct types. 428 unsafe { 429 qemu_chr_fe_set_handlers( 430 addr_of!(self.char_backend) as *mut CharBackend, 431 Some(pl011_can_receive), 432 Some(pl011_receive), 433 Some(pl011_event), 434 None, 435 addr_of!(*self).cast::<c_void>() as *mut c_void, 436 core::ptr::null_mut(), 437 true, 438 ); 439 } 440 } 441 442 pub fn reset(&mut self) { 443 self.line_control.reset(); 444 self.receive_status_error_clear.reset(); 445 self.dmacr = 0; 446 self.int_enabled = 0; 447 self.int_level = 0; 448 self.ilpr = 0; 449 self.ibrd = 0; 450 self.fbrd = 0; 451 self.read_trigger = 1; 452 self.ifl = 0x12; 453 self.control.reset(); 454 self.flags.reset(); 455 self.reset_rx_fifo(); 456 self.reset_tx_fifo(); 457 } 458 459 pub fn reset_rx_fifo(&mut self) { 460 self.read_count = 0; 461 self.read_pos = 0; 462 463 // Reset FIFO flags 464 self.flags.set_receive_fifo_full(false); 465 self.flags.set_receive_fifo_empty(true); 466 } 467 468 pub fn reset_tx_fifo(&mut self) { 469 // Reset FIFO flags 470 self.flags.set_transmit_fifo_full(false); 471 self.flags.set_transmit_fifo_empty(true); 472 } 473 474 pub fn can_receive(&self) -> bool { 475 // trace_pl011_can_receive(s->lcr, s->read_count, r); 476 self.read_count < self.fifo_depth() 477 } 478 479 pub fn receive(&mut self, ch: u32) { 480 if !self.loopback_enabled() && self.put_fifo(ch) { 481 self.update(); 482 } 483 } 484 485 pub fn event(&mut self, event: QEMUChrEvent) { 486 if event == QEMUChrEvent::CHR_EVENT_BREAK && !self.loopback_enabled() { 487 let update = self.put_fifo(registers::Data::BREAK.into()); 488 if update { 489 self.update(); 490 } 491 } 492 } 493 494 #[inline] 495 pub fn fifo_enabled(&self) -> bool { 496 self.line_control.fifos_enabled() == registers::Mode::FIFO 497 } 498 499 #[inline] 500 pub fn loopback_enabled(&self) -> bool { 501 self.control.enable_loopback() 502 } 503 504 #[inline] 505 pub fn fifo_depth(&self) -> u32 { 506 // Note: FIFO depth is expected to be power-of-2 507 if self.fifo_enabled() { 508 return PL011_FIFO_DEPTH; 509 } 510 1 511 } 512 513 #[must_use] 514 pub fn put_fifo(&mut self, value: u32) -> bool { 515 let depth = self.fifo_depth(); 516 assert!(depth > 0); 517 let slot = (self.read_pos + self.read_count) & (depth - 1); 518 self.read_fifo[slot] = registers::Data::from(value); 519 self.read_count += 1; 520 self.flags.set_receive_fifo_empty(false); 521 if self.read_count == depth { 522 self.flags.set_receive_fifo_full(true); 523 } 524 525 if self.read_count == self.read_trigger { 526 self.int_level |= registers::INT_RX; 527 return true; 528 } 529 false 530 } 531 532 pub fn update(&self) { 533 let flags = self.int_level & self.int_enabled; 534 for (irq, i) in self.interrupts.iter().zip(IRQMASK) { 535 irq.set(flags & i != 0); 536 } 537 } 538 539 pub fn post_load(&mut self, _version_id: u32) -> Result<(), ()> { 540 /* Sanity-check input state */ 541 if self.read_pos >= self.read_fifo.len() || self.read_count > self.read_fifo.len() { 542 return Err(()); 543 } 544 545 if !self.fifo_enabled() && self.read_count > 0 && self.read_pos > 0 { 546 // Older versions of PL011 didn't ensure that the single 547 // character in the FIFO in FIFO-disabled mode is in 548 // element 0 of the array; convert to follow the current 549 // code's assumptions. 550 self.read_fifo[0] = self.read_fifo[self.read_pos]; 551 self.read_pos = 0; 552 } 553 554 self.ibrd &= IBRD_MASK; 555 self.fbrd &= FBRD_MASK; 556 557 Ok(()) 558 } 559 560 pub fn read(&mut self, offset: hwaddr, _size: u32) -> ControlFlow<u64, u64> { 561 let mut update_irq = false; 562 let result = match RegisterOffset::try_from(offset) { 563 Err(v) if (0x3f8..0x400).contains(&(v >> 2)) => { 564 let device_id = self.get_class().device_id; 565 ControlFlow::Break(u64::from(device_id[(offset - 0xfe0) >> 2])) 566 } 567 Err(_) => { 568 // qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset 0x%x\n", (int)offset); 569 ControlFlow::Break(0) 570 } 571 Ok(field) => match self.regs_read(field) { 572 ControlFlow::Break(value) => ControlFlow::Break(value.into()), 573 ControlFlow::Continue(value) => { 574 update_irq = true; 575 ControlFlow::Continue(value.into()) 576 } 577 }, 578 }; 579 if update_irq { 580 self.update(); 581 } 582 result 583 } 584 585 pub fn write(&mut self, offset: hwaddr, value: u64) { 586 let mut update_irq = false; 587 if let Ok(field) = RegisterOffset::try_from(offset) { 588 // qemu_chr_fe_write_all() calls into the can_receive 589 // callback, so handle writes before entering PL011Registers. 590 if field == RegisterOffset::DR { 591 // ??? Check if transmitter is enabled. 592 let ch: u8 = value as u8; 593 // SAFETY: char_backend is a valid CharBackend instance after it's been 594 // initialized in realize(). 595 // XXX this blocks entire thread. Rewrite to use 596 // qemu_chr_fe_write and background I/O callbacks 597 unsafe { 598 qemu_chr_fe_write_all(&mut self.char_backend, &ch, 1); 599 } 600 } 601 602 update_irq = self.regs_write(field, value as u32); 603 } else { 604 eprintln!("write bad offset {offset} value {value}"); 605 } 606 if update_irq { 607 self.update(); 608 } 609 } 610 } 611 612 /// Which bits in the interrupt status matter for each outbound IRQ line ? 613 const IRQMASK: [u32; 6] = [ 614 /* combined IRQ */ 615 Interrupt::E 616 | Interrupt::MS 617 | Interrupt::RT as u32 618 | Interrupt::TX as u32 619 | Interrupt::RX as u32, 620 Interrupt::RX as u32, 621 Interrupt::TX as u32, 622 Interrupt::RT as u32, 623 Interrupt::MS, 624 Interrupt::E, 625 ]; 626 627 /// # Safety 628 /// 629 /// We expect the FFI user of this function to pass a valid pointer, that has 630 /// the same size as [`PL011State`]. We also expect the device is 631 /// readable/writeable from one thread at any time. 632 pub unsafe extern "C" fn pl011_can_receive(opaque: *mut c_void) -> c_int { 633 let state = NonNull::new(opaque).unwrap().cast::<PL011State>(); 634 unsafe { state.as_ref().can_receive().into() } 635 } 636 637 /// # Safety 638 /// 639 /// We expect the FFI user of this function to pass a valid pointer, that has 640 /// the same size as [`PL011State`]. We also expect the device is 641 /// readable/writeable from one thread at any time. 642 /// 643 /// The buffer and size arguments must also be valid. 644 pub unsafe extern "C" fn pl011_receive(opaque: *mut c_void, buf: *const u8, size: c_int) { 645 let mut state = NonNull::new(opaque).unwrap().cast::<PL011State>(); 646 unsafe { 647 if size > 0 { 648 debug_assert!(!buf.is_null()); 649 state.as_mut().receive(u32::from(buf.read_volatile())); 650 } 651 } 652 } 653 654 /// # Safety 655 /// 656 /// We expect the FFI user of this function to pass a valid pointer, that has 657 /// the same size as [`PL011State`]. We also expect the device is 658 /// readable/writeable from one thread at any time. 659 pub unsafe extern "C" fn pl011_event(opaque: *mut c_void, event: QEMUChrEvent) { 660 let mut state = NonNull::new(opaque).unwrap().cast::<PL011State>(); 661 unsafe { state.as_mut().event(event) } 662 } 663 664 /// # Safety 665 /// 666 /// We expect the FFI user of this function to pass a valid pointer for `chr`. 667 #[no_mangle] 668 pub unsafe extern "C" fn pl011_create( 669 addr: u64, 670 irq: qemu_irq, 671 chr: *mut Chardev, 672 ) -> *mut DeviceState { 673 unsafe { 674 let dev: *mut DeviceState = qdev_new(PL011State::TYPE_NAME.as_ptr()); 675 let sysbus: *mut SysBusDevice = dev.cast::<SysBusDevice>(); 676 677 qdev_prop_set_chr(dev, c_str!("chardev").as_ptr(), chr); 678 sysbus_realize_and_unref(sysbus, addr_of_mut!(error_fatal)); 679 sysbus_mmio_map(sysbus, 0, addr); 680 sysbus_connect_irq(sysbus, 0, irq); 681 dev 682 } 683 } 684 685 #[repr(C)] 686 #[derive(Debug, qemu_api_macros::Object)] 687 /// PL011 Luminary device model. 688 pub struct PL011Luminary { 689 parent_obj: ParentField<PL011State>, 690 } 691 692 impl ClassInitImpl<PL011Class> for PL011Luminary { 693 fn class_init(klass: &mut PL011Class) { 694 klass.device_id = DeviceId::LUMINARY; 695 <Self as ClassInitImpl<SysBusDeviceClass>>::class_init(&mut klass.parent_class); 696 } 697 } 698 699 qom_isa!(PL011Luminary : PL011State, SysBusDevice, DeviceState, Object); 700 701 unsafe impl ObjectType for PL011Luminary { 702 type Class = <PL011State as ObjectType>::Class; 703 const TYPE_NAME: &'static CStr = crate::TYPE_PL011_LUMINARY; 704 } 705 706 impl ObjectImpl for PL011Luminary { 707 type ParentType = PL011State; 708 } 709 710 impl DeviceImpl for PL011Luminary {} 711