1# -*- Mode: Python -*- 2# vim: filetype=python 3# 4# This work is licensed under the terms of the GNU GPL, version 2 or later. 5# See the COPYING file in the top-level directory. 6 7## 8# = Common machine types 9## 10 11## 12# @S390CpuEntitlement: 13# 14# An enumeration of CPU entitlements that can be assumed by a virtual 15# S390 CPU 16# 17# Since: 8.2 18## 19{ 'enum': 'S390CpuEntitlement', 20 'data': [ 'auto', 'low', 'medium', 'high' ] } 21 22## 23# @CpuTopologyLevel: 24# 25# An enumeration of CPU topology levels. 26# 27# @thread: thread level, which would also be called SMT level or 28# logical processor level. The @threads option in 29# SMPConfiguration is used to configure the topology of this 30# level. 31# 32# @core: core level. The @cores option in SMPConfiguration is used 33# to configure the topology of this level. 34# 35# @module: module level. The @modules option in SMPConfiguration is 36# used to configure the topology of this level. 37# 38# @cluster: cluster level. The @clusters option in SMPConfiguration 39# is used to configure the topology of this level. 40# 41# @die: die level. The @dies option in SMPConfiguration is used to 42# configure the topology of this level. 43# 44# @socket: socket level, which would also be called package level. 45# The @sockets option in SMPConfiguration is used to configure 46# the topology of this level. 47# 48# @book: book level. The @books option in SMPConfiguration is used 49# to configure the topology of this level. 50# 51# @drawer: drawer level. The @drawers option in SMPConfiguration is 52# used to configure the topology of this level. 53# 54# @default: default level. Some architectures will have default 55# topology settings (e.g., cache topology), and this special 56# level means following the architecture-specific settings. 57# 58# Since: 9.2 59## 60{ 'enum': 'CpuTopologyLevel', 61 'data': [ 'thread', 'core', 'module', 'cluster', 'die', 62 'socket', 'book', 'drawer', 'default' ] } 63 64## 65# @CacheLevelAndType: 66# 67# Caches a system may have. The enumeration value here is the 68# combination of cache level and cache type. 69# 70# @l1d: L1 data cache. 71# 72# @l1i: L1 instruction cache. 73# 74# @l2: L2 (unified) cache. 75# 76# @l3: L3 (unified) cache 77# 78# Since: 9.2 79## 80{ 'enum': 'CacheLevelAndType', 81 'data': [ 'l1d', 'l1i', 'l2', 'l3' ] } 82 83## 84# @SmpCacheProperties: 85# 86# Cache information for SMP system. 87# 88# @cache: Cache name, which is the combination of cache level 89# and cache type. 90# 91# @topology: Cache topology level. It accepts the CPU topology 92# enumeration as the parameter, i.e., CPUs in the same 93# topology container share the same cache. 94# 95# Since: 9.2 96## 97{ 'struct': 'SmpCacheProperties', 98 'data': { 99 'cache': 'CacheLevelAndType', 100 'topology': 'CpuTopologyLevel' } } 101 102## 103# @SmpCachePropertiesWrapper: 104# 105# List wrapper of SmpCacheProperties. 106# 107# @caches: the list of SmpCacheProperties. 108# 109# Since 9.2 110## 111{ 'struct': 'SmpCachePropertiesWrapper', 112 'data': { 'caches': ['SmpCacheProperties'] } } 113