1# -*- Mode: Python -*- 2# vim: filetype=python 3# 4# This work is licensed under the terms of the GNU GPL, version 2 or later. 5# See the COPYING file in the top-level directory. 6 7## 8# ******************** 9# Common machine types 10# ******************** 11## 12 13## 14# @S390CpuEntitlement: 15# 16# An enumeration of CPU entitlements that can be assumed by a virtual 17# S390 CPU 18# 19# Since: 8.2 20## 21{ 'enum': 'S390CpuEntitlement', 22 'data': [ 'auto', 'low', 'medium', 'high' ] } 23 24## 25# @CpuTopologyLevel: 26# 27# An enumeration of CPU topology levels. 28# 29# @thread: thread level, which would also be called SMT level or 30# logical processor level. The @threads option in 31# `SMPConfiguration` is used to configure the topology of this 32# level. 33# 34# @core: core level. The @cores option in `SMPConfiguration` is used 35# to configure the topology of this level. 36# 37# @module: module level. The @modules option in `SMPConfiguration` is 38# used to configure the topology of this level. 39# 40# @cluster: cluster level. The @clusters option in `SMPConfiguration` 41# is used to configure the topology of this level. 42# 43# @die: die level. The @dies option in `SMPConfiguration` is used to 44# configure the topology of this level. 45# 46# @socket: socket level, which would also be called package level. 47# The @sockets option in `SMPConfiguration` is used to configure 48# the topology of this level. 49# 50# @book: book level. The @books option in `SMPConfiguration` is used 51# to configure the topology of this level. 52# 53# @drawer: drawer level. The @drawers option in `SMPConfiguration` is 54# used to configure the topology of this level. 55# 56# @default: default level. Some architectures will have default 57# topology settings (e.g., cache topology), and this special 58# level means following the architecture-specific settings. 59# 60# Since: 9.2 61## 62{ 'enum': 'CpuTopologyLevel', 63 'data': [ 'thread', 'core', 'module', 'cluster', 'die', 64 'socket', 'book', 'drawer', 'default' ] } 65 66## 67# @CacheLevelAndType: 68# 69# Caches a system may have. The enumeration value here is the 70# combination of cache level and cache type. 71# 72# @l1d: L1 data cache. 73# 74# @l1i: L1 instruction cache. 75# 76# @l2: L2 (unified) cache. 77# 78# @l3: L3 (unified) cache 79# 80# Since: 9.2 81## 82{ 'enum': 'CacheLevelAndType', 83 'data': [ 'l1d', 'l1i', 'l2', 'l3' ] } 84 85## 86# @SmpCacheProperties: 87# 88# Cache information for SMP system. 89# 90# @cache: Cache name, which is the combination of cache level 91# and cache type. 92# 93# @topology: Cache topology level. It accepts the CPU topology 94# enumeration as the parameter, i.e., CPUs in the same 95# topology container share the same cache. 96# 97# Since: 9.2 98## 99{ 'struct': 'SmpCacheProperties', 100 'data': { 101 'cache': 'CacheLevelAndType', 102 'topology': 'CpuTopologyLevel' } } 103 104## 105# @SmpCachePropertiesWrapper: 106# 107# List wrapper of `SmpCacheProperties`. 108# 109# @caches: the list of `SmpCacheProperties`. 110# 111# Since 9.2 112## 113{ 'struct': 'SmpCachePropertiesWrapper', 114 'data': { 'caches': ['SmpCacheProperties'] } } 115