xref: /openbmc/qemu/qapi/cxl.json (revision ea9b6d64)
1# -*- Mode: Python -*-
2# vim: filetype=python
3
4##
5# = CXL devices
6##
7
8##
9# @CxlEventLog:
10#
11# CXL has a number of separate event logs for different types of
12# events.  Each such event log is handled and signaled independently.
13#
14# @informational: Information Event Log
15#
16# @warning: Warning Event Log
17#
18# @failure: Failure Event Log
19#
20# @fatal: Fatal Event Log
21#
22# Since: 8.1
23##
24{ 'enum': 'CxlEventLog',
25  'data': ['informational',
26           'warning',
27           'failure',
28           'fatal']
29 }
30
31##
32# @cxl-inject-general-media-event:
33#
34# Inject an event record for a General Media Event (CXL r3.0
35# 8.2.9.2.1.1).  This event type is reported via one of the event logs
36# specified via the log parameter.
37#
38# @path: CXL type 3 device canonical QOM path
39#
40# @log: event log to add the event to
41#
42# @flags: Event Record Flags.  See CXL r3.0 Table 8-42 Common Event
43#     Record Format, Event Record Flags for subfield definitions.
44#
45# @dpa: Device Physical Address (relative to @path device).  Note
46#     lower bits include some flags.  See CXL r3.0 Table 8-43 General
47#     Media Event Record, Physical Address.
48#
49# @descriptor: Memory Event Descriptor with additional memory event
50#     information.  See CXL r3.0 Table 8-43 General Media Event
51#     Record, Memory Event Descriptor for bit definitions.
52#
53# @type: Type of memory event that occurred.  See CXL r3.0 Table 8-43
54#     General Media Event Record, Memory Event Type for possible
55#     values.
56#
57# @transaction-type: Type of first transaction that caused the event
58#     to occur.  See CXL r3.0 Table 8-43 General Media Event Record,
59#     Transaction Type for possible values.
60#
61# @channel: The channel of the memory event location.  A channel is an
62#     interface that can be independently accessed for a transaction.
63#
64# @rank: The rank of the memory event location.  A rank is a set of
65#     memory devices on a channel that together execute a transaction.
66#
67# @device: Bitmask that represents all devices in the rank associated
68#     with the memory event location.
69#
70# @component-id: Device specific component identifier for the event.
71#     May describe a field replaceable sub-component of the device.
72#
73# Since: 8.1
74##
75{ 'command': 'cxl-inject-general-media-event',
76  'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8',
77            'dpa': 'uint64', 'descriptor': 'uint8',
78            'type': 'uint8', 'transaction-type': 'uint8',
79            '*channel': 'uint8', '*rank': 'uint8',
80            '*device': 'uint32', '*component-id': 'str' } }
81
82##
83# @cxl-inject-poison:
84#
85# Poison records indicate that a CXL memory device knows that a
86# particular memory region may be corrupted.  This may be because of
87# locally detected errors (e.g. ECC failure) or poisoned writes
88# received from other components in the system.  This injection
89# mechanism enables testing of the OS handling of poison records which
90# may be queried via the CXL mailbox.
91#
92# @path: CXL type 3 device canonical QOM path
93#
94# @start: Start address; must be 64 byte aligned.
95#
96# @length: Length of poison to inject; must be a multiple of 64 bytes.
97#
98# Since: 8.1
99##
100{ 'command': 'cxl-inject-poison',
101  'data': { 'path': 'str', 'start': 'uint64', 'length': 'size' }}
102
103##
104# @CxlUncorErrorType:
105#
106# Type of uncorrectable CXL error to inject.  These errors are
107# reported via an AER uncorrectable internal error with additional
108# information logged at the CXL device.
109#
110# @cache-data-parity: Data error such as data parity or data ECC error
111#     CXL.cache
112#
113# @cache-address-parity: Address parity or other errors associated
114#     with the address field on CXL.cache
115#
116# @cache-be-parity: Byte enable parity or other byte enable errors on
117#     CXL.cache
118#
119# @cache-data-ecc: ECC error on CXL.cache
120#
121# @mem-data-parity: Data error such as data parity or data ECC error
122#     on CXL.mem
123#
124# @mem-address-parity: Address parity or other errors associated with
125#     the address field on CXL.mem
126#
127# @mem-be-parity: Byte enable parity or other byte enable errors on
128#     CXL.mem.
129#
130# @mem-data-ecc: Data ECC error on CXL.mem.
131#
132# @reinit-threshold: REINIT threshold hit.
133#
134# @rsvd-encoding: Received unrecognized encoding.
135#
136# @poison-received: Received poison from the peer.
137#
138# @receiver-overflow: Buffer overflows (first 3 bits of header log
139#     indicate which)
140#
141# @internal: Component specific error
142#
143# @cxl-ide-tx: Integrity and data encryption tx error.
144#
145# @cxl-ide-rx: Integrity and data encryption rx error.
146#
147# Since: 8.0
148##
149
150{ 'enum': 'CxlUncorErrorType',
151  'data': ['cache-data-parity',
152           'cache-address-parity',
153           'cache-be-parity',
154           'cache-data-ecc',
155           'mem-data-parity',
156           'mem-address-parity',
157           'mem-be-parity',
158           'mem-data-ecc',
159           'reinit-threshold',
160           'rsvd-encoding',
161           'poison-received',
162           'receiver-overflow',
163           'internal',
164           'cxl-ide-tx',
165           'cxl-ide-rx'
166           ]
167 }
168
169##
170# @CXLUncorErrorRecord:
171#
172# Record of a single error including header log.
173#
174# @type: Type of error
175#
176# @header: 16 DWORD of header.
177#
178# Since: 8.0
179##
180{ 'struct': 'CXLUncorErrorRecord',
181  'data': {
182      'type': 'CxlUncorErrorType',
183      'header': [ 'uint32' ]
184  }
185}
186
187##
188# @cxl-inject-uncorrectable-errors:
189#
190# Command to allow injection of multiple errors in one go.  This
191# allows testing of multiple header log handling in the OS.
192#
193# @path: CXL Type 3 device canonical QOM path
194#
195# @errors: Errors to inject
196#
197# Since: 8.0
198##
199{ 'command': 'cxl-inject-uncorrectable-errors',
200  'data': { 'path': 'str',
201             'errors': [ 'CXLUncorErrorRecord' ] }}
202
203##
204# @CxlCorErrorType:
205#
206# Type of CXL correctable error to inject
207#
208# @cache-data-ecc: Data ECC error on CXL.cache
209#
210# @mem-data-ecc: Data ECC error on CXL.mem
211#
212# @crc-threshold: Component specific and applicable to 68 byte Flit
213#     mode only.
214#
215# @cache-poison-received: Received poison from a peer on CXL.cache.
216#
217# @mem-poison-received: Received poison from a peer on CXL.mem
218#
219# @physical: Received error indication from the physical layer.
220#
221# Since: 8.0
222##
223{ 'enum': 'CxlCorErrorType',
224  'data': ['cache-data-ecc',
225           'mem-data-ecc',
226           'crc-threshold',
227           'retry-threshold',
228           'cache-poison-received',
229           'mem-poison-received',
230           'physical']
231}
232
233##
234# @cxl-inject-correctable-error:
235#
236# Command to inject a single correctable error.  Multiple error
237# injection of this error type is not interesting as there is no
238# associated header log.  These errors are reported via AER as a
239# correctable internal error, with additional detail available from
240# the CXL device.
241#
242# @path: CXL Type 3 device canonical QOM path
243#
244# @type: Type of error.
245#
246# Since: 8.0
247##
248{'command': 'cxl-inject-correctable-error',
249 'data': {'path': 'str', 'type': 'CxlCorErrorType'}}
250