1 /* 2 * S390 Basic Architecture 3 * 4 * Copyright (c) 2019 Jason J. Herne <jjherne@us.ibm.com> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or (at 7 * your option) any later version. See the COPYING file in the top-level 8 * directory. 9 */ 10 11 #ifndef S390_ARCH_H 12 #define S390_ARCH_H 13 14 typedef struct PSW { 15 uint64_t mask; 16 uint64_t addr; 17 } __attribute__ ((aligned(8))) PSW; 18 _Static_assert(sizeof(struct PSW) == 16, "PSW size incorrect"); 19 20 /* Older PSW format used by LPSW instruction */ 21 typedef struct PSWLegacy { 22 uint32_t mask; 23 uint32_t addr; 24 } __attribute__ ((aligned(8))) PSWLegacy; 25 _Static_assert(sizeof(struct PSWLegacy) == 8, "PSWLegacy size incorrect"); 26 27 /* s390 psw bit masks */ 28 #define PSW_MASK_IOINT 0x0200000000000000ULL 29 #define PSW_MASK_SHORTPSW 0x0008000000000000ULL 30 #define PSW_MASK_WAIT 0x0002000000000000ULL 31 #define PSW_MASK_EAMODE 0x0000000100000000ULL 32 #define PSW_MASK_BAMODE 0x0000000080000000ULL 33 #define PSW_MASK_SHORT_ADDR 0x000000007fffffffULL 34 #define PSW_MASK_64 (PSW_MASK_EAMODE | PSW_MASK_BAMODE) 35 36 /* Low core mapping */ 37 typedef struct LowCore { 38 /* prefix area: defined by architecture */ 39 PSWLegacy ipl_psw; /* 0x000 */ 40 uint32_t ccw1[2]; /* 0x008 */ 41 union { 42 uint32_t ccw2[2]; /* 0x010 */ 43 struct { 44 uint32_t reserved10; 45 uint32_t ptr_iplb; 46 }; 47 }; 48 uint8_t pad1[0x80 - 0x18]; /* 0x018 */ 49 uint32_t ext_params; /* 0x080 */ 50 uint16_t cpu_addr; /* 0x084 */ 51 uint16_t ext_int_code; /* 0x086 */ 52 uint16_t svc_ilen; /* 0x088 */ 53 uint16_t svc_code; /* 0x08a */ 54 uint16_t pgm_ilen; /* 0x08c */ 55 uint16_t pgm_code; /* 0x08e */ 56 uint32_t data_exc_code; /* 0x090 */ 57 uint16_t mon_class_num; /* 0x094 */ 58 uint16_t per_perc_atmid; /* 0x096 */ 59 uint64_t per_address; /* 0x098 */ 60 uint8_t exc_access_id; /* 0x0a0 */ 61 uint8_t per_access_id; /* 0x0a1 */ 62 uint8_t op_access_id; /* 0x0a2 */ 63 uint8_t ar_access_id; /* 0x0a3 */ 64 uint8_t pad2[0xA8 - 0xA4]; /* 0x0a4 */ 65 uint64_t trans_exc_code; /* 0x0a8 */ 66 uint64_t monitor_code; /* 0x0b0 */ 67 uint16_t subchannel_id; /* 0x0b8 */ 68 uint16_t subchannel_nr; /* 0x0ba */ 69 uint32_t io_int_parm; /* 0x0bc */ 70 uint32_t io_int_word; /* 0x0c0 */ 71 uint8_t pad3[0xc8 - 0xc4]; /* 0x0c4 */ 72 uint32_t stfl_fac_list; /* 0x0c8 */ 73 uint8_t pad4[0xe8 - 0xcc]; /* 0x0cc */ 74 uint64_t mcic; /* 0x0e8 */ 75 uint8_t pad5[0xf4 - 0xf0]; /* 0x0f0 */ 76 uint32_t external_damage_code; /* 0x0f4 */ 77 uint64_t failing_storage_address; /* 0x0f8 */ 78 uint8_t pad6[0x110 - 0x100]; /* 0x100 */ 79 uint64_t per_breaking_event_addr; /* 0x110 */ 80 uint8_t pad7[0x120 - 0x118]; /* 0x118 */ 81 PSW restart_old_psw; /* 0x120 */ 82 PSW external_old_psw; /* 0x130 */ 83 PSW svc_old_psw; /* 0x140 */ 84 PSW program_old_psw; /* 0x150 */ 85 PSW mcck_old_psw; /* 0x160 */ 86 PSW io_old_psw; /* 0x170 */ 87 uint8_t pad8[0x1a0 - 0x180]; /* 0x180 */ 88 PSW restart_new_psw; /* 0x1a0 */ 89 PSW external_new_psw; /* 0x1b0 */ 90 PSW svc_new_psw; /* 0x1c0 */ 91 PSW program_new_psw; /* 0x1d0 */ 92 PSW mcck_new_psw; /* 0x1e0 */ 93 PSW io_new_psw; /* 0x1f0 */ 94 } __attribute__((packed, aligned(8192))) LowCore; 95 96 extern LowCore *lowcore; 97 98 static inline void set_prefix(uint32_t address) 99 { 100 asm volatile("spx %0" : : "m" (address) : "memory"); 101 } 102 103 static inline uint32_t store_prefix(void) 104 { 105 uint32_t address; 106 107 asm volatile("stpx %0" : "=m" (address)); 108 return address; 109 } 110 111 #endif 112