1 /* 2 * qemu user cpu loop 3 * 4 * Copyright (c) 2003-2008 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu.h" 22 #include "user-internals.h" 23 #include "cpu_loop-common.h" 24 #include "signal-common.h" 25 26 #define SPARC64_STACK_BIAS 2047 27 28 //#define DEBUG_WIN 29 30 /* WARNING: dealing with register windows _is_ complicated. More info 31 can be found at http://www.sics.se/~psm/sparcstack.html */ 32 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index) 33 { 34 index = (index + cwp * 16) % (16 * env->nwindows); 35 /* wrap handling : if cwp is on the last window, then we use the 36 registers 'after' the end */ 37 if (index < 8 && env->cwp == env->nwindows - 1) 38 index += 16 * env->nwindows; 39 return index; 40 } 41 42 /* save the register window 'cwp1' */ 43 static inline void save_window_offset(CPUSPARCState *env, int cwp1) 44 { 45 unsigned int i; 46 abi_ulong sp_ptr; 47 48 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; 49 #ifdef TARGET_SPARC64 50 if (sp_ptr & 3) 51 sp_ptr += SPARC64_STACK_BIAS; 52 #endif 53 #if defined(DEBUG_WIN) 54 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n", 55 sp_ptr, cwp1); 56 #endif 57 for(i = 0; i < 16; i++) { 58 /* FIXME - what to do if put_user() fails? */ 59 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); 60 sp_ptr += sizeof(abi_ulong); 61 } 62 } 63 64 static void save_window(CPUSPARCState *env) 65 { 66 #ifndef TARGET_SPARC64 67 unsigned int new_wim; 68 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) & 69 ((1LL << env->nwindows) - 1); 70 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); 71 env->wim = new_wim; 72 #else 73 /* 74 * cansave is zero if the spill trap handler is triggered by `save` and 75 * nonzero if triggered by a `flushw` 76 */ 77 save_window_offset(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2)); 78 env->cansave++; 79 env->canrestore--; 80 #endif 81 } 82 83 static void restore_window(CPUSPARCState *env) 84 { 85 #ifndef TARGET_SPARC64 86 unsigned int new_wim; 87 #endif 88 unsigned int i, cwp1; 89 abi_ulong sp_ptr; 90 91 #ifndef TARGET_SPARC64 92 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) & 93 ((1LL << env->nwindows) - 1); 94 #endif 95 96 /* restore the invalid window */ 97 cwp1 = cpu_cwp_inc(env, env->cwp + 1); 98 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; 99 #ifdef TARGET_SPARC64 100 if (sp_ptr & 3) 101 sp_ptr += SPARC64_STACK_BIAS; 102 #endif 103 #if defined(DEBUG_WIN) 104 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n", 105 sp_ptr, cwp1); 106 #endif 107 for(i = 0; i < 16; i++) { 108 /* FIXME - what to do if get_user() fails? */ 109 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); 110 sp_ptr += sizeof(abi_ulong); 111 } 112 #ifdef TARGET_SPARC64 113 env->canrestore++; 114 if (env->cleanwin < env->nwindows - 1) 115 env->cleanwin++; 116 env->cansave--; 117 #else 118 env->wim = new_wim; 119 #endif 120 } 121 122 static void flush_windows(CPUSPARCState *env) 123 { 124 int offset, cwp1; 125 126 offset = 1; 127 for(;;) { 128 /* if restore would invoke restore_window(), then we can stop */ 129 cwp1 = cpu_cwp_inc(env, env->cwp + offset); 130 #ifndef TARGET_SPARC64 131 if (env->wim & (1 << cwp1)) 132 break; 133 #else 134 if (env->canrestore == 0) 135 break; 136 env->cansave++; 137 env->canrestore--; 138 #endif 139 save_window_offset(env, cwp1); 140 offset++; 141 } 142 cwp1 = cpu_cwp_inc(env, env->cwp + 1); 143 #ifndef TARGET_SPARC64 144 /* set wim so that restore will reload the registers */ 145 env->wim = 1 << cwp1; 146 #endif 147 #if defined(DEBUG_WIN) 148 printf("flush_windows: nb=%d\n", offset - 1); 149 #endif 150 } 151 152 static void next_instruction(CPUSPARCState *env) 153 { 154 env->pc = env->npc; 155 env->npc = env->npc + 4; 156 } 157 158 static uint32_t do_getcc(CPUSPARCState *env) 159 { 160 #ifdef TARGET_SPARC64 161 return cpu_get_ccr(env) & 0xf; 162 #else 163 return extract32(cpu_get_psr(env), 20, 4); 164 #endif 165 } 166 167 static void do_setcc(CPUSPARCState *env, uint32_t icc) 168 { 169 #ifdef TARGET_SPARC64 170 cpu_put_ccr(env, (cpu_get_ccr(env) & 0xf0) | (icc & 0xf)); 171 #else 172 cpu_put_psr(env, deposit32(cpu_get_psr(env), 20, 4, icc)); 173 #endif 174 } 175 176 static uint32_t do_getpsr(CPUSPARCState *env) 177 { 178 #ifdef TARGET_SPARC64 179 const uint64_t TSTATE_CWP = 0x1f; 180 const uint64_t TSTATE_ICC = 0xfull << 32; 181 const uint64_t TSTATE_XCC = 0xfull << 36; 182 const uint32_t PSR_S = 0x00000080u; 183 const uint32_t PSR_V8PLUS = 0xff000000u; 184 uint64_t tstate = sparc64_tstate(env); 185 186 /* See <asm/psrcompat.h>, tstate_to_psr. */ 187 return ((tstate & TSTATE_CWP) | 188 PSR_S | 189 ((tstate & TSTATE_ICC) >> 12) | 190 ((tstate & TSTATE_XCC) >> 20) | 191 PSR_V8PLUS); 192 #else 193 return (cpu_get_psr(env) & (PSR_ICC | PSR_CWP)) | PSR_S; 194 #endif 195 } 196 197 /* Avoid ifdefs below for the abi32 and abi64 paths. */ 198 #ifdef TARGET_ABI32 199 #define TARGET_TT_SYSCALL (TT_TRAP + 0x10) /* t_linux */ 200 #define syscall_cc psr 201 #else 202 #define TARGET_TT_SYSCALL (TT_TRAP + 0x6d) /* tl0_linux64 */ 203 #define syscall_cc xcc 204 #endif 205 206 /* Avoid ifdefs below for the v9 and pre-v9 hw traps. */ 207 #ifdef TARGET_SPARC64 208 #define TARGET_TT_SPILL TT_SPILL 209 #define TARGET_TT_FILL TT_FILL 210 #else 211 #define TARGET_TT_SPILL TT_WIN_OVF 212 #define TARGET_TT_FILL TT_WIN_UNF 213 #endif 214 215 void cpu_loop (CPUSPARCState *env) 216 { 217 CPUState *cs = env_cpu(env); 218 int trapnr; 219 abi_long ret; 220 221 while (1) { 222 cpu_exec_start(cs); 223 trapnr = cpu_exec(cs); 224 cpu_exec_end(cs); 225 process_queued_cpu_work(cs); 226 227 /* Compute PSR before exposing state. */ 228 if (env->cc_op != CC_OP_FLAGS) { 229 cpu_get_psr(env); 230 } 231 232 switch (trapnr) { 233 case TARGET_TT_SYSCALL: 234 ret = do_syscall (env, env->gregs[1], 235 env->regwptr[0], env->regwptr[1], 236 env->regwptr[2], env->regwptr[3], 237 env->regwptr[4], env->regwptr[5], 238 0, 0); 239 if (ret == -QEMU_ERESTARTSYS || ret == -QEMU_ESIGRETURN) { 240 break; 241 } 242 if ((abi_ulong)ret >= (abi_ulong)(-515)) { 243 env->syscall_cc |= PSR_CARRY; 244 ret = -ret; 245 } else { 246 env->syscall_cc &= ~PSR_CARRY; 247 } 248 env->regwptr[0] = ret; 249 /* next instruction */ 250 env->pc = env->npc; 251 env->npc = env->npc + 4; 252 break; 253 254 case TT_TRAP + 0x01: /* breakpoint */ 255 case EXCP_DEBUG: 256 force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc); 257 break; 258 259 case TT_TRAP + 0x02: /* div0 */ 260 case TT_DIV_ZERO: 261 force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->pc); 262 break; 263 264 case TT_TRAP + 0x03: /* flush windows */ 265 flush_windows(env); 266 next_instruction(env); 267 break; 268 269 case TT_TRAP + 0x20: /* getcc */ 270 env->gregs[1] = do_getcc(env); 271 next_instruction(env); 272 break; 273 case TT_TRAP + 0x21: /* setcc */ 274 do_setcc(env, env->gregs[1]); 275 next_instruction(env); 276 break; 277 case TT_TRAP + 0x22: /* getpsr */ 278 env->gregs[1] = do_getpsr(env); 279 next_instruction(env); 280 break; 281 282 #ifdef TARGET_SPARC64 283 case TT_TRAP + 0x6e: 284 flush_windows(env); 285 sparc64_get_context(env); 286 break; 287 case TT_TRAP + 0x6f: 288 flush_windows(env); 289 sparc64_set_context(env); 290 break; 291 #endif 292 293 case TARGET_TT_SPILL: /* window overflow */ 294 save_window(env); 295 break; 296 case TARGET_TT_FILL: /* window underflow */ 297 restore_window(env); 298 break; 299 300 case TT_FP_EXCP: 301 { 302 int code = TARGET_FPE_FLTUNK; 303 target_ulong fsr = env->fsr; 304 305 if ((fsr & FSR_FTT_MASK) == FSR_FTT_IEEE_EXCP) { 306 if (fsr & FSR_NVC) { 307 code = TARGET_FPE_FLTINV; 308 } else if (fsr & FSR_OFC) { 309 code = TARGET_FPE_FLTOVF; 310 } else if (fsr & FSR_UFC) { 311 code = TARGET_FPE_FLTUND; 312 } else if (fsr & FSR_DZC) { 313 code = TARGET_FPE_FLTDIV; 314 } else if (fsr & FSR_NXC) { 315 code = TARGET_FPE_FLTRES; 316 } 317 } 318 force_sig_fault(TARGET_SIGFPE, code, env->pc); 319 } 320 break; 321 322 case EXCP_INTERRUPT: 323 /* just indicate that signals should be handled asap */ 324 break; 325 case TT_ILL_INSN: 326 force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->pc); 327 break; 328 case TT_PRIV_INSN: 329 force_sig_fault(TARGET_SIGILL, TARGET_ILL_PRVOPC, env->pc); 330 break; 331 case TT_TOVF: 332 force_sig_fault(TARGET_SIGEMT, TARGET_EMT_TAGOVF, env->pc); 333 break; 334 #ifdef TARGET_SPARC64 335 case TT_PRIV_ACT: 336 /* Note do_privact defers to do_privop. */ 337 force_sig_fault(TARGET_SIGILL, TARGET_ILL_PRVOPC, env->pc); 338 break; 339 #else 340 case TT_NCP_INSN: 341 force_sig_fault(TARGET_SIGILL, TARGET_ILL_COPROC, env->pc); 342 break; 343 case TT_UNIMP_FLUSH: 344 next_instruction(env); 345 break; 346 #endif 347 case EXCP_ATOMIC: 348 cpu_exec_step_atomic(cs); 349 break; 350 default: 351 /* 352 * Most software trap numbers vector to BAD_TRAP. 353 * Handle anything not explicitly matched above. 354 */ 355 if (trapnr >= TT_TRAP && trapnr <= TT_TRAP + 0x7f) { 356 force_sig_fault(TARGET_SIGILL, ILL_ILLTRP, env->pc); 357 break; 358 } 359 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr); 360 cpu_dump_state(cs, stderr, 0); 361 exit(EXIT_FAILURE); 362 } 363 process_pending_signals (env); 364 } 365 } 366 367 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) 368 { 369 int i; 370 env->pc = regs->pc; 371 env->npc = regs->npc; 372 env->y = regs->y; 373 for(i = 0; i < 8; i++) 374 env->gregs[i] = regs->u_regs[i]; 375 for(i = 0; i < 8; i++) 376 env->regwptr[i] = regs->u_regs[i + 8]; 377 } 378