1 /* 2 * qemu user cpu loop 3 * 4 * Copyright (c) 2003-2008 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/error-report.h" 22 #include "qemu.h" 23 #include "cpu_loop-common.h" 24 #include "elf.h" 25 26 void cpu_loop(CPURISCVState *env) 27 { 28 CPUState *cs = env_cpu(env); 29 int trapnr, signum, sigcode; 30 target_ulong sigaddr; 31 target_ulong ret; 32 33 for (;;) { 34 cpu_exec_start(cs); 35 trapnr = cpu_exec(cs); 36 cpu_exec_end(cs); 37 process_queued_cpu_work(cs); 38 39 signum = 0; 40 sigcode = 0; 41 sigaddr = 0; 42 43 switch (trapnr) { 44 case EXCP_INTERRUPT: 45 /* just indicate that signals should be handled asap */ 46 break; 47 case EXCP_ATOMIC: 48 cpu_exec_step_atomic(cs); 49 break; 50 case RISCV_EXCP_U_ECALL: 51 env->pc += 4; 52 if (env->gpr[xA7] == TARGET_NR_arch_specific_syscall + 15) { 53 /* riscv_flush_icache_syscall is a no-op in QEMU as 54 self-modifying code is automatically detected */ 55 ret = 0; 56 } else { 57 ret = do_syscall(env, 58 env->gpr[(env->elf_flags & EF_RISCV_RVE) 59 ? xT0 : xA7], 60 env->gpr[xA0], 61 env->gpr[xA1], 62 env->gpr[xA2], 63 env->gpr[xA3], 64 env->gpr[xA4], 65 env->gpr[xA5], 66 0, 0); 67 } 68 if (ret == -TARGET_ERESTARTSYS) { 69 env->pc -= 4; 70 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 71 env->gpr[xA0] = ret; 72 } 73 if (cs->singlestep_enabled) { 74 goto gdbstep; 75 } 76 break; 77 case RISCV_EXCP_ILLEGAL_INST: 78 signum = TARGET_SIGILL; 79 sigcode = TARGET_ILL_ILLOPC; 80 break; 81 case RISCV_EXCP_BREAKPOINT: 82 signum = TARGET_SIGTRAP; 83 sigcode = TARGET_TRAP_BRKPT; 84 sigaddr = env->pc; 85 break; 86 case RISCV_EXCP_INST_PAGE_FAULT: 87 case RISCV_EXCP_LOAD_PAGE_FAULT: 88 case RISCV_EXCP_STORE_PAGE_FAULT: 89 signum = TARGET_SIGSEGV; 90 sigcode = TARGET_SEGV_MAPERR; 91 break; 92 case EXCP_DEBUG: 93 gdbstep: 94 signum = TARGET_SIGTRAP; 95 sigcode = TARGET_TRAP_BRKPT; 96 break; 97 default: 98 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n", 99 trapnr); 100 exit(EXIT_FAILURE); 101 } 102 103 if (signum) { 104 target_siginfo_t info = { 105 .si_signo = signum, 106 .si_errno = 0, 107 .si_code = sigcode, 108 ._sifields._sigfault._addr = sigaddr 109 }; 110 queue_signal(env, info.si_signo, QEMU_SI_KILL, &info); 111 } 112 113 process_pending_signals(env); 114 } 115 } 116 117 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) 118 { 119 CPUState *cpu = env_cpu(env); 120 TaskState *ts = cpu->opaque; 121 struct image_info *info = ts->info; 122 123 env->pc = regs->sepc; 124 env->gpr[xSP] = regs->sp; 125 env->elf_flags = info->elf_flags; 126 127 if ((env->misa & RVE) && !(env->elf_flags & EF_RISCV_RVE)) { 128 error_report("Incompatible ELF: RVE cpu requires RVE ABI binary"); 129 exit(EXIT_FAILURE); 130 } 131 } 132