1 /* 2 * qemu user cpu loop 3 * 4 * Copyright (c) 2003-2008 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/error-report.h" 23 #include "qemu.h" 24 #include "user-internals.h" 25 #include "cpu_loop-common.h" 26 #include "signal-common.h" 27 #include "elf.h" 28 #include "semihosting/common-semi.h" 29 30 void cpu_loop(CPURISCVState *env) 31 { 32 CPUState *cs = env_cpu(env); 33 int trapnr, signum, sigcode; 34 target_ulong sigaddr; 35 target_ulong ret; 36 37 for (;;) { 38 cpu_exec_start(cs); 39 trapnr = cpu_exec(cs); 40 cpu_exec_end(cs); 41 process_queued_cpu_work(cs); 42 43 signum = 0; 44 sigcode = 0; 45 sigaddr = 0; 46 47 switch (trapnr) { 48 case EXCP_INTERRUPT: 49 /* just indicate that signals should be handled asap */ 50 break; 51 case EXCP_ATOMIC: 52 cpu_exec_step_atomic(cs); 53 break; 54 case RISCV_EXCP_U_ECALL: 55 env->pc += 4; 56 if (env->gpr[xA7] == TARGET_NR_arch_specific_syscall + 15) { 57 /* riscv_flush_icache_syscall is a no-op in QEMU as 58 self-modifying code is automatically detected */ 59 ret = 0; 60 } else { 61 ret = do_syscall(env, 62 env->gpr[(env->elf_flags & EF_RISCV_RVE) 63 ? xT0 : xA7], 64 env->gpr[xA0], 65 env->gpr[xA1], 66 env->gpr[xA2], 67 env->gpr[xA3], 68 env->gpr[xA4], 69 env->gpr[xA5], 70 0, 0); 71 } 72 if (ret == -TARGET_ERESTARTSYS) { 73 env->pc -= 4; 74 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 75 env->gpr[xA0] = ret; 76 } 77 if (cs->singlestep_enabled) { 78 goto gdbstep; 79 } 80 break; 81 case RISCV_EXCP_ILLEGAL_INST: 82 signum = TARGET_SIGILL; 83 sigcode = TARGET_ILL_ILLOPC; 84 break; 85 case RISCV_EXCP_BREAKPOINT: 86 signum = TARGET_SIGTRAP; 87 sigcode = TARGET_TRAP_BRKPT; 88 sigaddr = env->pc; 89 break; 90 case RISCV_EXCP_INST_PAGE_FAULT: 91 case RISCV_EXCP_LOAD_PAGE_FAULT: 92 case RISCV_EXCP_STORE_PAGE_FAULT: 93 signum = TARGET_SIGSEGV; 94 sigcode = TARGET_SEGV_MAPERR; 95 sigaddr = env->badaddr; 96 break; 97 case RISCV_EXCP_SEMIHOST: 98 env->gpr[xA0] = do_common_semihosting(cs); 99 env->pc += 4; 100 break; 101 case EXCP_DEBUG: 102 gdbstep: 103 signum = TARGET_SIGTRAP; 104 sigcode = TARGET_TRAP_BRKPT; 105 break; 106 default: 107 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n", 108 trapnr); 109 exit(EXIT_FAILURE); 110 } 111 112 if (signum) { 113 target_siginfo_t info = { 114 .si_signo = signum, 115 .si_errno = 0, 116 .si_code = sigcode, 117 ._sifields._sigfault._addr = sigaddr 118 }; 119 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 120 } 121 122 process_pending_signals(env); 123 } 124 } 125 126 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) 127 { 128 CPUState *cpu = env_cpu(env); 129 TaskState *ts = cpu->opaque; 130 struct image_info *info = ts->info; 131 132 env->pc = regs->sepc; 133 env->gpr[xSP] = regs->sp; 134 env->elf_flags = info->elf_flags; 135 136 if ((env->misa & RVE) && !(env->elf_flags & EF_RISCV_RVE)) { 137 error_report("Incompatible ELF: RVE cpu requires RVE ABI binary"); 138 exit(EXIT_FAILURE); 139 } 140 141 ts->stack_base = info->start_stack; 142 ts->heap_base = info->brk; 143 /* This will be filled in on the first SYS_HEAPINFO call. */ 144 ts->heap_limit = 0; 145 } 146