1 /* 2 * qemu user cpu loop 3 * 4 * Copyright (c) 2003-2008 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/error-report.h" 23 #include "qemu.h" 24 #include "cpu_loop-common.h" 25 #include "signal-common.h" 26 #include "elf.h" 27 #include "semihosting/common-semi.h" 28 29 void cpu_loop(CPURISCVState *env) 30 { 31 CPUState *cs = env_cpu(env); 32 int trapnr, signum, sigcode; 33 target_ulong sigaddr; 34 target_ulong ret; 35 36 for (;;) { 37 cpu_exec_start(cs); 38 trapnr = cpu_exec(cs); 39 cpu_exec_end(cs); 40 process_queued_cpu_work(cs); 41 42 signum = 0; 43 sigcode = 0; 44 sigaddr = 0; 45 46 switch (trapnr) { 47 case EXCP_INTERRUPT: 48 /* just indicate that signals should be handled asap */ 49 break; 50 case EXCP_ATOMIC: 51 cpu_exec_step_atomic(cs); 52 break; 53 case RISCV_EXCP_U_ECALL: 54 env->pc += 4; 55 if (env->gpr[xA7] == TARGET_NR_arch_specific_syscall + 15) { 56 /* riscv_flush_icache_syscall is a no-op in QEMU as 57 self-modifying code is automatically detected */ 58 ret = 0; 59 } else { 60 ret = do_syscall(env, 61 env->gpr[(env->elf_flags & EF_RISCV_RVE) 62 ? xT0 : xA7], 63 env->gpr[xA0], 64 env->gpr[xA1], 65 env->gpr[xA2], 66 env->gpr[xA3], 67 env->gpr[xA4], 68 env->gpr[xA5], 69 0, 0); 70 } 71 if (ret == -TARGET_ERESTARTSYS) { 72 env->pc -= 4; 73 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 74 env->gpr[xA0] = ret; 75 } 76 if (cs->singlestep_enabled) { 77 goto gdbstep; 78 } 79 break; 80 case RISCV_EXCP_ILLEGAL_INST: 81 signum = TARGET_SIGILL; 82 sigcode = TARGET_ILL_ILLOPC; 83 break; 84 case RISCV_EXCP_BREAKPOINT: 85 signum = TARGET_SIGTRAP; 86 sigcode = TARGET_TRAP_BRKPT; 87 sigaddr = env->pc; 88 break; 89 case RISCV_EXCP_INST_PAGE_FAULT: 90 case RISCV_EXCP_LOAD_PAGE_FAULT: 91 case RISCV_EXCP_STORE_PAGE_FAULT: 92 signum = TARGET_SIGSEGV; 93 sigcode = TARGET_SEGV_MAPERR; 94 sigaddr = env->badaddr; 95 break; 96 case RISCV_EXCP_SEMIHOST: 97 env->gpr[xA0] = do_common_semihosting(cs); 98 env->pc += 4; 99 break; 100 case EXCP_DEBUG: 101 gdbstep: 102 signum = TARGET_SIGTRAP; 103 sigcode = TARGET_TRAP_BRKPT; 104 break; 105 default: 106 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n", 107 trapnr); 108 exit(EXIT_FAILURE); 109 } 110 111 if (signum) { 112 target_siginfo_t info = { 113 .si_signo = signum, 114 .si_errno = 0, 115 .si_code = sigcode, 116 ._sifields._sigfault._addr = sigaddr 117 }; 118 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 119 } 120 121 process_pending_signals(env); 122 } 123 } 124 125 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) 126 { 127 CPUState *cpu = env_cpu(env); 128 TaskState *ts = cpu->opaque; 129 struct image_info *info = ts->info; 130 131 env->pc = regs->sepc; 132 env->gpr[xSP] = regs->sp; 133 env->elf_flags = info->elf_flags; 134 135 if ((env->misa & RVE) && !(env->elf_flags & EF_RISCV_RVE)) { 136 error_report("Incompatible ELF: RVE cpu requires RVE ABI binary"); 137 exit(EXIT_FAILURE); 138 } 139 140 ts->stack_base = info->start_stack; 141 ts->heap_base = info->brk; 142 /* This will be filled in on the first SYS_HEAPINFO call. */ 143 ts->heap_limit = 0; 144 } 145