1 /* 2 * Emulation of Linux signals 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "qemu.h" 21 #include "target_signal.h" 22 #include "signal-common.h" 23 #include "linux-user/trace.h" 24 25 /* Size of dummy stack frame allocated when calling signal handler. 26 See arch/powerpc/include/asm/ptrace.h. */ 27 #if defined(TARGET_PPC64) 28 #define SIGNAL_FRAMESIZE 128 29 #else 30 #define SIGNAL_FRAMESIZE 64 31 #endif 32 33 /* See arch/powerpc/include/asm/ucontext.h. Only used for 32-bit PPC; 34 on 64-bit PPC, sigcontext and mcontext are one and the same. */ 35 struct target_mcontext { 36 target_ulong mc_gregs[48]; 37 /* Includes fpscr. */ 38 uint64_t mc_fregs[33]; 39 #if defined(TARGET_PPC64) 40 /* Pointer to the vector regs */ 41 target_ulong v_regs; 42 #else 43 target_ulong mc_pad[2]; 44 #endif 45 /* We need to handle Altivec and SPE at the same time, which no 46 kernel needs to do. Fortunately, the kernel defines this bit to 47 be Altivec-register-large all the time, rather than trying to 48 twiddle it based on the specific platform. */ 49 union { 50 /* SPE vector registers. One extra for SPEFSCR. */ 51 uint32_t spe[33]; 52 /* Altivec vector registers. The packing of VSCR and VRSAVE 53 varies depending on whether we're PPC64 or not: PPC64 splits 54 them apart; PPC32 stuffs them together. 55 We also need to account for the VSX registers on PPC64 56 */ 57 #if defined(TARGET_PPC64) 58 #define QEMU_NVRREG (34 + 16) 59 /* On ppc64, this mcontext structure is naturally *unaligned*, 60 * or rather it is aligned on a 8 bytes boundary but not on 61 * a 16 bytes one. This pad fixes it up. This is also why the 62 * vector regs are referenced by the v_regs pointer above so 63 * any amount of padding can be added here 64 */ 65 target_ulong pad; 66 #else 67 /* On ppc32, we are already aligned to 16 bytes */ 68 #define QEMU_NVRREG 33 69 #endif 70 /* We cannot use ppc_avr_t here as we do *not* want the implied 71 * 16-bytes alignment that would result from it. This would have 72 * the effect of making the whole struct target_mcontext aligned 73 * which breaks the layout of struct target_ucontext on ppc64. 74 */ 75 uint64_t altivec[QEMU_NVRREG][2]; 76 #undef QEMU_NVRREG 77 } mc_vregs; 78 }; 79 80 /* See arch/powerpc/include/asm/sigcontext.h. */ 81 struct target_sigcontext { 82 target_ulong _unused[4]; 83 int32_t signal; 84 #if defined(TARGET_PPC64) 85 int32_t pad0; 86 #endif 87 target_ulong handler; 88 target_ulong oldmask; 89 target_ulong regs; /* struct pt_regs __user * */ 90 #if defined(TARGET_PPC64) 91 struct target_mcontext mcontext; 92 #endif 93 }; 94 95 /* Indices for target_mcontext.mc_gregs, below. 96 See arch/powerpc/include/asm/ptrace.h for details. */ 97 enum { 98 TARGET_PT_R0 = 0, 99 TARGET_PT_R1 = 1, 100 TARGET_PT_R2 = 2, 101 TARGET_PT_R3 = 3, 102 TARGET_PT_R4 = 4, 103 TARGET_PT_R5 = 5, 104 TARGET_PT_R6 = 6, 105 TARGET_PT_R7 = 7, 106 TARGET_PT_R8 = 8, 107 TARGET_PT_R9 = 9, 108 TARGET_PT_R10 = 10, 109 TARGET_PT_R11 = 11, 110 TARGET_PT_R12 = 12, 111 TARGET_PT_R13 = 13, 112 TARGET_PT_R14 = 14, 113 TARGET_PT_R15 = 15, 114 TARGET_PT_R16 = 16, 115 TARGET_PT_R17 = 17, 116 TARGET_PT_R18 = 18, 117 TARGET_PT_R19 = 19, 118 TARGET_PT_R20 = 20, 119 TARGET_PT_R21 = 21, 120 TARGET_PT_R22 = 22, 121 TARGET_PT_R23 = 23, 122 TARGET_PT_R24 = 24, 123 TARGET_PT_R25 = 25, 124 TARGET_PT_R26 = 26, 125 TARGET_PT_R27 = 27, 126 TARGET_PT_R28 = 28, 127 TARGET_PT_R29 = 29, 128 TARGET_PT_R30 = 30, 129 TARGET_PT_R31 = 31, 130 TARGET_PT_NIP = 32, 131 TARGET_PT_MSR = 33, 132 TARGET_PT_ORIG_R3 = 34, 133 TARGET_PT_CTR = 35, 134 TARGET_PT_LNK = 36, 135 TARGET_PT_XER = 37, 136 TARGET_PT_CCR = 38, 137 /* Yes, there are two registers with #39. One is 64-bit only. */ 138 TARGET_PT_MQ = 39, 139 TARGET_PT_SOFTE = 39, 140 TARGET_PT_TRAP = 40, 141 TARGET_PT_DAR = 41, 142 TARGET_PT_DSISR = 42, 143 TARGET_PT_RESULT = 43, 144 TARGET_PT_REGS_COUNT = 44 145 }; 146 147 148 struct target_ucontext { 149 target_ulong tuc_flags; 150 target_ulong tuc_link; /* ucontext_t __user * */ 151 struct target_sigaltstack tuc_stack; 152 #if !defined(TARGET_PPC64) 153 int32_t tuc_pad[7]; 154 target_ulong tuc_regs; /* struct mcontext __user * 155 points to uc_mcontext field */ 156 #endif 157 target_sigset_t tuc_sigmask; 158 #if defined(TARGET_PPC64) 159 target_sigset_t unused[15]; /* Allow for uc_sigmask growth */ 160 struct target_sigcontext tuc_sigcontext; 161 #else 162 int32_t tuc_maskext[30]; 163 int32_t tuc_pad2[3]; 164 struct target_mcontext tuc_mcontext; 165 #endif 166 }; 167 168 /* See arch/powerpc/kernel/signal_32.c. */ 169 struct target_sigframe { 170 struct target_sigcontext sctx; 171 struct target_mcontext mctx; 172 int32_t abigap[56]; 173 }; 174 175 #if defined(TARGET_PPC64) 176 177 #define TARGET_TRAMP_SIZE 6 178 179 struct target_rt_sigframe { 180 /* sys_rt_sigreturn requires the ucontext be the first field */ 181 struct target_ucontext uc; 182 target_ulong _unused[2]; 183 uint32_t trampoline[TARGET_TRAMP_SIZE]; 184 target_ulong pinfo; /* struct siginfo __user * */ 185 target_ulong puc; /* void __user * */ 186 struct target_siginfo info; 187 /* 64 bit ABI allows for 288 bytes below sp before decrementing it. */ 188 char abigap[288]; 189 } __attribute__((aligned(16))); 190 191 #else 192 193 struct target_rt_sigframe { 194 struct target_siginfo info; 195 struct target_ucontext uc; 196 int32_t abigap[56]; 197 }; 198 199 #endif 200 201 #if defined(TARGET_PPC64) 202 203 struct target_func_ptr { 204 target_ulong entry; 205 target_ulong toc; 206 }; 207 208 #endif 209 210 /* We use the mc_pad field for the signal return trampoline. */ 211 #define tramp mc_pad 212 213 /* See arch/powerpc/kernel/signal.c. */ 214 static target_ulong get_sigframe(struct target_sigaction *ka, 215 CPUPPCState *env, 216 int frame_size) 217 { 218 target_ulong oldsp; 219 220 oldsp = target_sigsp(get_sp_from_cpustate(env), ka); 221 222 return (oldsp - frame_size) & ~0xFUL; 223 } 224 225 #if ((defined(TARGET_WORDS_BIGENDIAN) && defined(HOST_WORDS_BIGENDIAN)) || \ 226 (!defined(HOST_WORDS_BIGENDIAN) && !defined(TARGET_WORDS_BIGENDIAN))) 227 #define PPC_VEC_HI 0 228 #define PPC_VEC_LO 1 229 #else 230 #define PPC_VEC_HI 1 231 #define PPC_VEC_LO 0 232 #endif 233 234 235 static void save_user_regs(CPUPPCState *env, struct target_mcontext *frame) 236 { 237 target_ulong msr = env->msr; 238 int i; 239 target_ulong ccr = 0; 240 241 /* In general, the kernel attempts to be intelligent about what it 242 needs to save for Altivec/FP/SPE registers. We don't care that 243 much, so we just go ahead and save everything. */ 244 245 /* Save general registers. */ 246 for (i = 0; i < ARRAY_SIZE(env->gpr); i++) { 247 __put_user(env->gpr[i], &frame->mc_gregs[i]); 248 } 249 __put_user(env->nip, &frame->mc_gregs[TARGET_PT_NIP]); 250 __put_user(env->ctr, &frame->mc_gregs[TARGET_PT_CTR]); 251 __put_user(env->lr, &frame->mc_gregs[TARGET_PT_LNK]); 252 __put_user(env->xer, &frame->mc_gregs[TARGET_PT_XER]); 253 254 for (i = 0; i < ARRAY_SIZE(env->crf); i++) { 255 ccr |= env->crf[i] << (32 - ((i + 1) * 4)); 256 } 257 __put_user(ccr, &frame->mc_gregs[TARGET_PT_CCR]); 258 259 /* Save Altivec registers if necessary. */ 260 if (env->insns_flags & PPC_ALTIVEC) { 261 uint32_t *vrsave; 262 for (i = 0; i < ARRAY_SIZE(env->avr); i++) { 263 ppc_avr_t *avr = &env->avr[i]; 264 ppc_avr_t *vreg = (ppc_avr_t *)&frame->mc_vregs.altivec[i]; 265 266 __put_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]); 267 __put_user(avr->u64[PPC_VEC_LO], &vreg->u64[1]); 268 } 269 /* Set MSR_VR in the saved MSR value to indicate that 270 frame->mc_vregs contains valid data. */ 271 msr |= MSR_VR; 272 #if defined(TARGET_PPC64) 273 vrsave = (uint32_t *)&frame->mc_vregs.altivec[33]; 274 /* 64-bit needs to put a pointer to the vectors in the frame */ 275 __put_user(h2g(frame->mc_vregs.altivec), &frame->v_regs); 276 #else 277 vrsave = (uint32_t *)&frame->mc_vregs.altivec[32]; 278 #endif 279 __put_user((uint32_t)env->spr[SPR_VRSAVE], vrsave); 280 } 281 282 /* Save VSX second halves */ 283 if (env->insns_flags2 & PPC2_VSX) { 284 uint64_t *vsregs = (uint64_t *)&frame->mc_vregs.altivec[34]; 285 for (i = 0; i < ARRAY_SIZE(env->vsr); i++) { 286 __put_user(env->vsr[i], &vsregs[i]); 287 } 288 } 289 290 /* Save floating point registers. */ 291 if (env->insns_flags & PPC_FLOAT) { 292 for (i = 0; i < ARRAY_SIZE(env->fpr); i++) { 293 __put_user(env->fpr[i], &frame->mc_fregs[i]); 294 } 295 __put_user((uint64_t) env->fpscr, &frame->mc_fregs[32]); 296 } 297 298 /* Save SPE registers. The kernel only saves the high half. */ 299 if (env->insns_flags & PPC_SPE) { 300 #if defined(TARGET_PPC64) 301 for (i = 0; i < ARRAY_SIZE(env->gpr); i++) { 302 __put_user(env->gpr[i] >> 32, &frame->mc_vregs.spe[i]); 303 } 304 #else 305 for (i = 0; i < ARRAY_SIZE(env->gprh); i++) { 306 __put_user(env->gprh[i], &frame->mc_vregs.spe[i]); 307 } 308 #endif 309 /* Set MSR_SPE in the saved MSR value to indicate that 310 frame->mc_vregs contains valid data. */ 311 msr |= MSR_SPE; 312 __put_user(env->spe_fscr, &frame->mc_vregs.spe[32]); 313 } 314 315 /* Store MSR. */ 316 __put_user(msr, &frame->mc_gregs[TARGET_PT_MSR]); 317 } 318 319 static void encode_trampoline(int sigret, uint32_t *tramp) 320 { 321 /* Set up the sigreturn trampoline: li r0,sigret; sc. */ 322 if (sigret) { 323 __put_user(0x38000000 | sigret, &tramp[0]); 324 __put_user(0x44000002, &tramp[1]); 325 } 326 } 327 328 static void restore_user_regs(CPUPPCState *env, 329 struct target_mcontext *frame, int sig) 330 { 331 target_ulong save_r2 = 0; 332 target_ulong msr; 333 target_ulong ccr; 334 335 int i; 336 337 if (!sig) { 338 save_r2 = env->gpr[2]; 339 } 340 341 /* Restore general registers. */ 342 for (i = 0; i < ARRAY_SIZE(env->gpr); i++) { 343 __get_user(env->gpr[i], &frame->mc_gregs[i]); 344 } 345 __get_user(env->nip, &frame->mc_gregs[TARGET_PT_NIP]); 346 __get_user(env->ctr, &frame->mc_gregs[TARGET_PT_CTR]); 347 __get_user(env->lr, &frame->mc_gregs[TARGET_PT_LNK]); 348 __get_user(env->xer, &frame->mc_gregs[TARGET_PT_XER]); 349 __get_user(ccr, &frame->mc_gregs[TARGET_PT_CCR]); 350 351 for (i = 0; i < ARRAY_SIZE(env->crf); i++) { 352 env->crf[i] = (ccr >> (32 - ((i + 1) * 4))) & 0xf; 353 } 354 355 if (!sig) { 356 env->gpr[2] = save_r2; 357 } 358 /* Restore MSR. */ 359 __get_user(msr, &frame->mc_gregs[TARGET_PT_MSR]); 360 361 /* If doing signal return, restore the previous little-endian mode. */ 362 if (sig) 363 env->msr = (env->msr & ~(1ull << MSR_LE)) | (msr & (1ull << MSR_LE)); 364 365 /* Restore Altivec registers if necessary. */ 366 if (env->insns_flags & PPC_ALTIVEC) { 367 ppc_avr_t *v_regs; 368 uint32_t *vrsave; 369 #if defined(TARGET_PPC64) 370 uint64_t v_addr; 371 /* 64-bit needs to recover the pointer to the vectors from the frame */ 372 __get_user(v_addr, &frame->v_regs); 373 v_regs = g2h(v_addr); 374 #else 375 v_regs = (ppc_avr_t *)frame->mc_vregs.altivec; 376 #endif 377 for (i = 0; i < ARRAY_SIZE(env->avr); i++) { 378 ppc_avr_t *avr = &env->avr[i]; 379 ppc_avr_t *vreg = &v_regs[i]; 380 381 __get_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]); 382 __get_user(avr->u64[PPC_VEC_LO], &vreg->u64[1]); 383 } 384 /* Set MSR_VEC in the saved MSR value to indicate that 385 frame->mc_vregs contains valid data. */ 386 #if defined(TARGET_PPC64) 387 vrsave = (uint32_t *)&v_regs[33]; 388 #else 389 vrsave = (uint32_t *)&v_regs[32]; 390 #endif 391 __get_user(env->spr[SPR_VRSAVE], vrsave); 392 } 393 394 /* Restore VSX second halves */ 395 if (env->insns_flags2 & PPC2_VSX) { 396 uint64_t *vsregs = (uint64_t *)&frame->mc_vregs.altivec[34]; 397 for (i = 0; i < ARRAY_SIZE(env->vsr); i++) { 398 __get_user(env->vsr[i], &vsregs[i]); 399 } 400 } 401 402 /* Restore floating point registers. */ 403 if (env->insns_flags & PPC_FLOAT) { 404 uint64_t fpscr; 405 for (i = 0; i < ARRAY_SIZE(env->fpr); i++) { 406 __get_user(env->fpr[i], &frame->mc_fregs[i]); 407 } 408 __get_user(fpscr, &frame->mc_fregs[32]); 409 env->fpscr = (uint32_t) fpscr; 410 } 411 412 /* Save SPE registers. The kernel only saves the high half. */ 413 if (env->insns_flags & PPC_SPE) { 414 #if defined(TARGET_PPC64) 415 for (i = 0; i < ARRAY_SIZE(env->gpr); i++) { 416 uint32_t hi; 417 418 __get_user(hi, &frame->mc_vregs.spe[i]); 419 env->gpr[i] = ((uint64_t)hi << 32) | ((uint32_t) env->gpr[i]); 420 } 421 #else 422 for (i = 0; i < ARRAY_SIZE(env->gprh); i++) { 423 __get_user(env->gprh[i], &frame->mc_vregs.spe[i]); 424 } 425 #endif 426 __get_user(env->spe_fscr, &frame->mc_vregs.spe[32]); 427 } 428 } 429 430 #if !defined(TARGET_PPC64) 431 void setup_frame(int sig, struct target_sigaction *ka, 432 target_sigset_t *set, CPUPPCState *env) 433 { 434 struct target_sigframe *frame; 435 struct target_sigcontext *sc; 436 target_ulong frame_addr, newsp; 437 int err = 0; 438 439 frame_addr = get_sigframe(ka, env, sizeof(*frame)); 440 trace_user_setup_frame(env, frame_addr); 441 if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 1)) 442 goto sigsegv; 443 sc = &frame->sctx; 444 445 __put_user(ka->_sa_handler, &sc->handler); 446 __put_user(set->sig[0], &sc->oldmask); 447 __put_user(set->sig[1], &sc->_unused[3]); 448 __put_user(h2g(&frame->mctx), &sc->regs); 449 __put_user(sig, &sc->signal); 450 451 /* Save user regs. */ 452 save_user_regs(env, &frame->mctx); 453 454 /* Construct the trampoline code on the stack. */ 455 encode_trampoline(TARGET_NR_sigreturn, (uint32_t *)&frame->mctx.tramp); 456 457 /* The kernel checks for the presence of a VDSO here. We don't 458 emulate a vdso, so use a sigreturn system call. */ 459 env->lr = (target_ulong) h2g(frame->mctx.tramp); 460 461 /* Turn off all fp exceptions. */ 462 env->fpscr = 0; 463 464 /* Create a stack frame for the caller of the handler. */ 465 newsp = frame_addr - SIGNAL_FRAMESIZE; 466 err |= put_user(env->gpr[1], newsp, target_ulong); 467 468 if (err) 469 goto sigsegv; 470 471 /* Set up registers for signal handler. */ 472 env->gpr[1] = newsp; 473 env->gpr[3] = sig; 474 env->gpr[4] = frame_addr + offsetof(struct target_sigframe, sctx); 475 476 env->nip = (target_ulong) ka->_sa_handler; 477 478 /* Signal handlers are entered in big-endian mode. */ 479 env->msr &= ~(1ull << MSR_LE); 480 481 unlock_user_struct(frame, frame_addr, 1); 482 return; 483 484 sigsegv: 485 unlock_user_struct(frame, frame_addr, 1); 486 force_sigsegv(sig); 487 } 488 #endif /* !defined(TARGET_PPC64) */ 489 490 void setup_rt_frame(int sig, struct target_sigaction *ka, 491 target_siginfo_t *info, 492 target_sigset_t *set, CPUPPCState *env) 493 { 494 struct target_rt_sigframe *rt_sf; 495 uint32_t *trampptr = 0; 496 struct target_mcontext *mctx = 0; 497 target_ulong rt_sf_addr, newsp = 0; 498 int i, err = 0; 499 #if defined(TARGET_PPC64) 500 struct target_sigcontext *sc = 0; 501 struct image_info *image = ((TaskState *)thread_cpu->opaque)->info; 502 #endif 503 504 rt_sf_addr = get_sigframe(ka, env, sizeof(*rt_sf)); 505 if (!lock_user_struct(VERIFY_WRITE, rt_sf, rt_sf_addr, 1)) 506 goto sigsegv; 507 508 tswap_siginfo(&rt_sf->info, info); 509 510 __put_user(0, &rt_sf->uc.tuc_flags); 511 __put_user(0, &rt_sf->uc.tuc_link); 512 target_save_altstack(&rt_sf->uc.tuc_stack, env); 513 #if !defined(TARGET_PPC64) 514 __put_user(h2g (&rt_sf->uc.tuc_mcontext), 515 &rt_sf->uc.tuc_regs); 516 #endif 517 for(i = 0; i < TARGET_NSIG_WORDS; i++) { 518 __put_user(set->sig[i], &rt_sf->uc.tuc_sigmask.sig[i]); 519 } 520 521 #if defined(TARGET_PPC64) 522 mctx = &rt_sf->uc.tuc_sigcontext.mcontext; 523 trampptr = &rt_sf->trampoline[0]; 524 525 sc = &rt_sf->uc.tuc_sigcontext; 526 __put_user(h2g(mctx), &sc->regs); 527 __put_user(sig, &sc->signal); 528 #else 529 mctx = &rt_sf->uc.tuc_mcontext; 530 trampptr = (uint32_t *)&rt_sf->uc.tuc_mcontext.tramp; 531 #endif 532 533 save_user_regs(env, mctx); 534 encode_trampoline(TARGET_NR_rt_sigreturn, trampptr); 535 536 /* The kernel checks for the presence of a VDSO here. We don't 537 emulate a vdso, so use a sigreturn system call. */ 538 env->lr = (target_ulong) h2g(trampptr); 539 540 /* Turn off all fp exceptions. */ 541 env->fpscr = 0; 542 543 /* Create a stack frame for the caller of the handler. */ 544 newsp = rt_sf_addr - (SIGNAL_FRAMESIZE + 16); 545 err |= put_user(env->gpr[1], newsp, target_ulong); 546 547 if (err) 548 goto sigsegv; 549 550 /* Set up registers for signal handler. */ 551 env->gpr[1] = newsp; 552 env->gpr[3] = (target_ulong) sig; 553 env->gpr[4] = (target_ulong) h2g(&rt_sf->info); 554 env->gpr[5] = (target_ulong) h2g(&rt_sf->uc); 555 env->gpr[6] = (target_ulong) h2g(rt_sf); 556 557 #if defined(TARGET_PPC64) 558 if (get_ppc64_abi(image) < 2) { 559 /* ELFv1 PPC64 function pointers are pointers to OPD entries. */ 560 struct target_func_ptr *handler = 561 (struct target_func_ptr *)g2h(ka->_sa_handler); 562 env->nip = tswapl(handler->entry); 563 env->gpr[2] = tswapl(handler->toc); 564 } else { 565 /* ELFv2 PPC64 function pointers are entry points, but R12 566 * must also be set */ 567 env->nip = tswapl((target_ulong) ka->_sa_handler); 568 env->gpr[12] = env->nip; 569 } 570 #else 571 env->nip = (target_ulong) ka->_sa_handler; 572 #endif 573 574 /* Signal handlers are entered in big-endian mode. */ 575 env->msr &= ~(1ull << MSR_LE); 576 577 unlock_user_struct(rt_sf, rt_sf_addr, 1); 578 return; 579 580 sigsegv: 581 unlock_user_struct(rt_sf, rt_sf_addr, 1); 582 force_sigsegv(sig); 583 584 } 585 586 #if !defined(TARGET_PPC64) 587 long do_sigreturn(CPUPPCState *env) 588 { 589 struct target_sigcontext *sc = NULL; 590 struct target_mcontext *sr = NULL; 591 target_ulong sr_addr = 0, sc_addr; 592 sigset_t blocked; 593 target_sigset_t set; 594 595 sc_addr = env->gpr[1] + SIGNAL_FRAMESIZE; 596 if (!lock_user_struct(VERIFY_READ, sc, sc_addr, 1)) 597 goto sigsegv; 598 599 #if defined(TARGET_PPC64) 600 set.sig[0] = sc->oldmask + ((uint64_t)(sc->_unused[3]) << 32); 601 #else 602 __get_user(set.sig[0], &sc->oldmask); 603 __get_user(set.sig[1], &sc->_unused[3]); 604 #endif 605 target_to_host_sigset_internal(&blocked, &set); 606 set_sigmask(&blocked); 607 608 __get_user(sr_addr, &sc->regs); 609 if (!lock_user_struct(VERIFY_READ, sr, sr_addr, 1)) 610 goto sigsegv; 611 restore_user_regs(env, sr, 1); 612 613 unlock_user_struct(sr, sr_addr, 1); 614 unlock_user_struct(sc, sc_addr, 1); 615 return -TARGET_QEMU_ESIGRETURN; 616 617 sigsegv: 618 unlock_user_struct(sr, sr_addr, 1); 619 unlock_user_struct(sc, sc_addr, 1); 620 force_sig(TARGET_SIGSEGV); 621 return -TARGET_QEMU_ESIGRETURN; 622 } 623 #endif /* !defined(TARGET_PPC64) */ 624 625 /* See arch/powerpc/kernel/signal_32.c. */ 626 static int do_setcontext(struct target_ucontext *ucp, CPUPPCState *env, int sig) 627 { 628 struct target_mcontext *mcp; 629 target_ulong mcp_addr; 630 sigset_t blocked; 631 target_sigset_t set; 632 633 if (copy_from_user(&set, h2g(ucp) + offsetof(struct target_ucontext, tuc_sigmask), 634 sizeof (set))) 635 return 1; 636 637 #if defined(TARGET_PPC64) 638 mcp_addr = h2g(ucp) + 639 offsetof(struct target_ucontext, tuc_sigcontext.mcontext); 640 #else 641 __get_user(mcp_addr, &ucp->tuc_regs); 642 #endif 643 644 if (!lock_user_struct(VERIFY_READ, mcp, mcp_addr, 1)) 645 return 1; 646 647 target_to_host_sigset_internal(&blocked, &set); 648 set_sigmask(&blocked); 649 restore_user_regs(env, mcp, sig); 650 651 unlock_user_struct(mcp, mcp_addr, 1); 652 return 0; 653 } 654 655 long do_rt_sigreturn(CPUPPCState *env) 656 { 657 struct target_rt_sigframe *rt_sf = NULL; 658 target_ulong rt_sf_addr; 659 660 rt_sf_addr = env->gpr[1] + SIGNAL_FRAMESIZE + 16; 661 if (!lock_user_struct(VERIFY_READ, rt_sf, rt_sf_addr, 1)) 662 goto sigsegv; 663 664 if (do_setcontext(&rt_sf->uc, env, 1)) 665 goto sigsegv; 666 667 do_sigaltstack(rt_sf_addr 668 + offsetof(struct target_rt_sigframe, uc.tuc_stack), 669 0, env->gpr[1]); 670 671 unlock_user_struct(rt_sf, rt_sf_addr, 1); 672 return -TARGET_QEMU_ESIGRETURN; 673 674 sigsegv: 675 unlock_user_struct(rt_sf, rt_sf_addr, 1); 676 force_sig(TARGET_SIGSEGV); 677 return -TARGET_QEMU_ESIGRETURN; 678 } 679